A full-pipelined AES real-time encryption system for high-speed transmission
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA UNIV OF SCI & TECH
- Filing Date
- 2026-04-14
- Publication Date
- 2026-06-26
Smart Images
Figure CN122293307A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of secure data transmission and hardware cryptography, specifically to a fully pipelined AES real-time encryption system and method based on field-programmable gate arrays for high-speed transmission. Background Technology
[0002] With the increasing demands for data acquisition bandwidth in fields such as high-energy physics experiments and radar detection, gigabit and even 10-gigabit high-speed data acquisition systems are being widely used. However, in these systems, data is often transmitted in plaintext over the network, posing a significant risk of data leakage and tampering.
[0003] Advanced Encryption Standard (AES) is currently the most widely used symmetric encryption algorithm. Existing AES hardware acceleration solutions mostly employ iterative multiplexing architectures, which save hardware area but generally limit throughput, failing to meet the Gbps-level line-speed transmission requirements of current high-speed acquisition systems. Furthermore, existing designs often rely on block random access memory (BRAM) when implementing the core nonlinear component "S-box" of AES, whose synchronous read characteristics introduce additional clock cycle delays. In column-mixed operations, traditional finite field multiplication implementations tend to generate long carry chains, resulting in excessively long critical paths and limiting the system's operating frequency. Summary of the Invention
[0004] To address the technical problems of existing AES hardware encryption modules, such as limited throughput, intense competition for storage resources, and long critical path latency preventing system clock speed increases when processing high-speed network data streams, this invention provides a fully pipelined AES real-time encryption system and method for high-speed transmission. This invention achieves line-speed encryption of Gbps-level high-speed network data through a fully deployed pipelined architecture and low-level operator-level logic reconstruction.
[0005] The technical solution for this proposal:
[0006] In a first aspect, embodiments of the present invention provide a fully pipelined AES real-time encryption system for high-speed transmission, the system comprising:
[0007] The data input buffer module is used to receive external high-speed network data streams and perform bit width matching to construct continuous 128-bit plaintext data blocks;
[0008] The round key parallel generation module is used to pre-perform key expansion operations and output 10 sets of 128-bit round keys in parallel;
[0009] The fully pipelined encryption operation module comprises 10 cascaded round transformation units, with inter-stage pipelined registers inserted between each unit. The first to ninth round transformation units each sequentially include a byte substitution subunit, a row shift subunit, a column mixing subunit, and a round key addition subunit; the tenth round transformation unit includes a byte substitution subunit, a row shift subunit, and a round key addition subunit. These 10 round transformation units are used to pipelined concurrently process the plaintext data block under the drive of a global clock signal.
[0010] The data output driver module is used to buffer and output the ciphertext data blocks processed by the fully pipelined encryption operation module in sequence.
[0011] Optionally, in one embodiment of the present invention, the byte substitution subunit adopts a lookup table architecture based on distributed ROM; its hardware logic implementation specifically includes:
[0012] The constant table of the nonlinear S-box in the AES algorithm is mapped to the lookup table resource at the bottom layer of the field programmable gate array to construct a distributed read-only memory.
[0013] The input 8-bit status byte is directly used as the address of the lookup table resource;
[0014] The lookup table resource responds to the address through internal combinational logic and outputs the corresponding 8-bit replacement byte directly within the current clock cycle in an asynchronous reading manner.
[0015] Optionally, in one embodiment of the present invention, the column hybrid sub-unit adopts a carry-free XOR tree architecture based on the XTime operator; its hardware logic implementation specifically includes:
[0016] An XTime hardware operator is constructed. The XTime hardware operator extracts the most significant bit of the input byte as a condition signal through physical connections and shifts the entire input byte left by one bit. When the condition signal is active, the left-shifted data is XORed with a preset polynomial constant.
[0017] The finite field matrix multiplication operation in the column hybrid sub-unit is all decomposed into the combination logic of multiple XTime hardware operators;
[0018] The finite field matrix accumulation operation in the column hybrid sub-unit is implemented through a purely parallel XOR gate logic network, which directly performs bitwise XOR on the outputs and input status bytes of multiple XTime hardware operators to form a combinational logic tree that eliminates carry propagation chains.
[0019] Optionally, in one embodiment of the present invention, when the system is reset or a key update instruction is received, the parallel generation module for round keys simultaneously hardwires the 10 sets of round keys generated by the extension to the input end of the round key addition subunit in the corresponding 10-level round transformation unit through a multiplexing network, thereby realizing the parallel static supply of keys.
[0020] Secondly, embodiments of the present invention also provide a fully pipelined AES real-time encryption method for high-speed transmission, applied to the system described in the first aspect above, the method comprising the following steps:
[0021] The data input buffer module continuously receives data streams and outputs 128-bit plaintext data blocks.
[0022] The round key parallel generation module generates 10 sets of 128-bit round keys at once and maintains parallel output.
[0023] Driven by the global clock cycle, the 10-stage wheel transformation units in the fully pipelined encryption operation module work concurrently; at the effective edge of each clock cycle, each stage of the wheel transformation unit synchronously receives the data output from the previous stage pipeline register, executes the combinational logic operation of the encryption wheel function of this stage, and latches the operation result into the next stage pipeline register.
[0024] The data output driver module continuously receives and outputs a 128-bit ciphertext data block every clock cycle.
[0025] The technical solutions provided by the embodiments of the present invention bring the following beneficial effects:
[0026] Breaking through throughput bottlenecks and achieving ultra-fast encryption: This invention fully expands 10 levels of AES round function operations in space and utilizes inter-pipeline registers for data isolation and timing control. Once the pipeline is fully utilized, the system can achieve the maximum efficiency of processing a set of 128 bits of data per clock cycle, overcoming the low throughput of traditional multiplexing architectures and seamlessly meeting Gbps encryption requirements.
[0027] Achieving zero-cycle lookup latency and optimizing storage resource allocation: This invention breaks away from the conventional approach of using block random access memory (BRAM) for byte substitution. By directly mapping the S-box lookup logic to the underlying lookup table resources to construct a distributed ROM, true asynchronous reading is achieved. This not only eliminates the inherent synchronous read latency of at least one clock cycle in BRAM but also frees up valuable BRAM resources for large-scale data caching within the system, greatly optimizing the overall utilization of hardware resources.
[0028] Eliminating long carry chains and significantly improving system operating frequency: This invention features a deep underlying logic reconstruction for column-wise mixed operations, stripping away traditional multiplier and adder resources and innovatively utilizing shift and conditional XOR logic to construct the XTime operator. Matrix accumulation operations are completely transformed into a parallel XOR tree physical interconnect network. This architecture physically eliminates the unavoidable carry chains in arithmetic operations, compressing critical path latency to the latency limit of pure logic gates, thereby significantly improving the maximum operating frequency of the encryption engine and the system's timing margin. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0030] Figure 1 This is a schematic diagram of the overall architecture of a fully pipelined AES real-time encryption system for high-speed transmission provided by an embodiment of the present invention.
[0031] Figure 2 This is a schematic diagram of the 10-level spatial expansion structure of the fully pipelined encryption operation module in this embodiment of the invention.
[0032] Figure 3 This is a hardware implementation logic diagram of byte substitution (S-box) based on distributed ROM in an embodiment of the present invention.
[0033] Figure 4 This is a schematic diagram of a column-mixed, carry-free XOR tree logic structure based on the XTime operator in an embodiment of the present invention.
[0034] Figure 5 This is a flowchart illustrating a fully pipelined AES real-time encryption method for high-speed transmission provided by an embodiment of the present invention. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. The illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.
[0036] Example 1: System Overall Architecture.
[0037] Please see Figure 1This invention provides a fully pipelined AES real-time encryption system for high-speed transmission, deployed in a field-programmable gate array (FPGA). The system mainly consists of four parts: a data input buffer module, a round key parallel generation module, a fully pipelined encryption operation module, and a data output driver module.
[0038] Specifically, in high-speed network data acquisition scenarios, the data input buffer module receives data streams from upstream data links. This module contains bit-width conversion and clock domain handover logic, which concatenates input data of different bit widths into a standard 128-bit plaintext data block, and synchronously pushes the plaintext data block to the fully pipelined encryption operation module under the drive of the system's global encryption clock.
[0039] The round key parallel generation module starts upon system initialization or upon receiving a key update command. Unlike the traditional AES multiplexing mode, which calculates the round key in real time during each round of encryption, the round key parallel generation module in this embodiment runs the key expansion algorithm all at once, pre-generating 10 independent 128-bit round keys. These 10 round keys are then distributed in parallel to the corresponding levels of the fully pipelined encryption operation module in static voltage levels via a multiplexing network or direct physical hardwired connections.
[0040] Example 2: Cascaded architecture of fully pipelined encryption computing modules.
[0041] Please see Figure 2 The fully pipelined encryption computation module is the core acceleration unit of this system. To overcome the throughput bottleneck, this embodiment abandons the conventional single-level round function iterative reuse architecture and instead adopts a "space-for-time" fully pipelined fully expanded architecture.
[0042] The fully pipelined encryption operation module physically instantiates 10 concatenated round transformation units in space. The first to ninth round transformation units respectively include: byte substitution subunit, row shift subunit, column mixing subunit, and round key addition subunit; the tenth round transformation unit only includes byte substitution subunit, row shift subunit, and round key addition subunit.
[0043] At the output of each stage of the round-shift unit, a 128-bit interstage pipelined register is inserted. On the rising edge of the global clock, each pipelined register synchronously latches the result of the previous stage's combinational logic. After an initial delay of 10 clock cycles, once the pipeline is full, the system can process a 128-bit ciphertext data in parallel each clock cycle, achieving line-speed encryption.
[0044] Example 3: S-box zero-cycle lookup table design based on distributed ROM.
[0045] Please see Figure 3In the AES encryption algorithm, byte substitution (S-box) is the only non-linear operation, typically requiring a 256×8-bit lookup table operation. In traditional FPGA designs, the S-box is often implemented using the FPGA's internal block random access memory (BRAM). However, BRAM is a synchronous device; its read operation must be performed after the valid clock edge to output the result, which inevitably introduces a delay of at least one clock cycle, leading to pipeline bubbles or a lengthened critical path.
[0046] To address the aforementioned issues, the byte substitution subunit in this embodiment employs a lookup table architecture based on distributed ROM. Specifically, the nonlinear substitution constant of the S-box is directly instantiated using the underlying hardware description language. The FPGA synthesis tool then maps this constant to a lookup table resource in the underlying logic unit, forming a distributed read-only memory.
[0047] During runtime, the input 8-bit status byte is directly used as the address of this distributed ROM via a connection. Since the LUT is essentially a multi-input pure combinational logic gate array, this architecture enables purely asynchronous reads. This means that after the address is input, there is no need to wait for the clock edge to trigger; the replacement result can be directly output within the combinational logic delay of the current clock cycle, achieving "zero clock cycle" lookup latency and greatly optimizing the inter-stage timing of the pipeline.
[0048] Example 4: Design of a column-mixed carry-free XOR tree based on the XTime operator.
[0049] Please see Figure 4 Columnar mixed operations involve polynomial matrix multiplication and accumulation over the finite field GF(2^8), which is the most complex and time-consuming part of the AES algorithm in terms of combinational logic. Traditional designs typically call multiplier IPs or use serial adder trees, which results in lengthy carry-transfer chains, severely limiting the improvement of the system's operating frequency.
[0050] This embodiment refactors the column hybrid sub-unit at the operator level, employing a carry-free XOR tree architecture. First, the basic XTime hardware operator is constructed. For finite field multiplication by two, the hardware connection of the XTime operator is as follows: the most significant bit (Bit 7) of the 8-bit input data is extracted as a conditional control signal, and the original data is shifted left by 1 bit; when the conditional control signal is high, the left-shifted data is XORed with a fixed constant 0x1B (i.e., 8'b00011011).
[0051] Based on this, complex matrix multiplication operations (such as multiplication by 3 and multiplication by 4) in column mixing are all decomposed into multi-level cascades and shifts of XTime operators. For the accumulation step of matrix operations, this embodiment abandons the traditional adder and instead uses a purely parallel XOR gate network to directly perform bitwise XOR on the original values of the output and input of each XTime operator.
[0052] Since XOR gates can be directly mapped to combinational logic of a single LUT in an FPGA, this spatial multi-branch tree structure completely eliminates the carry chain delay caused by arithmetic addition. Data flow is entirely transmitted through parallel logic gates, greatly shortening the critical path and significantly increasing the maximum clock frequency of the entire pipelined encryption operation module.
[0053] Example 5: Encryption method flow.
[0054] Please see Figure 5 Based on the above system architecture, this invention also provides a fully pipelined AES real-time encryption method for high-speed transmission, which includes the following core steps:
[0055] S101: When the system is powered on or reset, the parallel round key generation module performs key expansion, generates 10 complete 128-bit round keys, and statically distributes them to the corresponding pipeline levels.
[0056] S102: The data input buffer module receives high-speed network data streams and splices them to generate 128-bit plaintext data blocks.
[0057] S103: After the plaintext data block is added to the round key of group 0, it enters the encryption pipeline with full space expansion at level 10.
[0058] S104: At the rising edge of each global clock cycle, the 10-stage round transformation unit concurrently executes its respective round function logic, including asynchronous byte substitution based on distributed ROM, row shifting, column mixing based on XTime XOR tree, and round key addition, and latches the result of the operation at this stage into the corresponding inter-stage pipeline register.
[0059] S105: After an initial pipeline setup time of 10 clock cycles, the data output driver module continuously receives and outputs a 128-bit ciphertext data block in each clock cycle, achieving seamless line-speed encryption of high-speed data streams.
[0060] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A fully pipelined AES real-time encryption system for high-speed transmission, characterized in that, include: The data input buffer module is used to receive external high-speed network data streams, perform bit width matching and clock domain conversion, and construct 128-bit plaintext data blocks; A fully pipelined encryption operation module, comprising a spatially cascaded 10-level wheel transformation unit, used to perform step-by-step pipelined encryption on the plaintext data block; The round key pre-computation module is used to complete the pre-computation of all round keys during the system initialization phase and distribute the corresponding 128-bit round keys in parallel to the 10-level round transformation unit; The data output driver module is used to sequentially buffer and output the 128-bit encrypted data blocks that have been processed by the 10-stage wheel transformation unit.
2. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 1, characterized in that, In the 10-level wheel transformation unit that is cascaded end-to-end in space, the first to ninth level wheel transformation units each include: a byte substitution subunit, a row shift subunit, a column mixing subunit, and a wheel key addition subunit; the tenth level wheel transformation unit includes: a byte substitution subunit, a row shift subunit, and a wheel key addition subunit.
3. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 2, characterized in that, The byte substitution subunit adopts a lookup table architecture based on distributed ROM; specifically, the S-box nonlinear substitution table in the AES algorithm is pre-frozen in the lookup table (LUT) resource of the field programmable gate array (FPGA) to construct a distributed read-only memory.
4. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 3, characterized in that, The distributed ROM-based lookup table architecture uses the input 8-bit data as the lookup table address and achieves asynchronous reading through the FPGA's underlying combinational logic connections. It directly outputs the corresponding 8-bit substitution data with zero clock cycle delay, avoiding the synchronous clock edge triggering delay caused by using block random access memory (BRAM).
5. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 2, characterized in that, The column hybrid sub-unit adopts a carry-free XOR tree architecture based on the XTime operator; specifically, the polynomial multiplication operation on the finite field GF(2^8) is decomposed into a combination of shift operations and logical XOR operations.
6. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 5, characterized in that, In the XTime operator-based carry-free XOR tree architecture, the hardware mapping logic of the XTime operator is as follows: the input 8-bit data is shifted left by 1 bit. If the original highest bit is 1, the result after the left shift is XORed with a fixed constant 0x1B. All matrix multiplication and addition operations in the column hybrid sub-unit are composed of the XTime operator and the parallel distributed XOR gate network, eliminating the carry chain delay caused by the multiplier.
7. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 1, characterized in that, The round key pre-computation module uses a dedicated multiplexing network or hardwired connection to simultaneously physically map the 10 sets of extended round keys to the input of the round key addition subunit of the corresponding 10-level round transformation unit, thereby achieving parallel static key supply.
8. The fully pipelined AES real-time encryption system for high-speed transmission according to claim 1, characterized in that, The fully pipelined encryption operation module inserts pipeline inter-stage registers between each stage of the round transformation unit, enabling the system to receive a new 128-bit plaintext data block and output a 128-bit ciphertext data block in each clock cycle.
9. A fully pipelined AES real-time encryption method for high-speed transmission, applied to the system described in any one of claims 1 to 8, characterized in that, The method includes the following steps: S1, the data input buffer module continuously receives external high-speed data streams, splices them together, and outputs continuous 128-bit plaintext data blocks; S2, after the round key parallel generation module detects the initialization command, it executes the key expansion algorithm to generate 10 sets of 128-bit round keys at once and maintains the output state; S3, the fully pipelined encryption operation module receives the plaintext data block, and after the initial round key addition operation, pushes the data into the spatially fully expanded 10-stage round transformation pipeline; S4, at the rising edge of each clock cycle, the 10-level round transformation unit concurrently executes the encryption round function operation of its respective level and latches the operation result of this level into the inter-level register of the next level; S5, after experiencing a corresponding number of clock cycle delays, the data output driver module continuously receives and outputs a 128-bit ciphertext data block every clock cycle.
10. The fully pipelined AES real-time encryption method for high-speed transmission according to claim 9, characterized in that, In the encryption round function operation in step S4: When performing byte substitution, the distributed ROM consisting of the FPGA's internal lookup table is read asynchronously using combinational logic to achieve zero-cycle data replacement; When performing column mixing, the data is input into a carry-free XOR tree network composed of XTime operators, and finite field multiplication and accumulation operations are completed through pure parallel logic gates.