A signal control device, method and host for a display interface

Abstract

This application relates to the field of signal control technology, and discloses a signal control device, method, and host for a display interface. The device is installed within a host computer. It includes: a power supply detection module connected to the power pin of the display signal interface, which generates a power supply hold signal if the host computer detects power supply to an external display device; a reset identification module that generates a warm restart flag signal if the motherboard is detected to be in a warm restart state; a handshake management module that generates a protection window enable signal in response to receiving the power supply hold signal and the warm restart flag signal; and a signal control module connected between a first hot-swappable pin on the motherboard and a second hot-swappable pin of the display signal interface, which clamps the level of the hot-swappable signal input to the second hot-swappable pin to a preset level value in response to receiving the protection window enable signal, and outputs it to the first hot-swappable pin. Through the above methods, this application improves the usability of the device.

Description

Technical Field

[0001] This application relates to the field of signal control technology, specifically to a signal control device, method, and host for a display interface. Background Technology

[0002] In modern computer display systems, the reliability of the High Definition Multimedia Interface (HDMI) link depends on two key handshake signals: Hot Plug Detect (HPD) notification and Extended Display Identification Data (EDID) reading.

[0003] The host continuously monitors the level of the HPD signal to detect the connection and removal of the display device. After detecting a connection event, it reads the EDID information of the display through the Display Data Channel (DDC) to negotiate and establish a stable video and audio transmission channel.

[0004] However, in applications such as industrial control and commercial display, the host device often needs to perform a software restart (i.e., a warm restart) while running the operating system. At the same time, the +5V power supply (VCC5) provided by its HDMI interface to the external monitor is usually uninterrupted, and the external monitor will continuously try to handshake with the host and send HPD pulses to the host.

[0005] If the HPD pulse happens to occur within the time window when the host operating system kernel loads and initializes the display driver, the operating system will incorrectly identify this pulse as a physical event of the display being disconnected and then reconnected. This misjudgment will severely interfere with the normal state machine of the display driver initialization, leading to driver configuration disorder or resource allocation errors.

[0006] Ultimately, although the operating system appears to have successfully booted to the user interface, the HDMI display output is in a malfunctioning state, displaying a black screen or no signal. Manual intervention (such as unplugging and replugging the cable or powering off and restarting the monitor) is required to restore the display. Such situations can easily lead to the loss of host availability, causing a large number of users to report repairs to the host device and external monitor, resulting in a waste of manpower.

[0007] Therefore, improving the availability of equipment has become an urgent technical problem to be solved. Summary of the Invention

[0008] In view of the above problems, embodiments of this application provide a signal control device, method and host for a display interface, which solves the problem that the availability of devices in the prior art needs to be improved.

[0009] According to one aspect of the embodiments of this application, a signal control device for a display interface is provided. The device is configured within a host computer, which includes a motherboard and a display signal interface for connecting to an external display device. The device includes: a power supply detection module connected to a power pin of the display signal interface, which generates a power supply hold signal if the host computer detects power supply to an external display device through the power pin; a reset identification module connected to the motherboard, which generates a warm restart flag signal if the motherboard is detected to be in a warm restart state; a handshake management module connected to both the power supply detection module and the reset identification module, which generates a protection window enable signal in response to receiving the power supply hold signal and the warm restart flag signal within a first preset time period; and a signal control module connected between a first hot-swappable pin of the motherboard and a second hot-swappable pin of the display signal interface and connected to the handshake management module, which clamps the level value of the hot-swappable signal input to the second hot-swappable pin to a preset level value and outputs it to the first hot-swappable pin in response to receiving the protection window enable signal.

[0010] Preferably, the handshake management module includes a timing unit; the timing unit is used to start timing when the protective window enable signal is generated, and to stop timing when the timing duration reaches the preset protective window duration, wherein the protective window enable signal remains valid during the timing unit's timing period; the signal control module is further used to: clamp the level value of the hot-plug signal input to the second hot-plug pin to a preset level value and output it to the first hot-plug pin during the period when the protective window enable signal is valid; and directly transmit the hot-plug signal input to the second hot-plug pin to the first hot-plug pin during the period when the protective window enable signal is invalid.

[0011] Preferably, the handshake management module is further configured to: continuously monitor the hot-plug signal from the second hot-plug pin starting from the receipt of the warm restart flag signal, and record the timestamp of the rising edge event in the monitored hot-plug signal until no new rising edge event is detected within a second preset time period from the last rising edge event, thereby obtaining multiple rising edge timestamps corresponding to this warm restart process; determine the earliest rising edge timestamp and the latest rising edge timestamp from the multiple rising edge timestamps; determine a reference protection duration based on the earliest rising edge timestamp and the latest rising edge timestamp, so as to adjust the protection window duration according to the reference protection duration.

[0012] Preferably, when the handshake management module is used to record the timestamp of the rising edge event in the detected hot-plug signal, it is specifically used to: when the rising edge of the hot-plug signal is detected, time the detected rising edge to obtain the pulse width duration; if the pulse width duration is greater than or equal to the preset debouncing time threshold, then the detected rising edge of the hot-plug signal is determined as a valid rising edge, and the timestamp of the valid rising edge is recorded.

[0013] Preferably, the host includes multiple display signal interfaces, and multiple power supply detection modules are connected one-to-one with the multiple display signal interfaces. Each power supply detection module is used to detect the power supply status of the display signal interface corresponding to it and generate a power supply hold signal. The handshake management module is connected to the multiple power supply detection modules and is used to generate a protection window enable signal corresponding to the target display signal interface in response to receiving the power supply hold signal and warm restart flag signal corresponding to the target display signal interface. The signal control module is used to connect between the first hot-swap pin of the motherboard and the second hot-swap pin of each display signal interface. In response to receiving the protection window enable signal corresponding to the target display signal interface, it clamps the level value of the hot-swap signal input to the second hot-swap pin of the target display signal interface to a preset level value and outputs it to the first hot-swap pin.

[0014] Preferably, the reset identification module is used to generate a warm restart flag signal if the motherboard is detected to be in a warm restart state. Specifically, it is used to sample the motherboard's platform reset signal, power ready signal, and system reset signal; if the platform reset signal is detected to undergo a transition from high level to low level and then back to high level, and the power ready signal and system reset signal are both kept at high level during the transition, then the motherboard is determined to be in a warm restart state, and a warm restart flag signal is generated.

[0015] Preferably, the preset level value is a first level value used to indicate to the motherboard that the external display device is in a connected state; or, the preset level value is a second level value used to indicate to the motherboard that the external display device is in a disconnected state.

[0016] Preferably, the display signal interface is a high-definition multimedia interface.

[0017] According to another aspect of the embodiments of this application, a host is provided, the host including a signal control device for a display interface as described in any of the above.

[0018] According to another aspect of the embodiments of this application, a signal control method for a display interface is provided. The method is applied to the signal control device of the display interface as described in any of the above claims. The method includes: detecting whether a host is supplying power to an external display device through a power pin; identifying whether the motherboard is in a warm restart state; if it is detected that the host is supplying power to an external display device through a power pin and the motherboard is identified as being in a warm restart state, then clamping the level value of the hot-plug signal input to the second hot-plug pin of the display signal interface to a preset level value and outputting it to the first hot-plug pin of the motherboard.

[0019] This application embodiment accurately identifies scenarios where the host undergoes a warm restart and the external display device continues to be powered by an configured power supply detection module and a reset identification module. A handshake management module generates a protection window enable signal upon simultaneously receiving a power supply hold signal and a warm restart flag signal, enabling rapid response when such scenarios occur. A signal control module is connected in series in the hot-plug detection signal path between the host and the external display device. Under the control of the protection window enable signal, the signal control module clamps the hot-plug signal from the external display device, which includes abnormal retry pulses, to a stable preset level. This prevents asynchronous retry pulses automatically emitted by the external display device from being transmitted to the host processor during the critical window period of the host's operating system display driver initialization. This avoids display driver initialization failure caused by the operating system misjudging hot-plug events, improving the success rate and stability of the HDMI display link establishment during the host's warm restart process, eliminating black screen, no signal, and other fault phenomena, and improving device availability.

[0020] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0021] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This paper shows a schematic diagram of the structure of the signal control device for the display interface provided in an embodiment of this application; Figure 2 This paper shows a schematic diagram of the signal control device for the multi-power supply detection module provided in an embodiment of the present application; Figure 3 A flowchart illustrating the signal control method for a display interface provided in an embodiment of this application is shown.

[0022] The reference numerals in the detailed embodiments are as follows: 1. Host computer; 10. Signal control device; 11. Power supply detection module; 12. Reset identification module; 13. Handshake management module; 131. Timing unit; 14. Signal control module; 21. Motherboard; 211. First hot-swappable pin; 22. Display signal interface; 221. Power supply pin; 222. Second hot-swappable pin; 2. External display device. Detailed Implementation

[0023] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein.

[0024] The host often needs to perform a software restart (i.e., a warm restart) while running the operating system. At the same time, the +5V power supply (VCC5) provided by its HDMI interface to the external display device is usually uninterrupted. The external display device will continuously try to handshake with the host and send HPD pulses to the host.

[0025] Under these conditions, the external display device, continuously powered by its internal microcontroller unit (MCU) or internal timing logic circuit, will continuously attempt to handshake with the host. If the external display device fails to detect a valid handshake signal from the host within a preset timeout window (the length of which varies depending on the model and design of the external display device), its internal logic will automatically generate a brief low-level HPD pulse to re-trigger the link establishment process.

[0026] This retry mechanism, initiated autonomously by the external display device, has a pulse timing that is completely asynchronous with the host operating system's startup process. When this automatically generated HPD pulse happens to occur within the time window when the host operating system kernel loads and initializes the display driver, the operating system will incorrectly identify this pulse as a physical event of the external display device being disconnected and then reconnected. This misjudgment will severely interfere with the normal state machine of the display driver initialization, leading to driver configuration disorder or resource allocation errors.

[0027] Based on this, the inventors of this application discovered that this special working condition can be identified, and when the special working condition occurs, the HPD pulse at this time can be clamped to a preset level value to avoid the HPD pulse interfering with the host's soft restart process.

[0028] The signal control device for the display interface provided in this application is widely applicable to various digital display interfaces that employ hot-plug detection mechanisms. Its application scenarios are not limited to specific physical interface forms, but rather apply to any display communication protocol that relies on connection status detection and device capability readout to establish a link.

[0029] Specifically, the display interface can be a traditional interface that uses independent hot-swap detection pins and display data channels, such as the High Definition Multimedia Interface (HDMI interface); it can also be an interface that uses bidirectional communication based on auxiliary channels for connection management, such as DisplayPort and its embedded variant eDP; or it can be a new type of multi-functional interface that realizes display functions through pin function redefinition and protocol negotiation, such as the USB Type-C interface that supports USB-C Alt-Mode.

[0030] Although different interfaces differ in physical layer, electrical standards, and upper-layer protocols, they all contain a core link initialization process: the host detects the access of an external display device by detecting a specific connection status signal (such as HPD for HDMI, HPDIRQ / Status for DP, or CC status and VBUS power supply for USB-C), and then reads the identity and capability data of the external display device through a dedicated configuration channel (such as DDC / AUX CH for HDMI / DP).

[0031] The core of this application lies in managing the most crucial connection status signals at the very beginning of this initialization process, preventing them from causing misleading jumps during system instability phases (early stages of a warm restart). Therefore, this application has broad applicability. For ease of explanation, the most widely used HDMI interface will be used as an example in the specific embodiments of this application for detailed description. However, it should be understood that this is not a limitation on the scope of protection of this application; any display interface based on the same or similar hot-plug detection principle falls within the scope of the technical concept of this application.

[0032] Specifically, Figure 1 A schematic diagram of the signal control device for the display interface provided in an embodiment of this application is shown, as follows: Figure 1The signal control device 10 of a display interface is shown and is installed inside a host 1. The host 1 includes a motherboard 21 and a display signal interface 22, which is used to connect to an external display device 2. The device 10 includes: a power supply detection module 11, which is connected to the power pin 221 of the display signal interface 22. If the host 1 detects that it is supplying power to the external display device 2 through the power pin 221, a power supply holding signal is generated; a reset identification module 12, which is connected to the motherboard 21. If the motherboard 21 is detected to be in a warm restart state, a warm restart flag signal is generated; and a handshake management module. Module 13 is connected to power supply detection module 11 and reset identification module 12 respectively, and is used to generate a protection window enable signal in response to receiving a power supply hold signal and a warm restart flag signal within a first preset time period; Signal control module 14 is connected between the first hot-swap pin 211 of motherboard 21 and the second hot-swap pin 222 of display signal interface 22 and is connected to handshake management module 13. In response to receiving the protection window enable signal, it clamps the level value of the hot-swap signal input to the second hot-swap pin 222 to a preset level value and outputs it to the first hot-swap pin 211.

[0033] In this application, the external display device 2 refers to any device that receives video signals from the host 1 and displays image information through a digital display interface. Its specific form is not limited to traditional desktop monitors or televisions, but encompasses all display terminals with built-in signal processing logic that rely on hot-plug detection mechanisms for link establishment, including but not limited to: home theater projectors and commercial large screens using HDMI interfaces; professional graphics displays and high-performance virtual reality headsets using DisplayPort interfaces; secondary screens for laptops or industrial control panels using embedded eDP interfaces; and portable monitors, tablets, or docking stations that receive display signals via USB-C Alt-Mode. For ease of understanding, the following embodiments will primarily use common HDMI displays as examples.

[0034] The logic function of the signal control device 10 of the display interface can be implemented by a programmable logic device, such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). This application does not limit the specific hardware form of the signal control device 10 of the display interface, and it can be selected according to actual use needs.

[0035] The power supply detection module 11 is a component of the signal control device 10 used to determine the power supply status of the external display device 2. Specifically, the power supply detection module 11 detects whether the host 1 continuously provides a valid +5V voltage to the external display device 2 through the VCC5 power pin 221 of the display signal interface 22 (such as the HDMI interface). If a valid +5V voltage is continuously provided to the external display device 2, a power supply hold signal is generated and sent to the handshake management module 13.

[0036] In implementation, the input of the power supply detection module 11 is connected to the VCC5 pin of the HDMI interface via a resistor divider network. For example, the divider network can be composed of resistors R1 and R2. The VCC5 voltage, after being divided, is connected to the non-inverting input of a voltage comparator with hysteresis characteristics, while the inverting input of the comparator is connected to a stable reference voltage Vref. The output of the comparator passes through a synchronous shaping circuit and finally outputs a digital signal, namely the power supply hold signal. When this signal is high, it indicates that the detected VCC5 voltage has been continuously higher than a preset threshold (e.g., about 4.5V) and has undergone sufficient filtering time (e.g., 50ms), thus determining that the external display device 2 has not been powered off during the restart process of the host 1. The hysteresis voltage of the comparator (e.g., 150-250mV) is designed to effectively filter out slight voltage fluctuations and prevent signal jitter, so as to accurately and reliably confirm the condition that the peripheral device (external display device 2) is continuously powered on from an electrical perspective, avoiding the activation of protection logic in unnecessary situations (such as when the peripheral device is powered off), thereby ensuring the reliability of the signal control device 10.

[0037] The reset identification module 12 is used to distinguish the reset type of host 1 and identify whether the current boot process of host 1 is a cold boot or a warm reboot.

[0038] A cold boot refers to the process of powering on the operating system from a completely powered-off state and starting up; a warm reboot refers to the process of restarting the operating system at the software level, but without cutting off the operating system's motherboard hardware power (including auxiliary power for external devices, such as the +5V pin power supply for the high-definition multimedia interface).

[0039] The input terminal of the reset identification module 12 is connected to the warm restart flag signal on the motherboard 21, such as multiple platform reset and power status signals.

[0040] The warm restart flag signal can be set according to the specific host type 1. For example, in a typical x86 architecture, a motherboard 21 using an Intel chipset can determine the status by sampling the timing relationship of standard signals such as the platform reset signal PLTRST#, the power ready signal PWROK, and the system reset signal SYS_RESET: when PLTRST# generates a valid low pulse, and PWROK and SYS_RESET remain high throughout the pulse, a warm restart can be determined. In ARM-based embedded systems, it is necessary to read the status register of the power management IC or monitor specific GPIO reset flags. The following explanation uses a typical x86 architecture motherboard 21 using an Intel chipset as an example.

[0041] In addition, to deal with incomplete signal situations, the reset identification module 12 can make inferences using combinations of available signals, such as monitoring the PGOOD signal combination of the core power rail to equivalent PWROK state, and combining the SLP_S3# sleep state signal to distinguish other reset types such as warm restart and sleep wake-up.

[0042] In implementation, the reset identification module 12 includes combinational logic and synchronous flip-flops for sampling and judging the timing relationship of the aforementioned input signals. Preferably, when the reset identification module 12 detects that the motherboard 21 is in a warm restart state, it generates a warm restart flag signal, specifically by: sampling the platform reset signal, power ready signal, and system reset signal of the motherboard 21; if it detects that the platform reset signal undergoes a transition from high level to low level and then back to high level, and the power ready signal and system reset signal both remain high during the transition, then it is determined that the motherboard 21 is in a warm restart state, and a warm restart flag signal is generated.

[0043] When the specific timing characteristic of "PLTRST# signal briefly goes low and then quickly returns to high level, while PWROK signal and SYS_RESET signal remain high throughout the process" is detected, the current reset process can be determined to be a warm restart.

[0044] If the user presses the power button of host 1 or unplugs and plugs in the power cord of host 1, causing host 1 to cold start, the PWROK signal will initially be low (because the power is not yet on). Then, after the power is established and a period of time (tens to hundreds of milliseconds) has elapsed, the power circuit confirms that all voltages are stable before pulling PWROK high. Before and after PWROK goes high, the reset circuit starts to work, and PLTRST# will generate a reset pulse that goes from high to low and then back to high. SYS_RESET will also go through a process from low to high.

[0045] When a warm restart is detected during the reset process, the reset identification module 12 outputs a digital signal, namely the warm restart flag signal. When the host 1 is in the warm restart state, the warm restart flag signal is valid (e.g., set high). Subsequently, the warm restart flag signal is sent to the handshake management module 13.

[0046] The handshake management module 13 is connected to the power supply detection module 11 and the reset identification module 12 respectively, and receives the aforementioned power supply hold signal and warm restart flag signal as input.

[0047] When the handshake management module 13 receives the power supply hold signal and the warm restart flag signal, it needs to determine whether these two signals are valid sequentially or simultaneously within a first preset duration. The first preset duration defines the allowed time window for the validity of the two signals, ensuring they correspond to the same startup event. This can be configured internally or set externally, for example, 1 second.

[0048] The handshake management module 13 can be configured to include a timer, a counter, a state machine, and related parameter registers. Preferably, the handshake management module 13 includes a timing unit 131; the timing unit 131 is used to start timing when the protection window enable signal is generated, and to stop timing when the timing duration reaches the preset protection window duration, wherein the protection window enable signal remains valid during the timing period of the timing unit 131.

[0049] When the condition of simultaneously receiving both valid signals within a first preset time period is met, the handshake management module 13 confirms that the target scenario of a warm restart and continuous power-on of peripheral devices has occurred. At this time, the handshake management module 13 starts its internal protection window timer to begin counting and simultaneously sets the output protection window enable signal.

[0050] The protection window enable signal is a pulse signal that is valid for a period of time (its validity period is the protection window duration, for example, 15 seconds by default, which can be adjusted through register configuration) to indicate that the clamping operation of the HPD signal needs to be performed in the subsequent stage.

[0051] The signal control module 14 is connected between the first hot-swappable pin 211 on the motherboard 21 (such as the HPD pin connected to the graphics processing unit or display controller) and the second hot-swappable pin 222 on the display signal interface 22 (such as the HPD pin), and receives control from the protection window enable signal from the handshake management module 13.

[0052] In implementation, the signal control module 14 can be configured as an analog switch chip (such as the Texas Instruments TS5A series) or a tri-state buffer. The control terminal of this structure is connected to the port of the handshake management module 13 that outputs the protection window enable signal, its signal input terminal is connected to the second hot-swap pin 222 (HPD_IN), and its signal output terminal is connected to the first hot-swap pin 211 (HPD_OUT).

[0053] Preferably, the signal control module 14 is further configured to: clamp the level value of the hot-plug signal input to the second hot-plug pin 222 to a preset level value and output it to the first hot-plug pin 211 during the period when the protection window enable signal is valid; and directly transmit the hot-plug signal input to the second hot-plug pin 222 to the first hot-plug pin 211 during the period when the protection window enable signal is invalid.

[0054] The timing unit 131 utilizes the existing reference clock on the motherboard 21 (e.g., a 24MHz or 48MHz crystal oscillator clock source) and generates a timing reference with an accuracy of 1 millisecond (1ms) or less through a frequency divider. When the handshake management module 13 decides to activate protection, the counter inside the timing unit 131 is cleared to zero and begins to accumulate.

[0055] The protection window duration is a configurable parameter stored in the internal registers of the signal control module 14 (such as PROTECT_MS). The default value can be set to 15000 milliseconds (15 seconds), which is sufficient to cover the entire process of operating system kernel loading and display driver initialization.

[0056] During the entire period from zero when the timing unit 131 starts timing until the accumulated time reaches the preset value, the protection window enable signal of the control output of the handshake management module 13 remains valid (e.g., kept high level); once the counter overflows or reaches the preset threshold, the timing unit 131 immediately stops timing and notifies the handshake management module 13 to set the protection window enable signal to invalid (e.g., pull low level).

[0057] By introducing the timing unit 131, the protection action is limited to the necessary time range, which not only ensures the signal stability within the critical initialization window, but also avoids the host 1 being unable to detect real physical plugging and unplugging events due to long-term shielding of the HPD signal, thus ensuring the reliability of the signal control device 10 during use.

[0058] When no valid protection window enable signal is received, the analog switch of the signal control module 14 is in the on or transparent state. At this time, HPD_OUT = HPD_IN, and the hot-plug detection signal is directly and transparently transmitted from the external display device 2 to the host 1, maintaining the normal working mode of the interface. When a valid protection window enable signal is received, the handshake management module 13 controls the analog switch to enter a specific non-transparent working state, and forces the level value of HPD_OUT to a stable preset level value according to the configuration.

[0059] Preferably, the preset level value is a first level value used to indicate to the motherboard 21 that the external display device 2 is in a connected state; or, the preset level value is a second level value used to indicate to the motherboard 21 that the external display device 2 is in a disconnected state.

[0060] For example, a preset level value is set to 1 to indicate that the external display device 2 is connected; or a preset level value is set to 0 to indicate that the external display device 2 is disconnected. In this case, the actual electrical state of the external display device 2 is connected. To prevent the HDP signal of the external display device 2 from interfering with the warm restart process of the host 1, a signal with a preset level value can be input to the first hot-swap pin 211 of the motherboard 21 to conceal the handshake attempt behavior of the external display device 2 from the motherboard 21, which is in an unstable state.

[0061] During the protection window's operation, regardless of how the HPD_IN signal of the external display device 2 changes (e.g., a retry pulse is generated), the HPD_OUT signal observed by the host 1 remains a stable, jitter-free level.

[0062] By directly controlling the level on the hardware signal path, the interference of external asynchronous HPD pulses to host 1 within the protection window is fundamentally blocked, ensuring that the HPD signal received during the initialization of the operating system display driver is stable, thereby avoiding driver initialization errors and subsequent black screen problems.

[0063] If the protection window duration is too short, it will be difficult to fully cover the duration of special operating conditions, which may easily lead to interference with the display driving process of the host 1's operating system; if the protection window duration is too long, the host 1 may ignore the user's normal operation of powering off the external display device 2 or disconnecting the external display device 2 from the host 1, and thus be unable to respond. Therefore, preferably, the handshake management module 13 is also used to: continuously monitor the hot-plug signal from the second hot-plug pin 222 from the moment the warm restart flag signal is received, and record the timestamp of the rising edge event in the monitored hot-plug signal until no new rising edge event is detected within a second preset time period from the last rising edge event, thereby obtaining multiple rising edge timestamps corresponding to this warm restart process; determine the earliest rising edge timestamp and the latest rising edge timestamp from the multiple rising edge timestamps; determine a reference protection duration based on the earliest rising edge timestamp and the latest rising edge timestamp, so as to adjust the protection window duration according to the reference protection duration.

[0064] The handshake management module 13 has the function of continuously monitoring and recording hot-plug signal edge events from the moment it receives the warm restart flag signal. Specifically, when the reset identification module 12 outputs a valid warm restart flag signal and the power supply detection module 11 confirms that the peripheral device is continuously powered on, the high-precision edge detection logic inside the handshake management module 13 is activated.

[0065] The high-precision edge detection logic continuously scans the signal waveform from the second hot-pluggable pin 222 (HPD_IN) based on the time scale of an internal timer (e.g., 1 millisecond). When a transition from low to high level (i.e., a rising edge event) is detected in the HPD signal, the module records the specific timestamp of the event, typically expressed in milliseconds relative to the warm restart time or the start of the protection window.

[0066] The handshake management module 13 also has the function of determining the end time of data acquisition based on the monitored edge activity state, that is, determining whether the external display device 2 has finished retrying by using a second preset duration (e.g., 1 second). During the continuous recording of rising edge timestamps, the handshake management module 13 maintains a silent timer for the last rising edge event. Whenever a new rising edge event is recorded, the silent timer is reset and restarted. If no new rising edge event is detected before the silent timer reaches the preset second preset duration, the handshake management module 13 determines that the external display device 2 has completed all retry attempts in this round, and the operating system has entered a stable period. At this time, the handshake management module 13 stops recording timestamps and locks all collected rising edge timestamp data as a complete behavioral sample of this warm restart process, effectively distinguishing between the continuous retries and the final silent state of the external display device 2, avoiding the risk of missing subsequent retry signals due to the premature end of the protection window, and ensuring data integrity.

[0067] The handshake management module 13 further has the function of calculating a reference protection duration based on the collected timestamp data and adjusting the protection window duration accordingly. After determining the end time of data collection, the handshake management module 13 analyzes the multiple rising edge timestamps stored in the dataset. First, it extracts the earliest rising edge timestamp (TS_First) and the latest rising edge timestamp (TS_Last) from the dataset. Second, by calculating the difference between these two timestamps, it obtains the actual retry active duration of the external display device 2 during this warm restart process. To ensure that the protection window can completely cover the retry behavior of the external display device 2, the handshake management module 13 determines a reference protection duration based on this actual active duration. For example, a certain safety margin (such as increasing by 10% or a fixed increase of 1 second) can be added to the difference between TS_First and TS_Last. Finally, the handshake management module 13 writes the generated reference protection duration as a new configuration value to or updates the protection window duration parameter (t_protect_ms) in the internal storage.

[0068] During the subsequent warm restart process, the handshake management module 13 will directly use this adjusted protection window duration to generate the protection window enable signal, or provide this value to the maintenance personnel of host 1 for reference.

[0069] For example, suppose an external display device of a certain model sends the first HPD retry pulse at the 2nd second after restarting, the second at the 4th second, and the last at the 8th second, after which it enters a silent state. The handshake management module 13 records the above time points, and determines that the activity ends after no new pulse is detected within a second preset duration (e.g., 3 seconds). By calculating (8 seconds - 2 seconds = 6 seconds) and adding a safety margin, the handshake management module 13 automatically calculates the reference protection duration as 8 seconds. Therefore, the handshake management module 13 updates the protection window duration parameter to 8 seconds. In subsequent restarts, the handshake management module 13 will generate a protection window enable signal that lasts for 8 seconds, and the signal control module 14 will stably clamp the HPD signal during these 8 seconds to ensure that all retry pulses of the external display device 2 are blocked, and then quickly restore pass-through after 8 seconds, thereby realizing intelligent adaptation to the response characteristics of different external display devices 2, which greatly improves the convenience of equipment maintenance and operating efficiency in industrial and commercial display scenarios.

[0070] The handshake management module 13 has the function of monitoring HPD signals and recording rising edge timestamps. However, in actual circuit environments, signal transmission links may be affected by electromagnetic interference or line reflections, generating instantaneous short pulses (i.e., glitches). Therefore, in order to prevent non-real interference signals from being mistakenly identified as valid retry behavior of the external display device 2, thereby leading to errors in the calculation of the reference protection duration, preferably, when the handshake management module 13 records the timestamp of the rising edge event in the monitored hot-plug signal, it specifically performs the following: when the rising edge of the hot-plug signal is detected, it times the detected rising edge to obtain the pulse width duration; if the pulse width duration is greater than or equal to a preset dejittering time threshold, the detected rising edge of the hot-plug signal is determined as a valid rising edge, and the timestamp of the valid rising edge is recorded.

[0071] The above method introduces pulse width verification-based dejitter logic in the handshake management module 13. This logic accurately identifies real physical connection events by measuring the duration of the rising edge of the HPD signal (pulse width duration) and comparing it with a preset dejitter time threshold (such as 50ms).

[0072] When the handshake management module 13 detects the rising edge of the hot-plug signal, it immediately starts timing the rising edge to obtain the pulse width duration. Specifically, the handshake management module 13 internally includes a counter or timer unit driven by a high-frequency clock. This unit continuously samples the signal from the second hot-plug pin 222 (HPD_IN). When the signal level changes from low to high (i.e., the rising edge event) is detected, the counter is triggered and begins to accumulate a count value. This timing process continuously monitors the duration of the high level until the signal level flips to low or reaches the maximum measurement range. The resulting count value, after conversion, yields the pulse width duration corresponding to the rising edge, i.e., the duration of the high-level pulse.

[0073] In practice, this can be achieved by establishing edge detection logic and pulse width measurement logic circuits inside the CPLD or FPGA.

[0074] The handshake management module 13 is further used to compare the measured pulse width duration with the preset de-jitter time threshold to determine whether the rising edge is a valid rising edge.

[0075] The register group of the handshake management module 13 stores a dejittering time threshold parameter. This threshold is an empirical value set based on the electrical characteristics of the display interface and the duration of common noise interference. The comparison logic circuit inside the handshake management module 13 compares the pulse width duration measured in real time with this threshold. Specifically, the judgment logic is as follows: if the detected pulse width duration is greater than or equal to the preset dejittering time threshold, the rising edge is determined to be a stable and real signal transition, i.e., it is determined to be a valid rising edge; conversely, if the pulse width duration is less than the threshold, the rising edge is determined to be a transient glitch caused by external interference and is not processed as a valid event. Through rigorous pulse width verification, high-frequency noise and short pulse interference are filtered out at the source, avoiding false triggering caused by interference signals, and greatly improving the accuracy and robustness of the system's HPD behavior recognition of the external display device 2.

[0076] The handshake management module 13 is also used to record the timestamp of the valid rising edge after determining that the rising edge is a valid rising edge. The handshake management module 13 will only trigger a register write operation when the comparison logic confirms that the pulse width duration meets the debouncing condition, writing the current time value (usually the number of milliseconds relative to the start of the protection window or the system startup time) to the corresponding timestamp register (such as TS_First or TS_Last). If the comparison determines that the rising edge is invalid (i.e., the pulse width is too short), the handshake management module 13 will ignore the event, not update any timestamp registers, and not increase the edge count, thereby further improving the accuracy of the compatibility adaptation of the signal control device 10 with different models of external display devices 2, and eliminating the protection window duration setting deviation caused by noise interference.

[0077] In this embodiment of the application, in addition to determining the reference protection duration by detecting the rising edge of the hot-plug signal, the reference protection duration can also be determined by detecting the falling edge of the hot-plug signal. The determination of the reference protection duration by detecting the falling edge of the hot-plug signal, as well as the determination of the effective falling edge in the hot-plug signal, can be referred to the above description of the implementation process of the rising edge, and will not be repeated here.

[0078] Furthermore, the signal control device 10 also includes an optional configuration and log interface module to enhance the debuggability and maintainability of the signal control device 10.

[0079] The optional configuration and log interface module connects to the internal integrated circuit or system management bus signal of the motherboard 21. This module enables register address decoding and read / write interfaces. For example, it can write parameters to configuration registers such as the PROTECT_MS protection window duration parameter register, DEBOUNCE_MS debouncing time threshold register, and MODE protection mode configuration register within the handshake management module 13. This allows for flexible setting of the protection window duration, debouncing threshold, and operating mode according to actual needs. Simultaneously, this module can read jitter statistics from registers such as the EDGE_CNT valid HPD edge count register, TS_FIRST first valid edge timestamp register, and TS_LAST last valid edge timestamp register. This provides a programmable entry point for protection window parameters and debouncing thresholds, enabling engineers to perform parameterized configuration based on the response characteristics of different display devices without modifying the operating system or BIOS firmware code. Furthermore, it provides a unified access method for production debugging and after-sales maintenance.

[0080] In addition, the signal control device 10 provided in this application embodiment is also used for safe rollback and abnormal handling, so as to ensure that the operating system can still be displayed when the signal control device 10 itself malfunctions.

[0081] The signal control device 10 connects an analog switch or tri-state buffer U1 in series between HPD_IN and HPD_OUT. The control terminal of U1 is driven by the BYPASS_EN signal output by the handshake management module 13. The hardware default state of U1 is set to bypass through a pull-up or pull-down resistor so that HPD_IN and HPD_OUT are directly connected when the signal control device 10 is not powered on, is in the reset / reconfiguration stage, or the BYPASS_EN signal is not effectively driven.

[0082] Once the signal control device 10 is powered on, configured, and enters normal operating mode, it controls U1 and its internal logic according to the protection window enable signal. If the internal watchdog detects an anomaly (such as prolonged lack of clock signal or state machine freeze), it triggers a self-reset and releases BYPASS_EN to the default level during the reset, returning U1 to the bypass pass-through state. Even if the handshake management module 13 experiences a logic anomaly or deadlock, the HPD signal can still be transmitted to the host 1 through the hardware bypass path, avoiding prolonged black screen due to policy circuit failure and ensuring the operating system's safe rollback capability and basic availability.

[0083] Furthermore, the electromagnetic interference and electrical tolerance of the signal control device 10 can be designed to improve its anti-interference capability and mass production consistency. The signal control device 10 incorporates electrostatic discharge protection devices at the HPD_IN and HPD_OUT pins to meet electrostatic and surge protection requirements. The level shifting devices selected in the signal path strictly meet the HDMI specification requirements for input threshold and output swing. In addition, the VCC5 comparator in the power supply detection module 11 is equipped with a hysteresis voltage of approximately 150 to 250 millivolts to prevent repeated jitter in the output signal due to slight voltage fluctuations. In the printed circuit board design, traces are routed according to differential-mode or common-mode interference control specifications, and small-value resistors are connected in series in the HPD signal path when necessary to suppress overshoot. Through these multi-layered electrical protection measures, the anti-interference capability and electrical safety of the signal control device 10 are improved, ensuring the consistency and mass production controllability of the signal control device 10 in complex electromagnetic environments.

[0084] like Figure 2 As shown, preferably, the host 1 includes multiple display signal interfaces 22, and multiple power supply detection modules 11 are connected one-to-one with the multiple display signal interfaces 22. Each power supply detection module 11 is used to detect the power supply status of the display signal interface 22 corresponding to it and generate a power supply hold signal. The handshake management module 13 is connected to the multiple power supply detection modules 11 and is used to generate a protection window enable signal corresponding to the target display signal interface 22 in response to receiving the power supply hold signal and the warm restart flag signal corresponding to the target display signal interface 22. The signal control module 14 is used to connect between the first hot-swap pin 211 of the motherboard 21 and the second hot-swap pin 222 of each display signal interface 22. In response to receiving the protection window enable signal corresponding to the target display signal interface 22, it clamps the level value of the hot-swap signal input to the second hot-swap pin 222 of the target display signal interface 22 to a preset level value and outputs it to the first hot-swap pin 211.

[0085] The interface types of the multiple display signal interfaces 22 can be the same or different. For example, they can all be HDMI interfaces, or they can be HDMI interfaces and DP interfaces respectively.

[0086] The motherboard 21 has multiple display signal interfaces 22, each with an independent VCC5 power pin 221. Correspondingly, the signal control device 10 includes multiple power supply detection modules 11. The input of each power supply detection module 11 is connected to the power pin 221 of its corresponding display signal interface 22, for real-time monitoring of the VCC5 voltage of that specific port. When the host 1 restarts, if an external display is connected to a port and the display remains powered on, the corresponding power supply detection module 11 generates and outputs a valid power supply hold signal. For example, if the external display connected to port A is not powered off, the power supply detection module 111 outputs a high-level signal; while if port B is not connected to a display or is powered off, the power supply detection module 112 outputs a low-level signal.

[0087] The handshake management module 13 is connected to multiple power supply detection modules 11, and is responsible for coordinating the protection logic of all ports and generating control signals for specific ports. The handshake management module 13 also receives a warm restart flag signal from the reset identification module 12 and power supply hold signals from each power supply detection module 11.

[0088] The handshake management module 13 can adopt an instantiation design indexed by port number (PORT_ID), that is, maintaining an independent logic judgment unit and state machine for each port. Specifically, for a specific target port (e.g., port A), the handshake management module 13 will only generate the protection window enable signal corresponding to the target display signal interface 22 when it simultaneously receives a globally valid warm restart flag signal and the power supply hold signal corresponding to port A. If other ports (e.g., port B) do not meet the power supply hold conditions, the handshake management module 13 will not generate a protection window enable signal for port B, even if port A is within the protection window.

[0089] The signal control module 14 is connected between the first hot-swappable pin 211 of the motherboard 21 and the second hot-swappable pin 222 of each display signal interface 22, and performs independent signal clamping operations. In actual hardware circuits, it can be designed to configure an independent signal path control unit for each port inside the CPLD or FPGA, or it can be implemented using an integrated multi-channel analog switch array.

[0090] The signal control module 14 is connected to the handshake management module 13. In response to receiving a protection window enable signal corresponding to the target display signal interface 22, it performs an operation on that specific port, clamping the level of the hot-plug signal input to the second hot-plug pin 222 of the target display signal interface 22 to a preset level and outputting it to the first hot-plug pin 211 of the motherboard 21 corresponding to the target display signal interface 22. Simultaneously, for other ports that have not received the corresponding protection window enable signal, the signal control module 14 maintains a transparent pass-through state for its signal path (or operates independently according to its own state). Even if port A is performing HPD signal clamping protection, the HPD signal of port B can still be transparently transmitted to the host 1 in real time without interference, thus realizing the multi-port parallel processing capability of the signal control device 10.

[0091] According to another aspect of the embodiments of this application, a host 1 is also provided, which includes a signal control device 10 for the display interface as described in any of the above embodiments.

[0092] This application embodiment uses a power supply detection module 11 and a reset identification module 12 to accurately identify scenarios where the host 1 undergoes a warm restart and the external display device continues to be powered. The handshake management module 13 generates a protection window enable signal when simultaneously receiving a power supply hold signal and a warm restart flag signal, enabling a rapid response when the host 1 undergoes a warm restart and the external display device continues to be powered. A signal control module 14 is connected in series in the hot-plug detection signal path between the host 1 and the external display device 2. Under the control of the protection window enable signal, the signal control module 14 clamps the hot-plug signal from the external display device 2, which includes abnormal retry pulses, to a stable preset level. This prevents asynchronous retry pulses automatically emitted by the external display device 2 from being transmitted to the host 1's processor during the critical window period of the host 1's operating system display driver initialization. This avoids display driver initialization failure caused by the operating system misjudging hot-plug events, improves the success rate and stability of establishing the HDMI display link during the host 1's warm restart process, eliminates black screen and no signal malfunctions, and improves device availability.

[0093] Figure 3 A flowchart illustrating the signal control method for the display interface provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 3This application also provides a signal control method for a display interface, applied to the signal control device 10 of the display interface as described in any of the above embodiments. The method includes: S310, detecting whether the host 1 supplies power to the external display device 2 through the power pin 221; S320, identifying whether the motherboard 21 is in a warm restart state; S330, if it is detected that the host 1 supplies power to the external display device 2 through the power pin 221 and the motherboard 21 is identified as being in a warm restart state, then the level value of the hot-plug signal input to the second hot-plug pin 222 of the display signal interface 22 is clamped to a preset level value and output to the first hot-plug pin 211 of the motherboard 21.

[0094] In the several embodiments provided in this application, any function, if implemented as a software functional module / unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of this application can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or other electronic device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0095] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, the embodiments of this application are not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0096] It should be noted that the above embodiments are illustrative of this application and not restrictive, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In claims enumerating several means, several units or modules of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

[0097] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A signal control device for a display interface, characterized in that, The device is installed inside a host computer, the host computer including a motherboard and a display signal interface, the display signal interface being used to connect to an external display device; the device includes: A power supply detection module is used to connect to the power pin of the display signal interface. If it is detected that the host is supplying power to the external display device through the power pin, a power supply hold signal is generated. A reset identification module is used to connect to the motherboard. If the motherboard is detected to be in a warm restart state, a warm restart flag signal is generated. The handshake management module is connected to the power supply detection module and the reset identification module respectively, and is used to generate a protection window enable signal in response to receiving the power supply hold signal and the warm restart flag signal within a first preset time period; A signal control module is used to connect between the first hot-swappable pin of the motherboard and the second hot-swappable pin of the display signal interface and to the handshake management module. In response to receiving the protection window enable signal, the module clamps the level value of the hot-swappable signal input to the second hot-swappable pin to a preset level value and outputs it to the first hot-swappable pin.

2. The apparatus according to claim 1, characterized in that, The handshake management module includes a timing unit; the timing unit is used to start timing when the protection window enable signal is generated, and to stop timing when the timing duration reaches the preset protection window duration, wherein the protection window enable signal remains valid during the timing period of the timing unit; The signal control module is also used for: During the period when the protection window enable signal is active, the level value of the hot-plug signal input to the second hot-plug pin is clamped to the preset level value and output to the first hot-plug pin; During the period when the protection window enable signal is invalid, the hot-plug signal input from the second hot-plug pin is directly transmitted to the first hot-plug pin.

3. The apparatus according to claim 2, characterized in that, The handshake management module is also used for: Starting from the receipt of the warm restart flag signal, continuously monitor the hot-plug signal from the second hot-plug pin and record the timestamp of the rising edge event in the monitored hot-plug signal until no new rising edge event is detected within a second preset time period from the last rising edge event, and obtain multiple rising edge timestamps corresponding to this warm restart process. The earliest and latest rising edge timestamps are determined from the plurality of rising edge timestamps. A reference protection duration is determined based on the earliest rising edge timestamp and the latest rising edge timestamp, and the protection window duration is adjusted accordingly.

4. The apparatus according to claim 3, characterized in that, When the handshake management module records the timestamp of the rising edge event in the monitored hot-plug signal, it is specifically used for: When the rising edge of the hot-plug signal is detected, the detected rising edge is timed to obtain the pulse width duration; If the pulse width duration is greater than or equal to the preset debouncing time threshold, the rising edge of the hot-plug signal is determined as a valid rising edge, and the timestamp of the valid rising edge is recorded.

5. The apparatus according to claim 1, characterized in that, The host includes multiple display signal interfaces, and there are multiple power supply detection modules, which are connected one-to-one with the multiple display signal interfaces. Each power supply detection module is used to detect the power supply status of the display signal interface corresponding to the power supply detection module and generate a power supply hold signal. The handshake management module is connected to multiple power supply detection modules and is used to generate a protection window enable signal corresponding to the target display signal interface in response to receiving the power supply hold signal and the warm restart flag signal corresponding to the target display signal interface. The signal control module is used to connect between the first hot-swappable pin of the motherboard and the second hot-swappable pin of each display signal interface. In response to receiving the protection window enable signal corresponding to the target display signal interface, the module clamps the level value of the hot-swappable signal input to the second hot-swappable pin of the target display signal interface to a preset level value and outputs it to the first hot-swappable pin.

6. The apparatus according to claim 1, characterized in that, The reset recognition module is used to generate a warm restart flag signal if it detects that the motherboard is in a warm restart state. Specifically, it is used for: The platform reset signal, power-ready signal, and system reset signal of the motherboard are sampled. If the platform reset signal is detected to undergo a transition from high level to low level and then back to high level, and both the power ready signal and the system reset signal remain at high level during the transition, then the motherboard is determined to be in a warm restart state, and a warm restart flag signal is generated.

7. The apparatus according to claim 1, characterized in that, The preset level value is a first level value used to indicate to the motherboard that the external display device is in a connected state; or, the preset level value is a second level value used to indicate to the motherboard that the external display device is in a disconnected state.

8. The apparatus according to claim 1, characterized in that, The display signal interface is a high-definition multimedia interface.

9. A host computer, characterized in that, The host computer includes a signal control device for the display interface as described in any one of claims 1 to 8.

10. A signal control method for a display interface, characterized in that, The method, applied to a signal control device for a display interface as described in any one of claims 1 to 8, comprises: Detect whether the host is supplying power to the external display device through the power pin; Identify whether the motherboard is in a warm restart state; If it is detected that the host is supplying power to the external display device through the power pin, and the motherboard is identified as being in a warm restart state, the level value of the hot-plug signal input to the second hot-plug pin of the display signal interface is clamped to a preset level value and output to the first hot-plug pin of the motherboard.

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