Instruction processing device, instruction processing method, and related product

Abstract

The present disclosure discloses an instruction processing device, an instruction processing method and related products, including an integrated circuit device, a board card and a computer readable storage medium. The method can be included in a combined processing device, which can include a computing device, an interface device, a processing device and a storage device. The technical solution of the present disclosure can process based on the type of instructions to be processed, which is more conducive to software personnel to directly intervene in the decoding behavior of instruction disassembly.

Description

Technical Field

[0001] This disclosure generally relates to the field of computer technology. More specifically, this disclosure relates to an instruction processing apparatus, an instruction processing method, and related products. Background Technology

[0002] With the continuous development of artificial intelligence technology, artificial intelligence processors have received widespread attention in recent years. Among them, application-specific integrated circuits (ASICs) such as neural network processing units (NPUs) and tensor processing units (TPUs) have developed rapidly.

[0003] Instructions serve as the interface between computer software and hardware, forming a crucial part of the computer system architecture. When processing complex instructions such as convolution and pooling instructions, application-specific integrated circuits (ASICs) require dedicated decoding modules within the chip to break down each complex instruction into sub-instructions of a scale that downstream modules can process. However, this breakdown significantly impacts the performance and flexibility of complex instructions, and software engineers have no control over this process. When the hardware decoding process fails to meet expectations or encounters problems, it cannot be adjusted through software. Summary of the Invention

[0004] In order to at least address one or more of the technical problems mentioned above, this disclosure provides, in various aspects, an instruction processing apparatus, an instruction processing method, an integrated circuit apparatus, a circuit board, and a computer-readable storage medium.

[0005] In a first aspect, this disclosure provides an instruction processing apparatus, comprising: a microinstruction processing module, a data reading module, an arithmetic module, a data writing module, and a storage module. The microinstruction processing module is configured to process the instruction and send it to the data reading module, the arithmetic module, and the data writing module based on the type of the instruction to be processed; the data reading module is configured to send read data to the arithmetic module; the arithmetic module is configured to perform arithmetic on the received data to obtain an execution result; and the data writing module is configured to write the execution result into the storage module.

[0006] In a second aspect, this disclosure provides an integrated circuit apparatus including the instruction processing apparatus of the first aspect.

[0007] In a third aspect, this disclosure provides a board that includes the integrated circuit device of the second aspect mentioned above.

[0008] In the fourth aspect, this disclosure provides an instruction processing method, comprising: processing the instruction and sending it to a data reading module, an arithmetic module and a data writing module based on the type of the instruction to be processed; sending the read data to the arithmetic module; performing an arithmetic operation on the received data to obtain an execution result; and writing the execution result into the storage module.

[0009] In a fifth aspect, this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when run by one or more processing devices, executes the instruction processing method of the fourth aspect described above.

[0010] Through the instruction processing apparatus provided above, the embodiments disclosed herein can, through the microinstruction processing module, process the instructions based on the type of the instruction to be processed and send the processed instructions to the downstream data reading module, arithmetic module, and data writing module for corresponding subsequent processing. Compared to the prior art, where application-specific integrated circuits (ASICs) employ complex instructions that require decomposition into sub-instructions of a predetermined format according to hardware configuration, the processing based on the type of instruction to be processed in this disclosure is more conducive to software personnel directly intervening in the decoding behavior of instruction decomposition. Attached Figure Description

[0011] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0012] Figure 1 A schematic diagram of convolution instructions in the prior art is shown;

[0013] Figure 2 A schematic diagram of the structure of an instruction processing device in the prior art is shown;

[0014] Figure 3 A schematic diagram of the format of a microinstruction according to an embodiment of this disclosure is shown;

[0015] Figure 4 A schematic diagram of an instruction set comprising a microinstruction sequence according to an embodiment of this disclosure is shown;

[0016] Figure 5 A schematic diagram of an instruction set comprising a microinstruction sequence according to yet another embodiment of this disclosure is shown;

[0017] Figure 6 A schematic diagram of the structure of an instruction processing apparatus according to an embodiment of the present disclosure is shown;

[0018] Figure 7A schematic diagram illustrating instruction sequence optimization according to an embodiment of this disclosure is shown;

[0019] Figure 8 An exemplary flowchart of an instruction processing method according to an embodiment of this disclosure is shown;

[0020] Figure 9 A schematic diagram of the structure of a board 90 according to an embodiment of this disclosure is shown;

[0021] Figure 10 A structural diagram of the combined processing device 10 in chip 901 of this embodiment is shown; Detailed Implementation

[0022] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0023] It should be understood that the terms "first," "second," "third," and "fourth," etc., that may be used in the claims, specification, and drawings of this disclosure are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0024] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0026] To clearly understand the technical solution disclosed herein, the existing technical solutions will first be described in detail.

[0027] With the continuous development of artificial intelligence technology, artificial intelligence processors have received widespread attention in recent years. Among them, application-specific integrated circuits (ASICs) such as neural network processing units (NPUs) and tensor processing units (TPUs) have developed rapidly.

[0028] Instructions are the interface between computer software and hardware, and a crucial part of the computer system architecture. Instructions can be categorized into reduced instructions and complex instructions. Reduced instructions are characterized by simple single-instruction functionality and fast execution speed. Complex instructions are characterized by powerful and complex single-instruction functionality, and typically have a longer instruction length. Application-Specific Integrated Circuits (ASICs) often employ complex instructions.

[0029] An instruction consists of an opcode and an operation field. The opcode indicates the function that the instruction is to perform, while the operation field describes the object on which the instruction operates. For example, the operation field includes the source address and the destination address, and may also include one or more of the following as needed: operation parameters, data size, data type, etc.

[0030] Figure 1 This is a schematic diagram of convolution instructions in existing technology. Convolution instructions are a common type of complex instruction. For example... Figure 1 As shown, the opcode for the convolution instruction, name = conv, indicates that the instruction performs a convolution operation. The operation domain of the convolution instruction can include neuron_addr, synapse_addr, dst_addr, wo, ho, co, wi, hi, ci, kw, kh, sw, and sh. Specifically, the source addresses neuron_addr and synapse_addr represent the storage addresses of the objects operated on by the instruction (i.e., the neuron address and weight address), the target address dst_addr represents the address where the result of the instruction operation is written (i.e., the storage address of the convolution operation result), and wo, ho, co, wi, hi, ci, kw, kh, sw, and sh represent some parameters in the convolution operation. Figure 1 The ellipsis in the text indicates that other contents of the operation field of the convolution instruction can also be included.

[0031] Due to hardware design limitations, the vectors or matrices in the operands or results of computation instructions are generally of fixed size. However, the data size for processing actual tasks is arbitrary. Therefore, it is necessary to first break down the data to be processed into fixed-size data and corresponding operations that the hardware can perform before executing the operation.

[0032] In intelligent processors such as application-specific integrated circuits (ASICs), a dedicated decoding module is required when processing complex instructions such as convolution and pooling instructions. For example... Figure 2 As shown, a traditional instruction processing device includes a decoding module 201, a data reading module 202, an arithmetic module 203, a data writing module 204, and a storage module 205. After a complex instruction is input, the decoding module 201 breaks down the received complex instruction into several sub-instructions according to a predetermined instruction format and distributes the sub-instructions to the data reading module 202, the arithmetic module 203, and the data writing module 204. The sub-instructions include a read sub-instruction `sop_read`, an arithmetic sub-instruction `sop_compute`, and a write sub-instruction `sop_write`. The data reading module 202 receives the read sub-instruction, reads data from the storage module 205 according to the read sub-instruction, and inputs the read data to the arithmetic module 203. The arithmetic module 203 receives the arithmetic sub-instruction, executes the corresponding arithmetic sub-instruction on the received data to obtain the execution result, and outputs the execution result to the data writing module 204. The data writing module 204 receives the write sub-instruction and writes the execution result back to the storage module 205 according to the write sub-instruction. Due to the limitations of the instruction processing unit's hardware architecture design, the decoding module 201 needs to break down complex instructions into sub-instructions according to a predetermined instruction format. However, because it heavily relies on the hardware architecture design of the instruction processing unit, this breakdown behavior severely affects the performance and flexibility of complex instructions, and software engineers cannot control the breakdown behavior. When the instruction decoding process in hardware does not meet expectations or has problems, it cannot be adjusted through software.

[0033] Through research, the inventors discovered that they could creatively define the format of microinstructions, construct instructions in the form of microinstruction sequences, and process the instructions through a microinstruction processing module to break through the bottlenecks of traditional technology.

[0034] In view of this, the present disclosure provides an instruction processing device that, through a microinstruction processing module, processes instructions based on the type of the instruction to be processed and sends the processed instructions to downstream data reading modules, arithmetic modules, and data writing modules for corresponding subsequent processing. Compared to the prior art, where Application-Specific Integrated Circuits (ASICs) employ complex instructions that require decomposition into sub-instructions of a predetermined format according to hardware configuration, the present disclosure processes instructions based on their type, which is more conducive to software engineers directly intervening in the instruction decomposition and decoding process.

[0035] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0036] Unlike existing technologies that break down complex instructions into sub-instructions through decoding modules, this disclosure creatively defines the format of micro-instructions, which constitute instructions in the form of micro-instruction sequences.

[0037] As an example, Figure 3 Specific schematic diagrams of the format of some microinstructions according to embodiments of this disclosure are shown.

[0038] The read microinstruction `uop_read` includes the data read address `addr` and the data size `size`. It can also include data processing functions, such as `in_dtype` and `out_dtype`, which determine the data type conversion of the read data. Of course, depending on the operational needs, the read microinstruction can also include other data processing functions, such as data sorting, data filtering, and other data preprocessing functions.

[0039] The arithmetic microinstruction uop_compute includes the operation type op and the data size size. The operation type op determines the type of operation, such as addition, subtraction, comparison, etc.

[0040] The write microinstruction `uop_write` includes the data write address `addr` and the size of the data to be written `size`. Similar to the read microinstruction, the write microinstruction can also include data processing functions, such as `in_dtype` and `out_dtype` determining the data type conversion of the written data; and, depending on the operational needs, the write microinstruction can also include other data processing functions, such as data sorting, data filtering, etc.

[0041] Based on the above microinstruction format definition, microinstructions can be directly concatenated into a microinstruction sequence to form an instruction. For example... Figure 4 An example is shown of an instruction consisting of a sequence of microinstructions, which includes N read microinstructions uop_read, N operation microinstructions uop_compute, and N write microinstructions uop_write, where N is an integer greater than or equal to 1.

[0042] It should be noted that the data for computation comes from the data read. Therefore, the total amount of computation data for several operation micro-instructions uop_compute, the amount of data written out for several write micro-instructions uop_write, and the amount of data read out for several read micro-instructions uop_read need to match. However, the number of read micro-instructions uop_read, operation micro-instructions uop_compute, and write micro-instructions uop_write in the micro-instruction sequence that constitutes the instruction does not need to be consistent.

[0043] As an example, Figure 5 A schematic diagram illustrates the use of microinstruction sequences with mixed operations to implement complex computational operations. For example... Figure 5 As shown, the example instruction uses only one read microinstruction `uop_read` and one write microinstruction `uop_write`, both with a data size of 512. However, this instruction uses four arithmetic microinstructions `uop_compute`, each with a data size of 128. These four arithmetic microinstructions perform different operation types (`op`), namely multiplication (`mult`), addition (`add`), subtraction (`sub`), and division (`div`), thus enabling four different operations to be performed on a data size of 512. Therefore, the microinstruction sequence operation is very flexible, requiring only that the total data size of the read, write, and arithmetic microinstructions be consistent.

[0044] Normally, the sub-instruction design within hardware is invisible to software, and software cannot intervene in or adjust hardware decoding. This disclosed embodiment employs direct concatenation of microinstructions; instructions composed of microinstruction sequences allow software to directly control the execution of the hardware microarchitecture.

[0045] Figure 6 A schematic diagram of an instruction processing apparatus according to an embodiment of this disclosure is shown. Figure 6 As shown, the instruction processing device includes: a microinstruction processing module 600, a data reading module 602, an arithmetic module 603, a data writing module 604, and a storage module 605.

[0046] The micro-instruction processing module 600 is used to process the instruction and send it to the data reading module 602, the arithmetic module 603 and the data writing module 604 based on the type of instruction to be processed; the data reading module 602 is used to send the read data to the arithmetic module 603; the arithmetic module 603 is used to perform arithmetic on the received data and obtain the execution result; the data writing module 604 is used to write the execution result to the storage module 605.

[0047] The instruction processing apparatus provided in this disclosure can, through a micro-instruction processing module, process instructions based on the type of instruction to be processed and send the processed instructions to downstream data reading modules, arithmetic modules, and data writing modules for corresponding subsequent processing. Compared to the prior art, where application-specific integrated circuits (ASICs) employ complex instructions that require decomposition into sub-instructions of a predetermined format according to hardware configuration, this disclosure, which processes instructions based on their type, allows software engineers to directly intervene in the instruction decomposition and decoding process.

[0048] In some embodiments, the microinstruction processing module 600 is used to determine the type of instruction to be processed; in response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module 602, the calculation module 603, and the data writing module 604. The microinstructions may include the read microinstruction uop_read, the calculation microinstruction uop_compute, and the write microinstruction uop_write.

[0049] As described above, microinstructions can be directly concatenated into a microinstruction sequence to form an instruction. Therefore, when the microinstruction processing module 600 determines that the instruction to be processed is an instruction composed of a microinstruction sequence, it can simply break the microinstruction sequence into multiple microinstructions and directly send the corresponding type of microinstruction to the downstream data reading module 602, the arithmetic module 603, and the data writing module 604 for subsequent processing.

[0050] Specifically, the data reading module 602 receives a read micro-instruction, reads data from the storage module 605 according to the read micro-instruction, and sends the read data to the arithmetic module 603; the arithmetic module 603 receives an arithmetic micro-instruction, executes the corresponding arithmetic micro-instruction on the received data to obtain the execution result, and outputs the execution result to the data writing module 604; the data writing module 604 receives a write micro-instruction and writes the execution result into the storage module 605 according to the write micro-instruction.

[0051] Traditional instruction processing techniques for intelligent processors such as application-specific integrated circuits (ASICs) directly handle complex instructions, requiring a decoding module to analyze instruction parameters and the scale of data to be processed, resulting in a complex decomposition process. However, the embodiment disclosed in this paper employs a microinstruction processing module. When encountering an instruction consisting of a sequence of microinstructions, it breaks down the sequence into several microinstructions and distributes them to the data reading module, the arithmetic module, and the data writing module for subsequent processing, eliminating the need for the complex processing required by traditional decoding modules.

[0052] Within complex instruction sets, different instructions are used at varying frequencies. Statistics show that the 20% most frequently used complex instructions can account for up to 80% of all usage. Therefore, in some use cases, frequently used complex instructions can be replaced with instructions composed of the microinstruction sequences described earlier, while infrequently used complex instructions are left unreplaced.

[0053] In some other embodiments, the instruction processing apparatus further includes a decoding module 601. In response to determining that the instruction to be processed is a complex instruction, the microinstruction processing module 600 sends the complex instruction to the decoding module 601 for processing. The decoding module 601 receives the complex instruction, decomposes it into several sub-instructions according to a predetermined instruction format, and distributes them to the data reading module 602, the computation module 603, and the data writing module 604. The sub-instructions include a read sub-instruction `sop_read`, a computation sub-instruction `sop_compute`, and a write sub-instruction `sop_write`.

[0054] The decoding module analyzes the parameters of complex instructions and the scale of data to be processed, and performs targeted decoding. Due to hardware architecture design limitations, the data to be processed is broken down into fixed-scale data and corresponding operations that the hardware can perform. Therefore, it needs to be broken down into multiple sub-instructions according to a predetermined instruction format. The predetermined instruction format is determined by the hardware architecture design, and this disclosure does not impose any restrictive provisions.

[0055] Specifically, the data reading module 602 also receives a read sub-instruction, reads data from the storage module 605 according to the read sub-instruction, and sends the read data to the calculation module 603; the calculation module 603 also receives a calculation sub-instruction, executes the corresponding calculation sub-instruction on the received data to obtain the execution result, and outputs the execution result to the data writing module 604; the data writing module 604 also receives a write sub-instruction, and writes the execution result into the storage module 605 according to the write sub-instruction.

[0056] It should be noted that microinstructions and subinstructions are units at a smaller level than instructions, and both can be received and executed by downstream modules of the corresponding category. For example, the data reading module 602 can receive read microinstructions and read subinstructions, and can input the read data to the arithmetic module 603; the arithmetic module 603 can receive arithmetic microinstructions and arithmetic subinstructions, and can perform corresponding operations on the received data; the data writing module 604 can receive write microinstructions and write subinstructions, and can write the operation results to the storage module. Microinstructions are a creative definition in this disclosure, and can constitute instructions in the form of microinstruction sequences, while subinstructions are obtained by decomposing complex instructions through a decoding module. The two are also distinguished by their naming conventions.

[0057] Figure 7 A schematic diagram illustrating instruction sequence optimization according to one embodiment of this disclosure is shown. Figure 7As shown, an instruction sequence consisting of three instructions is illustrated. The left column represents the instruction sequence for verification analysis, including instruction 1, instruction 2, and instruction 3. When the software analyzes the execution results of this instruction sequence, it is found that the decoding scheme of instruction 2 leads to unexpected or problematic results such as incorrect output, low performance, and poor power consumption; that is, instruction 2 is deemed unsatisfactory. In this case, it is possible to consider writing a new microinstruction sequence to construct instruction 2, replacing instruction 2 in the original instruction sequence. The replaced instruction sequence is shown below. Figure 3 As shown in the column on the right.

[0058] The instruction design disclosed herein provides software engineers with greater flexibility in operating hardware, reducing the impact of erroneous hardware decoding schemes. Traditional decoding schemes, once the hardware architecture is determined, cannot be modified later. However, with the instruction design of this disclosed embodiment, when the hardware decoding scheme for one or more instructions does not meet expectations or has problems, software developers have the opportunity to bypass the unsatisfactory instructions and replace the traditional scheme by writing their own microinstruction sequences to construct new instructions.

[0059] Figure 8 An exemplary flowchart of an instruction processing method according to an embodiment of this disclosure is shown. The instruction processing method 800 may, for example, be... Figure 6 This is achieved through an instruction processing device.

[0060] like Figure 8 As shown, the instruction processing method includes:

[0061] Step S810: Based on the type of instruction to be processed, the micro-instruction processing module processes the instruction and sends it to the data reading module, the calculation module, and the data writing module.

[0062] Step S820: Send the read data to the computing module;

[0063] Step S830: Perform a calculation on the received data to obtain the execution result; and

[0064] Step S840: Write the execution result into the storage module.

[0065] The instruction processing method provided in this disclosure can, through a micro-instruction processing module, process instructions based on the type of instruction to be processed and send the processed instructions to downstream data reading, arithmetic, and data writing modules for corresponding subsequent processing. Compared to the prior art, where application-specific integrated circuits (ASICs) use complex instructions that need to be decomposed into sub-instructions of a predetermined format according to hardware configuration, this disclosure processes instructions based on their type, which is more conducive to software engineers directly intervening in the decoding process of instruction decomposition.

[0066] In some embodiments, step S810 further includes:

[0067] Determine the type of instruction to be processed;

[0068] In response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module, the arithmetic module and the data writing module. The microinstructions include read microinstructions, arithmetic microinstructions and write microinstructions.

[0069] Furthermore, in some embodiments, step S810 may further include:

[0070] In response to determining that the instruction to be processed is a complex instruction, the complex instruction is broken down into several sub-instructions according to a predetermined instruction format and distributed to the data reading module, the calculation module and the data writing module. The sub-instructions include read sub-instructions, calculation sub-instructions and write sub-instructions.

[0071] For details on the specific implementation process of the relevant steps, please refer to the preceding text. Figure 6 The relevant descriptions will not be repeated here.

[0072] The instruction processing method executed by the instruction processing apparatus of this disclosure embodiment has been described above with reference to the flowchart. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0073] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0074] Another embodiment of this disclosure is a computer-readable storage medium storing computer program code for instruction processing, which, when executed by a processor, performs actions such as... Figure 8The method is illustrated. In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage memory. Based on this, when the solution disclosed herein is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method of the embodiments disclosed herein. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0075] Another embodiment of this disclosure is a computer program product, including a computer program for instruction processing, which, when executed by a processor, implements the aforementioned... Figure 8 The steps of the method shown.

[0076] The above embodiments can be implemented using computer programs. The purpose of executing computer programs in the solution is to solve the technical problem that the decomposition of complex instructions is limited by hardware configuration. Running computer programs on a computer makes it easier for software personnel to directly intervene in the decoding behavior of instruction decomposition.

[0077] Figure 9 A schematic diagram of the structure of a board 90 according to an embodiment of this disclosure is shown. Figure 9 As shown, board 90 includes chip 901, which is a system-on-chip (SoC) that integrates one or more combined processing devices. The combined processing device is a computing unit used to support various encoding and decoding algorithms and meet the processing needs in fields such as computer vision, speech, natural language processing, and data mining.

[0078] Chip 901 is connected to external device 903 via external interface device 902. External device 903 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 903 to chip 901 via external interface device 902. The calculation results from chip 901 can be transmitted back to external device 903 via external interface device 902. Depending on the application scenario, external interface device 902 may have different interface types, such as a PCIe interface.

[0079] The board 90 also includes a storage device 904 for storing data, which includes one or more memory cells 905. The storage device 904 is connected to and transmits data with the controller 906 and the chip 901 via a bus. The controller 906 in the board 90 is configured to regulate the state of the chip 901. Therefore, in one application scenario, the controller 906 may include a microcontroller (MCU).

[0080] Figure 10 A structural diagram of the combined processing device 10 in chip 901 of this embodiment is shown. Figure 10 As shown, the combined processing device 10 includes a computing device 1001, an interface device 1002, a processing device 1003, and a DRAM 1004.

[0081] The computing device 1001 is configured to perform user-specified operations, mainly implemented as a single-core intelligent processor or a multi-core intelligent processor, used to divide video frames into encoding blocks. It can interact with the processing device 1003 through the interface device 1002 to jointly complete the user-specified operations.

[0082] Interface device 1002 is used to transmit data and control commands between computing device 1001 and processing device 1003. For example, computing device 1001 can obtain input data from processing device 1003 via interface device 1002 and write it to on-chip storage. Further, computing device 1001 can obtain control commands from processing device 1003 via interface device 1002 and write them to on-chip control cache. Alternatively or optionally, interface device 1002 can also read data from storage in computing device 1001 and transmit it to processing device 1003; for example, processing device 1003 can read encoded blocks in computing device 1001 and perform subsequent processing on them.

[0083] The processing device 1003, as a general-purpose processing device, performs basic controls including but not limited to data transfer and starting / stopping the computing device 1001. For example, the processing device 1003 can also perform inter-frame prediction coding on the coded blocks in the computing device 1001. Depending on the implementation, the processing device 1003 can be one or more types of processors, including but not limited to digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. Furthermore, the processing device 1003 can carry a compiler or compiler program to take the coded blocks output by the computing device 1001 as input data, execute the corresponding compiler program, and complete the inter-frame prediction coding of the coded blocks.

[0084] As previously stated, the computing device 1001 disclosed herein can be considered as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 1001 and the processing device 1003 are considered together as forming a heterogeneous multi-core structure.

[0085] DRAM1004 is used to store data to be processed. It is DDR memory, typically 16G or larger in size, and is used to store data of computing device 1001 and / or processing device 1003.

[0086] Based on the above combination Figure 9 and Figure 10 Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0087] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. Vehicles include airplanes, ships, and / or vehicles; home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, the electronic device or apparatus according to the present disclosure can be applied to a cloud device (e.g., a cloud server), while a low-power electronic device or apparatus can be applied to a terminal device and / or an edge device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or the edge device are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or the edge device based on the hardware information of the terminal device and / or the edge device, so as to complete the unified management, scheduling and collaborative work of the end-to-cloud or cloud-edge-end integration.

[0088] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this disclosure, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0089] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that the several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the aforementioned electronic device or apparatus embodiments, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0090] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution in this disclosure embodiment. Additionally, in some scenarios, multiple units in this disclosure embodiment may be integrated into one unit or each unit may exist physically independently.

[0091] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the disclosed solution is embodied in a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0092] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0093] The foregoing can be better understood in accordance with the following terms:

[0094] Clause A1. An instruction processing device, comprising: a microinstruction processing module, a data reading module, an arithmetic module, a data writing module, and a storage module, wherein,

[0095] The micro-instruction processing module is used to process the instruction and send it to the data reading module, the calculation module and the data writing module based on the type of instruction to be processed.

[0096] The data reading module is used to send the read data to the computing module;

[0097] The calculation module is used to perform calculations on the received data and obtain the execution result;

[0098] The data writing module is used to write the execution result into the storage module.

[0099] Clause A2. The instruction processing apparatus according to Clause A1, wherein the microinstruction processing module is further configured to:

[0100] Determine the type of instruction to be processed;

[0101] In response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module, the arithmetic module and the data writing module. The microinstructions include read microinstructions, arithmetic microinstructions and write microinstructions.

[0102] Clause A3. The instruction processing apparatus according to Clause A2, wherein,

[0103] The data reading module is used to receive the read micro-instruction and send the read data to the computing module according to the read micro-instruction;

[0104] The arithmetic module is used to receive the arithmetic micro-instructions, execute the arithmetic micro-instructions on the received data, and obtain the execution result;

[0105] The data writing module is used to receive the write micro-instruction and write the execution result into the storage module according to the write micro-instruction.

[0106] Clause A4. The instruction processing apparatus according to Clause A2 or A3 further includes a decoding module, wherein,

[0107] The micro-instruction processing module, in response to determining that the instruction to be processed is a complex instruction, sends the complex instruction to the decoding module for processing;

[0108] The decoding module is used to receive the complex instruction, decompose the complex instruction into several sub-instructions according to a predetermined instruction format, and distribute them to the data reading module, the calculation module, and the data writing module. The sub-instructions include read sub-instructions, calculation sub-instructions, and write sub-instructions.

[0109] Clause A5. The instruction processing apparatus according to Clause A4, wherein,

[0110] The data reading module is also used to receive the read sub-instruction and send the read data to the calculation module according to the read sub-instruction;

[0111] The arithmetic module is further configured to receive the arithmetic sub-instruction, execute the arithmetic sub-instruction on the received data, and obtain the execution result;

[0112] The data writing module is also used to receive the write sub-instruction and write the execution result into the storage module according to the write sub-instruction.

[0113] Clause A6. An integrated circuit device comprising an instruction processing means as described in any one of Clauses A1-A5.

[0114] Clause A7. A board including an integrated circuit device as described in Clause A6.

[0115] Clause A8. An instruction processing method, comprising:

[0116] Based on the type of instruction to be processed, the micro-instruction processing module processes the instruction and sends it to the data reading module, the calculation module, and the data writing module.

[0117] The read data is sent to the computing module;

[0118] Perform operations on the received data and obtain the results.

[0119] The execution result is written to the storage module.

[0120] Clause A9. The instruction processing method according to Clause A8, wherein the micro-instruction processing module processes the instruction and sends it to the data reading module, the calculation module, and the data writing module based on the type of instruction to be processed, further includes:

[0121] Determine the type of instruction to be processed;

[0122] In response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module, the arithmetic module and the data writing module. The microinstructions include read microinstructions, arithmetic microinstructions and write microinstructions.

[0123] Clause A10. The instruction processing method described in Clause A9 further includes:

[0124] In response to determining that the instruction to be processed is a complex instruction, the complex instruction is broken down into several sub-instructions according to a predetermined instruction format and distributed to the data reading module, the calculation module and the data writing module. The sub-instructions include read sub-instructions, calculation sub-instructions and write sub-instructions.

[0125] Clause A11. A computer-readable storage medium having a computer program stored thereon that, when run by one or more processing devices, performs the method described in any one of Clauses A8-A10.

[0126] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. An instruction processing apparatus, comprising: The module comprises a micro-instruction processing module, a data reading module, an arithmetic module, a data writing module, and a storage module. The micro-instruction processing module is used to process the instruction and send it to the data reading module, the calculation module and the data writing module based on the type of instruction to be processed. The data reading module is used to send the read data to the computing module; The calculation module is used to perform calculations on the received data and obtain the execution result; The data writing module is used to write the execution result into the storage module.

2. The instruction processing apparatus according to claim 1, wherein, The microinstruction processing module is further used for: Determine the type of instruction to be processed; In response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module, the arithmetic module and the data writing module. The microinstructions include read microinstructions, arithmetic microinstructions and write microinstructions.

3. The instruction processing apparatus according to claim 2, wherein, The data reading module is used to receive the read micro-instruction and send the read data to the computing module according to the read micro-instruction; The arithmetic module is used to receive the arithmetic micro-instructions, execute the arithmetic micro-instructions on the received data, and obtain the execution result; The data writing module is used to receive the write micro-instruction and write the execution result into the storage module according to the write micro-instruction.

4. The instruction processing apparatus according to claim 2 or 3 further includes a decoding module, wherein, The micro-instruction processing module, in response to determining that the instruction to be processed is a complex instruction, sends the complex instruction to the decoding module for processing; The decoding module is used to receive the complex instruction, decompose the complex instruction into several sub-instructions according to a predetermined instruction format, and distribute them to the data reading module, the calculation module, and the data writing module. The sub-instructions include read sub-instructions, calculation sub-instructions, and write sub-instructions.

5. The instruction processing apparatus according to claim 4, wherein, The data reading module is also used to receive the read sub-instruction and send the read data to the calculation module according to the read sub-instruction; The arithmetic module is further configured to receive the arithmetic sub-instruction, execute the arithmetic sub-instruction on the received data, and obtain the execution result; The data writing module is also used to receive the write sub-instruction and write the execution result into the storage module according to the write sub-instruction.

6. An integrated circuit device comprising an instruction processing apparatus according to any one of claims 1-5.

7. A board comprising the integrated circuit device according to claim 6.

8. An instruction processing method, comprising: Based on the type of instruction to be processed, the micro-instruction processing module processes the instruction and sends it to the data reading module, the calculation module, and the data writing module. The read data is sent to the computing module; Perform operations on the received data and obtain the results. The execution result is written to the storage module.

9. The instruction processing method according to claim 8, wherein, The step of the micro-instruction processing module processing the instruction based on the type of instruction to be processed and then sending it to the data reading module, the calculation module, and the data writing module further includes: Determine the type of instruction to be processed; In response to determining that the instruction to be processed is an instruction composed of a microinstruction sequence, the instruction composed of the microinstruction sequence is split into several microinstructions and distributed to the data reading module, the arithmetic module and the data writing module. The microinstructions include read microinstructions, arithmetic microinstructions and write microinstructions.

10. The instruction processing method according to claim 9, further comprising: In response to determining that the instruction to be processed is a complex instruction, the complex instruction is broken down into several sub-instructions according to a predetermined instruction format and distributed to the data reading module, the calculation module and the data writing module. The sub-instructions include read sub-instructions, calculation sub-instructions and write sub-instructions.

11. A computer-readable storage medium having a computer program stored thereon that, when run by one or more processing devices, performs the method as described in any one of claims 8-10.

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