A knowledge graph-based server running fault root cause mining method and system

Abstract

This invention belongs to the field of server fault monitoring technology in electronic information science, and relates to a method and system for root cause mining of server operation faults based on knowledge graphs. The method includes: obtaining the state index and basic knowledge graph of each hardware entity based on sensor data and simulation task logs of the server cluster; obtaining the cross-domain anomaly propagation confidence based on the topological relationship between nodes in the basic knowledge graph, combined with the state index of the hardware entity and the latency of the task entity; obtaining the trigger probability of the hardware entity based on the cross-domain anomaly propagation confidence and the state index of the hardware entity; and determining the server operation fault based on the magnitude of the trigger probability of each hardware entity. It can mine the hardware nodes that cause cluster faults from complex task congestion phenomena through cross-domain anomaly propagation confidence and trigger probability.

Description

Technical Field

[0001] This invention belongs to the field of server fault monitoring technology in the discipline of electronic information. It relates to a method and system for mining the root causes of server operation faults based on knowledge graphs. It is used for fault detection of server clusters with high concurrency resource contention, such as those used in semiconductor electronic design automation simulation calculations. It can eliminate the interference of software scheduling congestion and improve the accuracy of locating the source of physical faults in servers under high load conditions. Background Technology

[0002] Currently, server clusters play a crucial role in the automated simulation computing scenarios of semiconductor electronic design. The smooth progress of simulation tasks depends on the efficient operation of the underlying computing nodes. During the operation of server clusters, abnormal problems such as deadlock or partial physical downtime often occur. Therefore, the source detection of server operation failures is particularly important for ensuring the chip development cycle.

[0003] In existing related technologies, such as the Chinese patent document with authorization announcement number CN117033060B, a server fault diagnosis method, device, and system are disclosed. This method constructs an internal digital twin model by acquiring internal image data and non-image data detected by electrical performance sensors, compares it with a benchmark model, and combines it with fault information collected based on BMC maintenance logs and BIOS to determine the final diagnostic result. Related technologies focus on static model comparison and discrete low-level device log collection, lacking characterization of dynamic hardware-software interaction features. In complex simulation business flows, minor performance degradation often propagates upwards along the task chain, and relying on digital twins and hardware logs cannot effectively track cross-level anomaly propagation paths.

[0004] In related technologies, for example, Chinese patent document CN120803854B discloses a server fault monitoring system. This method extracts unified timestamps from multi-source data and sets a fixed-length sliding window, using association rules such as time, event, and device to merge and diagnose anomalies in log operations within the window. However, in semiconductor electronic design automation simulation, business latency caused by hardware performance degradation often exhibits nonlinear amplification and cross-domain multi-level propagation characteristics. This long-period cascading lag phenomenon easily breaks the constraints of the fixed short-time window, causing rule matching within the local time window to fail, and easily misjudging normal task queuing as a fault.

[0005] In related technologies, for example, Chinese patent document CN116126571B discloses a fault diagnosis method, a fault monitoring circuit, and a server. This method uses a specially designed fault monitoring circuit to acquire low-level monitoring information of the processor in the server and directly determines the fault diagnosis result based on this hardware-level monitoring information. This solution employs a direct hardware-level monitoring approach, and its diagnostic logic is independent of the virtual task execution state of the upper-level software. In high-concurrency computing during automated simulation of semiconductor electronic design, the processor is often in a fully loaded and high-heat state. Low-level hardware monitoring data alone cannot distinguish whether this state is due to normal ultra-large task scheduling or actual damage to physical components.

[0006] In summary, in semiconductor electronic design automation simulation scenarios, server clusters are typically in a state of extremely high concurrency and resource contention, and the changes in the physical state of the underlying hardware exhibit a dynamic correlation with the resource scheduling of the application layer. None of the aforementioned technologies can effectively decouple the aliasing characteristics of software and hardware interactions, making it easy for physical hardware degradation features to be masked by application-layer timeout alarms, resulting in the inability to accurately separate software deadlocks from actual component failures. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art, solve the technical problem of ambiguous fault source node location in the prior art, and provide a method and system for mining the root cause of server operation failures based on knowledge graphs.

[0008] To achieve the aforementioned objectives, the present invention provides a knowledge graph-based method for identifying the root causes of server malfunctions, comprising the following steps: acquiring sensor data and simulation task logs from a server cluster; using hardware devices in the sensor data as hardware entities and simulation processes in the simulation task logs as task entities; constructing a topological relationship between nodes based on the deployment location of the simulation processes; generating a basic knowledge graph; extracting memory paging frequency and CPU temperature from the sensor data; obtaining memory paging coefficients based on the memory paging frequency; and obtaining the state index of each hardware entity based on the memory paging coefficients and CPU temperature; and extracting task data from the simulation task logs. The system calculates the latency factor by comparing the actual execution time and standard execution cycle of each task entity. It then adjusts the latency factor based on the hardware entity's state index to obtain the cross-domain anomaly propagation confidence level. Finally, it traverses the basic knowledge graph to extract task entities directly connected to the hardware entities as a neighborhood set. The system aggregates the cross-domain anomaly propagation confidence levels of all task entities within the neighborhood set, and obtains the trigger probability of each hardware entity based on its state index and the aggregated cross-domain anomaly propagation confidence level. The system then compares the trigger probability of each hardware entity with a preset probability trigger threshold, and determines server malfunctions based on the comparison results.

[0009] This invention acquires sensor data and simulation task logs from a server cluster and constructs a basic knowledge graph. It extracts memory paging frequency and CPU temperature to calculate the state index of hardware entities and combines this with the latency factor of task entities to obtain cross-domain anomaly propagation confidence. By utilizing the implicit correlation between the latency manifestation of software tasks and the thermodynamic state and memory congestion state of underlying hardware devices, it overcomes the interference phenomenon of mutual masking of software and hardware anomalies caused by high-concurrency resource contention in semiconductor simulation scenarios. Thus, in complex business timeout avalanche phenomena, it accurately separates the normal waiting latency caused by pure software resource deadlock from the irreversible downtime latency caused by the deterioration of underlying physical components. By aggregating the cross-domain anomaly propagation confidence of all task entities within a neighborhood set to obtain the trigger probability of hardware entities, it accurately locates the source device that truly causes the entire server cluster to crash in a cluster environment with massive alarms, providing accurate source location basis for subsequent server cluster operation and maintenance and hardware replacement.

[0010] The present invention describes obtaining the memory paging coefficient based on the memory paging frequency, comprising: obtaining a safe upper limit value for the paging frequency; calculating the ratio of the memory paging frequency to the safe upper limit value for the paging frequency; and obtaining the memory paging coefficient based on the ratio.

[0011] This invention obtains the memory paging coefficient based on the ratio of the memory paging frequency to the safe upper limit of the paging frequency. By using the memory paging coefficient, the memory contention phenomenon of server nodes of different specifications is uniformly mapped to a standardized range, eliminating the absolute numerical differences between hardware devices of different capacities. Thus, when faced with memory congestion caused by high-density read and write operations in semiconductor simulation tasks, it can expose the deterioration of memory leaks or resource exhaustion in each hardware entity, providing reliable basic data support for subsequent evaluation of the status index of hardware entities.

[0012] The state index described in this invention satisfies the following relation: In the formula, For the first The state index of each hardware entity. For the first The memory paging factor of each hardware entity For the first CPU temperature of each hardware entity This refers to the rated temperature of the physical CPU.

[0013] This invention amplifies the state saturation response under high memory usage, effectively filtering out false alarms caused by simply maximizing computing power while maintaining good heat dissipation. This accurately reflects the hardware degradation trend caused by the combined effects of local overheating and memory congestion.

[0014] The present invention describes obtaining a latency factor based on the difference between the actual execution time and the standard execution cycle, comprising: calculating the difference between the actual execution time and the standard execution cycle; extracting the maximum value between the difference and zero; and calculating the ratio of the maximum value to the standard execution cycle to obtain the latency factor of the task entity.

[0015] The confidence level for cross-domain anomaly propagation described in this invention satisfies the following relationship: In the formula, For the first The hardware entity and the first Confidence of cross-domain anomaly propagation among task entities For the first The latency factor of each task entity. For the first The state index of a hardware entity.

[0016] This invention utilizes the state index of the underlying hardware entity to adjust the latency factor of the surface software application. When the state index of the hardware entity is small, the weight expression of the surface latency phenomenon is suppressed, thereby overcoming the interference of misjudging normal software queuing as hardware failure. This allows the final output cross-domain anomaly propagation confidence to establish a causal link between the congested task entity and the decaying hardware entity.

[0017] The cross-domain anomaly propagation confidence of all task entities within the neighborhood set described in this invention includes: summing the cross-domain anomaly propagation confidence of all task entities within the neighborhood set to obtain the aggregated result of the cross-domain anomaly propagation confidence.

[0018] The triggering probability described in this invention satisfies the following relationship: In the formula, For the first The trigger probability of a hardware entity. For the first The state index of each hardware entity. For the first The sum of cross-domain anomaly propagation confidence scores for all task entities within the neighborhood set of each hardware entity.

[0019] This invention transforms the accumulated peripheral task lag phenomenon into a data form with diminishing marginal effects to obtain the trigger probability, preventing the accidental collapse of individual task entities with extremely large loads from causing the trigger probability to overflow. At the same time, it uses the state index of the hardware entity itself to suppress the influence of the lag phenomenon by weighting, eliminating the victim nodes that are only on the fault propagation chain but whose hardware is completely healthy.

[0020] The present invention describes comparing the trigger probability of each hardware entity with a preset probability trigger threshold and determining server operation failure based on the comparison result, including: constructing a one-dimensional determination sequence, storing the trigger probability of each hardware entity in the basic knowledge graph into the one-dimensional determination sequence; extracting the values ​​in the one-dimensional determination sequence, comparing them with the probability trigger threshold in turn, and determining server operation failure based on the comparison result.

[0021] The present invention describes extracting values ​​from a one-dimensional decision sequence, comparing them sequentially with a probability trigger threshold, and determining server operational faults based on the comparison results. This includes: in response to a hardware entity's trigger probability being greater than the probability trigger threshold, determining that the hardware entity with a trigger probability greater than the threshold has a hidden physical fault and is the root cause node of the current server cluster operational fault; in response to the absence of any element in the one-dimensional decision sequence greater than the probability trigger threshold, sorting the one-dimensional decision sequence in descending order; extracting the first-ranked trigger probability and obtaining the hardware entity corresponding to it; extracting task entities with a direct connection to the hardware entity corresponding to the first-ranked trigger probability, and constructing a suspected scheduling deadlock alarm work order.

[0022] This invention also provides a knowledge graph-based server operation failure root cause mining system, including a processor and a memory. The memory stores computer program instructions, which, when executed by the processor, implement the aforementioned knowledge graph-based server operation failure root cause mining method. By adopting the above technical solution, the aforementioned knowledge graph-based server operation failure root cause mining method generates a computer program and stores it in the memory for loading and execution by the processor. This allows for the creation of a terminal device based on the memory and processor, facilitating its use.

[0023] Compared with existing technologies, this invention offers at least the following advantages: By constructing a fundamental knowledge graph containing the topological relationships between hardware entities and task entities, combining memory paging coefficients and CPU temperatures extracted from underlying sensor data, and using latency factors extracted from surface-level simulation task logs, a cross-domain anomaly propagation confidence level is constructed and the trigger probability is ultimately aggregated and output. Utilizing the aforementioned data fusion methods that cross software and hardware boundaries, the previously isolated local device deterioration phenomena and complex process scheduling blocking phenomena in the physical space are causally aligned and weighted within a unified topological network, alleviating the challenges of automated semiconductor electronic design. In simulated scenarios, the underlying degradation characteristics caused by high-concurrency computing power preemption are masked by massive application-layer congestion alarms. When facing a cascading failure scenario with large-scale timeouts of multi-node services, it can not only filter out regular load peaks induced by pure software logic deadlocks, but also accurately eliminate innocent victim nodes that are downstream in the propagation chain but have healthy underlying hardware. It enables the identification of the target of operation and maintenance troubleshooting from the complex cluster network performance to the physical hardware source device that caused the global paralysis, providing an accurate decision-making basis for rapid physical component replacement and hardware resource reconfiguration in high-load server cluster environments. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the knowledge graph-based root cause analysis method for server operation failures, which relates to the present invention.

[0025] Figure 2 This is a thermal diagram of the confidence level for cross-domain anomaly propagation, as per the present invention. Detailed Implementation

[0026] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings.

[0027] Example 1: This embodiment relates to a knowledge graph-based method for mining the root causes of server malfunctions, referring to... Figure 1 This includes steps S1-S4: S1. Obtain hardware status indices and construct a knowledge graph; It should be noted that in the semiconductor electronic design automation simulation scenario, there is a high-concurrency resource contention phenomenon. Under normal circumstances, the frequent memory paging of server nodes and local hardware overheating are implicitly coupled. In order to quantify the implicit degradation trend of the above physical hardware state, this embodiment obtains the state index and basic knowledge graph of each hardware entity based on the sensor data collected by the server node and the simulation task log, so as to reveal the potential hardware failure risk under extreme conditions.

[0028] This embodiment involves acquiring sensor data and simulation task logs from each node in a server cluster, extracting hardware devices as hardware entities, extracting simulation processes as task entities, constructing topological relationships between entity nodes based on the deployment location of the processes, and generating a basic knowledge graph. It also involves acquiring a pre-calibrated and stored safe upper limit value for page switching frequency in the controller, calculating the ratio of memory page switching frequency to this safe upper limit value, and mapping this ratio to a memory page switching coefficient through maximum-minimum value normalization. Simultaneously, it extracts CPU temperature from the sensor data and obtains the state index of the hardware entities based on the memory page switching coefficient and CPU temperature.

[0029] The state index involved in this embodiment satisfies the following relation: ; In the formula, For the first The state index of each hardware entity. For the first The memory paging factor of each hardware entity For the first CPU temperature of each hardware entity The rated temperature of the physical CPU. in, This represents the congestion level of memory resources when processing high-density simulation tasks. The larger the value, the greater the possibility of memory leaks or contention, thus improving the state index of the hardware entity; the smaller the value, the greater the possibility of smooth memory scheduling, resulting in a smaller state index for the hardware entity. This represents the degree of performance degradation of electronic components due to thermal radiation. A higher value indicates a greater risk of system downtime due to localized overheating, allowing the state index to better expose the deteriorating consequences of resource congestion; when... The smaller the value, the more likely the hardware is in a safe thermodynamic state, thus suppressing fluctuations caused solely by computing resource usage and effectively eliminating false alarms about hardware that is under high load but in good condition.

[0030] S2. Obtain the confidence level of cross-domain anomaly propagation; It should be noted that the fault propagation between hardware and software is not a one-to-one correspondence. In general, a slight degradation in hardware performance will cause nonlinear time delay amplification after the accumulation of complex simulation task chains, which will make it easy to fall into misjudgment when relying on network topology for root cause tracing. In order to accurately measure the actual interference of hardware status on specific virtual tasks, this embodiment obtains the confidence of cross-domain anomaly propagation based on the topological relationship between nodes in the basic knowledge graph, combined with the state index of hardware entities and the time delay factor of task entities. This embodiment extracts the standard execution cycle and actual execution time of each task entity from the simulation task log, calculates the difference between the actual execution time and the standard execution cycle, and sets the difference to 0 when the actual execution time is less than or equal to the standard execution cycle. The difference is then divided by the standard execution cycle to obtain the latency factor of the task entity. Combining the topological relationships between nodes in the basic knowledge graph, based on the... The state index of the first hardware entity is related to the state index of the first... The latency factor of each task entity is adjusted to obtain the confidence level of cross-domain anomaly propagation.

[0031] The confidence level for cross-domain anomaly propagation involved in this embodiment satisfies the following relationship: ; In the formula, For the first The hardware entity and the first Confidence of cross-domain anomaly propagation among task entities For the first The latency factor of each task entity. For the first The state index of a hardware entity; in, This reflects the congestion phenomenon in surface applications. The larger the value, the more severe the task lag, and the greater the possibility of deadlock in the surface application; Approaching This indicates a higher likelihood that the task will be completed on time and smoothly; This reflects the state of the underlying hardware; when The smaller the value, the healthier the underlying hardware is, thus suppressing the expression of surface latency phenomena. This indicates that the delay in the task is most likely caused by a pure software resource deadlock rather than a hardware failure; conversely, when... The larger the value, the greater the probability of hardware failure, ensuring that the true weight of the time delay is fully preserved, thereby establishing a cross-domain causal link between the congested task entity and the faulty hardware node.

[0032] Appendix Figure 2 This is a heatmap diagram illustrating the confidence level of cross-domain anomaly propagation in this embodiment. As can be seen from the diagram, the confidence level values ​​between most hardware entities and task entities are effectively suppressed, eliminating random software delay interference without causal correlation. For specific hardware entities that have degraded, the response values ​​between the hardware entity and the associated task entity exhibit a concentrated high confidence level distribution, thereby achieving the mapping of the fault source.

[0033] S3. Obtain the hardware trigger probability; It should be noted that network congestion or computing power exhaustion in a cluster often exhibits a multi-level avalanche characteristic, and relying solely on local confidence levels between node pairs often only identifies the affected nodes at the surface level. To uncover the deeper-level hardware sources that trigger global cluster paralysis, this invention combines cross-domain anomaly propagation confidence levels with the state index of hardware entities, along with a graph neighborhood aggregation mechanism, to obtain the trigger probability of hardware entities. This amplifies the characteristic responses of latent faulty nodes within the global graph architecture.

[0034] This embodiment involves traversing each hardware entity in the basic knowledge graph, extracting all task entities that have a direct connection with the hardware entity as a neighborhood set, aggregating the cross-domain anomaly propagation confidence of all task entities in the neighborhood set, and combining it with the state index of the hardware entity to obtain the trigger probability of the hardware entity. For example, in the topology middle, and The intermediate node is crossed. Therefore, it belongs to an indirect connection relationship. Cannot be included The neighborhood set; The triggering probabilities involved in this embodiment satisfy the following relationship: ; In the formula, For the first The trigger probability of a hardware entity. For the first The state index of each hardware entity. For the first The sum of cross-domain anomaly propagation confidence of all task entities within the neighborhood set of each hardware entity; in, The larger the value, the more severe the business timeout propagation caused by the node, resulting in a higher probability of triggering; the smaller the value, the more locally the anomaly of the node is controlled, resulting in a lower probability of triggering. This is achieved through the state index. right The modification ensures that even if a node experiences a large number of timeout tasks, its trigger probability will be suppressed as long as its own state index is extremely small, thereby eliminating non-source victim nodes in the fault propagation chain.

[0035] S4. Perform server malfunction assessment; Specifically, a one-dimensional decision sequence is constructed, and the trigger probabilities of all hardware entities in the basic knowledge graph are stored in the decision sequence; a pre-set probability trigger threshold is obtained and stored in the controller, the probability values ​​in the decision sequence are extracted, and the values ​​are compared with the probability trigger threshold in turn.

[0036] In one embodiment, if the trigger probability of a hardware entity is greater than the probability trigger threshold, then the hardware entity has a hidden physical fault, and the hardware entity is determined to be the root cause node of the current server cluster operation failure.

[0037] For example, the probability trigger threshold is 3.5.

[0038] In another embodiment, in response to the absence of an element in the determination sequence that is greater than the probability trigger threshold, the determination sequence is sorted in descending order, the hardware entity corresponding to the trigger probability at the top is extracted, and all task entities that have a direct connection relationship with the hardware entity are extracted; the simulation task log corresponding to each task entity is retrieved, and the task identifier sequence and the corresponding resource waiting status label are extracted from the simulation task log; the device physical number of the hardware entity is obtained, and the device physical number, the task identifier sequence, and the corresponding resource waiting status label are concatenated into text fields to construct a suspected scheduling deadlock alarm work order, and the suspected scheduling deadlock alarm work order is sent to the preset operation and maintenance display terminal.

[0039] This embodiment also discloses a knowledge graph-based server operation failure root cause mining system, including a processor and a memory. The memory stores computer program instructions, and when the computer program instructions are executed by the processor, the knowledge graph-based server operation failure root cause mining method according to the present invention is implemented.

[0040] The system also includes other components well known to those skilled in the art, such as communication buses and communication interfaces, the setup and functions of which are known in the art.

Claims

1. A method for mining the root causes of server operational failures based on knowledge graphs, characterized in that, include: Acquire sensor data and simulation task logs from the server cluster, use the hardware devices in the sensor data as hardware entities and the simulation processes in the simulation task logs as task entities, construct the topological relationship between nodes based on the deployment location of the simulation processes, and generate a basic knowledge graph. Extract memory paging frequency and CPU temperature from the sensor data, obtain the memory paging coefficient based on the memory paging frequency, and obtain the state index of each hardware entity based on the memory paging coefficient and CPU temperature; extract the actual execution time and standard execution cycle of the task entity from the simulation task log, and obtain the latency factor based on the difference between the actual execution time and the standard execution cycle. The confidence level for cross-domain anomaly propagation is obtained by adjusting the delay factor based on the state index of the hardware entity. Traverse the basic knowledge graph and extract task entities that have a direct connection with hardware entities as neighborhood sets; aggregate the cross-domain anomaly propagation confidence of all task entities in the neighborhood set, and obtain the trigger probability of the hardware entity based on the state index of the hardware entity and the aggregated cross-domain anomaly propagation confidence. The trigger probability of each hardware entity is compared with the preset trigger probability threshold, and the server operation failure is determined based on the comparison result.

2. The knowledge graph-based server operation failure root cause mining method according to claim 1, characterized in that, The step of obtaining the memory paging coefficient based on the memory paging frequency includes: obtaining a safe upper limit value for the paging frequency; calculating the ratio of the memory paging frequency to the safe upper limit value for the paging frequency; and obtaining the memory paging coefficient based on the ratio.

3. The knowledge graph-based server operation failure root cause mining method according to claim 1, characterized in that, The state index satisfies the following relation: ； In the formula, For the first The state index of each hardware entity. For the first The memory paging factor of each hardware entity For the first CPU temperature of each hardware entity This refers to the rated temperature of the physical CPU.

4. The knowledge graph-based server operation failure root cause mining method according to claim 1, characterized in that, The latency factor is obtained by calculating the difference between the actual execution time and the standard execution cycle, including: calculating the difference between the actual execution time and the standard execution cycle; extracting the maximum value between the difference and zero; and calculating the ratio of the maximum value to the standard execution cycle to obtain the latency factor of the task entity.

5. The knowledge graph-based server operation failure root cause mining method according to claim 4, characterized in that, The confidence level for cross-domain anomaly propagation satisfies the following relationship: ； In the formula, For the first The hardware entity and the first Confidence of cross-domain anomaly propagation among task entities For the first The latency factor of each task entity. For the first The state index of a hardware entity.

6. The knowledge graph-based server operation failure root cause mining method according to claim 1, characterized in that, Aggregate the cross-domain anomaly propagation confidence of all task entities within the neighborhood set, including: summing the cross-domain anomaly propagation confidence of all task entities within the neighborhood set to obtain the aggregated result of the cross-domain anomaly propagation confidence.

7. The knowledge graph-based server operation failure root cause mining method according to claim 6, characterized in that, The trigger probability satisfies the following relationship: ； In the formula, For the first The trigger probability of a hardware entity. For the first The state index of each hardware entity. For the first The sum of cross-domain anomaly propagation confidence scores for all task entities within the neighborhood set of each hardware entity.

8. The method for mining the root causes of server malfunctions based on knowledge graphs according to claim 1, characterized in that, The trigger probability of each hardware entity is compared with a preset probability trigger threshold. Based on the comparison result, server operation failure is determined. This includes: constructing a one-dimensional determination sequence and storing the trigger probability of each hardware entity in the basic knowledge graph into the one-dimensional determination sequence; extracting the values ​​in the one-dimensional determination sequence and comparing them with the probability trigger threshold in turn, and determining server operation failure based on the comparison result.

9. The knowledge graph-based server operation failure root cause mining method according to claim 8, characterized in that, The values ​​in the one-dimensional decision sequence are extracted and compared with the probability trigger thresholds in turn. Based on the comparison results, server operation faults are determined, including: if the trigger probability of a hardware entity is greater than the probability trigger threshold, the hardware entity with a trigger probability greater than the probability trigger threshold is determined to have a hidden physical fault and is the root cause node of the current server cluster operation fault; if there are no elements in the one-dimensional decision sequence greater than the probability trigger threshold, the one-dimensional decision sequence is sorted in descending order; the trigger probability at the top of the sequence is extracted, and the hardware entity corresponding to the trigger probability at the top of the sequence is obtained; task entities with a direct connection relationship with the hardware entity corresponding to the trigger probability at the top of the sequence are extracted, and a suspected scheduling deadlock alarm work order is constructed.

10. A knowledge graph-based system for mining the root causes of server malfunctions, characterized in that, include: A processor and a memory, the memory storing computer program instructions that, when executed by the processor, implement the knowledge graph-based server operation failure root cause mining method according to any one of claims 1-9.

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