System and method for automatic determination and visualized output of server slot failures

Abstract

The application discloses a kind of for server slot failure automatic determination and visual output system and method, the system includes slot adaptation interface module, signal sampling module, determination processing module, visual output module and interactive control module, signal sampling module built-in weak excitation source, for in the mainboard power-off state to slot preset signal line acquisition node voltage and impedance characteristics;Determination processing module is classified according to preset determination rule to sampling result, generates corresponding fault code and abnormal signal set;Visual output module is used to output detection conclusion in standardized format;Interactive control module is used to realize detection result automatic locking display and one-key retest trigger, to eliminate the misreading caused by plug jitter.The detection phenomenon of the present application will be converted into structured diagnostic results, which significantly improves the efficiency and safety of server mainboard batch testing and fault positioning.

Description

Technical Field

[0001] This invention relates to the field of server motherboard testing and fault diagnosis technology, and in particular to an automatic judgment and visualization output system and method for server slot faults. Background Technology

[0002] During the research, development, mass production, and repair / maintenance of server motherboards, DDR5 DIMM slot-related failures account for a very high percentage. A typical server motherboard has 16 memory slots, each with 288 pins covering signals such as voltage, reset, data, clock, alarm, command, control, test, and GND. Since the memory slots are directly connected to the CPU, testing the memory slots also involves testing the CPU's related circuitry. Currently, domestically produced CPU packages have around 4600 pins (e.g., the VIS H8000 has 4609 pins). If problems arise with the CPU or memory slots during research, development, mass production, or repair, troubleshooting is extremely difficult and time-consuming. Powering on a system with a short circuit to ground in the voltage or signal range can also lead to serious damage, such as burning out the CPU.

[0003] Existing DDR5 slot testing tools mostly rely on indicator lights or the motherboard's BMC (Block Memory Control Center) to test memory. Indicator light testing still depends on the tester's experience and requires consulting schematics and PCB layouts, using specialized instruments such as multimeters and oscilloscopes for judgment and problem localization. This approach suffers from issues such as unintuitive conclusions, inconsistent outputs, susceptibility to misjudgments, and low efficiency, making it difficult to meet the needs of batch testing and rapid fault localization for server motherboards. Partial testing via the BMC can only identify an anomaly in a specific slot, unable to detect specific signal pins. Furthermore, when address pins malfunction, the slot may not be recognized. This testing method has many limitations, low coverage, and poor versatility. Summary of the Invention

[0004] To address the above problems, this invention provides an automatic judgment and visualization output system and method for server slot faults that can quickly and automatically classify slot faults without the need for external instruments and improve testing efficiency and diagnostic consistency through standardized output methods.

[0005] The technical solution of the present invention is: an automatic judgment and visualization output system for server slot faults, including a slot adapter interface module, a signal sampling module, a judgment processing module, a visualization output module and an interactive control module; The slot adapter interface module is used to insert into the server slot and establish an electrical connection with the preset signal line set, and has an anti-misinsertion structure and an overcurrent protection structure. The signal sampling module is used to collect the detection features of the preset signal line set, and the detection features include at least node voltage features, impedance to ground features, and impedance to power supply features; The judgment processing module is used to automatically classify the detection features according to the preset judgment rules, map the sampled detection features to at least one of the preset fault types, and generate fault codes and abnormal signal sets corresponding to the fault types. The visualization output module is used to present the detection results in a standardized format, including status indication output, fault code output, and abnormal signal number output. The interactive control module is used to lock the output display after the detection conclusion is generated, and unlock it when a one-click retest command is received, triggering the system to re-execute the detection process and refresh the output.

[0006] The preset signal line set includes at least one or more of the following: power supply signals, reset signals, alarm signals, clock signals, chip select signals, management bus signals, and ground reference signals; wherein, the management bus signals include the data lines and clock lines of the SPD interface.

[0007] The signal sampling module includes a multi-channel analog switch, a sampling resistor network, an analog-to-digital conversion unit, and an internal weak excitation source. The internal weak excitation source is used to inject a reference current or apply a reference voltage to the signal line under test when the server motherboard is powered off, so as to measure its impedance characteristics to ground and to the power supply.

[0008] The preset determination rules include at least the following: When the impedance characteristic to ground is lower than the first threshold or the node voltage characteristic is lower than the low level criterion, it is determined to be a short circuit to ground; When the power supply impedance characteristic is lower than the second threshold or the node voltage characteristic is higher than the high level criterion, it is determined to be a short circuit to the power supply. When the detection characteristics meet the criteria of continuous high resistance, no effective conduction response, or open circuit, it is judged as an open circuit anomaly. When multiple sampling results are inconsistent, the item is determined to be unknown and requires verification.

[0009] The judgment and processing module performs multiple sampling and consistency judgments on each signal line, and uses a debouncing window to avoid misclassification caused by transient jitter; when the sampled data is detected to be consistent N times in a row, the result locking state is automatically triggered.

[0010] The determination and processing module includes providing a read-only result register or result data frame for outputting fault codes, abnormal signal masks, and lock status; the bit definition of the result register includes at least: a fault code field, an abnormal signal mask field, a lock status bit, and a retest request bit.

[0011] The visualization output module includes a display output unit and an indication output unit; wherein, the display output unit is used to display fault type text, fault code and abnormal signal list, and the indication output unit is used to output PASS / FAIL / CHECK status.

[0012] The interactive control module includes a result locking unit and a retest triggering unit, wherein, The result locking unit is used to lock and maintain the set of fault codes and abnormal signals currently displayed by the visualization output module after the test results are output, until a retest instruction is received. The retest trigger unit is used to receive a one-click retest command and trigger the system to re-execute the sampling and judgment process to update the output content.

[0013] An automatic method for determining and visualizing server slot failures includes the following steps: S1. Insertion detection: Insert the slot adapter interface module into the target slot and establish a signal line connection; S2. Sampling and detection: Using an internal weak excitation source, the voltage and impedance characteristics of nodes in a preset signal line set are collected. S3. Automatic judgment: Generate a set of fault types, fault codes and abnormal signals based on preset judgment rules; S4. Standardized output: Outputs test results in a standardized format, including status indications, fault codes, and abnormal signal numbers. S5. Result Lock: After output is complete, the result lock display state is entered. S6. One-click retest: After receiving the one-click retest command, exit the locked state and re-execute steps S2 to S4 to refresh the output.

[0014] In step S3, multiple samplings are performed on each signal line and a consistency judgment is made. When the sampling results are inconsistent, an unknown fault code is output and a retest is prompted. When the sampling results are consistently consistent, a lock signal is automatically generated.

[0015] In operation, this invention first inserts the test board into the server slot, and then uses an internal weak excitation source to sample the signal line to be tested. If the sampling result is consistent with the settings, the memory slot test is considered OK. If the sampling result is inconsistent with the settings, the system determines the fault according to preset rules, generates a fault code and abnormal signal set, and then outputs a standardized test conclusion and enters the result lock display state. If a retest command is received, the system clears the original test result and restarts the test process, thereby ensuring the stability and accuracy of the test conclusion.

[0016] This invention upgrades the output of phenomena to automatic judgment conclusions, eliminating the need for empirical interpretation; it adopts a standardized output format (status, code, and number / name) for easy recording, traceability, and statistics; it outputs a list of abnormal objects, making the location path more direct; through result locking and one-click retesting mechanisms, it isolates unstable factors such as insertion / removal jitter and contact changes from the judgment process, significantly reducing the probability of misreading and improving the consistency and reliability of test conclusions; it is compatible with production line FQC, rework centers, and after-sales rapid screening, forming a closed-loop data foundation for quality. Furthermore, through hardware-level anti-misinsertion and current-limiting protection designs, the safety of the tested motherboard is further ensured.

[0017] This invention is based on the principle of direct sampling at the physical layer. It can achieve full coverage detection of all signal pins without server power-on, BMC involvement, or address matching. It transforms detection phenomena that rely on human experience into structured diagnostic results, significantly improving the efficiency and safety of batch testing and fault location of server motherboards. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In the drawings, the parts are not necessarily drawn to scale.

[0019] Figure 1 This is a system structure block diagram of the present invention. Figure 2 This is a flowchart of the signal sampling and judgment processing in this invention. Detailed Implementation

[0020] The present invention is as follows Figure 1 As shown, an automatic fault diagnosis and visualization output system for server slots is provided, including a slot adapter interface module, a signal sampling module, a fault diagnosis and processing module, a visualization output module, and an interactive control module, all of which are integrated into the test board. The test board is inserted into the DDR5 DIMM slot of the server motherboard (i.e., the object under test) through the slot adapter interface module, establishing an electrical connection with the signal line under test, thereby realizing the automatic detection and diagnosis of slot faults.

[0021] The slot adapter interface module is used to insert into the server slot and establish an electrical connection with the preset signal line set. Specifically, the slot adapter interface module has an anti-misinsertion structure (such as a physical notch guide) and a current limiting protection structure (such as a self-resetting fuse or electronic current limiting circuit) to reduce the risks of misinsertion, reverse insertion, transient short circuits, etc., and protect the expensive server motherboard and CPU from damage.

[0022] The signal sampling module is used to acquire detection features of a preset set of signal lines. The detection features include at least one or more of the following: node voltage feature Vnode; impedance to ground feature Zgnd; and impedance to power supply feature Zvcc.

[0023] Optionally, the signal sampling module includes a multiplexer analog switch, a sampling resistor network, an analog-to-digital converter (ADC), and an internal weak excitation source. The internal weak excitation source is used to inject a small current (e.g., in the microampere range) into the pin under test to measure impedance when the motherboard is powered off, ensuring the safety and passivity of the detection process.

[0024] The signal sampling module polls and samples each signal line in a preset order, and introduces multiple sampling and filtering strategies to reduce the impact of transient noise on the decision.

[0025] The judgment and processing module is used to automatically classify the detected features according to preset judgment rules and generate: fault type; fault code; abnormal signal set.

[0026] Optionally, the decision processing module is implemented using a microcontroller (MCU) or a programmable logic device and includes a decision state machine. The state machine includes at least the following states: IDLE (standby), TEST (detection), DECIDE (decision), OUTPUT (output), LOCK (lock), and RETEST (retest).

[0027] The preset signal line set includes at least one or more of the following: power supply signals (VDD, VPP, etc.), reset signals, alarm signals, clock signals, chip select signals, management bus signals, and ground reference signals; wherein, the management bus signals include the data lines and clock lines of the SPD / management interface.

[0028] The preset determination rules include at least the following: When the impedance characteristic to ground is lower than the first threshold or the node voltage characteristic is lower than the low level criterion, it is determined to be a short circuit to ground; When the power supply impedance characteristic is lower than the second threshold or the node voltage characteristic is higher than the high level criterion, it is determined to be a short circuit to the power supply. When the detection characteristics meet the criteria of continuous high resistance, no effective conduction response, or open circuit, it is judged as an open circuit anomaly. When multiple sampling results are inconsistent, the item is determined to be unknown and requires verification.

[0029] The first and second thresholds are configurable. For example, an impedance to ground <2Ω is considered a short circuit, and >1MΩ is considered an open circuit. The node voltage criterion uses a proportional threshold relative to the I / O reference voltage VIO, where the low-level criterion satisfies Vnode≤0.2×VIO, and the high-level criterion satisfies Vnode≥0.8×VIO.

[0030] The fault types output by the judgment and processing module include at least: open circuit abnormality, short circuit to ground, short circuit to power supply, and unknown items requiring verification.

[0031] The fault codes include at least the following: E0 indicates no abnormality passed, E1 indicates open circuit abnormality, E2 indicates short circuit to ground, E3 indicates short circuit to power supply, and E9 indicates unknown item requiring verification.

[0032] The abnormal signal set is identified by numbers S01 to Sxx, and a mapping relationship between signal number and signal name is established; the visualization output module outputs at least the abnormal signal number, and preferably also outputs the abnormal signal name.

[0033] The decision processing module performs multiple samplings and consistency checks on each signal line, and uses a debouncing window to avoid misclassification caused by transient jitter. The number of samplings is no less than 3, and the debouncing window is no less than 10 milliseconds. When the sampled data is detected to be consistent N times consecutively, the system automatically enters a locked state.

[0034] The judgment processing module includes providing a read-only result register or result data frame for outputting fault codes, abnormal signal masks, and lock status. The register bit definitions include: FAULT_CODE (fault code), SIG_MASK (abnormal signal mask), LOCKED (lock status bit), and RETEST_REQ (retest request bit), etc.

[0035] The specific execution logic of the preset determination rule of the present invention is as follows: Short circuit to ground criterion: When Zgnd is lower than the first threshold, or Vnode≤0.2×VIO, it is determined to be E2; Short circuit to power supply criterion: When Zvcc is lower than the second threshold, or Vnode ≥ 0.8 × VIO, it is determined to be E3; Open circuit criterion: If the conduction response is continuously absent or the impedance meets the open circuit criterion, it is determined to be E1; Unknown verification criteria: When multiple sampling results are inconsistent, output E9 and prompt for retesting.

[0036] like Figure 2As shown, the signal sampling and judgment processing flow of the present invention includes: establishing an electrical connection with the DDR5 DIMM slot through the slot adapter interface module and initializing the detection parameters; sequentially sampling the node voltage characteristics and / or impedance characteristics of the preset signal lines; performing consistency judgment on the sampling results; when the sampling results are inconsistent, generating an unknown fault and prompting for retesting; when the sampling results are consistent, automatically determining the fault type according to the preset judgment rules, generating a fault code and abnormal signal set; outputting the detection conclusion in a standardized format, and then entering the result lock display state; after receiving a one-click retest command, clearing the lock and re-executing the detection process.

[0037] The visualization output module is used to output standardized diagnostic conclusions, and the output content should include at least: Status indicator output: PASS / FAIL / CHECK; Fault code output: E0 / E1 / E2 / E3 / E9; Abnormal signal output: A list of abnormal signal numbers and preferred names. Optionally, the visualization output module can be one or a combination of display output units (such as screens / digital tubes) and indicator output units (such as LEDs / buzzers). When the number of abnormal signals exceeds the number of signals that can be displayed on a single screen, a scrolling or paginated display method is used, and it is preferred to display power supply and ground short circuit signals in a preset priority order.

[0038] The interactive control module includes a result locking unit and a retest triggering unit. The result locking unit is used to lock and maintain the set of fault codes and abnormal signals currently displayed by the visualization output module after the test results are output, to prevent changes in readings due to hand tremors; the retest triggering unit is used to receive a one-click retest command and trigger the system to re-execute the sampling and judgment process.

[0039] This invention, by introducing a standardized output system, transforms traditionally human-experience-dependent detection phenomena into structured diagnostic results that can be machine-analyzed, system-recorded, and statistically analyzed. The standardized output format is defined as follows: (A) Status indication: PASS (passed without abnormality); FAIL (there is a clear fault); CHECK (boundary or unknown, retest recommended).

[0040] (B) Fault codes: E0 (PASS); E1 (OPEN); E2 (SHORT-GND); E3 (SHORT-VCC); E9 (UNKNOWN).

[0041] (C) Abnormal signal set representation: Output with numbers S01 to Sxx, and the name can be displayed. For example: STATUS: FAIL; FAULT: E2 SHORT-GND; SIG1: S03 RESET_n.

[0042] An automatic method for determining and visualizing server slot failures includes the following steps: S1. Insertion detection: Insert the slot adapter interface module into the target slot and establish a signal line connection; S2. Sampling and detection: Using an internal weak excitation source, the voltage and impedance characteristics of nodes in a preset signal line set are collected. S3. Automatic judgment: Generate a set of fault types, fault codes and abnormal signals based on preset judgment rules; S4. Standardized output: Outputs test results in a standardized format, including status indications, fault codes, and abnormal signal numbers. S5. Result Lock: After output is complete, the result lock display state is entered. S6. One-click retest: After receiving the one-click retest command, exit the locked state and re-execute steps S2 to S4 to refresh the output.

[0043] In step S3, multiple samplings are performed on each signal line and a consistency judgment is made. When the results of multiple samplings are inconsistent, an unknown fault code is output and a retest is prompted.

[0044] In practical applications, this embodiment deploys the system as a diagnostic tool that can be inserted into a DDR5 DIMM slot. The system establishes a numbered mapping table for a preset set of signal lines (e.g., S01=CK0_P, S03=RESET_n, etc.). This mapping table can be stored in memory and supports online updates based on different server motherboard versions. The judgment processing module employs a multiple sampling and debouncing window strategy (N≥3 times, window≥10ms) for each signal line to ensure stable test results even in complex electromagnetic environments.

[0045] Once a test is completed, the interactive control module switches the system to LOCK state. In this state, the output content remains locked, and minor contact changes or plug-in jitter do not trigger a re-decision. Only pressing the "Retest" button enters RETEST state and retests. After retesting, the system refreshes the output and re-enters the locked display, thus forming a closed-loop process of "testing—output—locking—retesting".

[0046] This invention can detect all signal pins (including voltage, reset, data, clock, alarm, etc.). The principle is as follows: the system establishes an electrical connection directly with the physical pins (gold fingers) of the memory slot through a slot adapter interface module, and uses a signal sampling module to independently collect the physical layer characteristics (voltage, impedance) of each pin. This detection method does not rely on logic protocol handshakes or data communication, but directly measures the static electrical characteristics of the pins. Therefore, regardless of whether the pin is an address line, data line, or control line, as long as a physical connection exists, it can be sampled and determined, thus achieving full pin coverage detection. Simultaneously, since the memory slot is directly connected to the CPU, the detection of the slot pins also indirectly covers the circuit connectivity of the corresponding CPU pins.

[0047] This invention has the following significant advantages: No power-on required: This invention is based on the principle of passive static feature detection. The system provides the reference voltage or current required for detection through an internal power supply or a weak excitation source, measuring the pin's impedance to ground / power supply and node voltage. These physical characteristics remain present and stable even when the motherboard is powered off (not powered on), thus completing fault screening without starting the server operating system or powering on, avoiding the risk of burning out the CPU during powered-on operation.

[0048] No BMC Required: Traditional BMC testing relies on the motherboard management controller firmware and bus communication protocol, and can only read the logic state. This invention uses an independent hardware test board with a built-in dedicated signal sampling and judgment processing module (such as MCU+FPGA architecture), which directly completes signal acquisition and logic judgment at the physical layer. It is completely independent of the motherboard's BMC system and is not limited by the motherboard firmware version or BMC function.

[0049] No address matching required: Since this invention directly samples the electrical characteristics of physical pins in parallel or polling manner, rather than reading data by sending address commands via a bus, address decoding or address matching is unnecessary. Even if the address pin itself has an open or short circuit fault, it will not affect the system's detection of other pins, solving the problem in traditional methods where an entire slot cannot be identified due to an address line fault.

[0050] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. An automatic fault diagnosis and visualization output system for server slots, characterized in that, It includes a slot adapter interface module, a signal sampling module, a decision processing module, a visualization output module, and an interactive control module; The slot adapter interface module is used to insert into the server slot and establish an electrical connection with the preset signal line set, and has an anti-misinsertion structure and an overcurrent protection structure. The signal sampling module is used to collect the detection features of the preset signal line set, and the detection features include at least node voltage features, impedance to ground features, and impedance to power supply features; The judgment processing module is used to automatically classify the detection features according to the preset judgment rules, map the sampled detection features to at least one of the preset fault types, and generate fault codes and abnormal signal sets corresponding to the fault types. The visualization output module is used to present the detection results in a standardized format, including status indication output, fault code output, and abnormal signal number output. The interactive control module is used to lock the output display after the detection conclusion is generated, and unlock it when a one-click retest command is received, triggering the system to re-execute the detection process and refresh the output.

2. The automatic judgment and visualization output system for server slot faults according to claim 1, characterized in that, The preset signal line set includes at least one or more of the following: power supply signals, reset signals, alarm signals, clock signals, chip select signals, management bus signals, and ground reference signals; wherein, the management bus signals include the data lines and clock lines of the SPD interface.

3. The automatic determination and visualization output system for server slot faults according to claim 1, characterized in that, The signal sampling module includes a multi-channel analog switch, a sampling resistor network, an analog-to-digital conversion unit, and an internal weak excitation source. The internal weak excitation source is used to inject a reference current or apply a reference voltage to the signal line under test when the server motherboard is powered off, so as to measure its impedance characteristics to ground and to the power supply.

4. The automatic determination and visualization output system for server slot faults according to claim 1, characterized in that, The preset determination rules include at least the following: When the impedance characteristic to ground is lower than the first threshold or the node voltage characteristic is lower than the low level criterion, it is determined to be a short circuit to ground; When the power supply impedance characteristic is lower than the second threshold or the node voltage characteristic is higher than the high level criterion, it is determined to be a short circuit to the power supply. When the detection characteristics meet the criteria of continuous high resistance, no effective conduction response, or open circuit, it is judged as an open circuit anomaly. When multiple sampling results are inconsistent, the item is determined to be unknown and requires verification.

5. The automatic judgment and visualization output system for server slot faults according to claim 1, characterized in that, The judgment and processing module performs multiple sampling and consistency judgments on each signal line, and uses a debouncing window to avoid misclassification caused by transient jitter; when the sampled data is detected to be consistent N times in a row, the result locking state is automatically triggered.

6. The automatic determination and visualization output system for server slot faults according to claim 1, characterized in that, The determination and processing module includes providing a read-only result register or result data frame for outputting fault codes, abnormal signal masks, and lock status; the bit definition of the result register includes at least: a fault code field, an abnormal signal mask field, a lock status bit, and a retest request bit.

7. The automatic determination and visualization output system for server slot faults according to claim 1, characterized in that, The visualization output module includes a display output unit and an indication output unit; wherein, the display output unit is used to display fault type text, fault code and abnormal signal list, and the indication output unit is used to output PASS / FAIL / CHECK status.

8. The automatic determination and visualization output system for server slot faults according to claim 1, characterized in that, The interactive control module includes a result locking unit and a retest triggering unit, wherein, The result locking unit is used to lock and maintain the set of fault codes and abnormal signals currently displayed by the visualization output module after the test results are output, until a retest instruction is received. The retest trigger unit is used to receive a one-click retest command and trigger the system to re-execute the sampling and judgment process to update the output content.

9. An automatic determination and visualization output method for server slot faults, applied to the automatic determination and visualization output system for server slot faults as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1. Insertion detection: Insert the slot adapter interface module into the target slot and establish a signal line connection; S2. Sampling and detection: Using an internal weak excitation source, the voltage and impedance characteristics of nodes in a preset signal line set are collected. S3. Automatic judgment: Generate a set of fault types, fault codes and abnormal signals based on preset judgment rules; S4. Standardized output: Outputs test results in a standardized format, including status indications, fault codes, and abnormal signal numbers. S5. Result Lock: After output is complete, the result lock display state is entered. S6. One-click retest: After receiving the one-click retest command, exit the locked state and re-execute steps S2 to S4 to refresh the output.

10. The method for automatic determination and visual output of server slot faults according to claim 9, characterized in that, In step S3, multiple samplings are performed on each signal line and a consistency decision is made. When the results of multiple samplings are inconsistent, an unknown fault code is output and a retest is prompted. When the sampling results are consistent, a lock signal is automatically generated.

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