A high-speed serdes performance optimization method and system based on linear parameter scanning

Abstract

This invention discloses a high-speed SERDEs performance optimization method and system based on linear parameter scanning, comprising: setting linear parameters for CTLE gain and transmission rate to perform stepwise scanning, collecting signal performance and power consumption data; constructing first and second performance features and analyzing performance at each time point; introducing a clustering algorithm to cluster and analyze performance features, marking abnormal aggregation periods; linearly evaluating power consumption data, filtering abnormal power consumption periods, extracting overlapping periods and abnormal linear parameter segments, and further generating a target test plan. This invention, through linear parameter scanning and multi-dimensional analysis, accurately mines parameter coupling relationships and abnormal parameter segments, achieving targeted optimization, improving chip performance and stability, and is applicable to performance testing and optimization scenarios for various high-speed SERDEs chips.

Description

Technical Field

[0001] This invention relates to the field of high-speed transmission and SERDEs performance analysis, and more specifically, to a method and system for optimizing high-speed SERDEs performance based on linear parameter scanning. Background Technology

[0002] With the rapid development of cutting-edge technologies such as big data, cloud computing, 5G communication, and artificial intelligence, the requirements of systems for data transmission rate, bandwidth efficiency, and signal integrity are increasing. Traditional parallel bus architecture can no longer meet the needs of modern high-speed systems. Therefore, SERDES (Serializer / Deserializer) technology based on serial communication has become one of the key solutions for high-bandwidth, long-distance, and low-power data transmission. It is widely used in data center switches, high-performance computing interconnects, optical communication modules, radar signal processing, and other fields, and is an indispensable core supporting technology in modern information infrastructure.

[0003] Currently, performance optimization of high-speed SERDES chips mainly relies on engineers' experience for parameter tuning or simple parameter scanning methods for testing, which has many shortcomings. On the one hand, existing parameter scanning methods are mostly discrete parameter scans, which cannot accurately capture the dynamic changes in chip performance during the linear changes of CTLE gain and transmission rate, and it is difficult to discover potential anomalies during the linear parameter changes. On the other hand, existing technologies are unable to uncover potential abnormal parameter patterns and factors during chip operation, especially in the abnormal parameter segments under linear parameter scanning conditions. There is a lack of corresponding performance parameter anomaly analysis methods, making it difficult to conduct efficient linear scan testing and high-speed SERDES chip optimization, which makes it difficult to optimize the production and evaluate abnormal parameters of high-speed SERDES chips. Summary of the Invention

[0004] This invention overcomes the shortcomings of the prior art and proposes a high-speed SERDEs performance optimization method and system based on linear parameter scanning.

[0005] The first aspect of this invention provides a high-speed SERDEs performance optimization method based on linear parameter scanning, comprising: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time points to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

[0006] In this solution, S1 specifically refers to: For the target high-speed SERDE chip, multi-time period testing is carried out based on linear parameter scanning, and linear change scanning test of CTLE gain and transmission rate is introduced; In the CTLE gain linear parameter scan, starting from 0dB, the value is gradually increased to the preset maximum value in steps of 0.1dB. In the linear change scanning test of transmission rate, a linear scanning scheme for setting the serial communication baud rate in SERDE transmission is introduced, and the baud rate is set to increase linearly within a preset range for testing.

[0007] In this solution, S1 further includes: The collected raw signal performance data underwent cleaning, denoising, and normalization preprocessing. Outlier data was removed using the 3σ criterion. Wavelet transform was used to remove data noise. The min-max normalization method was employed to standardize data of different dimensions and magnitudes to a preset numerical range. The raw power consumption data is processed by calculating outliers at different time points using the IQR method, and then outliers are removed and interpolated with adjacent data.

[0008] In this solution, S2 specifically refers to: The preprocessed signal performance data is used to extract parameters. The bit error rate and signal-to-noise ratio are used as the core performance indicators to construct a two-dimensional first performance feature vector. The bit error rate is logarithmically transformed to convert it into a linearly analyzable value, and the signal-to-noise ratio is normalized to keep the numerical range of the two consistent, thus obtaining a standardized first performance feature vector. A second performance feature vector is constructed based on the remaining performance parameters; Analyze the first and second performance feature vectors at each time point.

[0009] In this solution, S3 specifically refers to: The K-medoids clustering algorithm is used to take the performance characteristics of each time node as sample data, determine the optimal K value through the elbow rule, and randomly select K time nodes corresponding to the performance characteristics as center points. Set the neighborhood radius and minimum number of samples, perform iterative clustering on the sample data, and update the center points in a loop. In the process of calculating the similarity between data points, evaluate the similarity by the Euclidean distance between the first performance vector and the second performance feature vector in the data points, and set the preset weights of the first performance feature and the second performance feature. Clustering is performed cyclically until a preset number of iterations is reached. Clusters exceeding the preset number of clusters are recorded, and the corresponding time nodes of the clusters are statistically analyzed and marked as abnormal aggregation periods.

[0010] In this solution, S4 specifically refers to: Linear evaluation is performed based on power consumption data. For nonlinear segments, abnormal power consumption periods are selected. Overlapping periods are extracted from abnormal aggregation periods and abnormal power consumption periods. Abnormal linear parameter segments are extracted from overlapping periods. By using power consumption data, the core power consumption value at each time point is serialized, and the linear change of power consumption across multiple time points is evaluated. Linear change is determined by linearly fitting the power consumption change across multiple time points. If the numerical error after fitting is less than 80%, it indicates that a linear relationship exists. By marking time points where no linear relationship exists, abnormal power consumption periods can be obtained.

[0011] In this solution, S4 further includes: The overlapping periods are extracted from the abnormal aggregation periods and the abnormal power consumption periods, and the overlapping periods are used as the abnormal periods of linear scanning. Based on the time nodes corresponding to the abnormal periods of linear scanning, extract the CTLE gain and transmission rate parameter data corresponding to the linear scanning process, and generate abnormal linear parameter information; The abnormal linear parameter information includes parameter segments based on CTLE gain and transmission rate, time node information, and parameter linear scan change rate information.

[0012] In this solution, S4 further includes: By using abnormal linear parameter information, the linear scan parameter segment based on CTLE gain and transmission rate is dynamically set, including adjusting the parameter adjustment strategy for the coupling relationship between CTLE gain and transmission rate, and generating the target test scheme.

[0013] A second aspect of the present invention also provides a high-speed SERDes performance optimization system based on linear parameter scanning. The system includes: a memory, a processor, and a general-purpose interface. The memory includes a high-speed SERDes performance optimization program based on linear parameter scanning. When executed by the processor, the high-speed SERDes performance optimization program based on linear parameter scanning performs the following steps: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time points to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

[0014] A third aspect of the present invention also provides a computer-readable storage medium comprising a high-speed SERDes performance optimization program based on linear parameter scanning, wherein when the high-speed SERDes performance optimization program based on linear parameter scanning is executed by a processor, it implements the steps of the high-speed SERDes performance optimization method based on linear parameter scanning as described in any of the preceding claims.

[0015] This invention discloses a high-speed SERDEs performance optimization method and system based on linear parameter scanning, comprising: setting linear parameters for CTLE gain and transmission rate to perform stepwise scanning, collecting signal performance and power consumption data; constructing first and second performance features and analyzing performance at each time point; introducing a clustering algorithm to cluster and analyze performance features, marking abnormal aggregation periods; linearly evaluating power consumption data, filtering abnormal power consumption periods, extracting overlapping periods and abnormal linear parameter segments, and further generating a target test plan. This invention, through linear parameter scanning and multi-dimensional analysis, accurately mines parameter coupling relationships and abnormal parameter segments, achieving targeted optimization, improving chip performance and stability, and is applicable to performance testing and optimization scenarios for various high-speed SERDEs chips. Attached Figure Description

[0016] Figure 1A flowchart of a high-speed SERDEs performance optimization method based on linear parameter scanning according to the present invention is shown; Figure 2 The flowchart of the abnormal aggregation period analysis of the present invention is shown.

[0017] Figure 3 A block diagram of a high-speed SERDEs performance optimization system based on linear parameter scanning according to the present invention is shown. Detailed Implementation

[0018] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that, unless otherwise specified, the embodiments and features described in the embodiments of this application can be combined with each other.

[0019] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0020] Figure 1 A flowchart of a high-speed SERDEs performance optimization method based on linear parameter scanning according to the present invention is shown.

[0021] like Figure 1 As shown, the first aspect of the present invention provides a high-speed SERDEs performance optimization method based on linear parameter scanning, comprising: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time points to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

[0022] Here, through the example, abnormal linear parameter segments can be evaluated. In S5, a targeted test plan with specific optimizations is generated to perform targeted testing and chip optimization on the target high-speed SERDES chip.

[0023] According to an embodiment of the present invention, S1 specifically includes: For the target high-speed SERDE chip, multi-time period testing is carried out based on linear parameter scanning, and linear change scanning test of CTLE gain and transmission rate is introduced; In the CTLE gain linear parameter scan, starting from 0dB, the value is gradually increased to the preset maximum value in steps of 0.1dB. In the linear change scanning test of transmission rate, a linear scanning scheme for setting the serial communication baud rate in SERDE transmission is introduced, and the baud rate is set to increase linearly within a preset range for testing.

[0024] In this embodiment, the preset maximum value for linear scan testing can be 30dB. The scanning process is performed by a linear scan unit, which is used to perform linear gradient scanning on multi-dimensional parameters. It employs a continuous linear sampling method, setting the scan step size according to the parameter value range (adaptively adjustable based on scenario requirements, with a minimum step size of 0.01) to avoid missing optimal parameters due to discrete sampling. For example, when performing a linear scan on CTLE gain, it starts from 0dB, gradually increasing to 30dB in 0.1dB steps. Transmission rate parameters include baud rate, and linear growth scan testing is performed within the range of 10Gbps-112Gbps, with a step size that can be set to 2Gbps. Each adjustment to gain or transmission rate triggers a performance data acquisition, ensuring the continuous correlation between parameter changes and performance / power consumption fluctuations is captured. Simultaneously, this unit supports multi-parameter parallel linear scanning, allowing simultaneous scanning of multiple correlated parameters to uncover the coupling relationships between parameters and improve scanning efficiency.

[0025] Within a given time point, there is a period of linear parameter change corresponding to one or more step sizes. The accuracy of linear scan analysis can be adjusted by setting the time point span. The higher the accuracy, the larger the amount of data required for analysis.

[0026] According to an embodiment of the present invention, step S1 further includes: The collected raw signal performance data underwent cleaning, denoising, and normalization preprocessing. Outlier data was removed using the 3σ criterion. Wavelet transform was used to remove data noise. The min-max normalization method was employed to standardize data of different dimensions and magnitudes to a preset numerical range. The raw power consumption data is processed by calculating outliers at different time points using the IQR method, and then outliers are removed and interpolated with adjacent data.

[0027] It is important to understand that in this embodiment, data preprocessing is used to eliminate outlier data and noise interference. Power consumption data is prone to significant fluctuations due to environmental factors and changes in linear parameters. This preprocessing approach reduces the workload of the preprocessing process and effectively removes outliers (power consumption data points) with abnormal fluctuations, thereby improving the accuracy of subsequent linear change assessments.

[0028] Here, signal performance data includes bit error rate (BER), eye diagram parameters (eye height, eye width, eye opening), jitter (random jitter RJ, deterministic jitter DJ), signal-to-noise ratio (SNR), and inter-symbol interference (ISI) level; power consumption data includes real-time power consumption at the transmitter (target high-speed SERDES chip), real-time power consumption at the receiver, overall power consumption, and power consumption fluctuation values. For the second and third performance feature vectors, some parameters can be selected for feature analysis, such as eye opening and ISI level. ISI level can be characterized by signal amplitude attenuation.

[0029] According to an embodiment of the present invention, step S2 specifically includes: The preprocessed signal performance data is used to extract parameters. The bit error rate and signal-to-noise ratio are used as the core performance indicators to construct a two-dimensional first performance feature vector. The bit error rate is logarithmically transformed to convert it into a linearly analyzable value, and the signal-to-noise ratio is normalized to keep the numerical range of the two consistent, thus obtaining a standardized first performance feature vector. A second performance feature vector is constructed based on the remaining performance parameters; Analyze the first and second performance feature vectors at each time point.

[0030] It should be understood that in this embodiment, the weight of the first performance characteristic is set to 60%~80%, which is used to reflect the core quality of data transmission. The bit error rate generally ranges from 10. - ¹ 5 ~10 - ³.

[0031] Figure 2 The flowchart of the abnormal aggregation period analysis of the present invention is shown.

[0032] According to an embodiment of the present invention, step S3 specifically includes: The K-medoids clustering algorithm is used to take the performance characteristics of each time node as sample data, determine the optimal K value through the elbow rule, and randomly select K time nodes corresponding to the performance characteristics as center points. Set the neighborhood radius and minimum number of samples, perform iterative clustering on the sample data, and update the center points in a loop. In the process of calculating the similarity between data points, evaluate the similarity by the Euclidean distance between the first performance vector and the second performance feature vector in the data points, and set the preset weights of the first performance feature and the second performance feature. Clustering is performed cyclically until a preset number of iterations is reached. Clusters exceeding the preset number of clusters are recorded, and the corresponding time nodes of the clusters are statistically analyzed and marked as abnormal aggregation periods.

[0033] Here, the cosine similarity or Euclidean distance between performance feature vectors at different time points is calculated. The shorter the distance, the more similar the performance features of the two time points; the longer the distance, the greater the difference in performance features between the two time points. Each cluster corresponds to a clustering time period. Additionally, the K value can be set by the user or a default number can be set.

[0034] In this embodiment, the performance characteristics include a first performance feature vector and a second performance feature vector. Regarding the neighborhood radius and minimum number of samples, the neighborhood radius is specifically set based on the average distance between data points, and the minimum number of samples is set to 3-5. The preset number of clusters can be set to >= (total number of time nodes × 30%).

[0035] Here, performance parameters from different dimensions are introduced for aggregate analysis. Multi-dimensional performance features with aggregation are screened and performance anomaly segments are marked. Subsequently, the power consumption anomaly segments are combined for overlap evaluation, effectively analyzing the test anomaly periods under the coupling of various scan parameters. It is worth mentioning that, based on the linear parameter scanning process, if the performance distribution is under normal or ideal conditions, the corresponding performance feature distribution is a certain degree of discretization or a certain degree of linear numerical growth, making it difficult to form aggregate segments. Through this invention, the dynamic changes in chip performance during the linear change of CTLE gain and transmission rate can be effectively captured, potential anomalies in the linear change process of parameters can be discovered, and new test schemes can be dynamically set.

[0036] According to an embodiment of the present invention, step S4 specifically includes: Linear evaluation is performed based on power consumption data. For nonlinear segments, abnormal power consumption periods are selected. Overlapping periods are extracted from abnormal aggregation periods and abnormal power consumption periods. Abnormal linear parameter segments are extracted from overlapping periods. By using power consumption data, the core power consumption value at each time point is serialized, and the linear change of power consumption across multiple time points is evaluated. Linear change is determined by linearly fitting the power consumption change across multiple time points. If the numerical error after fitting is less than 80%, it indicates that a linear relationship exists. By marking time points where no linear relationship exists, abnormal power consumption periods can be obtained.

[0037] It is important to understand that in the embodiment, when evaluating whether the power consumption changes linearly across multiple time points, 5-10 time points can be selected consecutively for fitting, and the time step is also 5-10 time points.

[0038] According to an embodiment of the present invention, step S4 further includes: The overlapping periods are extracted from the abnormal aggregation periods and the abnormal power consumption periods, and the overlapping periods are used as the abnormal periods of linear scanning. Based on the time nodes corresponding to the abnormal periods of linear scanning, extract the CTLE gain and transmission rate parameter data corresponding to the linear scanning process, and generate abnormal linear parameter information; The abnormal linear parameter information includes parameter segments based on CTLE gain and transmission rate, time node information, and parameter linear scan change rate information.

[0039] In the embodiments described herein, the present invention uses linear parameter scanning and multi-dimensional analysis to accurately uncover parameter coupling relationships and abnormal parameter segments, thereby achieving targeted optimization, improving chip performance and stability, and reducing power consumption. It is applicable to performance testing and optimization scenarios for various high-speed SerDes chips.

[0040] According to an embodiment of the present invention, step S4 further includes: By using abnormal linear parameter information, the linear scan parameter segment based on CTLE gain and transmission rate is dynamically set, including adjusting the parameter adjustment strategy for the coupling relationship between CTLE gain and transmission rate, and generating the target test scheme.

[0041] Here, for abnormal linearity parameter information, the linear adjustment range of CTLE gain, the adjustment step size of transmission rate, or the gain configuration of CTLE circuit can be adjusted to discover parameter segments that improve signal performance while reducing test power consumption.

[0042] Here, refined scanning tests and performance and power consumption tests are performed according to the target test plan. Test data is collected and analyzed to verify the chip performance status of abnormal linear parameter segments, further explore the impact of coupling parameters on the performance of the SERDE chip, and thus evaluate the performance distribution of the high-speed SERDE chip.

[0043] According to an embodiment of the present invention, the abnormal aggregation segment further includes: Calculate the proportion of overlapping time periods within abnormal aggregation periods. If the proportion is <= 50%, evaluate the aggregation period based on the similarity of performance characteristics between adjacent time nodes. Specifically... Select a time node, calculate the average performance characteristic difference between the time node and the adjacent time nodes by weighting, and if the average performance characteristic difference is greater than the preset difference, mark the time node and the adjacent time nodes as an abnormal aggregation period. Analyze each time point and filter out all abnormal aggregation periods.

[0044] It is important to understand that in this embodiment, performance characteristics are represented in the form of feature vectors. The above percentage = overlapping period / abnormal aggregation period × 100%. Adjacent time nodes generally include the preceding and following time nodes. Performance characteristic differences include the weighted evaluation value of the differences between the first and second performance characteristics.

[0045] Here, if the percentage is <= 50%, it means that the overlap percentage is low and there is a large inconsistency between the power consumption abnormal period and the performance abnormal period. In this case, there will be a large error in analyzing the linear parameters of the corresponding abnormal period. Here, the continuous node performance difference is introduced for evaluation, which can improve the analysis capability of abnormal aggregation period to a certain extent and improve the screening capability of abnormal parameter segment, thereby reducing the error and omission of abnormal parameter segment analysis.

[0046] Figure 3 A block diagram of a high-speed SERDEs performance optimization system based on linear parameter scanning according to the present invention is shown.

[0047] A second aspect of the present invention also provides a high-speed SERDes performance optimization system based on linear parameter scanning. The system includes: a memory, a processor, and a general-purpose interface. The memory includes a high-speed SERDes performance optimization program based on linear parameter scanning. When executed by the processor, the high-speed SERDes performance optimization program based on linear parameter scanning performs the following steps: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time points to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

[0048] When the system is running, it can perform one or more steps of the high-speed SERDEs performance optimization method based on linear parameter scanning as described above.

[0049] A third aspect of the present invention also provides a computer-readable storage medium comprising a high-speed SERDes performance optimization program based on linear parameter scanning, wherein when the high-speed SERDes performance optimization program based on linear parameter scanning is executed by a processor, it implements the steps of the high-speed SERDes performance optimization method based on linear parameter scanning as described in any of the preceding claims.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0051] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0052] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0053] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0054] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed SERDES performance optimization method based on linear parameter scanning, characterized in that, include: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time nodes to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

2. The high-speed SERDEs performance optimization method based on linear parameter scanning according to claim 1, characterized in that, Specifically, S1 is: For the target high-speed SERDE chip, multi-time period testing is carried out based on linear parameter scanning, and linear change scanning test of CTLE gain and transmission rate is introduced; In the CTLE gain linear parameter scan, starting from 0dB, the value is gradually increased to the preset maximum value in steps of 0.1dB. In the linear change scanning test of transmission rate, a linear scanning scheme for setting the serial communication baud rate in SERDE transmission is introduced, and the baud rate is set within a preset range for linear growth test.

3. The high-speed SERDES performance optimization method based on linear parameter scanning according to claim 2, characterized in that, S1 further includes: The collected raw signal performance data underwent cleaning, denoising, and normalization preprocessing. Outlier data was removed using the 3σ criterion. Wavelet transform was used to remove data noise. The min-max normalization method was employed to standardize data of different dimensions and magnitudes to a preset numerical range. The raw power consumption data is processed by calculating outliers at different time points using the IQR method, and then outliers are removed and interpolated with adjacent data.

4. The high-speed SERDEs performance optimization method based on linear parameter scanning according to claim 3, characterized in that, Specifically, S2 is: The preprocessed signal performance data is used to extract parameters. The bit error rate and signal-to-noise ratio are used as the core performance indicators to construct a two-dimensional first performance feature vector. The bit error rate is logarithmically transformed to convert it into a linearly analyzable value, and the signal-to-noise ratio is normalized to keep the numerical range of the two consistent, thus obtaining a standardized first performance feature vector. A second performance feature vector is constructed based on the remaining performance parameters; Analyze the first and second performance feature vectors at each time point.

5. The high-speed SERDES performance optimization method based on linear parameter scanning according to claim 4, characterized in that, Specifically, S3 is: The K-medoids clustering algorithm is used to take the performance characteristics of each time point as sample data, determine the optimal K value through the elbow rule, and randomly select K time points corresponding to the performance characteristics as center points. Set the neighborhood radius and minimum number of samples, perform iterative clustering on the sample data, and update the center points in a loop. In the process of calculating the similarity between data points, evaluate the similarity by the Euclidean distance between the first performance vector and the second performance feature vector in the data points, and set the preset weights of the first performance feature and the second performance feature. Clustering is performed cyclically until a preset number of iterations is reached. Clusters exceeding the preset number of clusters are recorded, and the corresponding time nodes of the clusters are statistically analyzed and marked as abnormal aggregation periods.

6. The high-speed SERDES performance optimization method based on linear parameter scanning according to claim 5, characterized in that, Specifically, S4 is: Linear evaluation is performed based on power consumption data. For nonlinear segments, abnormal power consumption periods are selected. Overlapping periods are extracted from abnormal aggregation periods and abnormal power consumption periods. Abnormal linear parameter segments are extracted from overlapping periods. By using power consumption data, the core power consumption value at each time point is serialized, and the linear change of power consumption across multiple time points is evaluated. Linear change is determined by linearly fitting the power consumption change across multiple time points. If the numerical error after fitting is less than 80%, it indicates that a linear relationship exists. By marking time points where no linear relationship exists, abnormal power consumption periods can be obtained.

7. The high-speed SERDEs performance optimization method based on linear parameter scanning according to claim 6, characterized in that, The S4 further includes: The overlapping periods are extracted from the abnormal aggregation periods and the abnormal power consumption periods, and the overlapping periods are used as the abnormal periods of linear scanning. Based on the time nodes corresponding to the abnormal periods of linear scanning, extract the CTLE gain and transmission rate parameter data corresponding to the linear scanning process, and generate abnormal linear parameter information; The abnormal linear parameter information includes parameter segments based on CTLE gain and transmission rate, time node information, and parameter linear scan change rate information.

8. The high-speed SERDES performance optimization method based on linear parameter scanning according to claim 7, characterized in that, The S4 further includes: By using abnormal linear parameter information, the linear scan parameter segment based on CTLE gain and transmission rate is dynamically set, including adjusting the parameter adjustment strategy for the coupling relationship between CTLE gain and transmission rate, and generating the target test scheme.

9. A high-speed SERDES performance optimization system based on linear parameter scanning, characterized in that, The system includes: a memory, a processor, and a general-purpose interface. The memory includes a high-speed SERDes performance optimization program based on linear parameter scanning. When the processor executes the high-speed SERDes performance optimization program based on linear parameter scanning, it performs the following steps: S1: In the target high-speed SERDES chip, set linear parameters based on CTLE gain and transmission rate to perform step-by-step scan test, and set multiple time nodes to collect signal performance data and power consumption data; S2: Based on signal performance data, construct the first performance feature with bit error rate and signal-to-noise ratio, and use the remaining performance parameters as the second performance feature, and analyze the performance feature at each time point; S3: Introduce a clustering algorithm to perform cluster analysis on performance characteristics at different time points, and match the similarity of performance characteristics according to preset weight values ​​to form multiple cluster time periods. Mark abnormal aggregation periods according to the cluster time periods. S4: Perform linear evaluation based on power consumption data, filter out abnormal power consumption periods for nonlinear segments, extract overlapping periods based on abnormal aggregation periods and abnormal power consumption periods, and extract abnormal linear parameter information based on overlapping periods. S5: Generate a target test plan for the target high-speed SERDES chip based on abnormal linear parameter information.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a high-speed SERDes performance optimization program based on linear parameter scanning, which, when executed by a processor, implements the steps of the high-speed SERDes performance optimization method based on linear parameter scanning as described in any one of claims 1 to 8.

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