Communication module, SoC chip, embedded system and communication system

Abstract

A communication module, a SoC chip, an embedded system and a communication system, the communication module transmits a first wake-up signal and log data to the SoC chip via a pin multiplexing interface when the SoC chip is in a low-power standby mode, that is, the pin multiplexing interface has both wake-up function and log transmission function, which can avoid the problem of log loss of the communication module when the SoC chip is in a low-power standby mode, and is conducive to improving the resource utilization of the communication module, and accordingly helps to improve the overall energy efficiency and integration of the embedded system.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of data processing, and more particularly to a communication module, a SoC chip, an embedded system, and a communication system. Background Technology

[0002] Embedded systems are intelligent electronic devices that integrate dedicated computer hardware and software. Their core characteristics are specialization, resource constraints, and real-time performance. They are widely used in consumer electronics, industrial control, IoT terminals, and mobile communication devices, and are the cornerstone for realizing device intelligence.

[0003] In the fields of IoT and portable devices, low-power design is one of the core requirements of embedded systems. To extend battery life, System-on-Chips (SoCs) enter low-power modes such as deep sleep when there are no tasks being processed, and their CPU and most peripheral modules are powered off or suspended. At this time, they need to be woken up by external events (such as user key presses, timer expiration, or coprocessor requests) to resume full-function operation.

[0004] In a typical embedded system consisting of a communication module (such as a Wi-Fi / BT communication module) and a SoC chip, how to avoid the loss of communication module logs when the SoC chip is in low-power standby mode and improve the utilization rate of hardware pin resources has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a communication module, SoC chip, embedded system and communication system that can avoid the problem of log loss of the communication module when the SoC chip is in low power standby mode and improve resource utilization.

[0006] To address the above problems, embodiments of the present invention provide a communication module, comprising: The pin-multiplexed interface is used to transmit a first wake-up signal and log data to the SoC chip if the SoC chip is in a low-power standby mode; it is also used to transmit log data to the SoC chip if the SoC chip is in a normal operating mode.

[0007] Optionally, the first wake-up signal is a level sequence carrying wake-up reason information.

[0008] Optionally, the pin multiplexing interface includes a first communication interface, which is used to transmit a first wake-up signal and log data to the SoC chip if the SoC chip is in a low-power standby mode; and to transmit log data to the SoC chip if the SoC chip is in a normal operating mode.

[0009] Optionally, the pin multiplexing interface further includes: A multiplexer, coupled to the first communication interface and the second communication interface, is configured to, in response to receiving a first mode switching control signal from the SoC chip, couple either the first communication interface or the second communication interface to the SoC chip, wherein the first mode switching control signal is used to instruct the SoC chip to switch from a normal operating mode to the low-power standby mode; and is further configured to, in response to receiving a second mode switching control signal from the SoC chip, couple the first communication interface to the SoC chip, wherein the second mode switching control signal is used to instruct the SoC chip to switch from the low-power standby mode to the normal operating mode; The second communication interface is used to transmit a second wake-up signal to the SoC chip if the SoC chip is in a low-power standby mode. The second wake-up signal is a level transition signal.

[0010] Optionally, the first communication interface includes a UART interface, an SPI interface, or an I2C interface, and the second communication interface includes a GPIO interface.

[0011] Accordingly, embodiments of the present invention also provide a SoC chip, comprising: A low-power CPU, coupled to low-power memory, is used to acquire log data from the communication module and write it to the low-power memory if the SoC chip is in low-power standby mode; and to trigger a wake-up operation of the SoC chip if the SoC chip is in low-power standby mode and a first wake-up signal from the communication module is detected. The low-power memory is used to store log data written by the low-power CPU; The main CPU is also used to acquire and save the log data of the communication module if the SoC chip switches from the low-power standby mode to the normal operating mode.

[0012] Optionally, the low-power CPU is also coupled to the main CPU and is further configured to read log data of the communication module from the low-power memory and transmit it to the main CPU if the SoC chip switches from the low-power standby mode to the normal operating mode; The main CPU is also used to receive and save the log data of the communication module sent by the low-power CPU if the SoC chip switches from the low-power standby mode to the normal operation mode.

[0013] Optionally, the SoC chip further includes a pin multiplexing controller; The low-power CPU is also configured to output a first indication signal to the pin multiplexing controller in response to the SoC chip switching from a low-power standby mode to a normal operating mode; The main CPU is also configured to output a second indication signal to the pin multiplexing controller in response to the SoC chip switching from normal operating mode to low power standby mode; The pin multiplexing controller is configured to, in response to receiving the first indication signal, transmit a first mode switching control signal to the communication module, wherein the first mode switching control signal is configured to instruct the SoC chip to switch from the normal operating mode to the low-power standby mode; and in response to receiving the second indication signal, transmit a second mode switching control signal to the communication module, wherein the second mode switching control signal is configured to instruct the SoC chip to switch from the low-power standby mode to the normal operating mode.

[0014] Accordingly, embodiments of the present invention also provide an embedded system, including a communication module as described in any of the preceding claims, and / or a SoC chip as described in any of the preceding claims.

[0015] Accordingly, embodiments of the present invention also provide a communication system, including the embedded system and remote log server as described above; The remote log server is coupled to the main CPU of the SoC chip and is used to acquire and store the log data transmitted by the main CPU.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: The communication module of this invention transmits a first wake-up signal and log data to the SoC chip when the SoC chip is in low-power standby mode via a pin multiplexing interface. That is, the pin multiplexing interface has both wake-up and log transmission functions, which can avoid the problem of log loss of the communication module when the SoC chip is in low-power standby mode, and is conducive to improving the resource utilization of the communication module, which in turn helps to improve the overall energy efficiency and integration of the embedded system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the framework structure of an embedded system; Figure 2 This is a schematic diagram of the structure of an embodiment of the embedded system provided by the technical solution of the present invention; Figure 3 This is a schematic diagram of an embodiment of the pin multiplexing interface provided by the technical solution of the present invention; Figure 4 This is a schematic diagram of another embodiment of the pin multiplexing interface provided by the technical solution of the present invention; Figure 5 This is a schematic diagram illustrating the interaction between the communication module and the SoC chip in the embedded system provided by the technical solution of this invention, when the SoC chip is in low-power standby mode and normal operation mode. Figure 6 This is a schematic diagram of the structure of an embodiment of the communication system provided by the technical solution of the present invention. Detailed Implementation

[0019] In embedded systems such as IoT terminals and portable devices, a dual-chip architecture of "SoC + external communication module" is commonly used to achieve wireless connectivity.

[0020] Figure 1 A schematic diagram of a typical embedded system is shown. Figure 1 As shown, the embedded system includes a SoC chip 110 and a communication module 120 coupled to the SoC chip 110.

[0021] The SoC chip 110, as the core processing unit of the embedded system, typically adopts a heterogeneous architecture of CPU and dedicated accelerator, and integrates a power management unit (PMU) to complete specific tasks with minimal power consumption.

[0022] The communication module 120 typically refers to a Wi-Fi module, Bluetooth module, or a Wi-Fi and Bluetooth combination module that integrates a radio frequency front-end, a baseband processor, and a protocol stack. As a key peripheral of the SoC chip 110, it is responsible for wireless data transmission and reception and protocol processing.

[0023] In terms of physical connection, the communication module 120 can be connected to the input / output (IO) pins of the SoC chip 110 through wires on the printed circuit board (PCB) to form a master-slave communication architecture.

[0024] The SoC chip 110 can enter a low-power standby mode, such as deep sleep, when there are no tasks being processed. Its CPU and most peripheral modules will be powered off or stop working. At this time, it needs to be woken up by an external event (such as a user pressing a key, a timer expiring, or a coprocessor request) to resume full-function operation.

[0025] In the Figure 1 In a typical embedded system, as exemplified by the example shown, a common interactive design is to use a dedicated wake-up interface (such as a General Purpose Input / Output (GPIO) interface) to transmit the wake-up signal.

[0026] Specifically, when the communication module 120 needs to wake up the SoC chip 110, it generates a simple level transition signal by pulling the level of the wake-up interface high or low and transmits it to the wake-up interface of the SoC chip 110. After the wake-up detection circuit of the SoC chip 110 (usually located in the normally open power domain) detects this level transition, it immediately triggers the power management unit to power on the CPU core, thereby completing the system wake-up.

[0027] However, the inventors of this application recognize that this traditional level-transition wake-up method has obvious drawbacks: First, the wake-up interface is used only to transmit simple level-transition signals most of the time, failing to fully utilize its potential as a communication medium, which is particularly wasteful in compact designs where interface resources are scarce; Second, during standby wake-up, the CPU of the SoC chip is in sleep mode and cannot record the debugging log of the communication module in real time, resulting in the loss of critical system mode information and debugging information.

[0028] Therefore, how to avoid the loss of communication module logs when the SoC chip is in low-power standby mode and improve the utilization rate of hardware pin resources has become an urgent problem to be solved by those skilled in the art.

[0029] To address the aforementioned technical problems, this invention provides a communication module comprising: a pin-multiplexed interface for transmitting a first wake-up signal and log data to the SoC chip if the SoC chip is in a low-power standby mode.

[0030] The communication module provided in this embodiment of the invention transmits a first wake-up signal and log data to the SoC chip when the SoC chip is in low-power standby mode via a pin multiplexing interface. That is, the pin multiplexing interface has both wake-up function and log transmission function, which can avoid the problem of log loss of the communication module when the SoC chip is in low-power standby mode, and is conducive to improving the resource utilization of the communication module, which in turn helps to improve the overall energy efficiency and integration of the embedded system.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 2A schematic diagram of an embodiment of the embedded system provided by the technical solution of the present invention is shown. (Refer to reference...) Figure 2 An embedded system may specifically include a communication module 210 and a SoC chip 220 coupled to the communication module 210.

[0033] The communication module 210 is the wireless nerve center of the embedded system. As a communication coprocessor, it is responsible for the transmission and reception of physical layer wireless signals, network access and registration, and deeply integrates a series of network services and autonomous management functions to establish short-range, high-speed data connections between devices and routers, smart terminals (such as mobile phones and smart TVs) and peripheral accessories, allowing devices to break free from the constraints of network cables and achieve plug-and-play wireless capabilities.

[0034] In some embodiments, the communication module 210 integrates a Wi-Fi communication module and / or a Bluetooth (BT) communication module. The Wi-Fi communication module is used for wireless communication processing based on protocols such as IEEE 802.11, supporting 2.4G / 5G dual-band for high-speed data upload and download. The Bluetooth communication module is used for low-power network configuration, near-field data transmission, and audio playback based on Bluetooth Low Energy (BLE), Basic Rate (BR), or Enhanced Data Rate (EDR) protocols.

[0035] In some embodiments, the communication module 210 includes a pin multiplexing interface 211, which is used to transmit a first wake-up signal and log data to the SoC chip 220 if the SoC chip 220 is in a low-power standby mode.

[0036] Therefore, the pin multiplexing interface 211 can transmit the log data of the communication module 210 when the SoC chip 220 is in low-power standby mode, in addition to transmitting the first wake-up signal to the SoC chip 220. Compared with the method of only transmitting the wake-up signal to the SoC chip 220 when the SoC chip 220 is in low-power standby mode, the pin multiplexing interface 211 has both wake-up function and log transmission function, which is beneficial to improving the resource utilization of the pin multiplexing interface 211.

[0037] The communication module has limited storage space. In existing solutions, log data generated by the communication module in the low-power standby mode of the SoC chip is typically overwritten in a circular manner, leading to data loss during this period. The pin-multiplexed interface 211, while transmitting a wake-up signal to the SoC chip 220 in its low-power standby mode, also transmits the log data of the communication module 210 during this mode. This avoids data loss during SoC chip 220 low-power standby mode, providing more complete and reliable log data support for fault diagnosis of the communication module 210, improving the accuracy of fault diagnosis, and consequently reducing the maintenance costs of the communication module 210.

[0038] Please refer to the reference. Figure 3 In some embodiments, the pin multiplexing interface 211 includes a first communication interface 211a. Specifically, the first communication interface 211a is a serial communication interface. Accordingly, the first communication interface 211a transmits a first wake-up signal and log data with the SoC chip 220 based on a serial communication protocol.

[0039] In some implementations, the first communication interface 211a is a Universal Asynchronous Receiver and Transmitter (UART) interface. The UART interface requires only two signal lines (transmit and receive) to achieve full-duplex communication, offering advantages such as fewer pin resources, high stability and reliability in point-to-point communication, longer communication distances under the same voltage level, configurable baud rate, data bits, stop bits, parity, and strong compatibility. These advantages facilitate the stable and reliable transmission of the first wake-up signal and the log data of the communication module 210.

[0040] In other embodiments, the first communication interface may also be a Serial Peripheral Interface (SPI) interface, an Inter-Integrated Circuit (IIC / I2C) interface, or a Secure Digital Input and Output (SDIO) interface, etc. The specific interface can be configured according to data throughput, real-time performance, power consumption, and hardware pin resources, etc., and is not limited here.

[0041] The pin multiplexing interface 211 includes a first communication interface 211a. Accordingly, by means of interface multiplexing, the first communication interface 211a can simultaneously have wake-up function and log data transmission function.

[0042] In some implementations, the communication module 210 obtains information about the operating mode of the SoC chip 220 through a preset PowerIndicator interface, which receives a power status indicator signal (PWR_IND). Specifically, if the power status indicator signal is high (e.g., 3.3V), it indicates that the SoC chip 220 is in normal operating mode; if the power status indicator signal is low (e.g., 0V), it indicates that the SoC chip 220 is in low-power standby mode.

[0043] In some implementations, the first wake-up signal is a sequence of high and low levels, and the sequence carries wake-up reason information. In other words, the first wake-up signal is a wake-up string.

[0044] The wake-up reason information and the level sequence have a one-to-one mapping relationship. Accordingly, for a level sequence, the wake-up reason information that matches the wake-up signal in the form of the level sequence can be determined through the one-to-one mapping relationship between the level sequence and the wake-up reason information.

[0045] The first wake-up signal, which carries a level sequence containing wake-up reason information, enables the SoC chip 220 to directly obtain the matching wake-up reason information through the first wake-up signal, without needing to further interact with the communication module 210 to obtain the corresponding wake-up reason information after the SoC chip 220 is woken up. This helps to save interaction resources and improve the efficiency of the wake-up operation.

[0046] Furthermore, compared with a wake-up signal using a level transition, the first wake-up signal using the level sequence can avoid false triggering caused by external electromagnetic interference or circuit noise, thereby preventing the SoC chip 220 from being falsely woken up and adding system functions. This is beneficial for improving the anti-interference capability of the wake-up signal and saving resources.

[0047] In some implementations, the wake-up reason information includes: pressing the up button on the Bluetooth remote control ("WAKE_BT_KEY_UP"), pressing the down button on the Bluetooth remote control ("WAKE_BT_KEY_DOWN"), establishing a Wi-Fi connection ("WAKE_WIFI_CONNECT"), discovering a Bluetooth device ("WAKE_BT_DISCOVERY"), and being ready to transfer logs ("WAKE_LOG_TRANSFER_READY"), etc. The specific settings can be configured by those skilled in the art according to actual needs, without limitation.

[0048] In some implementations, the first wake-up signal and log data transmitted by the first communication interface 211a adopt a binary frame structure. Accordingly, a corresponding identification field is set in the binary frame structure to distinguish between the wake-up frame transmitting the first wake-up signal and the log data frame used to transmit the log data of the communication module.

[0049] As an example, the binary frame structure includes a frame header, a length field, a payload data field, and a checksum field. The frame header includes a Protocol ID field, which distinguishes between wake-up frames transmitting the first wake-up signal and log data frames transmitting log data from the communication module. The length field indicates the length of the subsequent payload data field and is crucial for resolving packet fragmentation, variable-length data, and checksum issues. The payload data field stores the first wake-up signal or log data. The checksum field uses a checksum algorithm (such as Cyclic Redundancy Check (CRC)) to verify the data from the frame header to the payload data field, ensuring the integrity and reliability of data transmission.

[0050] In other embodiments, the first wake-up signal can also be a level transition signal to be compatible with existing wake-up schemes, which is beneficial to improving the compatibility of the communication module of the present invention with existing embedded systems.

[0051] In some embodiments, the pin-multiplexed interface 211 is further configured to transmit log data to the SoC chip 220 if the SoC chip 220 is in normal operating mode. Correspondingly, the first communication interface 211a is also configured to transmit log data to the SoC chip 220 if the SoC chip 220 is in normal operating mode.

[0052] Therefore, the first communication interface 211a can not only transmit the first wake-up signal and log data to the SoC chip 220 when the SoC chip 220 is in low-power standby mode, but also transmit log data to the SoC chip 220 when the SoC chip 220 is in normal operation mode, which is conducive to further improving the utilization rate of the first communication interface 211a.

[0053] In some implementations, when the first communication interface 211a transmits log data to the SoC chip 220 in normal operating mode, it means that the communication module (Controller) 210 interacts with the SoC chip (Host) 220 through the Host Controller Interface (HCI) protocol. The log data is the SoC chip 220's capture and recording of communication data packets transmitted via the first communication interface 211a as the HCI interface. In other words, the communication module 210 and the SoC chip 220 exchange and save log data through the HCI mechanism. For details on the HCI mechanism, please refer to existing solutions; further explanation is unnecessary.

[0054] In some implementation methods, please refer to the references. Figure 4 The pin multiplexing interface 211 also includes a second communication interface 211b and a multiplexer 211c.

[0055] The multiplexer 211c has a control terminal, at least two input terminals and an output terminal. The control terminal of the multiplexer 211c is coupled to the SoC chip 220, one of the at least two input terminals of the multiplexer 211c is coupled to the first communication interface 211a, and the other of the at least two input terminals of the multiplexer 211c is coupled to the second communication interface 211b.

[0056] The multiplexer 211c is configured to couple either the first communication interface 211a or the second communication interface 211b to the SoC chip 220 in response to receiving a first mode switching control signal from the SoC chip 220, wherein the first mode switching control signal is used to indicate that the SoC chip 220 switches from a normal operating mode to the low-power standby mode; and is also configured to couple the first communication interface 211a to the SoC chip 220 in response to receiving a second mode switching control signal from the SoC chip 220, wherein the second mode switching control signal is used to indicate that the SoC chip 220 switches from a normal operating mode to the low-power standby mode.

[0057] Accordingly, the second communication interface 211b is used to transmit a second wake-up signal to the SoC chip 220 if the SoC chip 220 is in a low-power standby mode, wherein the second wake-up signal is a level transition signal.

[0058] Please refer to the reference. Figure 5 When the SoC chip 220 is in low-power standby mode, the multiplexer 211c can couple the first communication interface 211a or the second communication interface 211b to the SoC chip 220 according to a pre-configured setting.

[0059] If the multiplexer 211c couples the first communication interface 211a to the SoC chip 220, then when the SoC chip 220 is in low-power standby mode, the first wake-up signal and log data can be transmitted to the SoC chip 220 through the first communication interface 211a. This can avoid the problem of log loss of the communication module when the SoC chip 220 is in low-power standby mode, and is conducive to improving the resource utilization of the communication module, which in turn helps to improve the overall energy efficiency and integration of the embedded system.

[0060] If the multiplexer 211c couples the second communication interface 211b to the SoC chip 220, then when the SoC chip 220 is in a low-power standby mode, a second wake-up signal in the form of a level transition can be transmitted to the SoC chip 220 through the second communication interface 211a. Thus, the compatibility between the embodiments of the present invention and existing wake-up methods in the form of level transitions can be achieved, which is beneficial to achieving a smooth transition of embedded systems.

[0061] The SoC chip 220, as an application processor, runs an embedded operating system and upper-layer business applications, and is responsible for executing core business logic, human-computer interaction, sensor data aggregation, and external data interfaces.

[0062] In some implementations, in conjunction with reference Figure 2 and Figure 5 The SoC chip 220 includes a low-power CPU 221 and a low-power memory 222 coupled to the low-power CPU 221.

[0063] The low-power CPU 221 is used to acquire the log data of the communication module 210 and write it to the low-power memory 222 if the SoC chip 220 is in low-power standby mode; and to trigger the wake-up operation of the SoC chip 220 if the SoC chip 220 is in low-power standby mode and a wake-up signal from the communication module is detected.

[0064] The low-power CPU 221 is a processor with low operating power. It runs in the low-power standby mode of the SoC chip 220 to meet the light-load tasks and low-power requirements of the SoC chip 220 in the low-power standby mode.

[0065] By using the low-power CPU 221 to acquire the log data of the communication module 210 and write it to the low-power memory 222 when the SoC chip 220 is in low-power standby mode, the loss of the log data of the communication module 210 can be avoided when the SoC chip 220 is in low-power standby mode. This helps to ensure the integrity of the log data of the communication module 210 and correspondingly reduces the operation and maintenance cost of the communication module 210.

[0066] In some implementations, the low-power CPU 221 acquires the first wake-up signal and log data transmitted by the communication module 210 via the first communication interface 211a of the pin multiplexing interface 211 through a first preset interface on the SoC chip 220. The first preset interface and the first communication interface 211a are matched and configured in a one-to-one correspondence. For example, when the first communication interface 211a is a UART interface, the first preset interface is also a UART interface.

[0067] In some implementations, the log data and the first wake-up signal transmitted by the communication module 210 are both transmitted in the form of binary frames, and the log data frame and the wake-up frame are distinguished by a protocol identifier field in the frame header of the binary frame. Accordingly, the low-power CPU 221 can distinguish between the log data frame and the wake-up frame by parsing the frame header of the received binary frame.

[0068] In some implementations, the low-power memory 222 is the on-chip memory of the SoC chip 220, which is used to temporarily store the log data of the communication module 210 transmitted by the low-power CPU 221 when the SoC chip 220 is in low-power standby mode.

[0069] As an example, the low-power memory 222 is a random access memory (RAM). RAM can directly exchange data with the low-power CPU 221 and has the advantages of being able to read and write at any time (except during refresh) and having a fast speed. It is suitable as a temporary data storage medium for the log data of the communication module 210 when the SoC chip 220 is in low-power standby mode.

[0070] In some implementations, the low-power CPU 221 and the low-power memory 222 are coupled via an Advanced eXtensible Interface (AXI) bus. The AXI bus is a core component of the Advanced Microcontroller Bus Architecture (AMBA) protocol family, designed for high-performance, high-bandwidth, and low-latency on-chip systems, facilitating efficient interaction between the low-power CPU 221 and the low-power memory 222.

[0071] In some implementations, in conjunction with reference Figure 2 and Figure 5 The SoC chip 220 also includes a main CPU 223, and the main CPU 223 is coupled to the low-power CPU 221.

[0072] In some implementations, the low-power CPU 221 is also used to obtain log data of the communication module from the low-power memory 222 and transmit it to the main CPU 223 after the SoC chip 220 switches from the low-power standby mode to the normal operation mode.

[0073] Accordingly, the main CPU 223 is used to receive and save log data from the communication module of the low-power CPU 221 after the SoC chip 220 switches from the low-power standby mode to the normal operation mode.

[0074] In other words, when the SoC chip 220 is in low-power standby mode, the low-power CPU 221 receives log data from the communication module 210 and temporarily stores it in the low-power memory 222. Then, after the SoC chip 220 switches from low-power standby mode to normal operation mode, the low-power CPU 221 sends the log data of the communication module temporarily stored in the low-power memory 222 to the main CPU 223 and stores it in the storage peripheral.

[0075] Therefore, through the collaborative work between the low-power CPU 221 and the main CPU 223, the resource utilization rate of the hardware pin resources of the embedded system can be improved, while the log data of the communication module can be completely saved, providing complete and critical information for subsequent fault diagnosis and troubleshooting. This helps to improve the accuracy of fault diagnosis and reduce the operation and maintenance cost of the communication module.

[0076] In some embodiments, the main CPU 223 receiving and saving log data from the communication module of the low-power CPU 221 means that the main CPU 223 receives log data from the communication module of the low-power CPU 221 and stores it to a preset storage peripheral (not shown).

[0077] In some implementations, the storage peripheral can be the off-chip storage space of the SoC chip 220, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0078] In some embodiments, the SoC chip 220 further includes a pin multiplexing controller 224. The pin multiplexing controller 224 is coupled to the low-power CPU 221 and also to the pin multiplexing interface 211 of the communication module 210.

[0079] The low-power CPU is also configured to output a first indication signal to the pin multiplexing controller if the SoC chip 220 is detected to switch from low-power standby mode to normal operation mode. The first indication signal is used to instruct the pin multiplexing controller 224 to transmit a first mode switching control signal to the communication module.

[0080] In some implementations, the low-power CPU 221 may send a first indication signal to the pin multiplexing controller 224 upon detecting a wake-up signal from the communication module 210.

[0081] Accordingly, the pin multiplexing controller 224 is configured to generate a first mode switching control signal and send it to the pin multiplexing interface 211 of the communication module 210 if the first indication signal is received, so that the multiplexer 211c in the pin multiplexing interface 211 couples the first communication interface 211a or the second communication interface 211b to the SoC chip 220, thereby enabling the communication module 210 to transmit a first wake-up signal and log data through the first communication interface 211a, or to transmit a second wake-up signal in the form of a level transition through the second communication interface 211b, when the SoC chip 220 is in the low-power standby mode.

[0082] In the SoC chip 220, a first indication signal is sent to the pin multiplexing controller 224 via the low-power CPU 221, and then the pin multiplexing controller 224, in response to receiving the first indication signal, sends a first mode switching control signal to the pin multiplexing interface 211 of the communication module 210, which enables the pin multiplexing interface 211 of the communication module 210 to perform routing control when the SoC chip 220 switches from the normal operation mode to the low-power standby mode.

[0083] In some implementations, when the SoC chip 220 is in a low-power mode and the communication module 210 routes the second communication interface 211a to the low-power CPU 221 via the multiplexer 211c in the pin multiplexing interface 211 according to the first mode switching control signal, the first wake-up signal and log data transmitted by the first communication interface 211a are both in binary frame format. For details, please refer to the description in the relevant sections above, which will not be repeated here.

[0084] In some implementations, when the SoC chip 220 is in a low-power mode, and the communication module 210 routes the second communication interface 211a to the low-power CPU 221 via the multiplexer 211c in the pin multiplexing interface 211 according to the first mode switching control signal, the second wake-up signal transmitted by the communication module 210 to the low-power CPU 221 via the second communication interface 211a takes the form of a level transition. Accordingly, the low-power CPU 221 can trigger the wake-up operation of the SoC chip 220 when it detects the level-transition second wake-up signal.

[0085] Therefore, it is beneficial to achieve compatibility of the embedded system of the present invention with the wake-up scheme of level transition, thereby facilitating a smooth transition between the embedded system of the present invention and existing embedded systems.

[0086] In some implementations, the pin multiplexing controller 224 is also coupled to the main CPU 223.

[0087] Accordingly, the main CPU 223 is also configured to output a second indication signal to the pin multiplexing controller 224 if the SoC chip 220 switches from the normal operation mode to the low power standby mode. The second indication signal is used to instruct the pin multiplexing controller 224 to transmit a second mode switching control signal to the communication module 210.

[0088] Accordingly, the pin multiplexing controller 224 is configured to generate a second mode switching control signal and send it to the pin multiplexing interface 211 of the communication module 210 if the second indication signal is received, so that the multiplexer 211c in the pin multiplexing interface 211 couples the first communication interface 211a to the SoC chip 220, thereby enabling the communication module 210 to transmit log data to the SoC chip 220 through the first communication interface 211a when the SoC chip 220 is in the normal operation mode.

[0089] The main CPU 223 sends a second indication signal to the pin multiplexing controller 224, and the pin multiplexing controller 224, in response to receiving the second indication signal, sends a second mode switching control signal to the pin multiplexing interface 211 of the communication module 210, which enables the pin multiplexing interface 211 of the communication module 210 to perform routing control when the SoC chip 220 switches from the low-power standby mode to the normal operation mode.

[0090] Therefore, through the collaborative working mechanism between the low-power CPU and the main CPU, the complete preservation of the log data of the communication module 210 in both the low-power standby mode and the normal operation mode of the SoC chip 220 can be achieved, thereby providing a complete basis for the fault diagnosis of the communication module 210, which is conducive to improving the accuracy and reliability of the fault diagnosis of the communication module 210, and correspondingly helps to improve the accuracy of fault diagnosis and reduce the operation and maintenance cost of the communication module 210.

[0091] In some implementations, the main CPU 223 acts as the decision-maker and executor for the SoC chip 220 to enter the low-power standby mode. By executing a specific software process, it commands the power management unit (PMU) of the SoC chip 220 to switch the SoC chip 220 from the normal operation mode to the low-power standby mode.

[0092] In some implementations, the power management unit can cause the SoC chip 220 to enter the low-power standby mode upon detecting a hardware interrupt event. Correspondingly, the main CPU 223 can obtain information about the SoC chip 220 entering the low-power standby mode through a preset power state (PER_STATE) register.

[0093] Based on the same inventive concept, embodiments of the present invention also provide a communication system.

[0094] Figure 6 A schematic diagram of an embodiment of the communication system provided by the present invention is shown. Please refer to the reference. Figure 6 The communication system shown includes an embedded system 200 and a remote log server 300. The embedded system 200 is the embedded system provided in this embodiment of the invention; for details regarding the embedded system provided in this embodiment, please refer to the foregoing description in the relevant sections, which will not be repeated here.

[0095] In some implementations, the main CPU 223 of the SoC chip in the embedded system 200 transmits the log data of the communication module 210 of the embedded system 200 to the remote log server 300 in real time or periodically, so that users can perform remote fault diagnosis and system optimization on the communication module 210.

[0096] In some implementations, the remote log server 300 is coupled to the main CPU 223 of the SoC chip 220 of the embedded system 200 via a network debugging channel, and is used to acquire and store the log data transmitted by the main CPU 223.

[0097] In some implementations, the network debugging channel is an Android Debug Bridge over Network (ADB over Network) based on a TCP / IP network. An Android Debug Bridge over Network is a means of remotely connecting to devices via the TCP / IP protocol in Android development. Compared to traditional USB cables, it allows the remote log server 300 to communicate with the main CPU 223 of the SoC chip 220 in a Wi-Fi or LAN environment and perform various operations, such as viewing and filtering log data, greatly improving the convenience of communication across devices and physical locations.

[0098] In some implementations, the network debugging channel is a Secure Shell (SSH) protocol channel. SSH is an encrypted network protocol used to provide secure remote login, command execution, and file transfer services in insecure networks (such as the Internet) to improve the convenience and security of communication between the main CPU of the SoC chip in the embedded system 200 and the remote log server.

[0099] In some embodiments, the communication system further includes a user interface 400, which is coupled to the main CPU of the SoC chip in the embedded system 200 through an external interface to obtain and output the log data of the main CPU of the SoC chip in the embedded system 200, so as to facilitate the user's viewing of the log data of the communication module, thereby facilitating the user to perform remote fault diagnosis and system optimization of the communication module.

[0100] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0101] In firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0102] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A communication module, characterized in that, include: A pin-multiplexed interface is used to transmit a first wake-up signal and log data to the SoC chip if the SoC chip is in a low-power standby mode; It is also used to transmit log data to the SoC chip if the SoC chip is in normal operating mode.

2. The communication module as described in claim 1, characterized in that, The first wake-up signal is a level sequence carrying wake-up reason information.

3. The communication module as described in claim 1 or 2, characterized in that, The pin multiplexing interface includes a first communication interface, which is used to transmit a first wake-up signal and log data to the SoC chip if the SoC chip is in a low-power standby mode; and to transmit log data to the SoC chip if the SoC chip is in a normal operating mode.

4. The communication module as described in claim 3, characterized in that, The pin multiplexing interface also includes: A multiplexer, coupled to the first communication interface and the second communication interface, is configured to, in response to receiving a first mode switching control signal from the SoC chip, couple either the first communication interface or the second communication interface to the SoC chip, wherein the first mode switching control signal is used to instruct the SoC chip to switch from a normal operating mode to the low-power standby mode; and is further configured to, in response to receiving a second mode switching control signal from the SoC chip, couple the first communication interface to the SoC chip, wherein the second mode switching control signal is used to instruct the SoC chip to switch from the low-power standby mode to the normal operating mode; The second communication interface is used to transmit a second wake-up signal to the SoC chip if the SoC chip is in a low-power standby mode. The second wake-up signal is a level transition signal.

5. The communication module as described in claim 4, characterized in that, The first communication interface includes a UART interface, an SPI interface, or an I2C interface, and the second communication interface includes a GPIO interface.

6. A SoC chip, characterized in that, include: A low-power CPU, coupled to low-power memory, is used to acquire log data from the communication module and write it to the low-power memory if the SoC chip is in low-power standby mode. If the SoC chip is in low-power standby mode and detects a first wake-up signal from the communication module, the wake-up operation of the SoC chip is triggered. The low-power memory is used to store log data written by the low-power CPU; The main CPU is used to acquire and save the log data of the communication module when the SoC chip switches from the low-power standby mode to the normal operating mode.

7. The SoC chip as described in claim 6, characterized in that, The low-power CPU is also coupled to the main CPU and is also used to read the log data of the communication module from the low-power memory and transmit it to the main CPU if the SoC chip switches from the low-power standby mode to the normal operation mode. The main CPU is also used to receive and save the log data of the communication module sent by the low-power CPU if the SoC chip switches from the low-power standby mode to the normal operation mode.

8. The SoC chip as described in claim 6 or 7, characterized in that, It also includes a pin multiplexing controller; The low-power CPU is also configured to output a first indication signal to the pin multiplexing controller in response to the SoC chip switching from a low-power standby mode to a normal operating mode; The main CPU is also configured to output a second indication signal to the pin multiplexing controller in response to the SoC chip switching from normal operating mode to low power standby mode; The pin multiplexing controller is configured to transmit a first mode switching control signal to the communication module in response to receiving the first indication signal. The first mode switching control signal is configured to instruct the SoC chip to switch from the normal operation mode to the low power standby mode. In response to receiving the second indication signal, a second mode switching control signal is transmitted to the communication module. The second mode switching control signal is used to instruct the SoC chip to switch from the low-power standby mode to the normal operation mode.

9. An embedded system, characterized in that, It includes the communication module as described in any one of claims 1 to 6, and / or the SoC chip as described in any one of claims 6 to 8.

10. A communication system, characterized in that, Including the embedded system and remote log server as described in claim 9; The remote log server is coupled to the main CPU of the SoC chip and is used to acquire and store the log data transmitted by the main CPU.

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