Light ray tracing debugging method, device, system, equipment, medium and program product

Abstract

The present disclosure provides a light ray tracing debugging method, device, system, equipment, medium and program product, relating to the technical field of computer. The method comprises: intercepting a light ray tracing rendering instruction in a command buffer, and performing instruction extension processing on the light ray tracing rendering instruction to obtain a processed instruction; collecting debugging information of light ray tracing based on the processed instruction; and outputting the debugging information to an application layer used for light ray tracing debugging. The method can realize more comprehensive debugging of light ray tracing.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to a ray tracing debugging method, apparatus, system, device, medium, and program product. Background Technology

[0002] In modern graphics processing systems, ray tracing has become a crucial tool for achieving high-quality real-time rendering. Ray tracing calculates pixel colors by simulating the propagation path of light rays in a scene, producing realistic lighting and shadow effects. However, the complexity of ray tracing makes debugging and optimization difficult. Traditional ray tracing debugging methods typically rely on external tools, but these methods often lack comprehensive monitoring of the accelerated structure construction process and the ray traversal process. Summary of the Invention

[0003] This disclosure provides a ray tracing debugging method, apparatus, system, electronic device, computer-readable storage medium, and computer program product.

[0004] In a first aspect, embodiments of this disclosure propose a ray tracing debugging method, which includes: intercepting ray tracing rendering instructions in a command buffer and performing instruction expansion processing on the ray tracing rendering instructions to obtain processed instructions; collecting ray tracing debugging information based on the processed instructions; and outputting the debugging information to an application layer for ray tracing debugging.

[0005] In some embodiments, the command buffer includes the ray tracing rendering instructions; the step of intercepting the ray tracing rendering instructions in the command buffer and performing instruction expansion processing on the ray tracing rendering instructions to obtain processed instructions includes: intercepting the application layer's call to the ray tracing application programming interface (API) function in the command buffer to achieve the interception of ray tracing rendering instructions in the command buffer; wherein, the ray tracing API function corresponds to the ray tracing rendering instructions in the command buffer; in response to the interception of the API function call, inserting additional instructions for collecting debugging information into the command buffer to obtain processed instructions containing the ray tracing rendering instructions and additional instructions.

[0006] In some embodiments, the step of collecting ray tracing debugging information based on post-processed instructions includes: executing a ray tracing pipeline based on ray tracing rendering instructions; and collecting debugging information during the execution of the ray tracing pipeline based on additional instructions.

[0007] In some embodiments, the ray tracing pipeline is bound to a pre-allocated debug buffer; the step of collecting debug information during the execution of the ray tracing pipeline includes: determining debug information by executing the ray tracing pipeline, and collecting debug information by writing the debug information into the pre-allocated debug buffer.

[0008] In some embodiments, the step of determining debugging information by executing a ray tracing pipeline includes: during the execution of the ray tracing pipeline, recording ray tracing-related statistical data through a debugging counter, the statistical data being used to characterize the operational features of ray tracing; reading the statistical data from the debugging counter to determine debugging information related to ray tracing.

[0009] In some embodiments, the step of recording ray tracing-related statistics by a debug counter during the execution of the ray tracing pipeline includes: during the execution of the accelerated structure construction in the ray tracing pipeline, recording at least one of the following by a debug counter: the construction parameters for building the accelerated structure, the total number of nodes in the accelerated structure, the storage tree depth information of the accelerated structure, and the construction time required to build the accelerated structure, thereby obtaining statistical data.

[0010] In some embodiments, the step of recording ray tracing-related statistical data by a debug counter during the execution of the ray tracing pipeline includes: during the execution of the acceleration structure update in the ray tracing pipeline, recording at least one of the following by a debug counter: update parameters of the acceleration structure, modification nodes that need to be modified in the acceleration structure, update time required to update the acceleration structure, and reconstruction operation information related to the reconstruction of the acceleration structure, to obtain statistical data.

[0011] In some embodiments, the step of recording ray tracing-related statistics by a debug counter during the execution of the ray tracing pipeline includes: during the execution of the accelerated structure copying process in the ray tracing pipeline, recording at least one of the following by a debug counter: the copying parameters of the accelerated structure, the memory transfer information related to the accelerated structure, and the copying time required to copy the accelerated structure, to obtain statistical data.

[0012] In some embodiments, the step of recording ray tracing-related statistics by means of a debug counter during the execution of the ray tracing pipeline includes: during the execution of ray tracing pipeline traversal, recording at least one of ray tracing parameters and ray tracing commands by means of a debug counter to obtain statistical data.

[0013] In some embodiments, the step of outputting debugging information to the application layer for ray tracing debugging includes: storing the debugging information in a pre-allocated debugging buffer; mapping the debugging information in the debugging buffer to an application buffer accessible to the application layer; and passing the debugging information in the application buffer to the application layer for ray tracing debugging.

[0014] In some embodiments, the debug buffer includes a graphics processing unit (GPU) buffer, and the application buffer includes a central processing unit (CPU) buffer.

[0015] Secondly, this disclosure also provides a ray tracing debugging device, which includes: an interception and processing module, an information collection module, and an output module; wherein, the interception and processing module is used to intercept ray tracing rendering instructions in the command buffer and perform instruction expansion processing on the ray tracing rendering instructions to obtain processed instructions; the information collection module is used to collect ray tracing debugging information based on the processed instructions; and the output module is used to output the debugging information to the application layer for ray tracing debugging.

[0016] Thirdly, embodiments of this disclosure also provide a ray tracing debugging system, including the ray tracing debugging device as described in the second aspect of the above embodiments.

[0017] The information collection module of the system also includes: a graphics processor, wherein the graphics processor is used to execute the ray tracing pipeline; and a ray tracing debugging device is built into the graphics processor.

[0018] In some embodiments, the system further includes a central processing unit; wherein the ray tracing debugging device is further configured to send debugging information to the central processing unit; the central processing unit is configured to perform ray tracing debugging based on the debugging information.

[0019] Fourthly, embodiments of this disclosure provide an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the ray tracing debugging method as described in any implementation of the first aspect.

[0020] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer to implement the ray tracing debugging method as described in any implementation of the first aspect.

[0021] In a sixth aspect, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the ray tracing debugging method as described in any implementation of the first aspect.

[0022] This embodiment of the disclosure intercepts ray tracing rendering commands in the command buffer and performs command extension processing on the intercepted ray tracing rendering commands. This adds an information collection function to the original ray tracing rendering commands, allowing debugging information related to the ray tracing task to be collected based on the processed commands without interfering with the execution of the ray tracing task. Furthermore, by outputting the debugging information to the application layer used for ray tracing debugging, ray tracing debugging is achieved. Attached Figure Description

[0023] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart of a ray tracing debugging method provided in this disclosure embodiment; Figure 2 This is a schematic diagram illustrating the debugging of the entire lifecycle of ray tracing, as provided in an embodiment of this disclosure. Figure 3 A flowchart for collecting debugging information on ray traversal is provided as an embodiment of this disclosure; Figure 4 A flowchart for collecting debugging information of an acceleration structure is provided as an embodiment of this disclosure; Figure 5 A flowchart illustrating another method for debugging an acceleration structure provided in this disclosure; Figure 6 A flowchart illustrating another method for debugging ray traversal provided in this embodiment of the present disclosure; Figure 7 A structural block diagram of a ray tracing debugging device provided in an embodiment of this disclosure; Figure 8 A structural block diagram of a ray tracing debugging system provided in this disclosure embodiment; Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0025] In modern graphics processing systems, the overall architecture can be divided into a lower-level architecture layer and an upper-level application layer. The lower-level architecture layer can further include a driver layer and a hardware layer. The driver layer is the core component connecting the application layer and the hardware layer in the graphics system. The entire lifecycle of the acceleration structure, from construction to traversal, is completed within the driver and hardware layers, completely hidden from the upper-level application layer.

[0026] Specifically, under the existing Application Programming Interface (API) architecture, the construction process of accelerated structures is transparent to the application layer. The application layer initiates construction requests via API functions, but the intermediate states during the accelerated structure construction process are entirely handled internally by the driver and hardware layers, and are not exposed to the application layer. Similarly, statistical data such as specific node access paths and intersection counts during ray traversal are also completed internally by the driver and hardware layers and cannot be obtained through the standard API. Therefore, debugging tools that rely on API interception in related technologies can only record the input parameters of the application layer and the final output memory blocks of the accelerated structure, but cannot obtain the internal details of the accelerated structure construction, nor can they statistically analyze the performance metrics of the ray traversal process. This results in a lack of comprehensive monitoring of the accelerated structure construction and ray traversal processes, making it difficult for developers to locate performance bottlenecks related to the accelerated structure and to verify the effectiveness of the construction strategy.

[0027] Based on this, embodiments of this disclosure propose a ray tracing debugging method, which can be applied to the underlying architecture layer, where the underlying architecture layer refers to the system layer corresponding to the upper application layer. This underlying architecture layer deploys functional components, processors, or electronic devices that perform ray tracing. In some embodiments, the underlying architecture layer includes a hardware layer and a driver layer located between the hardware layers. The hardware layer deploys functional components, processors, or electronic devices that perform ray tracing, and the driver layer is used to drive and schedule the relevant components in the hardware layer; this disclosure does not limit the scope of the method.

[0028] Figure 1 This is a flowchart of a ray tracing debugging method provided in an embodiment of the present disclosure.

[0029] like Figure 1 As shown, the process 100 specifically includes the following steps: Step 101: Intercept ray tracing rendering commands in the command buffer and perform command expansion processing on the ray tracing rendering commands to obtain the processed commands.

[0030] Specifically, the command buffer is a memory area in a graphics processing system used to store execution instructions. Application-layer programs can record ray tracing tasks as instructions or commands into the command buffer through the graphics API, and then submit the command buffer to the underlying architecture layer, where the hardware reads and executes the instructions.

[0031] In this disclosure, intercepting ray tracing rendering instructions refers to intercepting the instruction stream along the instruction transmission path through a preset mechanism during the process of ray tracing rendering instructions being generated from the application layer and transmitted to the hardware processor of the underlying architecture layer for execution, thereby gaining temporary control over the ray tracing rendering instructions so as to parse, record, modify or enhance the ray tracing rendering instructions before they are executed by the hardware.

[0032] Interception points can be set in the command buffer or, depending on requirements, in other intermediate stages of instruction transmission, such as the graphics API call layer, the driver layer, or the final checkpoint before instructions are submitted to the hardware. Interception points can be embedded in any suitable layer of the system software stack, as long as that layer has access to the original instruction stream. The intercepted object is the ray tracing rendering instruction, which includes instructions such as initiating ray traversal, building acceleration structures, updating acceleration structures, and copying acceleration structures. These ray tracing rendering instructions typically exist in the form of data structures (such as API function call parameters or command buffer entries).

[0033] Instruction extension processing refers to adding additional functions without changing the original functionality of the instruction. In this disclosure, instruction extension processing refers to extending the original ray tracing rendering instruction to add a debugging information collection function. This enables the processed instruction to collect the debugging information required for the ray tracing execution process, allowing functional components in the underlying structure layer to extract relevant debugging information throughout the entire lifecycle of ray tracing execution. In some embodiments, instruction extension processing of ray tracing rendering instructions can be performed by modifying the original ray tracing rendering instruction. For example, the instruction flags, control fields, or execution parameters in the original ray tracing rendering instruction can be modified to enable the information collection function in the processed instruction. Alternatively, additional instructions for collecting information can be inserted into the ray tracing rendering instruction; this disclosure does not limit this approach.

[0034] Furthermore, after intercepting the ray tracing rendering instruction, a series of processes can be performed on the intercepted ray tracing rendering instruction, including but not limited to: parsing the parameters of the ray tracing rendering instruction to obtain its content, storing the instruction information of the ray tracing rendering instruction in a log or debug buffer, modifying the ray tracing rendering instruction, etc., which are not limited in this disclosure. The main purpose of interception is to inject additional control or data collection capabilities into the system without modifying the application code, such as collecting debugging information, monitoring performance, inserting synchronization points, or injecting fault tests.

[0035] Furthermore, the interception process is typically transparent to the upper application layer, which does not need to be aware of the interception logic. The processed instructions generated after interception are ultimately passed to the hardware for execution, ensuring that the original rendering task is not disturbed.

[0036] Step 102: Based on the processed instructions, collect debugging information for ray tracing.

[0037] Specifically, the post-processing instructions extend the original ray tracing rendering instructions and add information collection functionality. As a result, based on the post-processing instructions, the functional components that perform ray tracing in the underlying architecture layer can extract debugging information related to the entire lifecycle of the ray tracing execution process.

[0038] Step 103: Output the debugging information to the application layer used for ray tracing debugging.

[0039] Specifically, in this disclosure, the underlying architecture layer is used to implement low-level functions such as ray tracing logic, hardware interaction, instruction scheduling, accelerated structure construction, ray traversal, debugging information collection, and debugging buffer read / write. The upper application layer runs on top of the underlying architecture layer, facing the user or upper-level debugging tools, and does not directly control the underlying hardware or execute the core ray tracing calculation logic.

[0040] In this disclosure, the application layer used for ray tracing debugging is used to receive debugging information output from the underlying architecture layer. The debugging information is collected by the functional components that perform ray tracing in the underlying architecture layer and can be reported to the application layer through the driver layer in the underlying architecture layer. The application layer then receives, views, or parses the debugging information.

[0041] This disclosure intercepts ray tracing rendering commands in the command buffer and performs command extension processing on the intercepted ray tracing rendering commands. This adds an information collection function to the original ray tracing rendering commands, allowing for the collection of debugging information related to the ray tracing task without interfering with the execution of the ray tracing task. Furthermore, by outputting the debugging information to the application layer used for ray tracing debugging, ray tracing debugging is achieved. In related technologies, methods relying on external tools for ray tracing debugging lack comprehensive monitoring of the acceleration structure construction process and ray traversal process because the application layer cannot obtain debugging information from the underlying architecture layer. This disclosure can collect debugging information throughout the entire lifecycle of ray tracing, enabling complete debugging of the entire ray tracing lifecycle and quickly locating and resolving problems in ray tracing applications.

[0042] In some embodiments, the step of outputting debug information to the application layer for debugging ray tracing includes: storing the debug information in a pre-allocated debug buffer; mapping the debug information in the debug buffer to an application buffer accessible to the application layer; and passing the debug information in the application buffer to the application layer for debugging ray tracing.

[0043] Specifically, the debug buffer can be allocated and managed by the functional components that perform ray tracing in the underlying architecture layer (such as the driver layer) to collect ray tracing-related debug information in real time; the application buffer accessible to the application layer can be allocated by the application layer or a memory area that the application layer can safely access through the operating system mapping mechanism.

[0044] The debug buffer is a storage space within the functional component performing ray tracing, located at the lower-level architecture layer (such as the driver layer). The application layer and driver layer are strictly isolated, and the application layer cannot directly access any memory / video memory space (including the debug buffer) of the driver layer. Due to this isolation limitation, directly passing debug information from the debug buffer to the application layer will fail because the application layer lacks access permissions, thus preventing ray tracing debugging. Therefore, this disclosure first stores the debug information in a pre-allocated debug buffer, then maps the debug information in the debug buffer to an application buffer accessible to the application layer, and finally passes the debug information in the application buffer to the application layer used for ray tracing debugging. This effectively transfers debug information from the driver layer to the application layer, ensuring the normal implementation of the debugging function.

[0045] Specifically, before the ray tracing process starts, a memory space for debugging can be pre-allocated within the functional component that performs ray tracing as a debugging cache. The size and storage format of the debugging cache can be determined based on the debugging target, and this disclosure does not limit it.

[0046] Based on the processed instructions, the functional components performing ray tracing in the underlying architecture layer can extract debugging information throughout the entire lifecycle related to the ray tracing execution process. After collecting the debugging information, it can be written into a pre-allocated debugging buffer according to a preset storage format. In some embodiments, a direct write method can be used during storage, which ensures that the debugging information written to the debugging buffer is consistent with the debugging information obtained from the processed instructions, thereby improving the accuracy of ray tracing debugging. In other embodiments, the debugging information can also be processed during storage, such as data conversion and compression, to reduce the size of the debugging buffer occupied by the debugging information.

[0047] After storing debug information in the debug buffer at the underlying architecture layer, a memory mapping from the debug buffer to the application buffer is triggered. Through a pre-defined memory mapping interface, all debug information stored in the debug buffer is read and synchronously mapped to the prepared application buffer in raw data form. During this mapping process, no additional processing such as modification, filtering, or encryption of the debug information is performed, ensuring complete consistency between the debug information in the application buffer and the debug buffer. Furthermore, the mapping operation does not affect the storage state of the driver-layer debug buffer, nor does it interfere with the normal execution flow of the ray tracing functional components.

[0048] This disclosure achieves effective transmission of debugging information from the underlying architecture layer to the upper application layer and ensures the normal implementation of debugging functions by first storing debugging information in a pre-allocated debugging buffer and then mapping the debugging information in the debugging buffer to the application buffer.

[0049] Furthermore, in some embodiments, the debug buffer includes a graphics processing unit (GPU) buffer, and the application buffer includes a central processing unit (CPU) buffer.

[0050] Specifically, since the core computations of ray tracing (such as accelerating structure construction and ray traversal) are mainly performed by the GPU in the underlying architecture layer, the driver layer in the underlying architecture layer stores debugging information in the GPU buffer, enabling fast storage and retrieval of debugging information to meet the high-speed computational requirements of ray tracing. The CPU buffer, on the other hand, is a memory space directly accessible to the application layer and is compatible with the application layer's software execution logic. It enables stable reception and relay of debugging information, and then the debugging information in the CPU buffer (i.e., the application buffer) is passed to the application layer used for ray tracing debugging. This ensures that debugging information is effectively transferred from the GPU buffer to the application layer, guaranteeing the normal implementation of debugging functions.

[0051] In some embodiments, the command buffer includes ray tracing rendering instructions. The steps of intercepting ray tracing rendering instructions in the command buffer and performing instruction expansion processing on the ray tracing rendering instructions to obtain processed instructions include: intercepting application layer calls to ray tracing application programming interface (API) functions in the command buffer to achieve interception of ray tracing rendering instructions in the command buffer; and in response to the interception of the API function call, inserting additional instructions for collecting debugging information into the command buffer to obtain processed instructions containing ray tracing rendering instructions and additional instructions.

[0052] Specifically, the command buffer acts as an intermediary for instruction transmission between the driver layer and the application layer in the underlying architecture layer. It is used to receive various ray tracing-related instructions issued by the application layer, including ray tracing rendering instructions used to drive the GPU to perform ray tracing core calculations. These ray tracing rendering instructions are issued by the application layer through ray tracing application programming interface (API) function calls to instruct the GPU to perform specific ray tracing rendering operations. The command buffer temporarily stores and schedules these ray tracing rendering instructions to ensure that the instructions are issued to the GPU for execution in a preset order.

[0053] To collect debugging information, ray tracing rendering commands need to be intercepted in the command buffer and processed so that the processed commands can collect debugging information during the ray tracing process.

[0054] The functional components that perform ray tracing, such as the GPU, can monitor the command buffer in real time. When the application layer issues ray tracing rendering instructions to the command buffer—that is, when the application layer issues instructions by calling the ray tracing application programming interface (API) function—this API function call is intercepted in the command buffer. This interception operation only captures the API function call; it does not modify the API function itself, interrupt the normal instruction scheduling process of the command buffer, or affect the core logic of the ray tracing rendering instructions.

[0055] After intercepting the API function call, additional instructions for collecting debugging information are inserted into the command buffer at a preset position corresponding to the ray tracing rendering instruction. These additional instructions can cover all aspects required for collecting debugging information, enabling the collection of debugging information throughout the entire ray tracing lifecycle and thus achieving complete debugging of the entire ray tracing lifecycle. For example, these additional instructions can be identification instructions for identifying the collection of debugging information, control instructions for specifying the collection type or timing, configuration instructions for configuring collection parameters or the collection range, trigger instructions for triggering information reporting or storage, etc., and this disclosure does not limit their scope. Furthermore, the preset position can be a location that does not affect the execution order and logic of the ray tracing rendering instructions, such as inserting additional instructions after the ray tracing rendering instructions, and this disclosure does not limit their scope either.

[0056] After inserting additional instructions, the command buffer forms a processed instruction containing the original ray tracing rendering instructions and additional instructions. The processed instruction is based on the ray tracing rendering instructions, and the additional instructions are only used as auxiliary instructions. They are sent to the ray tracing function components for execution along with the ray tracing rendering instructions, ensuring that debugging information is collected and stored in the pre-set GPU buffer (debugging buffer) while completing ray tracing rendering.

[0057] This embodiment of the disclosure intercepts the application layer's calls to ray tracing API functions in the command buffer and inserts additional instructions for collecting debugging information into the command buffer, ensuring that debugging information is collected simultaneously while ray tracing rendering is completed, thereby enabling debugging of ray tracing based on the debugging information.

[0058] Furthermore, in some embodiments, the step of collecting ray tracing debugging information based on processed instructions includes: executing the ray tracing pipeline based on ray tracing rendering instructions; and collecting debugging information during the execution of the ray tracing pipeline based on additional instructions.

[0059] Specifically, the ray tracing function component, based on the processed instructions (including ray tracing rendering instructions and additional instructions) generated in the command buffer, prioritizes the ray tracing rendering instructions in the processed instructions to execute the complete ray tracing pipeline. The ray tracing pipeline covers the entire process of core ray tracing calculations, including but not limited to accelerating structure construction, accelerating structure updates, accelerating structure replication, ray traversal, and ray-primitive intersection. The execution process is based on the preset logic of the ray tracing rendering instructions to ensure the normal implementation of the ray tracing rendering function.

[0060] During the execution of the ray tracing pipeline by the ray tracing function component, additional instructions in the processed instructions are responded to synchronously, and debugging information is collected according to the preset requirements of the additional instructions. The collected debugging information corresponds one-to-one with the execution status of the ray tracing rendering instructions, specifically including but not limited to: node partitioning parameters and bounding box coordinate information during the accelerated structure construction process; node access sequence and intersection test results during ray traversal; and intersection point coordinates and intersection time during ray-primitive intersection. Furthermore, the debugging information collection process only synchronously extracts the raw state data during pipeline execution and does not interfere with the normal execution of the ray tracing pipeline, nor does it modify the pipeline execution results.

[0061] This disclosure ensures the accuracy of the collected debugging information by collecting it during the execution of the ray tracing pipeline, without affecting the normal execution of the ray tracing pipeline.

[0062] In some embodiments, the ray tracing pipeline is bound to a pre-allocated debug buffer, and the step of collecting debug information during the execution of the ray tracing pipeline includes: determining debug information by executing the ray tracing pipeline, and collecting debug information by writing the debug information into the pre-allocated debug buffer.

[0063] Specifically, before the ray tracing process starts, a memory space for debugging can be pre-allocated within the functional component that performs ray tracing as a debugging cache. The size and storage format of the debugging cache can be determined based on the debugging target, and this disclosure does not limit it.

[0064] A debug buffer is a pre-allocated buffer within a functional component that performs ray tracing, such as a GPU buffer. The ray tracing pipeline is a complete computational process involving ray tracing executed by the functional component (such as the GPU). The pre-allocated debug buffer (GPU buffer) is used only to store ray tracing-related debug information. Binding operations can clearly define the unique correspondence between the ray tracing pipeline and this debug buffer, preventing debug information collected by the ray tracing pipeline from being written to other unrelated memory spaces, and also preventing other unrelated data from being written to the debug buffer, thereby ensuring the accuracy and integrity of the debug information stored in the debug buffer.

[0065] One approach is to bind a pre-allocated debug buffer (such as a GPU buffer) to the ray tracing pipeline before initializing the pipeline, so that the pipeline can directly access the debug buffer and perform write operations.

[0066] This embodiment of the disclosure improves the storage efficiency of debugging information by pre-binding a pre-allocated debug buffer to the ray tracing pipeline, enabling the collected debugging information to be quickly located and stored in the pre-allocated debug buffer during the execution of the ray tracing pipeline.

[0067] Furthermore, in some embodiments, the step of determining debugging information by executing the ray tracing pipeline includes: during the execution of the ray tracing pipeline, recording ray tracing-related statistical data through a debugging counter, the statistical data being used to characterize the operational features of ray tracing; reading the statistical data from the debugging counter to determine debugging information related to ray tracing.

[0068] Specifically, the ray tracing pipeline generates a large amount of related data during execution. Collecting all of this data as debugging information would occupy a large buffer, reduce the execution efficiency of ray tracing, and be unsuitable for debugging. Therefore, this disclosure can collect a portion of the data generated during the execution of the ray tracing pipeline using a debug counter as debugging information.

[0069] The debug counter can be built into the functional components performing ray tracing, such as within the GPU. The debug counter records ray tracing-related statistics based on preset debug fields. In some embodiments, debug fields can be pre-set based on the debug type, and these debug counter fields indicate the debug information the debug counter needs to record. Different debug task types correspond to different debug fields. In other embodiments, debug fields can also be pre-set based on debug precision. Higher debug precision requires more debug information, thus allowing for more debug fields to be set; this disclosure does not limit this. Additionally, debug fields for the debug counter can be added to the ray tracing scheduling information structure, and the debug counter collects corresponding debug information based on these debug fields.

[0070] This disclosure uses a debug counter to record ray tracing-related statistical data, and then reads the statistical data from the debug counter as debug information. This allows only information relevant to ray tracing debugging to be collected, reducing the storage space required for debug information and improving the efficiency of ray tracing debugging based on debug information. The debug information collected in this disclosure can include detailed information about the entire lifecycle of ray tracing, enabling debugging throughout the entire ray tracing lifecycle.

[0071] Figure 2 This is a schematic diagram illustrating the debugging of the entire lifecycle of ray tracing, as provided in an embodiment of this disclosure.

[0072] like Figure 2 As shown, ray tracing debugging includes: Step 201: Debugging the acceleration structure.

[0073] Step 202: Adjusting the ray traversal.

[0074] Step 203: Collect and output debugging information.

[0075] In this process, steps 201 and 202 can be executed by either step 201 or step 202 depending on the debugging requirements, or both steps 201 and 202 can be executed. This disclosure does not limit this.

[0076] In some embodiments, step 201 of debugging the acceleration structure further includes: Step 211: Accelerate structure construction.

[0077] Step 221: Accelerate structural updates.

[0078] Step 231: Accelerate structure replication.

[0079] Steps 211, 221 and 231 may be performed in one or more of them according to debugging requirements, and this disclosure does not limit them.

[0080] In some embodiments, step 202, adjusting the ray traversal, further includes: Step 212: Modify the ray traversal shader.

[0081] Step 222: Command generation and execution.

[0082] Steps 212 and 222 may be performed in one or more of the following steps, depending on the debugging requirements, and this disclosure does not limit them.

[0083] Specifically, debugging the acceleration structure includes debugging the construction, updating, and copying of the acceleration structure. Debugging ray traversal includes debugging the modification of the ray traversal shader and the process of command generation and execution.

[0084] In each of the debugging processes—debugging the accelerated structure construction, debugging the accelerated structure update, debugging the accelerated structure copy, debugging the modification of the ray traversal shader, and debugging the command generation and execution—the corresponding ray tracing operation must be executed first. Then, during the execution of the ray tracing operation, the corresponding debugging information is collected and output to complete the corresponding debugging.

[0085] Figure 3 This is a flowchart illustrating the collection of debugging information for ray traversal, as provided in an embodiment of this disclosure.

[0086] like Figure 3 As shown, the steps for collecting debugging information for ray traversal include: Step 301: Ray tracing traversal.

[0087] Step 302: Debug counter integration. Specifically, a debug counter can be set in the functional component performing ray tracing to collect debug information during ray tracing traversal.

[0088] Step 303: Debug Resource Binding. Specifically, the debug counter is bound to the debug resource, thereby caching the debug information collected by the debug counter during ray tracing into the debug resource. The debug resource may include a debug buffer related to debugging and a constant buffer related to ray tracing.

[0089] Step 304: Debug buffer allocation.

[0090] Step 305: Configure constant buffer.

[0091] The debug resources may include debug buffers related to debugging and constant buffers related to performing ray tracing. During the resource binding process in step 303, a debug counter can be bound to the debug buffer.

[0092] Step 306: GPU memory pre-allocation. Specifically, the functional component performing ray tracing can be the GPU. A block of GPU memory can be pre-allocated as a debug buffer to store debug information, and the pre-allocated GPU memory is bound to the ray tracing process.

[0093] Step 307: CPU Memory Mapping. Specifically, since upper-layer applications cannot directly access GPU memory, it is also necessary to map the debugging information in GPU memory to CPU memory.

[0094] Step 308: Debug Information Collection. Specifically, debugging information from the CPU can be used to debug the acceleration structure during ray tracing.

[0095] Figure 4 This is a flowchart illustrating the collection of debugging information for an acceleration structure, as provided in an embodiment of this disclosure.

[0096] like Figure 4 As shown, the steps for collecting debugging information for the acceleration structure include: Step 401: Accelerate structure construction.

[0097] Step 402: Accelerate structure updates.

[0098] Step 403: Accelerate structure replication.

[0099] Steps 401 to 403 can be selectively executed based on debugging needs. Specifically, if only debugging of the accelerated structure construction is required, only step 401 can be executed, without executing steps 402 and 403.

[0100] Step 404: Debug the counter integration.

[0101] Step 405: Debug resource binding.

[0102] Step 406: GPU memory pre-allocation.

[0103] Step 407: CPU memory mapping.

[0104] Step 408: Debugging information collection.

[0105] Among them, steps 404 to 408 and Figure 3 The corresponding parts of the embodiments are similar and will not be repeated here.

[0106] The debugging information collected in this disclosure may include detailed information about the entire lifecycle of ray tracing. The debugging information differs for different stages of ray tracing. The following embodiments describe the specific debugging information for each process.

[0107] In some embodiments, the step of recording ray tracing-related statistics by using a debug counter during the ray tracing pipeline includes: during the acceleration structure construction process, recording at least one of the following by using a debug counter: the construction parameters for building the acceleration structure, the total number of nodes in the acceleration structure, the storage tree depth information of the acceleration structure, and the construction time required to build the acceleration structure, thereby obtaining statistical data.

[0108] Specifically, the construction parameters of an acceleration structure refer to the configuration items or hyperparameters passed in when constructing the acceleration structure, used to control its construction. In summary, these construction parameters include the acceleration structure type, segmentation strategy, construction algorithm type, and maximum leaf node size.

[0109] The total number of nodes in an accelerated structure refers to the total number of nodes in the accelerated structure after its construction. The total number of nodes in an accelerated structure can reflect its complexity; a higher number of nodes usually results in greater memory usage, but may lead to higher traversal accuracy.

[0110] The storage tree depth information of the acceleration structure is used to describe the hierarchical distribution of the acceleration structure. This storage tree depth information may include information such as maximum depth, average depth, and a depth distribution histogram.

[0111] The build time required to build an accelerated structure refers to the total time from initiating the accelerated structure build to completion, and can be used to evaluate the build efficiency of the accelerated structure.

[0112] This disclosure embodiment records at least one of the following in the accelerated structure construction parameters, total number of nodes, storage tree depth information, and construction time required to construct the accelerated structure using a debug counter, thereby obtaining debug information that allows for performance debugging of the accelerated structure construction based on this debug information.

[0113] In some embodiments, the step of recording ray tracing-related statistical data by a debug counter during the ray tracing pipeline includes: during the acceleration structure update process, recording at least one of the following by a debug counter: update parameters of the acceleration structure, modification nodes that need to be modified in the acceleration structure, update time required to update the acceleration structure, and reconstruction operation information related to the reconstruction of the acceleration structure, to obtain statistical data.

[0114] Specifically, update parameters refer to the input configuration options set to control the behavior of accelerated structure updates. They determine the specific execution method of the update operation and are considered control variables. Update parameters may include: update mode (e.g., fast update or complete reconstruction), change threshold (e.g., setting a threshold for geometric displacement or deformation; when the change exceeds this threshold, an update is performed), parallelism control (limiting the number of GPU threads or resource allocation used for update operations), and update scope (e.g., updating only the accelerated structure of dynamic objects or updating the entire scene's accelerated structure).

[0115] Modified nodes refer to nodes in the accelerated structure whose bounding boxes or contents are actually modified during the update process. Modified nodes include leaf nodes, internal nodes, and added / deleted nodes. Modified nodes are used to record the update process and belong to the output / observation data of the update operation.

[0116] Update time refers to the length of time it takes to complete an accelerated structural update, and is used to measure update performance.

[0117] Refactoring operation information refers to the additional diagnostic information recorded when an update triggers a full refactoring. This information helps developers understand why the refactoring occurred and its impact on the quality of the accelerated structure. The refactoring operation information includes at least one of the following: the reason for the refactoring, the refactoring parameters, a comparison of the accelerated structure before and after the refactoring, and the refactoring time.

[0118] This disclosure achieves accurate debugging of accelerated structure updates by recording information such as update parameters, modified nodes, update time, and reconstruction operation information during the accelerated structure update process.

[0119] In some embodiments, the step of recording ray tracing-related statistics by a debug counter during the ray tracing pipeline's ray tracing process includes: during the ray tracing pipeline's accelerated structure replication process, recording at least one of the replication parameters of the replicated accelerated structure, memory transfer information related to the replicated accelerated structure, and replication time required for the replicated accelerated structure by a debug counter to obtain statistical data.

[0120] Specifically, the replication parameters in the accelerated structure replication process refer to the input configuration options set by the developer or driver to control the accelerated structure replication operation. These replication parameters may include source and target resources (i.e., the source accelerated structure to be replicated and the target location), replication mode (including full replication or partial replication, etc.), and replication target, etc.

[0121] Memory transfer information describes the details of the underlying data transfers that actually occur during the copying process, including transfer size, transfer direction, and memory bandwidth usage.

[0122] Replication time refers to the length of time it takes to complete the entire replication operation, and can be used to measure the performance of replication acceleration structures.

[0123] This disclosure embodiment records at least one of the following as debugging information during the accelerated structure replication process performed by the ray tracing pipeline: replication parameters, memory transfer information, and replication time. Based on this debugging information, accurate debugging of the replication acceleration structure can be achieved.

[0124] In some embodiments, the step of recording ray tracing-related statistics by means of a debug counter during the ray tracing pipeline includes: during the ray tracing pipeline traversal, recording at least one of the ray tracing parameters and ray tracing commands by means of a debug counter to obtain statistical data.

[0125] Specifically, ray tracing parameters refer to the attributes or state variables directly related to each ray during ray generation, traversal, and intersection. Ray tracing parameters can be set by the application through shaders or APIs and are used by hardware or software during ray traversal. Ray tracing parameters include at least one of the following: ray geometry properties (such as ray origin, ray direction, ray type, etc.), ray payload (such as color, importance, recursion depth, etc.), traversal control parameters (including ray mask, ray flag, etc.), and ray source information.

[0126] Ray tracing commands are instructions or calls that initiate or control ray traversal in the ray tracing pipeline, including API-level commands, shader-level commands, etc.

[0127] This disclosure obtains debugging information by recording at least one of the ray tracing parameters and ray tracing commands during the execution of ray tracing in the ray tracing pipeline. This debugging information includes a complete view from the macroscopic command level to the microscopic ray level, and based on this information, performance bottlenecks and algorithmic defects in the ray tracing process can be accurately located.

[0128] Figure 5 A flowchart illustrating another method for debugging an acceleration structure provided in this disclosure.

[0129] like Figure 5 As shown, the method specifically includes the following steps: Step 501: Start the accelerated structural debugging process.

[0130] Step 502: Initialize the debug counter.

[0131] Step 503: Allocate a debug buffer.

[0132] Step 504: Bind debug resources.

[0133] Step 505: Determine the type of acceleration structure operation.

[0134] In the case of accelerating structure operation type being accelerated structure construction, steps 516 to 556 are executed.

[0135] Step 516: Debug build.

[0136] Step 526: Capture build parameters.

[0137] Step 536: Record the number of nodes.

[0138] Step 546: Store tree depth information.

[0139] Step 556: Record the build time.

[0140] In step 505, if the accelerated structure operation type is accelerated structure update, steps 517 to 557 are executed.

[0141] Step 517: Debug update.

[0142] Step 527: Capture update parameters.

[0143] Step 537: Record the modified node.

[0144] Step 547: Record the update time.

[0145] Step 557: Track the refactoring operation.

[0146] In step 505, if the accelerated structure operation type is accelerated structure replication, steps 518 to 548 are executed.

[0147] Step 518: Debug copying.

[0148] Step 528: Capture copy parameters.

[0149] Step 538: Record memory transfers.

[0150] Step 548: Record the copy time.

[0151] After completing steps 556, 557, or 548, continue with steps 509 to 530.

[0152] Step 509: Write debug data.

[0153] Step 510: Refresh the debug cache.

[0154] Step 520: Update the debug counter.

[0155] Step 530: End the accelerated structure debugging process.

[0156] The specific processes in this embodiment are similar to those in the corresponding embodiments described above, and will not be repeated here.

[0157] Figure 6 This is a flowchart of another method for debugging ray traversal provided in this embodiment of the present disclosure.

[0158] like Figure 6 As shown, the method specifically includes the following steps: Step 601: Start traversal and debugging.

[0159] Step 602: Initialize debug resources.

[0160] Step 603: Determine the type of ray tracing operation.

[0161] Ray tracing types include ray distribution and ray query. When the ray tracing type is ray distribution, step 604 is executed; when the ray tracing type is ray query, step 605 is executed.

[0162] Step 604: Process light distribution.

[0163] Step 605: Process the ray query.

[0164] After completing step 604 or step 605, continue with steps 606 to 609.

[0165] Step 606: Record ray tracing parameters.

[0166] Step 607: Send ray tracing command.

[0167] Step 608: Write debug data.

[0168] Step 609: Parse the debugging data.

[0169] The specific process in this embodiment is the same as described above. Figure 5 The corresponding implementations have a similar framework, the only difference being the operation type and the specific debugging information obtained, which will not be repeated here.

[0170] The embodiments provided in this disclosure integrate debugging functionality into the ray tracing functional components. Debug commands are intercepted and processed through a command buffer, and memory management and allocation for debugging purposes are added, including pre-allocation of GPU memory as a debug buffer and CPU mapping. A debug counter field is added to the ray tracing scheduling information structure, allowing for the collection of debug counter information. Debugging functionality is implemented by binding the debug counter to debug resources (including debug buffers and constant buffers).

[0171] This disclosure achieves accelerated collection of debugging information by intercepting and processing debugging commands in the command buffer, and rewriting key methods such as accelerating structure construction, accelerating structure updating, and accelerating structure copying.

[0172] Furthermore, this disclosure not only supports debugging information related to acceleration structures but also supports debugging data collection during ray traversal, enabling a dual collection mechanism that simultaneously collects acceleration structure information and ray traversal information. This disclosure supports collecting detailed information throughout the entire lifecycle of acceleration structure construction, updates, and ray traversal, enabling complete debugging of the entire ray tracing lifecycle. Specifically, it can collect corresponding debugging data for different ray tracing operations, such as DispatchRays (ray distribution / scheduling) and RayQuery (ray query). This disclosure supports fine-grained configuration based on acceleration structure type and debugging information type, allowing selective information collection as needed. This disclosure enables multi-level, multi-type debugging configuration strategies.

[0173] The embodiments provided in this disclosure can achieve more comprehensive debugging functions. In addition to supporting the collection of debugging information for accelerated structures, they also support the collection of debugging information during ray traversal. Furthermore, they support multi-dimensional debugging configuration options, allowing developers to precisely control the scope and level of detail of debugging information collection according to specific needs, thereby avoiding unnecessary performance impact.

[0174] Based on the same inventive concept as the above-described debugging method, this disclosure also provides a ray tracing debugging device.

[0175] Figure 7 This is a structural block diagram of a ray tracing debugging device provided in an embodiment of the present disclosure.

[0176] Further reference Figure 7 As an implementation of the methods shown in the above figures, this device embodiment is similar to... Figure 1 Corresponding to the method embodiments shown, the device can be specifically applied to functional components, processors, or various electronic devices that perform ray tracing deployed in the underlying architecture layer.

[0177] like Figure 7 As shown, the ray tracing debugging device in this embodiment includes: an interception and processing module 701, an information collection module 702, and an output module 703. The interception and processing module 701 intercepts ray tracing rendering commands in the command buffer and performs command expansion processing on the ray tracing rendering commands to obtain processed commands; the information collection module 702 collects ray tracing debugging information based on the processed commands; and the output module 703 outputs the debugging information to the application layer used for ray tracing debugging.

[0178] In this embodiment, the specific processing of the interception and processing module 701, the information collection module 702, and the output module 703 in the ray tracing debugging device, and the resulting technical effects, can be found in reference to [reference needed]. Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0179] The ray tracing debugging apparatus provided in this disclosure intercepts ray tracing rendering commands in the command buffer and performs command extension processing on the intercepted ray tracing rendering commands. This adds an information collection function to the original ray tracing rendering commands, enabling the collection of debugging information related to the ray tracing task based on the processed commands without interfering with the execution of the ray tracing task. Furthermore, by outputting the debugging information to the application layer used for ray tracing debugging, ray tracing debugging is achieved.

[0180] In some embodiments, the command buffer includes ray tracing rendering instructions. The interception and processing module 701 is specifically configured to: intercept calls to ray tracing application programming interface (API) functions at the application layer in the command buffer, thereby intercepting ray tracing rendering instructions in the command buffer; wherein, the ray tracing API functions correspond to the ray tracing rendering instructions in the command buffer; in response to intercepting the call, insert additional instructions for collecting debugging information into the command buffer to obtain processed instructions containing ray tracing rendering instructions and additional instructions.

[0181] In some embodiments, the information collection module 702 is specifically used to: execute the ray tracing pipeline based on ray tracing rendering instructions; and collect debugging information during the execution of the ray tracing pipeline based on additional instructions.

[0182] In some embodiments, the ray tracing pipeline is bound to a pre-allocated debug buffer; the information collection module 702 is further configured to: collect debug information by executing the ray tracing pipeline, and collect debug information by writing the debug information into the pre-allocated debug buffer bound to the ray tracing pipeline.

[0183] In some embodiments, the information collection module 702 is further configured to: record ray tracing-related statistical data through a debug counter during the execution of the ray tracing pipeline, the statistical data being used to characterize the operating characteristics of ray tracing; and read the statistical data from the debug counter to determine debug information related to ray tracing.

[0184] In some embodiments, the information collection module 702 is further configured to: during the process of building the accelerated structure in the ray tracing pipeline, record at least one of the following through a debug counter: the construction parameters for building the accelerated structure, the total number of nodes in the accelerated structure, the storage tree depth information of the accelerated structure, and the construction time required to build the accelerated structure, thereby obtaining statistical data.

[0185] In some embodiments, the information collection module 702 is further configured to: during the process of the ray tracing pipeline performing an acceleration structure update, record at least one of the following through a debug counter: the update parameters of the acceleration structure, the modification nodes that need to be modified in the acceleration structure, the update time required to update the acceleration structure, and the reconstruction operation information related to the reconstruction of the acceleration structure, and obtain statistical data.

[0186] In some embodiments, the information collection module 702 is further configured to: during the process of copying the accelerated structure in the ray tracing pipeline, record at least one of the following by using a debug counter: the copying parameters of the accelerated structure, the memory transfer information related to the accelerated structure, and the copying time required to copy the accelerated structure, to obtain statistical data.

[0187] In some embodiments, the information collection module 702 is further configured to: record at least one of the ray tracing parameters and ray tracing commands by a debug counter during the ray tracing pipeline's ray tracing process to obtain statistical data.

[0188] In some embodiments, the output module 703 is specifically used to: store debugging information in a pre-set debugging buffer; map the debugging information in the debugging buffer to an application buffer accessible to the application layer; and pass the debugging information in the application buffer to the application layer for debugging ray tracing.

[0189] In some embodiments, the debug buffer includes a graphics processing unit (GPU) buffer, and the application buffer includes a central processing unit (CPU) buffer.

[0190] The specific implementation details and technical effects of the ray tracing debugging device embodiments provided in this disclosure are the same as the implementation details and technical effects of the ray tracing debugging method embodiments described above, and will not be repeated here.

[0191] This embodiment exists as a device embodiment corresponding to the method embodiment described above. The ray tracing debugging device provided in this embodiment intercepts ray tracing rendering commands in the command buffer and performs command extension processing on the intercepted ray tracing rendering commands. This adds an information collection function to the original ray tracing rendering commands, allowing debugging information related to the ray tracing task to be collected based on the processed commands without interfering with the execution of the ray tracing task. Furthermore, by outputting the debugging information to the application layer used for ray tracing debugging, ray tracing debugging is achieved.

[0192] The ray tracing debugging device provided in this embodiment supports fine-grained configuration according to the acceleration structure type and debugging information type, allowing selective information collection as needed.

[0193] Furthermore, this disclosure also provides a ray tracing debugging system.

[0194] Figure 8 This is a structural block diagram of a ray tracing debugging system provided in an embodiment of the present disclosure.

[0195] like Figure 8 As shown, the system includes a ray tracing debugging device 801 and a graphics processor 802. The ray tracing debugging device 801 can be any of the aforementioned device embodiments. The graphics processor is used by 802 to execute the ray tracing pipeline; and the ray tracing debugging device 801 is built into the graphics processor 802.

[0196] In some embodiments, the system further includes a central processing unit 803; wherein the ray tracing debugging device 801 is further configured to send debugging information to the central processing unit; and the central processing unit 803 is configured to perform ray tracing debugging based on the debugging information.

[0197] For specific details in this embodiment, please refer to the above embodiment of the ray tracing debugging device, which will not be repeated here.

[0198] The ray tracing debugging system provided in this embodiment supports fine-grained configuration according to acceleration structure type and debugging information type, allowing selective information collection as needed.

[0199] According to embodiments of the present disclosure, the present disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the ray tracing debugging method described in any of the above embodiments when executed.

[0200] Figure 9 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 9 As shown, the electronic device 900 of this embodiment includes a processor 901 and a memory 902; wherein, the memory 902 is used to store computer execution instructions; the processor 901 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the electronic device in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments. For example, the electronic device 900 can be a general-purpose processor, a graphics processing device, a neural network computing device, or a graph neural network computing device.

[0201] In some embodiments, the memory 902 can be either standalone or integrated with the processor 901.

[0202] When the memory 902 is set up independently, the electronic device also includes a bus 903 for connecting the memory 902 and the processor 901.

[0203] It should be understood that the processor 901 described above can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0204] The memory 902 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0205] Bus 903 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0206] This disclosure also provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the steps of the ray tracing debugging method in any of the above method embodiments.

[0207] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the ray tracing debugging method according to any of the above embodiments.

[0208] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0209] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0210] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The aforementioned modular unit can be implemented in hardware or in a combination of hardware and software functional units.

[0211] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods in the various embodiments of this application.

[0212] The aforementioned storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0213] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in application-specific integrated circuits (ASICs). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0214] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0215] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0216] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0217] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A ray tracing debugging method, characterized in that, The method includes: Intercept ray tracing rendering commands in the command buffer and perform command expansion processing on the ray tracing rendering commands to obtain processed commands; Based on the processed instructions, collect debugging information for ray tracing; The debugging information is output to the application layer used for ray tracing debugging.

2. The method according to claim 1, characterized in that, The command buffer includes the ray tracing rendering instructions; The step of intercepting ray tracing rendering commands in the command buffer and performing command expansion processing on the ray tracing rendering commands to obtain processed commands includes: The application layer calls to ray tracing application programming interface (API) functions are intercepted in the command buffer to intercept the ray tracing rendering instructions in the command buffer; wherein, the ray tracing API functions correspond to the ray tracing rendering instructions in the command buffer. In response to the interception of an API function call, additional instructions for collecting debugging information are inserted into the command buffer, resulting in a processed instruction containing the ray tracing rendering instructions and the additional instructions.

3. The method according to claim 2, characterized in that, The process of collecting ray tracing debugging information based on the processed instructions includes: Based on the ray tracing rendering instructions, the ray tracing pipeline is executed; Based on the additional instructions, debugging information is collected during the execution of the ray tracing pipeline.

4. The method according to claim 3, characterized in that, The ray tracing pipeline is bound to a pre-allocated debug buffer; The collection of debugging information during the execution of the ray tracing pipeline includes: The debugging information is determined by executing the ray tracing pipeline and collected by writing the debugging information into the pre-allocated debugging buffer.

5. The method according to claim 4, characterized in that, The process of determining debugging information by executing the ray tracing pipeline includes: During the execution of the ray tracing pipeline, a debug counter records ray tracing-related statistical data, which is used to characterize the operational features of ray tracing. The statistical data is read from the debug counter to determine the debug information.

6. The method according to claim 5, characterized in that, During the execution of the ray tracing pipeline, ray tracing-related statistical data is recorded by debugging counters, including: During the process of building the accelerated structure in the ray tracing pipeline, at least one of the following is recorded by a debug counter: the construction parameters for building the accelerated structure, the total number of nodes in the accelerated structure, the storage tree depth information of the accelerated structure, and the construction time required to build the accelerated structure, so as to obtain the statistical data.

7. The method according to claim 5, characterized in that, During the execution of the ray tracing pipeline, ray tracing-related statistical data is recorded by debugging counters, including: During the process of accelerating structure updates in the ray tracing pipeline, at least one of the following is recorded by a debug counter: the update parameters of the accelerating structure, the modification nodes that need to be modified in the accelerating structure, the update time required to update the accelerating structure, and the reconstruction operation information related to the reconstruction of the accelerating structure, to obtain the statistical data.

8. The method according to claim 5, characterized in that, During the execution of the ray tracing pipeline, ray tracing-related statistical data is recorded by debugging counters, including: During the process of copying the accelerated structure in the ray tracing pipeline, at least one of the following is recorded by debugging a counter: the copying parameters of the accelerated structure, the memory transfer information related to the copying of the accelerated structure, and the copying time required to copy the accelerated structure, to obtain the statistical data.

9. The method according to claim 5, characterized in that, During the execution of the ray tracing pipeline, ray tracing-related statistical data is recorded by debugging counters, including: During the ray traversal process of the ray tracing pipeline, at least one of the ray tracing parameters and ray tracing commands is recorded by a debug counter to obtain the statistical data.

10. The method according to any one of claims 1-9, characterized in that, The step of outputting the debugging information to the application layer for ray tracing debugging includes: The debugging information is stored in a pre-allocated debugging buffer; Map the debugging information in the debugging buffer to the application buffer accessible at the application layer; The debugging information in the application buffer is passed to the application layer used for ray tracing debugging.

11. The method according to claim 10, characterized in that, The debug buffer includes a graphics processing unit (GPU) buffer, and the application buffer includes a central processing unit (CPU) buffer.

12. A ray tracing debugging device, characterized in that, The device includes: The interception and processing module is used to intercept ray tracing rendering commands in the command buffer and perform command expansion processing on the ray tracing rendering commands to obtain processed commands. An information collection module is used to collect ray tracing debugging information based on the processed instructions; The output module is used to output the debugging information to the application layer used for ray tracing debugging.

13. A ray tracing debugging system, characterized in that, Includes the ray tracing debugging device as described in claim 12.

14. The debugging system according to claim 13, characterized in that, The system also includes: A graphics processing unit (GPU) for executing the ray tracing pipeline; wherein the ray tracing debugging device is built into the GPU.

15. The debugging system according to claim 13, characterized in that, The system also includes: CPU; The ray tracing debugging device is also used to send the debugging information to the central processing unit; The central processing unit is used to perform ray tracing debugging based on the debugging information.

16. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the ray tracing debugging method according to any one of claims 1-11.

17. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the ray tracing debugging method according to any one of claims 1-11.

18. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the steps of the ray tracing debugging method according to any one of claims 1-11.

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