Semiconductor memory device

Abstract

Embodiments of the present application provide a semiconductor memory device capable of high integration. The semiconductor memory device of the embodiments includes a plurality of memory block regions arranged in a first direction; a wiring region arranged in the first direction with respect to the plurality of memory block regions; and a wiring region extending in the first direction and arranged in a second direction intersecting the first direction with the plurality of memory block regions and the wiring region. The plurality of memory block regions each includes a plurality of memory strings extending in the first direction and arranged in the second direction, and a first wiring extending in the second direction and commonly connected to the plurality of memory strings. The wiring region includes a second wiring extending in the first direction and commonly connected to a plurality of the first wirings corresponding to the plurality of memory block regions. The wiring region includes a third wiring electrically connected to the second wiring, and a contact electrode extending in a third direction intersecting the first and second directions and connected to the third wiring.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on August 26, 2021, with application number 202110986485.6 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application enjoys priority to Japanese Patent Application No. 2021-047990 (filed on March 22, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0005] This embodiment relates to a semiconductor memory device. Background Technology

[0006] As is well known, a semiconductor memory device has multiple memory cells stacked in a direction intersecting with the substrate surface. Summary of the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor memory device that can be highly integrated.

[0008] One embodiment of a semiconductor memory device includes: a plurality of memory block regions arranged along a first direction; a wiring region arranged relative to the plurality of memory block regions along the first direction; and a wiring region extending in the first direction and arranged with the plurality of memory block regions and the wiring region in a second direction intersecting the first direction. Each of the plurality of memory block regions includes: a plurality of memory strings extending in the first direction and arranged in the second direction; and a first wiring extending in the second direction and commonly connected to the plurality of memory strings. The wiring region includes a second wiring extending in the first direction and commonly connected to the plurality of first wirings corresponding to the plurality of memory block regions. The wiring region includes: a third wiring electrically connected to the second wiring; and a contact electrode extending in a third direction intersecting the first and second directions and connected to the third wiring.

[0009] One embodiment of a semiconductor memory device includes: a plurality of memory cells arranged along a first direction; a plurality of first wirings arranged along the first direction and electrically connected to the plurality of memory cells; and a contact electrode extending in the first direction and connected to any one of the plurality of first wirings. The contact electrode includes: a first portion extending in the first direction; and a second portion connected to the first portion and connected to a side of any one of the plurality of first wirings in a second direction intersecting the first direction. When a cross-section perpendicular to the first direction and including the second portion of the contact electrode is defined as a first cross-section, in the first cross-section, a portion of the outline of the second portion is provided along the circumference of a first circle, and the portion of the outline of the second portion other than the first portion is provided inside the first circle.

[0010] One embodiment of a semiconductor memory device includes: a plurality of memory layers arranged along a first direction; a plurality of contact electrodes extending in the first direction and connected to the plurality of memory layers; and a voltage supply line extending in the first direction and connected to the plurality of memory layers. Each of the plurality of memory layers includes: a memory cell; a first wiring electrically connected to the memory cell; a second wiring electrically connected to any one of the plurality of contact electrodes; a first transistor electrically connected between the first wiring and the second wiring; a second transistor electrically connected between the second wiring and the voltage supply line; and a third transistor electrically connected between the second transistor and the voltage supply line. The first wiring functions as the gate electrode of the third transistor. Attached Figure Description

[0011] Figure 1 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment.

[0012] Figure 2 It is Figure 1 The diagram shows a schematic top view of part A, which is an enlarged representation.

[0013] Figure 3 It is Figure 2 The diagram shows a schematic top view of part B, which is an enlarged representation.

[0014] Figure 4 It includes Figure 3 A schematic 3D view of the part shown.

[0015] Figure 5 It is Figure 1 The diagram shows a schematic top view of part C, which is an enlarged representation.

[0016] Figure 6 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line D-D' and viewed in the direction of the arrow.

[0017] Figure 7 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line E-E' and viewed in the direction of the arrow.

[0018] Figure 8 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0019] Figure 9 This is a schematic top view used to illustrate the manufacturing method.

[0020] Figure 10 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 11 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 12 This is a schematic top view used to illustrate the manufacturing method.

[0023] Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 14 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 15 This is a schematic top view used to illustrate the manufacturing method.

[0026] Figure 16 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 17 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 18 This is a schematic top view used to illustrate the manufacturing method.

[0029] Figure 19 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 20 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 21 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 22 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 23 This is a schematic top view used to illustrate the manufacturing method.

[0034] Figure 24 This is a schematic top view used to illustrate the manufacturing method.

[0035] Figure 25 This is a schematic top view used to illustrate the manufacturing method.

[0036] Figure 26 This is a schematic top view used to illustrate the manufacturing method.

[0037] Figure 27 This is a schematic top view used to illustrate the manufacturing method.

[0038] Figure 28 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0039] Figure 29 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0040] Figure 30 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0041] Figure 31 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0042] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0044] Figure 34 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0045] Figure 35 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 36 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0047] Figure 37 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0048] Figure 38 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0049] Figure 39 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0050] Figure 40 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the second embodiment.

[0051] Figure 41 This is a schematic circuit diagram representing a portion of the semiconductor memory device.

[0052] Figure 42 This is a schematic perspective view showing a portion of the semiconductor memory device.

[0053] Figure 43 This is a schematic top view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment.

[0054] Figure 44 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0055] Figure 45 This is a schematic top view used to illustrate the manufacturing method.

[0056] Figure 46 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0057] Figure 47 This is a schematic top view used to illustrate the manufacturing method.

[0058] Figure 48 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0059] Figure 49 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0060] Figure 50 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0061] Figure 51 This is a schematic top view used to illustrate the manufacturing method.

[0062] Figure 52 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0063] Figure 53 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0064] Figure 54 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0065] Figure 55 This is a schematic top view used to illustrate the manufacturing method.

[0066] Figure 56 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0067] Figure 57This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0068] Figure 58 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0069] Figure 59 This is a schematic top view used to illustrate the manufacturing method.

[0070] Figure 60 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0071] Figure 61 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0072] Figure 62 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0073] Figure 63 This is a schematic top view used to illustrate the manufacturing method.

[0074] Figure 64 This is a schematic top view used to illustrate the manufacturing method.

[0075] Figure 65 This is a schematic top view used to illustrate the manufacturing method.

[0076] Figure 66 This is a schematic top view used to illustrate the manufacturing method.

[0077] Figure 67 This is a schematic top view used to illustrate the manufacturing method.

[0078] Figure 68 This is a schematic top view used to illustrate the manufacturing method.

[0079] Figure 69 This is a schematic top view used to illustrate the manufacturing method.

[0080] Figure 70 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0081] Figure 71 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0082] Figure 72 This is a schematic cross-sectional view used to illustrate the manufacturing method.

[0083] Figure 73 This is a schematic top view illustrating a variation of the semiconductor memory device according to the second embodiment.

[0084] Figure 74This is a schematic top view illustrating a variation of the semiconductor memory device according to the second embodiment.

[0085] Figure 75 This is a schematic circuit diagram illustrating a variation of the semiconductor memory device of the second embodiment.

[0086] Figure 76 This is a schematic top view illustrating a variation of the semiconductor memory device according to the second embodiment.

[0087] Figure 77 This is a schematic top view illustrating a variation of the semiconductor memory device according to the second embodiment. Detailed Implementation

[0088] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments shown below are merely examples and are not intended to limit the present invention. In addition, the following drawings are schematic diagrams, and sometimes some components are omitted for ease of explanation. Furthermore, sometimes the same reference numerals are used for common parts in multiple embodiments, and descriptions are omitted.

[0089] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to a memory chip, and sometimes to a memory system that includes a controller chip, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0090] Furthermore, when this specification refers to the first component and the second component as "electrically connected," it can mean that the first component and the second component are directly connected, or that the first component and the second component are connected via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor can still be "electrically connected" to the third transistor.

[0091] Furthermore, in this specification, when it is mentioned that the first component is "connected" "between" the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0092] Furthermore, in this specification, when it is mentioned that a circuit or the like "conducts" two wirings, for example, sometimes it means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings, and that the transistor or the like is in an ON state.

[0093] Furthermore, in this specification, the specific direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0094] Furthermore, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to any one of the X, Y, and Z directions.

[0095] Furthermore, in this specification, terms such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, for a given configuration, when referring to a lower surface or lower end, it refers to the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that configuration on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0096] [First Implementation]

[0097] [constitute]

[0098] Figure 1 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of this embodiment includes multiple memory block regions R. BLK Multiple wiring areas R HU and multiple bit line regions R BL Storage block region R BLK Arranged in a matrix pattern in both the X and Y directions. Wiring area R HU These correspond to multiple storage block regions R arranged along the Y direction. BLK And the settings. Wiring area R HU Arranged along the X direction and along the Y direction with the storage block region R BLK Adjacent. Bit line region R BL These correspond to multiple storage block regions R arranged along the Y direction. BLK and these storage block areas R BLK The corresponding wiring area R HU And set. Bit line region R BL With these multiple storage block regions R BLK and wiring area R HU Arranged along the X direction.

[0099] Figure 1In the example, in the two storage block regions R arranged along the Y direction BLK Between these two storage block regions, a local block connector (LBI) extending in the X direction is provided. BLK The components are connected to the local block interconnect line (LBI). Furthermore, in the bit line region R... BL A bit line BL extending in the Y direction is provided. Multiple local block connection lines LBI arranged along the Y direction are commonly connected to this bit line BL. Furthermore, the bit line BL passes through a wiring area R. HU It is electrically connected to a peripheral circuit (not shown) in a configuration.

[0100] Figure 2 It is Figure 1 The diagram shows a schematic top view of part A, which is an enlarged representation. Figure 3 It is Figure 2 The diagram shows a schematic top view of part B, which is an enlarged representation. Figure 4 It includes Figure 3 A schematic 3D view of the part shown.

[0101] like Figure 2 As shown, in the storage block region R BLK It is configured with: multiple storage unit regions R MC Arranged along the Y direction; and the stepped region R LD It is set in two adjacent memory cell regions R in the Y direction. MC Between. Furthermore, in the storage block region R BLK The end in the Y direction is provided with a selection transistor region R. SGD Additionally, there are two storage block regions R arranged along the Y direction. BLK A local block connection area R is set between them. LBI .

[0102] Figure 4 This refers to a portion of the semiconductor substrate Sub. The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). As shown in the figure, the semiconductor memory device of this embodiment includes a plurality of memory layers ML arranged along the Z direction. Furthermore, an insulating layer 101 such as silicon oxide (SiO2) is provided between two adjacent memory layers ML in the Z direction.

[0103] The memory layer ML has multiple semiconductor layers 110 arranged along the X direction. These multiple semiconductor layers 110 respectively span a reference... Figure 2 The described multiple memory cell regions R MC Multiple stepped areas R LD and selection of transistor region R SGDIt extends in the Y direction. The semiconductor layer 110 functions, for example, as a channel region for a plurality of memory transistors (memory cells) connected in series and selection transistors connected to these memory transistors. Furthermore, in the following description, the configuration comprising a plurality of memory transistors connected in series and selection transistors connected to these memory transistors is sometimes referred to as a memory string. The semiconductor layer 110 may also comprise, for example, undoped polysilicon (Si).

[0104] For example Figure 3 As shown, storage cell region R MC Multiple conductive layers 120 are disposed therein, these conductive layers 120 are located between two adjacent semiconductor layers 110 in the X direction and are arranged along the Y direction. Furthermore, in the memory cell region R... MC In the memory layer ML, there are multiple gate insulating layers 130, which are disposed between the side surfaces of multiple conductive layers 120 in the X direction and the semiconductor layer 110.

[0105] The conductive layer 120 functions, for example, as the gate electrode of a plurality of memory transistors and word lines connected to the gate electrodes of these memory transistors. Figure 3 As shown, the conductive layer 120 may also include a barrier conductive layer 121 such as titanium nitride (TiN) and a conductive layer 122 such as tungsten (W). For example Figure 4 As shown, the conductive layer 120 extends in the Z direction, penetrating multiple storage layers ML. Furthermore, an insulating layer 123, such as silicon oxide (SiO2), is disposed between two adjacent conductive layers 120 in the Y direction. Figure 3 ).

[0106] The gate insulating layer 130 includes, for example, a tunnel insulating layer 131 disposed on the side of the semiconductor layer 110 in the X direction; a charge storage layer 132 disposed on the side of the semiconductor layer 110 in the X direction; and a barrier insulating layer 133 disposed on the side of the semiconductor layer 110 in the X direction.

[0107] The tunnel insulation layer 131 may also contain silicon oxide (SiO2), for example.

[0108] The charge storage layer 132 may, for example, contain polycrystalline silicon (Si). Furthermore, the polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may not contain these impurities.

[0109] The barrier insulating layer 133 may also include, for example, silicon oxide (SiO2). Alternatively, the barrier insulating layer 133 may also include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0110] Select transistor region R SGD ( Figure 2A conductive layer 140 and a conductive layer 150 are disposed in the transistor region. The conductive layers 140 and 150 are located between two adjacent semiconductor layers 110 in the X direction and are arranged along the Y direction. In the transistor selection region R... SGD In the memory layer ML, there are multiple semiconductor layers 160, which are connected to one end of the multiple semiconductor layers 110 in the Y direction.

[0111] The conductive layer 140 functions, for example, as a contact electrode, used to form channels for holes in the semiconductor layer 110, or to supply voltage to channels for holes formed in the semiconductor layer 110. For example Figure 3 As shown, the conductive layer 140 may also include: a semiconductor layer 141 such as polysilicon (Si) containing P-type impurities such as boron (B); and a conductive layer 142 such as titanium nitride (TiN). The conductive layer 140 extends in the Z direction through multiple memory layers ML. Furthermore, a semiconductor layer 143 containing undoped polysilicon (Si) or the like may be provided on the outer peripheral surface of the conductive layer 140. Alternatively, the semiconductor layer 143 may be omitted.

[0112] The conductive layer 150 functions, for example, as the gate electrode of a transistor and the wiring connected to the gate electrode of the transistor. Figure 3 As shown, the conductive layer 150 may also include: a semiconductor layer 151 such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P); and a conductive layer 152 such as titanium nitride (TiN). The conductive layer 150 extends in the Z direction through multiple memory layers ML. Furthermore, an insulating layer 153 such as silicon oxide (SiO2) is provided on the outer peripheral surface of the conductive layer 150. Additionally, an insulating layer 154 such as silicon oxide (SiO2) may be provided in the central portion of the conductive layer 150. Furthermore, the width of the conductive layer 150 in the Y direction may be greater than the width of the conductive layer 140 in the Y direction.

[0113] Semiconductor layer 160 may, for example, comprise a semiconductor layer such as polysilicon (Si) containing N-type impurities such as phosphorus (P). Furthermore, an insulating layer 161 is provided between two adjacent semiconductor layers 160 in the X direction. The insulating layer 161 may, for example, comprise silicon oxide (SiO2). The insulating layer 161 extends in the Z direction, penetrating multiple memory layers ML.

[0114] In the stepped region R LD ( Figure 2 In this structure, a conductive layer 140 or a conductive layer 150 is disposed between two adjacent semiconductor layers 110 in the X direction. Furthermore, a semiconductor layer 143 is disposed on the outer peripheral surface of the conductive layers 140 and 150 respectively. Figure 3 ) and insulating layer 153 ( Figure 3 (), but this illustration is omitted.

[0115] In the local block connection region R LBI ( Figure 2 In this structure, the storage layer ML includes a conductive layer 170. Furthermore, in the local block interconnect region R... LBI In the middle, a plurality of insulating layers 171 are arranged along the conductive layer 170 in the X direction. Figure 3 ).

[0116] Conductive layer 170, for example, serves as a local block interconnect (LBI). Figure 1 To perform its function, the conductive layer 170 may include, for example, a conductive layer such as titanium nitride (TiN). The conductive layer 170 extends in the X direction and is connected to the multiple semiconductor layers 110 via multiple semiconductor layers 160. Additionally, the conductive layer 170 is electrically connected to two memory block regions R arranged along the Y direction. BLK Semiconductor layer 110 in the middle.

[0117] The insulating layer 171 may also include, for example, silicon oxide (SiO2). Figure 4 As shown, the insulating layer 171 extends in the Z direction through multiple storage layers ML.

[0118] In bit line region R BL In the memory layer ML, a pair of conductive layers 180 extending in the Y direction are provided. Furthermore, in the bit line region R... BL Multiple insulating layers 181 are provided in the middle, which are located between two adjacent conductive layers 180 in the X direction and arranged in the Y direction.

[0119] Conductive layer 180, for example, serves as bit line BL ( Figure 1 The conductive layer 180 may, for example, comprise a conductive layer such as titanium nitride (TiN). The conductive layer 180 extends in the Y direction and is connected to one end of the plurality of conductive layers 170 in the X direction.

[0120] The insulating layer 181 may include, for example, silicon oxide (SiO2). The insulating layer 181 extends through multiple storage layers ML in the Z direction. In addition, an insulating layer 182, such as silicon oxide (SiO2), is provided between two adjacent insulating layers 181 in the Y direction. The width of the insulating layer 181 in the X direction may be greater than the width of the insulating layer 182 in the X direction.

[0121] Figure 5 It is Figure 1 The diagram shows a schematic top view of part C, which is an enlarged representation. Figure 6 It is Figure 5 The structure shown is a schematic cross-sectional view cut along line D-D' and viewed in the direction of the arrow. Figure 7 It is Figure 5The structure shown is a schematic cross-sectional view cut along line E-E' and viewed in the direction of the arrow.

[0122] like Figure 5 As shown, in the wiring area R HU The system includes: multiple lead-out areas R LL Arranged along the X direction; and contact electrode region R CC Set in two adjacent lead-out regions R in the X direction LL between.

[0123] In the lead-out region R LL In the memory layer ML, a conductive layer 190 extending in the Y direction is provided. Furthermore, in the lead-out region R... LL Multiple insulating layers 191 are provided in the middle, and these insulating layers 191 are arranged in the Y direction along the conductive layer 190.

[0124] The conductive layer 190 may also include, for example, a conductive layer such as titanium nitride (TiN). The conductive layer 190 and the reference... Figures 2-4 The conductive layers 180 described are conductive, and through these conductive layers 180, there is contact with the reference. Figures 2-4 The conductive layer 170 is conductive. Additionally... Figure 5 In the example, multiple convex curved surfaces are provided on the side of the conductive layer 190 in the X direction, and these curved surfaces correspond to multiple insulating layers 191.

[0125] The insulating layer 191 may also include, for example, an insulating layer such as silicon oxide (SiO2). Figure 6 As shown, the insulating layer 191 extends in the Z direction through multiple storage layers ML.

[0126] For example Figure 5 As shown, in the contact electrode region R CC Multiple contact electrodes CC are disposed therein, and these contact electrodes CC are arranged in the Y direction along the conductive layer 190. Furthermore, in the contact electrode region R... CC In the storage layer ML, there is an insulating layer 102 such as silicon nitride (Si3N4).

[0127] For example Figure 6 As shown, the contact electrode CC includes: a generally cylindrical portion 192; and a generally disc-shaped portion 193 disposed at the lower end of the portion 192.

[0128] Part 192 may also include, for example, a barrier conductive layer 194 such as titanium nitride (TiN) and a conductive layer 195 such as tungsten (W). Part 192 extends in the Z direction through multiple storage layers ML. Furthermore, an insulating layer 196 such as silicon oxide (SiO2) may be provided on the outer peripheral surface of this part 192. A portion of the outer peripheral surface of the insulating layer 196 is in contact with the insulating layer 101. Additionally, a portion of the outer peripheral surface of the insulating layer 196 is in contact with the insulating layer 102. The radial thickness of the portion of the insulating layer 196 in contact with the insulating layer 102 may be greater than the radial thickness of the portion of the insulating layer 196 in contact with the insulating layer 101.

[0129] Part 193 may also include, for example, a barrier conductive layer 194 such as titanium nitride (TiN). Part 193 is included in any storage layer ML and is connected to the side surface in the X direction of the conductive layer 190 contained in any storage layer ML. Additionally, in the wiring region R... HU Contact electrodes CC may also be provided, which correspond to all memory layers ML. In this case, the number of contact electrodes CC can be the same as or more than the number of memory layers ML.

[0130] In addition, for example Figure 5 As illustrated, the outline of portion 192 may also be provided along the circumference of a circle having a specific radius. Furthermore, a portion of the outline of portion 193 may also be provided along the circumference of a circle having a radius larger than the stated circle. Additionally, portions of the outline of portion 193 other than the stated portion may also be provided inside the circle. For example... Figure 5 In the example, the connection portion of portion 193 to the conductive layer 190 includes multiple concave curved surfaces. This connection portion is located inside the circle. Furthermore, Figure 5 In the example, the connection portion of portion 193 to the insulating layer 196 includes a concave curved surface, which is provided along the outer peripheral surface of a circle centered on the center point of the contact electrode CC corresponding to the insulating layer 196. The connection portion is located inside the circle. Additionally, the area in the XY cross-section of portion 193 may be larger than the area in the XY cross-section of portion 192.

[0131] [Effect]

[0132] Semiconductor memory devices having multiple conductive or semiconductor layers arranged along the Z-direction are well known. Such semiconductor memory devices sometimes include a wiring region for connecting the multiple conductive or semiconductor layers to peripheral circuitry. Multiple contact electrodes extending in the Z-direction are provided in the wiring region. Furthermore, in order to connect the multiple conductive or semiconductor layers to the multiple contact electrodes in the wiring region, the ends of the multiple conductive or semiconductor layers are sometimes offset to form a generally stepped structure, for example. In this case, the more the number of conductive or semiconductor layers arranged along the Z-direction increases, the larger the area of ​​the wiring region becomes.

[0133] Here, as shown in the reference Figure 1 As explained, in the semiconductor memory device of this embodiment, multiple memory block regions R BLK Arranged along the Y direction. Furthermore, it does not correspond to these multiple storage block regions R. BLK Instead of setting up separate wiring areas, the connection is set up with these multiple storage block areas R. BLK The corresponding common wiring area R HU This configuration allows for a significant reduction in the wiring area R. HU The area.

[0134] Furthermore, when employing the aforementioned roughly stepped structure, the entire lower surface of the conductive or semiconductor layer faces the upper surface of a lower conductive or semiconductor layer. Consequently, the electrostatic capacitance between two adjacent conductive or semiconductor layers in the Z direction sometimes becomes relatively large. Moreover, the lower the conductive or semiconductor layer is, the larger this facing area becomes.

[0135] Therefore, in the semiconductor memory device of this embodiment, a reference is used. Figures 5-7 The described contact electrode CC replaces the generally stepped structure described above. This contact electrode CC includes: a portion 192 extending in the Z direction; and a generally disk-shaped portion 193 connected to the lower end of the portion 192. Furthermore, the generally disk-shaped portion 193 is connected to the side surfaces of the conductive layer 190.

[0136] This configuration allows for a relatively small facing area between the two portions 193 arranged along the Z-direction. Consequently, the electrostatic capacitance between two adjacent conductive or semiconductor layers in the Z-direction can be relatively small. Furthermore, according to this configuration, the electrostatic capacitance between the underlying conductive or semiconductor layers can be suppressed to a fixed range.

[0137] [Manufacturing Method]

[0138] Figures 8 to 39 This is a schematic cross-sectional view or top view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 8 , Figure 10 , Figure 11 , Figure 13 , Figure 14 , Figure 16 , Figure 17 , Figures 19-22 , Figure 28 and Figure 29 Corresponding to Figure 4 The cross-section shown is part of the figure. However, for ease of explanation, a cross-section corresponding to the insulating layer 181 is added to these figures. Figure 9 , Figure 12 , Figure 15 , Figure 18 ,and Figures 23-27 Indicates and Figure 3 The corresponding part. Figure 30 , Figure 32 , Figure 34 , Figure 36 and Figure 38 Indicates corresponding to Figure 6 The part. Figure 31 , Figure 33 , Figure 35 , Figure 37 and Figure 39 Indicates corresponding to Figure 7 The part.

[0139] In the manufacturing method, for example Figure 8 As shown, multiple insulating layers 101 and multiple insulating layers 102 are alternately formed. This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0140] Next, for example Figure 9 and Figure 10 As shown, opening 123A is formed. Opening 123A is as follows: Figure 9 As shown, it extends in the Y direction and is arranged along the X direction. Furthermore, opening 123A is as follows... Figure 10 The diagram shows multiple insulating layers 101 and 102 extending in the Z direction and traversing the Z-direction. This process is performed, for example, by RIE (Reactive Ion Etching).

[0141] Next, for example Figure 11 As shown, insulating layers 123 and 182 are formed. This process is performed, for example, by CVD.

[0142] Next, for example Figure 12 and Figure 13As shown, an opening 120A is formed at a position corresponding to the conductive layer 120. Furthermore, an opening 140A is formed at a position corresponding to the conductive layer 140. Additionally, an opening 161A is formed at a position corresponding to the insulating layer 161. These openings 120A, 140A, and 161A are as follows... Figure 13 As shown, it extends in the Z direction, exposing the sides in the X direction of the plurality of insulating layers 101 and 102 arranged along the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0143] Next, for example Figure 14 As shown, a sacrificial layer 120B is formed inside opening 120A. Furthermore, a sacrificial layer 140B is formed inside opening 140A, but this is not shown in the diagram. Additionally, a sacrificial layer 161B is formed inside opening 161A, but this is not shown in the diagram. This process is performed, for example, by CVD or the like.

[0144] Next, for example Figure 15 and Figure 16 As shown, an opening 150A is formed at a position corresponding to the conductive layer 150. Furthermore, an opening 171A is formed at a position corresponding to the insulating layer 171. Furthermore, an opening 181A is formed at a position corresponding to the insulating layer 181. Furthermore, an opening 171A is formed at a position corresponding to the insulating layer 191. Figure 5 The corresponding positions form openings, but this diagram is omitted. These openings, such as 150A, 171A, 181A, etc., are shown in the diagram. Figure 16 As shown, it extends in the Z direction, exposing the sides in the X direction of the plurality of insulating layers 101 and 102 arranged along the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0145] Next, for example Figure 17 As shown, a sacrificial layer 181B is formed inside opening 181A. Furthermore, a sacrificial layer 150B is formed inside opening 150A, but this is not shown in the diagram. Furthermore, a sacrificial layer 171B is formed inside opening 171A, but this is not shown in the diagram. Additionally, a sacrificial layer 171B is formed inside opening 171A, but this is not shown in the diagram. Furthermore, a sacrificial layer 181B is formed inside opening 171A. Figure 5 The corresponding position forms a sacrificial layer, but this illustration is omitted. This process is performed, for example, by CVD.

[0146] Next, for example Figure 18 and Figure 19 As shown, the sacrificial layer 120B is removed. This process is performed, for example, by wet etching.

[0147] Next, for example Figure 20 As shown, a portion of the semiconductor layer 110 is formed. In this process, a portion of the insulating layer 102 is removed, for example, by a method such as wet etching via opening 120A. Furthermore, a portion of the semiconductor layer 110 is formed by a method such as CVD.

[0148] Next, for example Figure 21 The tunnel insulating layer 131 and charge storage layer 132 are formed as shown. In this process, a portion of the semiconductor layer 110 is removed, for example, by a method such as wet etching through opening 120A, thereby exposing a portion of the upper surface and a portion of the lower surface of the insulating layer 101. Furthermore, the tunnel insulating layer 131 is formed by a method such as oxidation or CVD. Furthermore, the charge storage layer 132 is formed by a method such as CVD. Furthermore, a portion of the charge storage layer 132 is removed by a method such as wet etching, and the charge storage layer 132 is broken in the Z direction.

[0149] Next, for example Figure 22 As shown, a barrier insulating layer 133, a barrier conductive layer 121, and a conductive layer 122 are formed inside the opening 120A. This process is performed, for example, by a method such as CVD.

[0150] Next, for example Figure 23 As shown, the sacrificial layer 140B is removed. This process is performed, for example, by wet etching.

[0151] Next, for example Figure 24 As shown, a portion of the semiconductor layer 110 is formed. In this process, a portion of the insulating layer 102 is removed, for example, by a method such as wet etching via opening 140A. Furthermore, a portion of the semiconductor layer 110 is formed by a method such as CVD.

[0152] Next, semiconductor layer 143, semiconductor layer 141, and conductive layer 142 are formed inside the opening 140A. This process is performed, for example, by a method such as CVD.

[0153] Next, the sacrificial layer 150B is removed. This process is performed, for example, by wet etching.

[0154] Next, for example Figure 25 As shown, an insulating layer 153, a semiconductor layer 151, a conductive layer 152, and a semiconductor layer 154 are formed inside the opening 150A. This process is performed, for example, by a method such as CVD.

[0155] Next, the sacrificial layer 161B is removed. This process is performed, for example, by wet etching.

[0156] Next, for example Figure 26 As shown, a semiconductor layer 160 is formed. In this process, a portion of the insulating layer 102 is removed, for example, by a method such as wet etching via opening 161A. Furthermore, the semiconductor layer 160 is formed by a method such as CVD.

[0157] Next, an insulating layer 161 is formed inside the opening 161A. This process is performed, for example, by a method such as CVD.

[0158] Next, for example Figure 27 and Figure 28 As shown, sacrificial layers 171B and 181B are removed. Furthermore, the sacrificial layer is removed at the location corresponding to insulating layer 191, but this is not shown in the diagram. This process is performed, for example, by wet etching.

[0159] Next, for example Figure 29 As shown, a conductive layer 180 is formed. Furthermore, a conductive layer 170 is formed. Figure 3 ) and conductive layer 190 ( Figure 5 (The diagram is omitted.) In this process, a portion of the insulating layer 102 is removed, for example, by wet etching via openings 171A, 181A, etc. Furthermore, conductive layers 170, 180, and 190 are formed by methods such as CVD.

[0160] Next, for example Figure 3 and Figure 4 As shown, insulating layers 171 and 181 are formed inside openings 171A and 181A. Furthermore, an insulating layer 191 is formed. Figure 5 , Figure 6 (The diagram is omitted.) For example, this process is performed using methods such as CVD.

[0161] Next, for example Figure 30 and Figure 31 As shown, an opening CCA is formed at a position corresponding to the contact electrode CC. The opening CCA extends in the Z direction, exposing a portion of the upper surface of any insulating layer 101. In this process, an opening is formed in the wiring area R. HU A portion of the upper surface of all insulating layers 101 may also be exposed via multiple openings CCA. Furthermore, the multiple openings CCA extend in the Z direction through multiple insulating layers 101, 102, exposing the sides of these insulating layers 101, 102.

[0162] Next, for example Figure 32 and Figure 33 As shown, a portion of the insulating layer 102 is removed via the opening CCA. This process is performed, for example, by a method such as wet etching.

[0163] Next, for example Figure 34 and Figure 35 As shown, an insulating layer 196 is formed via an opening CCA. This process is performed, for example, by a method such as CVD.

[0164] Next, for example Figure 36 and Figure 37As shown, a portion of insulating layer 196 and a portion of insulating layer 101 are removed via the opening CCA, exposing the upper surface of insulating layer 102. This process is performed, for example, by a method such as RIE.

[0165] Next, for example Figure 38 and Figure 39 As shown, a portion of the insulating layer 102 is removed via the opening CCA. This process is performed, for example, by a method such as wet etching. In this process, the insulating layer 102 is removed until, for example, the side surface of the conductive layer 190 in the X direction is exposed inside the opening CCA.

[0166] Next, for example Figures 5-7 As shown, a contact electrode CC is formed inside the opening CCA. This process can be performed, for example, by methods such as CVD.

[0167] [Second Implementation]

[0168] [constitute]

[0169] Figure 40 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to the second embodiment. Figure 41 This is a schematic circuit diagram representing a portion of the semiconductor memory device. Figure 42 This is a schematic perspective view showing a portion of the semiconductor memory device.

[0170] In addition, in the following description, the same reference numerals are used for components that are the same as those in the first embodiment, and the descriptions are omitted.

[0171] The semiconductor memory device of the second embodiment is configured in essentially the same manner as the semiconductor memory device of the first embodiment. However, the semiconductor memory device of the second embodiment includes a memory layer ML2 ( Figure 42 ) is used to replace storage layer ML. Storage layer ML2 is constructed in basically the same way as storage layer ML. However, the structure of the wiring area of ​​storage layer ML2 is different from that of the wiring area R of storage layer ML. HU The structures are different.

[0172] In the wiring area, storage layer ML2 has Figure 41 The illustrated preamplifier circuit PA (signal amplifier circuit).

[0173] Next, the circuit configuration of the preamplifier circuit PA will be explained.

[0174] The preamplifier circuit PA has nodes N1 to N5. Node N1 is related to the reference... Figures 2-4 The conductive layer 180 (bit line BL) is conductive. Node N2 is connected to the reference. Figures 5-7The described contact electrode CC is conductive. Node N3 is conductive to the voltage supply line that supplies ground voltage. Nodes N4 and N5 are connected to a sequencer (not shown).

[0175] Furthermore, the preamplifier circuit PA includes: transistor Tr1, connected between nodes N1 and N2; and transistors Tr2 and Tr3, connected in series between nodes N2 and N3. Transistors Tr1 to Tr3 are, for example, N-channel field-effect transistors.

[0176] The source electrode of transistor Tr1 is connected to node N2. The drain electrode of transistor Tr1 is connected to node N1. The gate electrode of transistor Tr1 is connected to node N4.

[0177] The source electrode of transistor Tr2 is connected to the drain electrode of transistor Tr3. The drain electrode of transistor Tr2 is connected to node N2. The gate electrode of transistor Tr2 is connected to node N5.

[0178] The source electrode of transistor Tr3 is connected to node N3. The drain electrode of transistor Tr3 is connected to the source electrode of transistor Tr2. The gate electrode of transistor Tr3 is connected to node N1.

[0179] Next, we will briefly explain the operation of the preamplifier circuit PA.

[0180] For example, during the read operation of a semiconductor memory device, firstly, "H" and "L" signals are supplied to nodes N4 and N5. This turns transistor Tr1 on and transistor Tr2 off. In this state, the bit line BL is synced via nodes N1 and N2. Figure 1 (Charge)

[0181] Next, "L, L" signals are supplied to nodes N4 and N5. This turns transistors Tr1 and Tr2 off. In this state, the specific conductive layer 120 ( Figures 2-4 A readout voltage is supplied. Consequently, the selected memory cell connected to the conductive layer 120 becomes either on or off depending on the recorded data. Furthermore, multiple conductive layers 120 ( Figures 2-4 A read pass voltage higher than the read voltage is supplied. Therefore, the memory cell and bit line BL ( Figure 1 The source line SL (not shown) is turned on. As a result, the bit line connected to the selected memory cell in the on state releases its charge. Accompanying this, transistor Tr3 ( Figure 41 The transistor Tr3 becomes disconnected. On the other hand, the bit line connected to the selected memory cell remains charged while it is disconnected. At this time, transistor Tr3... Figure 41 It remains in the connected state.

[0182] Next, "L" and "H" signals are supplied to nodes N4 and N5. This turns transistor Tr1 off and transistor Tr2 on. At this time, current does not flow through the contact electrode CC corresponding to the selected memory cell in the on state. On the other hand, current flows through the contact electrode CC corresponding to the selected memory cell in the off state. Therefore, by detecting this current, the data recorded in the selected memory cell can be detected.

[0183] According to the aforementioned configuration, in the bit line BL (which is connected to node N1) Figure 1 During discharge, the bit line BL is electrically disconnected from the contact electrode CC. This allows for relatively high-speed discharge of the bit line BL.

[0184] Next, the configuration of the preamplifier circuit PA will be explained in more detail.

[0185] For example Figure 40 As shown, in the wiring region, the storage layer ML2 includes a conductive layer 210. Furthermore, a plurality of insulating layers 211 arranged along the conductive layer 210 are provided in the wiring region.

[0186] Conductive layer 210 as a reference Figure 41 The node N1 described herein performs its function. The conductive layer 210 may also include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0187] The insulating layer 211 may also include, for example, silicon oxide (SiO2). Figure 42 As shown, the insulating layer 211 extends in the Z direction through multiple storage layers ML2.

[0188] Furthermore, in the wiring area, the storage layer ML2 includes a conductive layer 220. Additionally, a plurality of insulating layers 221 arranged along the conductive layer 220 are provided in the wiring area.

[0189] Conductive layer 220 as a reference Figure 41 The node N2 described herein performs its function. The conductive layer 220 may also include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0190] The insulating layer 221 may also include, for example, silicon oxide (SiO2). The insulating layer 221 extends in the Z direction through multiple storage layers ML2.

[0191] Furthermore, in the wiring area, the storage layer ML2 includes a semiconductor layer 230. Additionally, a conductive layer 231 is provided in the wiring area, and this conductive layer 231 is connected to the semiconductor layer 230.

[0192] Semiconductor layer 230 as a reference Figure 41The source region of the transistor Tr3 described herein functions. The semiconductor layer 230 may also include, for example, polysilicon (Si) containing N-type impurities such as phosphorus (P).

[0193] Conductive layer 231 as a reference Figure 41 The described node N3 functions. The conductive layer 231 may also include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). Figure 42 As shown, the conductive layer 231 extends in the Z direction, penetrating multiple storage layers ML2.

[0194] Furthermore, in the wiring region, the storage layer ML2 includes a plurality of semiconductor layers 240. Additionally, in the wiring region, a plurality of conductive layers 241 are provided, corresponding to the plurality of semiconductor layers 240; and an insulating layer 242 covers the outer peripheral surfaces of the plurality of conductive layers 241.

[0195] Semiconductor layer 240 as a reference Figure 41 The channel regions of the transistors Tr1 and Tr2 described herein function. The semiconductor layer 240 may also include, for example, polysilicon (Si) containing P-type impurities such as boron (B).

[0196] Conductive layer 241 as a reference Figure 41 The gate electrodes of Tr1 and Tr2 described herein function. Furthermore, conductive layer 241 serves as a reference. Figure 41 The described node N4 or node N5 performs its function. The conductive layer 241 may also include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0197] Insulating layer 242 as a reference Figure 41 The gate insulating films of the transistors Tr1 and Tr2 described herein function. The insulating layer 242 may, for example, contain silicon oxide (SiO2). Figure 42 As shown, the conductive layer 241 and the insulating layer 242 extend in the Z direction through multiple storage layers ML2.

[0198] Furthermore, in the wiring region, the storage layer ML2 includes: a semiconductor layer 250 connected to a portion of the outer peripheral surface of the semiconductor layer 230; and an insulating layer 251 connected to a portion of the outer peripheral surface of the semiconductor layer 250. Additionally, in the wiring region, an insulating layer 252 connected to the semiconductor layer 250; and a semiconductor layer 253 connected to a portion of the outer peripheral surface of the semiconductor layer 250 are provided.

[0199] Semiconductor layer 250 as a reference Figure 41 The channel region of the transistor Tr3 described herein functions. The semiconductor layer 250 may also include, for example, polysilicon (Si) containing P-type impurities such as boron (B).

[0200] Insulating layer 251 as a reference Figure 41 The gate insulating film of the transistor Tr3 described herein functions. The insulating layer 251 may also include, for example, silicon oxide (SiO2).

[0201] The insulating layer 252 may also include, for example, silicon oxide (SiO2). Figure 42 As shown, the insulating layer 252 extends in the Z direction through multiple storage layers ML2.

[0202] Semiconductor layer 253 suppresses leakage current in transistor Tr3, which includes semiconductor layer 250, etc. Semiconductor layer 253 may, for example, contain polysilicon (Si) containing P-type impurities such as boron (B). Furthermore, the concentration of impurities in semiconductor layer 253 is greater than the concentration of impurities in semiconductor layer 250. Semiconductor layer 253 extends in the Z direction, penetrating multiple memory layers ML2.

[0203] Furthermore, in the wiring area, the storage layer ML2 includes multiple semiconductor layers 260. Additionally, multiple insulating layers 261 are provided in the wiring area, and these insulating layers 261 are connected to the multiple semiconductor layers 260.

[0204] A portion of a plurality of semiconductor layers 260 is connected to the conductive layer 210 and the semiconductor layer 240. The semiconductor layer 260 serves as a reference. Figure 41 The drain region of the transistor Tr1 described herein functions. Furthermore, portions of multiple semiconductor layers 260 are connected to two semiconductor layers 240 and a conductive layer 220. The semiconductor layers 260 are used as a reference. Figure 41 The source region of transistor Tr1 and the drain region of transistor Tr2, as described, function. Furthermore, portions of multiple semiconductor layers 260 are connected to semiconductor layers 240 and 250. The semiconductor layers 260 serve as a reference. Figure 41 The source region of transistor Tr2 and the drain region of transistor Tr3, as described, function. The semiconductor layer 260 may also include, for example, polysilicon (Si), which contains N-type impurities such as phosphorus (P).

[0205] The insulating layer 261 may also include, for example, silicon oxide (SiO2). The insulating layer 261 extends in the Z direction through multiple storage layers ML2.

[0206] Furthermore, in the wiring area, the storage layer ML2 includes a semiconductor layer 270. The semiconductor layer 270 faces the conductive layer 210 through an insulating layer 251. Additionally, an insulating layer 271 is provided in the wiring area, and this insulating layer 271 is connected to the semiconductor layer 270.

[0207] Semiconductor layer 270 as a reference Figure 41 The gate electrode of the transistor Tr3 described herein functions. The semiconductor layer 270 may also include, for example, polysilicon (Si) containing N-type impurities such as phosphorus (P).

[0208] The insulating layer 271 may also include, for example, silicon oxide (SiO2). The insulating layer 271 extends in the Z direction through multiple storage layers ML2.

[0209] [Manufacturing Method]

[0210] Figures 43 to 72 This is a schematic cross-sectional view or top view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 43 , Figure 45 , Figure 47 , Figure 51 , Figure 55 , Figure 59 ,and Figures 63-69 Indicates and Figure 40 The corresponding plane. Figure 44 , Figure 46 , Figures 48-50 , Figures 52-54 , Figures 56-58 , Figures 60-62 ,and Figures 70-72 Corresponding to Figure 42 A portion of the cross-section shown.

[0211] The semiconductor memory device of the second embodiment is manufactured in essentially the same manner as the semiconductor memory device of the first embodiment.

[0212] However, in the manufacturing method of the semiconductor memory device of the second embodiment, when referring to Figure 12 and Figure 13 The described process, or reference Figure 15 and Figure 16 In the described process, for example Figure 43 and Figure 44 As shown, an opening 210A is formed at a position corresponding to insulating layer 211. Furthermore, an opening 220A is formed at a position corresponding to insulating layer 221. Furthermore, an opening 230A is formed at a position corresponding to conductive layer 231. Furthermore, an opening 240A is formed at a position corresponding to conductive layer 241. Furthermore, an opening 250A is formed at a position corresponding to insulating layer 252. Furthermore, an opening 253A is formed at a position corresponding to semiconductor layer 253. Furthermore, an opening 260A is formed at a position corresponding to insulating layer 261. Furthermore, an opening 270A is formed at a position corresponding to insulating layer 271. These openings 210A, 220A, 230A, 240A, 250A, 253A, 260A, and 270A are as follows: Figure 44As shown, it extends in the Z direction, exposing the sides in the X direction of the plurality of insulating layers 101 and 102 arranged along the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0213] Next, for example Figure 45 and Figure 46 As shown, sacrificial layers 230B, 240B, 250B, 253A, 260A, and 270B are formed inside openings 210A, 220A, 230A, 240A, 250A, 253B, 260B, and 270B. This process is performed, for example, by CVD.

[0214] Next, for example Figure 47 and Figure 48 The sacrificial layer 250B is removed, as shown. This process is performed, for example, by wet etching.

[0215] Next, for example Figure 49 The semiconductor layer 250 is formed as shown. In this process, a portion of the insulating layer 102 is removed, for example, by a method such as wet etching via opening 250A. Furthermore, the semiconductor layer 250 is formed by a method such as CVD.

[0216] Next, for example Figure 50 As shown, an insulating layer 251 is formed inside the opening 250A. This process is performed, for example, by a method such as CVD.

[0217] Next, for example Figure 51 and Figure 52 The sacrificial layer 240B is removed, as shown. This process is performed, for example, by wet etching.

[0218] Next, for example Figure 53 The semiconductor layer 240 is formed as shown. In this process, a portion of the insulating layer 102 is removed, for example, by a method such as wet etching via opening 240A. Furthermore, the semiconductor layer 240 is formed by a method such as CVD.

[0219] Next, for example Figure 54 As shown, an insulating layer 242 and a conductive layer 241 are formed inside the opening 240A. This process is performed, for example, by a method such as CVD.

[0220] Next, for example Figure 55 and Figure 56 The sacrificial layer 230B is removed, as shown. This process is performed, for example, by wet etching.

[0221] Next, for example Figure 57The semiconductor layer 230 is formed as shown. In this process, a portion of the insulating layer 102 is removed, for example, by wet etching via opening 230A. Furthermore, the semiconductor layer 230 is formed by methods such as CVD.

[0222] Next, for example Figure 58 As shown, a conductive layer 231 is formed inside the opening 230A. This process is performed, for example, by a method such as CVD.

[0223] Next, for example Figure 59 and Figure 60 The sacrificial layer 260B is removed, as shown. This process is performed, for example, by wet etching.

[0224] Next, for example Figure 61 The semiconductor layer 260 is formed as shown. In this process, a portion of the insulating layer 102 is removed, for example, by wet etching via opening 260A. Furthermore, the semiconductor layer 260 is formed by methods such as CVD.

[0225] Next, for example Figure 62 As shown, an insulating layer 261 is formed inside the opening 260A. This process is performed, for example, by a method such as CVD.

[0226] Next, for example Figure 63 The sacrificial layer 270B is removed, as shown. This process is performed, for example, by wet etching.

[0227] Next, for example Figure 64 An insulating layer 251 is formed as shown. In this process, a portion of the insulating layer 102 is removed, for example, by wet etching through opening 270A. Furthermore, a portion of the outer peripheral surface of the semiconductor layer 250 is oxidized by methods such as thermal oxidation, thereby forming the insulating layer 251.

[0228] Next, for example Figure 65 The semiconductor layer 270 is formed as shown. This process is performed, for example, by a method such as CVD.

[0229] Next, for example Figure 66 As shown, an insulating layer 271 is formed inside the opening 270A. This process is performed, for example, by a method such as CVD.

[0230] Next, for example Figure 67 The sacrificial layer 253B is removed, as shown. This process is performed, for example, by wet etching.

[0231] Next, for example Figure 68 As shown, a semiconductor layer 253 is formed inside the opening 253A. This process is performed, for example, by a method such as CVD.

[0232] Next, for example, in reference Figure 27 and Figure 28 In the described process, for example Figure 69 and Figure 70 The sacrificial layers 210B and 220B are removed, as shown. This process is performed, for example, by wet etching.

[0233] Next, for example, in reference Figure 29 In the described process, for example Figure 71 The conductive layer 210 is shown. Additionally, a conductive layer 220 is formed, but this is not shown in the diagram. In this process, a portion of the insulating layer 102 is removed, for example, by wet etching via openings 210A and 220A. Furthermore, the conductive layers 210 and 220 are formed by methods such as CVD.

[0234] Next, for example Figure 72 As shown, an insulating layer 211 is formed inside the opening 210A. Furthermore, an insulating layer 221 is formed inside the opening 220A, but this is not shown in the diagram. This process is performed, for example, by a method such as CVD.

[0235] [Example of a preamplifier circuit PA]

[0236] Figures 40-42 The illustrated preamplifier circuit PA is merely an example; the actual configuration can be adjusted accordingly.

[0237] For example, Figure 40 The illustrated configuration includes a semiconductor layer 250 and a semiconductor layer 253 connected to a portion of the outer peripheral surface of the semiconductor layer 250. On the other hand, Figure 73 The illustrated structure is basically based on and Figure 40 The configuration illustrated is constructed in the same manner, but with a semiconductor layer 350 replacing the semiconductor layer 250. Furthermore, this configuration does not include a semiconductor layer 253.

[0238] Semiconductor layer 350 is constructed in essentially the same manner as semiconductor layer 250. However, an insulating layer 251 is provided on the outer peripheral surface of semiconductor layer 250, and semiconductor layer 250 faces semiconductor layer 270 through this insulating layer 251. On the other hand, two insulating layers 251 are provided on the outer peripheral surface of semiconductor layer 350, and semiconductor layer 350 faces two semiconductor layers 270 through these insulating layers 251. In this configuration, the channel width of transistor Tr3 containing semiconductor layer 350 can be increased, thereby increasing the on-state current.

[0239] In addition, for example Figure 40 The illustrated configuration includes a semiconductor layer 250 and an insulating layer 252 bonded to the semiconductor layer 250. On the other hand, Figure 74The illustrated structure is basically based on and Figure 40 The configuration is the same as that shown, but a semiconductor layer 450 is provided instead of a semiconductor layer 250, and two insulating layers 252 are connected to the semiconductor layer 450.

[0240] Semiconductor layer 450 is constructed in essentially the same manner as semiconductor layer 250. However, a portion of the outer peripheral surface of semiconductor layer 250 is disposed along the circumference of a circle centered on the center position of one insulating layer 252. Furthermore, other portions of the outer peripheral surface of semiconductor layer 250 are disposed within the area of ​​this circle. On the other hand, a portion of the outer peripheral surface of semiconductor layer 450 is disposed along the circumference of two circles centered on the center positions of the two insulating layers 252, respectively. Furthermore, other portions of the outer peripheral surface of semiconductor layer 450 are disposed within the area of ​​at least one of these two circles. Additionally, the opposing area between semiconductor layer 450 and semiconductor layer 270 is larger than the opposing area between semiconductor layer 250 and semiconductor layer 270. In this configuration, the channel length of transistor Tr3 containing semiconductor layer 450 can be increased, thereby suppressing interruption leakage current.

[0241] In addition, for example Figure 75 As shown, the preamplifier circuit PA can also have two or more circuit elements pa, which are connected in parallel between nodes N1 and N2. Each circuit element pa can also have a reference... Figure 41 The transistors Tr1, Tr2, and Tr3 are described. In the case described, for example... Figure 76 As shown, any of the above-described constituent elements can also be placed in two or more wiring areas and connected in parallel between common conductive layers 210 and 220.

[0242] Furthermore, in the above example, at least a portion of the outlines of the conductive layers 210, 220, and the semiconductor layers 230, 240, 250, 260, and 270 are formed in a curved shape along the circumference of a circle centered on the central location of the configuration that permeates these semiconductor layers. However, this configuration is merely illustrative, and the specific configuration can be appropriately adjusted. For example... Figure 77 In the example, the outlines of conductive layers 210, 220 and semiconductor layers 230, 240, 250, 260, 270 are formed along straight lines extending in the X or Y direction. When manufacturing the configuration, for example, in reference... Figure 9 and Figure 10 The described process allows for the patterning of the wiring area to form multiple grooves, as shown in the reference. Figure 11 In the process described, insulating layers such as silicon oxide (SiO2) can be formed in these multiple tanks.

[0243] [Other Implementation Methods]

[0244] The semiconductor memory devices of the first and second embodiments have been described above. However, these semiconductor memory devices are merely examples, and their specific configurations and operations can be adjusted as appropriate.

[0245] For example, the semiconductor memory devices of the first and second embodiments include so-called NAND (Not AND) flash memory. However, the configurations illustrated in the first and second embodiments can also be applied to semiconductor memory devices other than NAND flash memory. For example, the configurations illustrated in the first and second embodiments can also be applied to configurations having one or more memory transistors, wherein a semiconductor layer extending in the Y direction is provided in multiple memory layers ML, ML2, and the semiconductor layer serves as a channel region. Furthermore, the configurations illustrated in the first and second embodiments can also be applied to configurations having other memory transistors. Furthermore, the configurations illustrated in the first and second embodiments can also be applied to other memories.

[0246] In addition, as referenced Figure 1 As described above, the semiconductor memory devices of the first and second embodiments include: a plurality of memory block regions R BLK Arranged along the Y direction; and one wiring area R HU This corresponds to these multiple storage block regions R BLK And set. However, wiring area R HU The configuration can be adjusted appropriately. For example, in the first and second embodiments, it can also correspond to multiple storage block regions R. BLK And set up multiple wiring areas R HU In this case, the bit line region R can also be omitted. BL .

[0247] In addition, as referenced Figures 5-7 As described, the contact electrode CC in the first and second embodiments includes: a portion 192 extending in the Z direction; and a generally disk-shaped portion 193 connected to the lower end of the portion 192. However, the configuration of the contact electrode CC can be appropriately adjusted. For example, in the first and second embodiments, the generally disk-shaped portion 193 may be omitted from the contact electrode CC. In such cases, for example, the lower ends of the plurality of contact electrodes CC may be respectively connected to the upper surface of the plurality of conductive layers 190 stacked in the Z direction.

[0248] [other]

[0249] Several embodiments of the present invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included in the invention as described in the claims and within the same scope.

[0250] [Explanation of Symbols]

[0251] 110 semiconductor layer

[0252] 120 conductive layer

[0253] 130 gate insulating layer

[0254] 140 conductive layer

[0255] 150 conductive layers

[0256] 160 semiconductor layers

[0257] 170 conductive layer

[0258] 180 conductive layer

[0259] R BLK Storage block area

[0260] R HU Wiring area

[0261] R BL Bit line area.

Claims

1. A semiconductor memory device comprising: The substrate extends in a first direction and in a second direction intersecting the first direction; The first region includes a first insulating layer extending in a third direction intersecting the first direction and the second direction, and a plurality of first conductive layers arranged along the third direction; A second region, disposed adjacent to the first region in the first direction, and including a first contact electrode extending in the third direction, wherein... The first contact electrode comprises: Part 1 extends in the third direction; and The second part is connected to the first part, and a portion of the outer peripheral surface of the second part is in contact with the side surface of one of the plurality of first conductive layers, and In the cross-section extending in the first direction and the second direction, the area of ​​the second part is larger than that of the first part, and in the cross-section, a portion of the outline of the second part is arranged along the circumference of a circle.

2. The semiconductor memory device according to claim 1, further comprising: The third region includes a second insulating layer extending in the third direction and a plurality of second conductive layers arranged along the third direction, wherein The second region is positioned in the first direction between the first region and the third region.

3. The semiconductor memory device according to claim 2, wherein... The second region also includes a second contact electrode. The second contact electrode comprises: Part 3 extends in the third direction; and Part 4 is connected to Part 3, and a portion of the outer peripheral surface of Part 4 is in contact with the side surface of one of the plurality of second conductive layers.

4. The semiconductor memory device according to claim 3, wherein The second region also includes: A plurality of first contact electrodes, comprising the first contact electrodes and arranged in the second direction; and A plurality of second contact electrodes, comprising the second contact electrodes and arranged in the second direction.

5. The semiconductor memory device according to claim 1, wherein... The second region also includes: A plurality of third insulating layers and a plurality of fourth insulating layers are alternately stacked in the third direction.

6. The semiconductor memory device according to claim 5, wherein The plurality of third insulating layers extend in the first direction in the first region and the second region.

7. The semiconductor memory device according to claim 5, wherein The second part and one of the plurality of fourth insulating layers are disposed on one of the plurality of third insulating layers.

8. The semiconductor memory device according to claim 5, wherein A portion of the outer peripheral surface of the second part is in contact with the side of one of the plurality of fourth insulating layers.

9. The semiconductor memory device according to claim 5, wherein The outer peripheral surface of the first part is provided with a silicon oxide layer, a portion of the outer peripheral surface of the silicon oxide layer is in contact with one of the plurality of third insulating layers, and another portion of the outer peripheral surface of the silicon oxide layer is in contact with one of the plurality of fourth insulating layers.

10. The semiconductor memory device according to claim 1, wherein The first insulating layer is disposed in the first region between the plurality of first conductive layers and the plurality of third conductive layers.

11. The semiconductor memory device according to claim 1, wherein The first region also includes: Multiple third insulating layers are alternately deposited with multiple first conductive layers in the third direction.

12. The semiconductor memory device according to claim 1, wherein The first part contains titanium nitride and tungsten.

13. The semiconductor memory device according to claim 1, wherein The second part contains titanium nitride.

14. The semiconductor memory device according to claim 1, wherein The first insulating layer comprises silicon oxide.

15. A method for manufacturing a semiconductor memory device, comprising the following steps: Multiple first insulating layers and multiple second insulating layers are alternately formed in a third direction that intersects the first and second directions; A first opening extending in the third direction is formed; Multiple conductive layers are formed through the first opening; A third insulating layer is formed within the first opening; A second opening extending in the third direction is formed; A fourth insulating layer is formed through the second opening; A portion of the fourth insulating layer and a portion of one of the plurality of second insulating layers are removed through the second opening, exposing the side of one of the plurality of conductive layers in the first direction; and A contact electrode is formed inside the second opening, and the contact electrode is in contact with the side of one of the plurality of conductive layers.

16. The method of manufacturing a semiconductor memory device according to claim 15, wherein... In the cross-section extending in the first and second directions, a portion of the fourth insulating layer and a portion of one of the plurality of second insulating layers are removed, such that a portion of the outline of the second opening is provided along the circumference of a circle.

17. The method for manufacturing a semiconductor memory device according to claim 15, further comprising: A portion of the fourth insulating layer and a portion of one of the plurality of second insulating layers are removed, thereby enlarging the bottom of the second opening in both the first and second directions.

18. A method for manufacturing a semiconductor memory device, comprising: Multiple first insulating layers and multiple second insulating layers are alternately formed in a third direction that intersects the first and second directions; A first opening extending in the third direction is formed; Multiple conductive layers are formed through the first opening; A third insulating layer is formed within the first opening; A second opening extending in the third direction is formed; A fourth insulating layer is formed through the second opening; The side of one of the plurality of conductive layers is exposed in the first direction via the second opening; and A contact electrode is formed inside the second opening, and the contact electrode is in contact with the side of one of the plurality of conductive layers.

19. The method of manufacturing a semiconductor memory device according to claim 18, wherein... In the cross-section extending in the first and second directions, after the side of one of the plurality of conductive layers is exposed, a portion of the outline of the second opening is provided along the circumference of the circle.

20. The method for manufacturing a semiconductor memory device according to claim 18, further comprising: The bottom of the second opening is widened in the first direction, exposing the side of one of the plurality of conductive layers.

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