A method, system, device, and medium for grid-forming converter fault current limiting

Abstract

The present application relates to the technical field of grid-forming converter control, and provides a grid-forming converter fault current limiting method, system, device and medium, which comprises extracting positive and negative sequence current components from two-phase synchronous rotating coordinate system according to the obtained three-phase static coordinate system current signal of the converter, obtaining positive and negative sequence current components, after analyzing the positive and negative sequence virtual impedance voltage drop based on the obtained positive sequence current reference value, negative sequence current reference value and angle difference value of the outer loop voltage control output, obtaining positive and negative sequence impedance voltage drop, and combining the positive and negative sequence current components to perform voltage and current double closed loop control to obtain control output voltage and perform pulse width modulation. The present application can eliminate current amplitude calculation oscillation problem without current saturation limiter, ensure that the virtual impedance intervenes in advance and continues to act when the current approaches the limit value, effectively suppresses the fault current, maintains the voltage source characteristics, and further enhances the system stability.

Description

Technical Field

[0001] This invention relates to the field of grid-type converter control technology, and in particular to a fault current limiting method, system, device and medium for grid-type converters. Background Technology

[0002] Grid-Forming Converters (GFMs) can autonomously establish voltage and frequency and simulate synchronous machine characteristics using Virtual Synchronous Generator (VSG) technology, providing core technical support for power electronic grids. Considering the limited overcurrent capacity of the underlying power electronic devices in VSGs, a threshold virtual impedance (TVI) current limiting technology is applied, which simulates the connection impedance to limit the short-circuit current when the converter current exceeds a set value.

[0003] In existing TVI current limiting control technology, the current amplitude that triggers TVI control and generates virtual impedance is within stationary coordinate system or In a synchronous rotating coordinate system, the calculation transforms from a constant value to an oscillation superimposed with twice the fundamental frequency sine wave. If this oscillating current is directly used for control, the virtual voltage drop and voltage reference value will oscillate accordingly, causing the VSG's performance under asymmetrical fault conditions to fail to meet requirements. Although some studies on improved TVI current limiting control calculate the current based on the three-phase current amplitude or trigger TVI control based on the output voltage difference to generate virtual impedance to adapt to asymmetrical faults, these techniques all rely on the current saturation limiter to activate TVI control. This results in the VSG's voltage source characteristics not being maintained in the current-unsaturated stage. Essentially, they can only serve as an anti-integral saturation means for the outer-loop voltage PI controller, failing to achieve current limiting in advance when the current approaches the limit, thus making it difficult to enhance system stability. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a fault current limiting method, system, device, and medium for grid-type converters. This method, based on the decoupling of positive and negative current components in a synchronous rotating coordinate system and combined with a current limiting control mechanism using real-time positive and negative sequence virtual impedance voltage drop analysis, reduces reliance on current saturation limiters and eliminates oscillation problems in current amplitude calculation. This allows the virtual impedance to intervene early and continue acting when the current approaches the limit, effectively suppressing fault current and maintaining voltage source characteristics throughout both symmetrical and asymmetrical fault processes.

[0005] In a first aspect, embodiments of the present invention provide a fault current limiting method for a grid-type converter, the method comprising: The three-phase current signal of the converter in the three-phase stationary coordinate system is obtained, and the positive and negative sequence current components in the two-phase synchronous rotating coordinate system are extracted based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. Obtain the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer loop voltage control output, and perform positive and negative sequence virtual impedance voltage drop analysis based on the positive-sequence current reference value, the negative-sequence current reference value, and the angle difference value to obtain the positive-sequence impedance voltage drop and the negative-sequence impedance voltage drop. Based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component, voltage and current dual closed-loop control is performed to obtain the control output voltage of the three-phase stationary coordinate system, and pulse width modulation is performed based on the control output voltage.

[0006] Further, the step of extracting the positive and negative sequence current components from the three-phase current signal of the converter in a two-phase synchronous rotating coordinate system to obtain the positive sequence current component and the negative sequence current component includes: The three-phase current signal of the converter is subjected to Clarke transformation to obtain the first current signal in the two-phase stationary coordinate system. The first current signal is delayed by a quarter cycle to obtain the second current signal; Based on the second current signal and the first current signal, a transformation process is performed based on a preset symmetric component matrix to obtain the first positive sequence current component and the first negative sequence current component in the two-phase stationary coordinate system. The first positive-sequence current component and the first negative-sequence current component are subjected to Park transformation to obtain the positive-sequence current component and the negative-sequence current component in the two-phase synchronous rotating coordinate system.

[0007] Furthermore, the step of obtaining the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer-loop voltage control output includes: Obtain the positive-sequence current reference component and the negative-sequence current reference component of the outer loop voltage control output; The positive sequence current reference value is obtained by combining the d-axis positive sequence current reference value and the q-axis positive sequence current reference value in the positive sequence current reference component. The negative sequence current reference value is obtained by combining the d-axis negative sequence current reference value and the q-axis negative sequence current reference value in the negative sequence current reference component. The positive sequence phase angle is obtained by the ratio of the q-axis positive sequence current reference value to the d-axis positive sequence current reference value in the positive sequence current reference component. The negative sequence phase angle is obtained by the ratio of the q-axis negative sequence current reference value to the d-axis negative sequence current reference value in the negative sequence current reference component. The angle difference is obtained based on the difference between the negative phase angle and the positive phase angle.

[0008] Further, the step of performing positive and negative sequence virtual impedance voltage drop analysis based on the positive sequence current reference value, the negative sequence current reference value, and the angle difference to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop includes: Based on the positive sequence current reference value, the negative sequence current reference value and the angle difference, the three-phase current reference amplitude is compared and analyzed to obtain the maximum current reference amplitude. The virtual resistance value is obtained based on the difference between the maximum current reference amplitude and the rated current, using a preset virtual resistance gain coefficient. Based on the virtual resistance value and the preset virtual impedance ratio, the corresponding virtual reactance value is obtained; The impedance voltage drop is calculated based on the virtual resistance value, the virtual reactance value, the positive sequence current component, and the negative sequence current component to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop.

[0009] Further, the step of performing voltage and current dual closed-loop control based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component to obtain the control output voltage of the three-phase stationary coordinate system includes: Obtain the voltage compensation amount and virtual rotor angle of the virtual synchronous generator control output; Based on the voltage compensation amount, the virtual rotor angle, the positive sequence impedance voltage drop, and the positive sequence current component, perform positive sequence voltage and current dual closed-loop control to obtain the first control output voltage; Based on the negative sequence impedance voltage drop, the virtual rotor angle, and the negative sequence current component, a negative sequence voltage and current dual closed-loop control is performed to obtain the second control output voltage. The first control output voltage and the second control output voltage are combined to obtain the control output voltage.

[0010] Further, the step of performing positive-sequence voltage and current dual closed-loop control based on the voltage compensation amount, the virtual rotor angle, the positive-sequence impedance voltage drop, and the positive-sequence current component to obtain the first control output voltage includes: The voltage control is performed based on the voltage compensation amount, the d-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop, the positive sequence voltage at the common coupling point and the d-axis positive sequence current at the common coupling point to obtain the reference value of the converter output d-axis positive sequence current. The converter output d-axis positive sequence voltage is obtained by current control based on the reference value of the converter output d-axis positive sequence current, the positive sequence current component, and the d-axis positive sequence voltage at the common connection point. Voltage control is performed based on the q-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop, the positive sequence voltage at the common connection point, and the q-axis positive sequence current at the common connection point to obtain the reference value of the converter output q-axis positive sequence current. Current control is performed based on the reference value of the q-axis positive sequence current output of the converter, the positive sequence current component, and the q-axis positive sequence voltage at the common connection point to obtain the q-axis positive sequence voltage output of the converter. The first control output voltage is generated based on the d-axis positive sequence voltage output by the converter, the q-axis positive sequence voltage output by the converter, and the virtual rotor angle.

[0011] Further, the step of performing negative-sequence voltage and current dual closed-loop control based on the negative-sequence impedance voltage drop, the virtual rotor angle, and the negative-sequence current component to obtain the second control output voltage includes: The reference value of the converter output d-axis negative sequence current is obtained by voltage control based on the d-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common connection point and the d-axis negative sequence current at the common connection point. The converter output d-axis negative sequence voltage is obtained by current control based on the converter output d-axis negative sequence current reference value, the negative sequence current component, and the d-axis negative sequence voltage at the common connection point. Voltage control is performed based on the q-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common connection point, and the q-axis negative sequence current at the common connection point to obtain the reference value of the converter output q-axis negative sequence current. Current control is performed based on the reference value of the q-axis negative sequence current output of the converter, the negative sequence current component, and the q-axis negative sequence voltage at the common connection point to obtain the q-axis negative sequence voltage output of the converter. The second control output voltage is generated based on the d-axis negative sequence voltage of the converter output, the q-axis negative sequence voltage of the converter output, and the virtual rotor angle.

[0012] Secondly, embodiments of the present invention provide a fault current limiting system for a grid-type converter, the system comprising: The positive and negative sequence component extraction module is used to acquire the three-phase current signal of the converter in a three-phase stationary coordinate system, and extract the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. The impedance voltage drop analysis module is used to obtain the positive sequence current reference value, negative sequence current reference value and angle difference value of the outer loop voltage control output, and to perform positive and negative sequence virtual impedance voltage drop analysis based on the positive sequence current reference value, the negative sequence current reference value and the angle difference value to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop. The dual closed-loop control module is used to perform voltage and current dual closed-loop control based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component to obtain the control output voltage of the three-phase stationary coordinate system, and to perform pulse width modulation based on the control output voltage.

[0013] Thirdly, embodiments of the present invention also provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described method.

[0014] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0015] This invention provides a method, system, computer device, and storage medium for limiting fault current in a grid-type converter. The method acquires the three-phase current signal of the converter in a three-phase stationary coordinate system. Based on the three-phase current signal, it extracts the positive and negative sequence current components in a two-phase synchronous rotating coordinate system. Then, based on the acquired positive and negative sequence current reference values ​​and angle difference obtained from the outer loop voltage control, it performs positive and negative sequence virtual impedance voltage drop analysis to obtain the positive and negative sequence impedance voltage drops. Finally, it performs voltage and current dual closed-loop control based on the positive and negative sequence impedance voltage drops, the positive and negative sequence current components, and the control output voltage in the three-phase stationary coordinate system. Finally, it performs pulse width modulation based on the control output voltage. Compared with existing technologies, this fault current limiting method for grid-type converters can reduce the dependence on current saturation limiters and eliminate the oscillation problem in current amplitude calculation by decoupling positive and negative current components in a synchronous rotating coordinate system and combining a current limiting control mechanism based on real-time positive and negative sequence virtual impedance voltage drop analysis. This allows the virtual impedance to intervene in advance and continue to act when the current approaches the limit value, thereby effectively suppressing fault current and maintaining voltage source characteristics throughout the entire process of symmetrical and asymmetrical faults, thus enhancing system stability. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the fault current limiting method for a grid-type converter in an embodiment of the present invention. Figure 2 This is a schematic diagram of the execution logic of the voltage and current dual closed-loop control strategy in an embodiment of the present invention; Figure 3 This is a schematic diagram of the converter current change in the existing control scheme under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention; Figure 4This is a schematic diagram of the converter current change in the control scheme of the present invention under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention; Figure 5 This is a schematic diagram of the converter output voltage change in the existing control scheme under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention; Figure 6 This is a schematic diagram of the converter output voltage change in the control scheme of the present invention under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention; Figure 7 This is a schematic diagram comparing the negative sequence current changes in the control scheme of the present invention and the existing control scheme under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention. Figure 8 This is a schematic diagram comparing the negative sequence voltage changes in the control scheme of the present invention and the existing control scheme under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention. Figure 9 This is a schematic diagram comparing the active power changes of the control scheme of the present invention and the existing control scheme under the scenario of applying a single-phase short-circuit grounding at the common connection point in an embodiment of the present invention. Figure 10 This is a schematic diagram of the fault current limiting system of the grid-type converter in an embodiment of the present invention; Figure 11 This is an internal structural diagram of the computer device in an embodiment of the present invention; The attached figures are labeled as follows: 1. Positive and negative sequence component extraction module; 2. Impedance voltage drop analysis module; 3. Dual closed-loop control module. Detailed Implementation

[0017] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Obviously, the embodiments described below are only part of the embodiments of this invention and are used to illustrate the invention, but are not intended to limit the scope of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0018] The fault current limiting method for grid-connected converters provided by this invention can be understood as a solution to the current application situation where existing TVI current limiting control technology relies on current protection limiters and cannot achieve current limiting in advance when the current approaches the limit value. This invention proposes a TVI current limiting control scheme that does not require current saturation limiting, but controls the current in a synchronous rotating coordinate system with positive and negative sequences. This scheme effectively addresses symmetrical and asymmetrical fault conditions, strictly limiting the converter current within the maximum limit while maintaining the characteristics of the VSG voltage source. It can be applied to existing power electronic conversion systems. Considering that transformers in actual power electronic conversion systems are usually delta-connected, which can prevent zero-sequence current at the point of common coupling (PCC), this TVI current limiting control scheme only needs to focus on positive-sequence and negative-sequence currents. The following embodiments will provide a detailed description of the fault current limiting method for grid-connected converters of this invention.

[0019] In one embodiment, such as Figure 1 As shown, a fault current limiting method for a grid-type converter is provided, including: S11. Obtain the three-phase current signal of the converter in a three-phase stationary coordinate system, and extract the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. The three-phase current signal of the converter in the three-phase stationary coordinate system can be understood as the three-phase instantaneous current output by the grid-type converter in the abc three-phase stationary coordinate system. The corresponding positive sequence current component and negative sequence current component can be understood as the positive sequence and negative sequence current in the two-phase synchronous rotating dq coordinate system, and the positive sequence current component includes the d-axis positive sequence current component and the q-axis positive sequence current component, and the negative sequence current component includes the d-axis negative sequence current component and the q-axis negative sequence current component. Considering the coupling effect between the positive sequence current component and the negative sequence current component, this embodiment preferably uses a delay elimination method based on the Fortescue transform matrix to accurately extract the positive and negative sequence current components.

[0020] Specifically, the steps of extracting the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component include: The three-phase current signals of the converter are subjected to Clarke transform to obtain the first current signal in a two-phase stationary coordinate system; wherein, the first current signal can be understood as stationary. The acquisition process for the three-phase current signals in the coordinate system can be achieved by referring to the existing Clark transform technique, which will not be described in detail here.

[0021] Without considering the zero-sequence component, the first current signal can be represented by positive-sequence and negative-sequence components, using equation (1): (1) In the formula, in, This is the first current signal; and These are respectively the first current signal Axis current components and Axis current components; and These are the positive-sequence current component and the negative-sequence current component corresponding to the first current signal, respectively. and These are the positive sequence current components. positive sequence current components of the axis Positive sequence current component of the axis; and These are the negative sequence current components. negative sequence current components and Negative sequence current component; and The first current signal corresponds to the two-phase synchronous rotating dq coordinate system. and Rotating positive-sequence current components and negative-sequence current components; and These are the positive sequence current components in the two-phase synchronous rotating dq coordinate system. positive sequence current components of the axis Positive sequence current component of the axis; and These are the negative sequence current components in the two-phase synchronous rotating dq coordinate system. negative sequence current components and Negative sequence current component; ω represents the angular velocity of the system's fundamental wave; t represents the time variable.

[0022] Perform two Park transformations on equation (1), that is, multiply equation (1) by... and get: (2) It can be seen from equation (2) that and There is a coupling relationship; in order to eliminate this coupling effect, sequence extraction is required. In this embodiment, the following delay elimination sequence extraction method based on the Fortescue matrix is ​​preferably adopted.

[0023] The first current signal is delayed by a quarter-cycle to obtain the second current signal; wherein, the quarter-cycle delay can be understood as using a quarter-cycle of the fundamental frequency period to delay and cancel the signal of the first current signal, and the specific implementation can refer to relevant existing technologies; the corresponding second current signal can be denoted as: ,and , and These are the second current signals. Shaft delay current components and Shaft delay current component.

[0024] Based on the second current signal and the first current signal, a transformation process is performed using a preset symmetric component matrix to obtain the first positive-sequence current component and the first negative-sequence current component in the two-phase stationary coordinate system; wherein, the preset symmetric component matrix can be understood as being used to establish the second current signal and the first current signal, and the stationary coordinate system. The matrix relating the first positive-sequence current component to the first negative-sequence current component in the coordinate system can be obtained based on the following derivation: still Instantaneous positive-sequence current in the coordinate system (positive-sequence current component corresponding to the first current signal) It can be calculated using the following formula: (3) In the formula, in, and These are the Clarke transform matrix and the orthogonal symmetric component transform matrix, respectively; The phase shift operator in the time domain corresponds to the quarter-cycle delay T of the original in-phase waveform in the aforementioned quarter-cycle delay processing. b / 4(T) b (For the fundamental period) Similarly, we can obtain a state of stillness. Instantaneous negative sequence current in coordinate system for: (4) Combining equations (3) and (4) into matrix form, we get: (5) In the formula, in, This is a preset symmetric component matrix.

[0025] The first positive-sequence current component and the first negative-sequence current component are subjected to Park transformation to obtain the positive-sequence current component and the negative-sequence current component in the two-phase synchronous rotating coordinate system. The Park transformation can be understood as the virtual rotor angle based on the actual control output of VSG in the two-phase synchronous rotating dq coordinate system. However, it should be noted that the negative virtual rotor angle is used when Park transforming the first negative-sequence current component. The process of rotating and transforming the first positive-sequence current component and the first negative-sequence current component obtained above will not be described in detail here.

[0026] It should be noted that in practical applications, the adaptive inertia control of the VSG includes active-frequency control and reactive-voltage control: In the active-frequency control loop, the deviation between the input reference active power and the actual active power (positive-sequence active power) is processed and combined with the integral element of virtual inertia to simulate the rotor motion characteristics and damping adjustment of the synchronous generator, ultimately outputting a virtual rotor angle for subsequent voltage synthesis and grid synchronization; In the reactive-voltage control loop, the deviations between the input reference voltage and the actual voltage, and between the input reference reactive power and the actual reactive power (positive-sequence reactive power), are processed by a PI controller and output as voltage compensation, used to correct voltage commands in subsequent voltage and current dual closed-loop control to ensure the stability of the point of common coupling voltage. In other words, the output of the VSG's adaptive inertia control includes a virtual rotor angle and voltage compensation. The specific control logic of the VSG's adaptive inertia control can be implemented by referring to the existing VGS control logic, and will not be detailed here.

[0027] The method for extracting positive and negative sequence components based on the Fortescue matrix in this application transforms "simple time-domain delay cancellation" into an integrated sequence extraction mechanism of "Clark transform - delay cancellation - precise mapping of the Fortescue matrix - Park transform" by using the Fortescue symmetric component matrix as the mathematical basis for delay cancellation. Compared with the traditional signal delay cancellation (DSC) technique, which delays the current signal by a quarter of the fundamental period and then roughly separates the positive and negative sequence components through simple time-domain addition and subtraction operations, and relies on the empirical method of "delay cancellation of the second harmonic component" without strict mathematical matrix mapping, this method can effectively solve the problems of incomplete decoupling and large component extraction deviation, and achieve uncoupled and accurate extraction of positive and negative sequence components in the dq synchronous rotating coordinate system.

[0028] S12. Obtain the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer-loop voltage control output, and perform positive and negative sequence virtual impedance voltage drop analysis based on the positive-sequence current reference value, the negative-sequence current reference value, and the angle difference value to obtain the positive-sequence impedance voltage drop and the negative-sequence impedance voltage drop; wherein, the outer-loop voltage control is implemented with reference to the VSG control in the existing grid-type converter control, which will not be described in detail here; specifically, the steps of obtaining the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer-loop voltage control output include: Obtain the positive-sequence current reference component and the negative-sequence current reference component of the outer loop voltage control output; wherein, the positive-sequence current reference component includes the d-axis positive-sequence current reference value and the q-axis positive-sequence current reference value in the two-phase synchronous rotating dq coordinate system; the negative-sequence current reference component includes the d-axis negative-sequence current reference value and the q-axis negative-sequence current reference value in the two-phase synchronous rotating dq coordinate system.

[0029] The positive sequence current reference value is obtained by combining the d-axis positive sequence current reference value and the q-axis positive sequence current reference value in the positive sequence current reference component; that is, the positive sequence current reference value is expressed as: (6) in, and These are the d-axis positive sequence current reference value and the q-axis positive sequence current reference value in the positive sequence current reference component, respectively; This is the reference value for the positive sequence current.

[0030] The negative sequence current reference value is obtained by combining the d-axis negative sequence current reference value and the q-axis negative sequence current reference value in the negative sequence current reference component; that is, the negative sequence current reference value is expressed as: (7) in, and These are the d-axis positive sequence current reference value and the q-axis positive sequence current reference value in the positive sequence current reference component, respectively; This is the reference value for the positive sequence current.

[0031] The positive sequence phase angle is obtained by the ratio of the q-axis positive sequence current reference value to the d-axis positive sequence current reference value in the positive sequence current reference component; wherein, the positive sequence phase angle can be expressed as: (8) In the formula, It is the positive sequence phase angle.

[0032] The negative sequence phase angle is obtained by the ratio of the q-axis negative sequence current reference value to the d-axis negative sequence current reference value in the negative sequence current reference component. (9) In the formula, It is a negative phase angle.

[0033] The angle difference is obtained based on the difference between the negative-sequence phase angle and the positive-sequence phase angle; that is, the angle difference is: (10) In the formula, This represents the angle difference.

[0034] After obtaining the positive-sequence current reference value, negative-sequence current reference value, and angle difference through the above methods and steps, virtual impedance calculation and voltage drop synthesis can be performed independently and dynamically in the synchronously rotating coordinate systems of positive and negative sequences, based on the real-time calculated maximum phase current reference value. This reduces the dependence on the current saturation limiter, allowing for early intervention and continuous fault current limiting before the current approaches the limit. Specifically, the step of performing positive and negative sequence virtual impedance voltage drop analysis based on the positive-sequence current reference value, the negative-sequence current reference value, and the angle difference to obtain the positive-sequence impedance voltage drop and the negative-sequence impedance voltage drop includes: Based on the positive-sequence current reference value, the negative-sequence current reference value, and the angle difference, a comparison analysis of the three-phase current reference amplitudes is performed to obtain the maximum current reference amplitude; wherein, the maximum current reference amplitude can be understood as the maximum value among the three-phase current reference amplitudes, and can be expressed as: (11) In the formula, in, , and They are respectively Phase current reference amplitude, b Phase current reference amplitude and c Phase current reference amplitude; This is the maximum current reference amplitude; This represents the square norm.

[0035] The virtual resistance value is obtained based on the difference between the maximum current reference amplitude and the rated current, using a preset virtual resistance gain coefficient. This preset virtual resistance gain coefficient can be understood as a virtual resistance gain proportional to the rated current, and can be set based on actual application requirements. The corresponding virtual resistance value can be expressed as: (12) In the formula, This is a virtual resistance value; Rated current; This is the preset virtual resistance gain coefficient.

[0036] Based on the virtual resistance value and the preset virtual impedance ratio, the corresponding virtual reactance value is obtained; wherein, the virtual reactance value can be understood as the product of the virtual resistance value and the preset virtual impedance ratio, and can be expressed as: (13) In the formula, This is the virtual reactance value; This is the preset virtual impedance ratio.

[0037] Impedance voltage drop is calculated based on the virtual resistance value, the virtual reactance value, the positive sequence current component, and the negative sequence current component to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop; wherein, the impedance voltage drop shown in equation (14) is calculated as follows: (14) In the formula, and These are the d-axis positive sequence impedance voltage drop and the q-axis positive sequence impedance voltage drop, respectively; and These are the d-axis negative sequence impedance voltage drop and the q-axis negative sequence impedance voltage drop, respectively.

[0038] Compared to existing dynamic virtual impedance designs that detect the maximum amplitude of three-phase current in real time and adjust it integrally based on the current state to obtain an overall virtual impedance value, which is then applied simultaneously to the differential terms of the mixed positive and negative sequence currents, and where "positive and negative sequence processing" only reaches the input signal decomposition level and the virtual impedance itself is not decoupled sequentially, the dynamic virtual impedance generation in this embodiment, based on the decoupling of the positive and negative sequence synchronous rotating coordinate system and the prediction of the reference current, does not directly respond to whether the instantaneous amplitude of the measured current exceeds the limit, but rather looks ahead. Based on the positive and negative sequence current reference values ​​and their phase difference from the outer loop voltage control output, the maximum possible amplitude of the synthesized current reference vector is calculated and compared with the rated current to generate virtual resistance and reactance values ​​more smoothly. At the same time, by multiplying the calculated virtual impedance parameters with the precisely decoupled positive sequence current dq component and negative sequence current dq component respectively, the virtual impedance voltage drop is calculated independently in the positive and negative sequence synchronous rotating coordinate system, ensuring that the effect of virtual impedance does not interfere with each other in the positive and negative sequence channels.

[0039] This embodiment proposes a delay elimination method based on the Fortescue matrix for accurate extraction of positive and negative sequence electrical components. It also proposes a virtual impedance voltage drop calculation mechanism that independently calculates virtual impedance and synthesizes voltage drops in synchronously rotating coordinate systems for both positive and negative sequences. This effectively decouples the positive and negative sequence components, eliminating the oscillation problem in current amplitude calculation. This results in a stable and accurate virtual voltage drop, solving the key problem of existing TVI control methods where fault current amplitude calculation in static or single synchronous coordinate systems introduces second-harmonic oscillations, causing the generated virtual impedance voltage drop and output voltage to oscillate accordingly. This makes them unsuitable for fault current limiting in asymmetrical fault scenarios. It can effectively suppress fault current under asymmetrical faults. At the same time, it dynamically generates virtual impedance based on the real-time calculated maximum phase current reference value, reducing the dependence on the current saturation limiter. This allows the virtual impedance to intervene in advance and continue to act when the current approaches the limit value. Thus, throughout the entire process of symmetrical and asymmetrical faults, it strictly limits the converter current within a safe range and always maintains the voltage source characteristics of the VSG. This effectively overcomes the fundamental defect of existing technologies that rely on the current saturation limiter as the trigger condition for virtual impedance, which cannot provide impedance support when the current does not reach the saturation threshold, causing the VSG to lose its autonomous voltage regulation capability during faults or at critical current states.

[0040] S13. Based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component, perform voltage-current dual-closed-loop control to obtain the control output voltage of the three-phase stationary coordinate system, and perform pulse width modulation based on the control output voltage; wherein, voltage-current dual-closed-loop control can be understood as a control strategy that breaks through the limitations of traditional control only targeting the positive-sequence component, integrating independent control of positive and negative sequence components with an active suppression control strategy for negative-sequence voltage; specifically, as follows... Figure 2 As shown, the step of performing voltage and current dual closed-loop control based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component to obtain the control output voltage of the three-phase stationary coordinate system includes: Obtain the voltage compensation amount and virtual rotor angle of the virtual synchronous generator control output; the logic for obtaining the voltage compensation amount and virtual rotor angle is as described above and will not be repeated here.

[0041] A first control output voltage is obtained by performing positive-sequence voltage and current dual closed-loop control based on the voltage compensation amount, the virtual rotor angle, the positive-sequence impedance voltage drop, and the positive-sequence current component. The first control output voltage can be understood as a three-phase voltage signal obtained by PI regulation based on the deviations of the positive-sequence voltage and positive-sequence current from their corresponding reference values. Specifically, the step of obtaining the first control output voltage by performing positive-sequence voltage and current dual closed-loop control based on the voltage compensation amount, the virtual rotor angle, the positive-sequence impedance voltage drop, and the positive-sequence current component includes: The reference value of the converter output d-axis positive sequence current is obtained by voltage control based on the voltage compensation amount, the d-axis positive sequence impedance voltage drop in the positive sequence impedance drop, the positive sequence voltage at the point of common coupling, and the d-axis positive sequence current at the point of common coupling. In practical applications, the voltage compensation amount is used to determine the reference value of the converter output d-axis positive sequence current. With the d-axis positive sequence impedance drop in the positive sequence impedance drop The difference is used to obtain the d-axis positive sequence voltage reference value at the point of common coupling. Then, based on the d-axis positive sequence voltage reference value at the point of common coupling... d-sequence voltage value at the common connection point The difference is used to generate the first control quantity through PI control, and the first control quantity is then compared with the positive sequence current of the d-axis at the point of common coupling. The superposition value and the q-axis current component flowing through the capacitor in the LC filter By subtracting the values, the required d-axis positive sequence current reference value can be obtained. It should be noted that, The synchronization angular frequency is obtained based on virtual synchronous generator control; This represents the filter capacitor value of the LC filter; This represents the positive q-sequence voltage value at the point of common coupling.

[0042] The converter output d-axis positive sequence voltage is obtained by current control based on the converter output d-axis positive sequence current reference value, the positive sequence current component, and the d-axis positive sequence voltage at the common coupling point. In practical applications, the converter output d-axis positive sequence current reference value is used... With the d-axis positive sequence current in the positive sequence current component The difference is used to generate a second control quantity through PI control, and this second control quantity is then compared with the positive sequence voltage of the d-axis at the point of common coupling. The superposition value and the q-axis current component flowing through the inductor in the LC filter By subtracting the values, the desired positive sequence voltage of the converter output d-axis can be obtained. It should be noted that, This represents the filter inductance value of the LC filter. This represents the d-axis positive sequence current value in the positive sequence current component.

[0043] Voltage control is performed based on the q-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop, the positive sequence voltage at the point of common coupling, and the q-axis positive sequence current at the point of common coupling to obtain a reference value for the converter output q-axis positive sequence current. In practical applications, the zero voltage compensation value and the q-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop are used to obtain a reference value for the converter output q-axis positive sequence current. The difference is used to obtain the q-axis positive sequence voltage reference value at the point of common coupling. Then, based on the q-axis positive sequence voltage reference value at the point of common coupling... q-sequence voltage at the common connection point The difference is used to generate a third control quantity through PI control, and this third control quantity is then compared with the q-axis positive sequence current at the common connection point. The superposition value and the d-axis current component flowing through the capacitor in the LC filter By performing the above operations, the required reference value for the positive sequence q-axis current of the converter output can be obtained. It should be noted that, This represents the positive sequence voltage value along the d-axis at the point of common coupling.

[0044] Current control is performed based on the converter output q-axis positive sequence current reference value, the positive sequence current component, and the q-axis positive sequence voltage at the point of common coupling to obtain the converter output q-axis positive sequence voltage. In practical applications, the converter output q-axis positive sequence current reference value is used... With the q-axis positive sequence current in the positive sequence current component The difference is used to generate a fourth control quantity through PI control, and this fourth control quantity is then compared with the positive sequence q-axis voltage at the point of common coupling. The superposition value and the q-axis current component flowing through the inductor in the LC filter By performing the above operations, the desired positive sequence q-axis output voltage of the converter can be obtained. .

[0045] The first control output voltage is generated based on the converter output d-axis positive sequence voltage, the converter output q-axis positive sequence voltage, and the virtual rotor angle; wherein, the first control output voltage can be understood as the converter output d-axis positive sequence voltage obtained above. and converter output q-axis positive sequence voltage Virtual rotor angle based on VSG control output The three-phase voltage signal obtained by performing the inverse Parker transformation; it should be noted that, in this embodiment, the positive sequence voltage value of the d-axis at the point of common coupling is... and the positive sequence q-axis voltage at the common junction This can be understood as based on the voltage V at the point of common coupling. o The positive sequence voltages of the d-axis and q-axis at the point of common coupling obtained by the positive and negative sequence component extraction method mentioned above can be obtained by simply replacing the three-phase instantaneous current output by the grid-type converter mentioned above with the three-phase voltage at the point of common coupling.

[0046] In this embodiment, the PI regulator is used to process the deviation between the positive sequence voltage reference value and the positive sequence voltage value, which can effectively ensure the dynamic response and steady-state accuracy of the base frequency voltage.

[0047] A second control output voltage is obtained by performing a dual closed-loop control of negative sequence voltage and current based on the negative sequence impedance voltage drop, the virtual rotor angle, and the negative sequence current component. The second control output voltage can be understood as a three-phase voltage signal obtained by PI regulation based on the deviations of the negative sequence voltage and negative sequence current from their corresponding reference values. Specifically, the step of obtaining the second control output voltage by performing a dual closed-loop control of negative sequence voltage and current based on the negative sequence impedance voltage drop, the virtual rotor angle, and the negative sequence current component includes: The reference value of the converter output d-axis negative sequence current is obtained by voltage control based on the d-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common coupling point, and the d-axis negative sequence current at the common coupling point. In practical applications, the reference value of the converter output d-axis negative sequence current is obtained based on the zero voltage compensation value and the d-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop. The difference is used to obtain the d-axis negative sequence voltage reference value at the point of common coupling. Then, based on the d-axis negative sequence voltage reference value at the point of common coupling... d-sequence voltage value at the common connection point The difference is used to generate a fifth control quantity through PI control, and this fifth control quantity is then compared with the d-axis negative sequence current at the point of common coupling. The superposition value and the q-axis current component flowing through the capacitor in the LC filter By summing the results, the required d-axis negative sequence current reference value can be obtained. It should be noted that, This represents the q-axis negative sequence voltage at the point of common coupling.

[0048] The converter output d-axis negative sequence voltage is obtained by current control based on the converter output d-axis negative sequence current reference value, the negative sequence current component, and the d-axis negative sequence voltage at the common coupling point; in practical applications, the converter output d-axis negative sequence current reference value is used as the basis for current control. With the d-axis negative sequence current in the negative sequence current component The difference is used to generate a sixth control quantity through PI control, and this sixth control quantity is then compared with the negative sequence voltage of the d-axis at the point of common coupling. The superposition value and the q-axis current component flowing through the inductor in the LC filter By performing the above operations, the required negative sequence voltage of the converter output d-axis can be obtained. It should be noted that, This represents the q-axis negative sequence current value in the negative sequence current component.

[0049] Voltage control is performed based on the q-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common coupling point, and the q-axis negative sequence current at the common coupling point to obtain a reference value for the converter output q-axis negative sequence current. In practical applications, the zero voltage compensation value and the q-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop are used to obtain a reference value for the converter output q-axis negative sequence current. The difference is used to obtain the q-axis negative sequence voltage reference value at the point of common coupling. Then, based on the q-axis negative sequence voltage reference value at the point of common coupling... negative q-sequence voltage at the point of common connection The difference is used to generate a seventh control quantity through PI control, and this seventh control quantity is then compared with the q-axis negative sequence current at the point of common connection. The superposition value and the d-axis current component flowing through the capacitor in the LC filter By subtracting the values, the required reference value for the negative sequence q-axis current of the converter output can be obtained. .

[0050] Current control is performed based on the converter output q-axis negative sequence current reference value, the negative sequence current component, and the q-axis negative sequence voltage at the common coupling point to obtain the converter output q-axis negative sequence voltage; in practical applications, the converter output q-axis negative sequence current reference value is used as the basis for current control. With the q-axis negative sequence current in the negative sequence current component The difference is used to generate the eighth control quantity through PI control, and the eighth control quantity is then compared with the q-axis negative sequence voltage at the point of common coupling. The superposition value and the d-axis current component flowing through the inductor in the LC filter By subtracting the values, the required negative sequence q-axis output voltage of the converter can be obtained. .

[0051] The second control output voltage is generated based on the converter output d-axis negative sequence voltage, the converter output q-axis negative sequence voltage, and the virtual rotor angle; wherein, the second control output voltage can be understood as the converter output d-axis negative sequence voltage obtained above. and converter output q-axis negative sequence voltage Virtual rotor angle based on VSG control output The three-phase voltage signal obtained by performing the inverse Parker transformation; it should be noted that, in this embodiment, the negative sequence voltage value of the d-axis at the point of common coupling is... negative q-sequence voltage at the common junction This can be understood as based on the voltage V at the point of common coupling. o The negative sequence voltages of the d-axis and q-axis at the point of common coupling obtained by the positive and negative sequence component extraction method mentioned above can be obtained by simply replacing the three-phase instantaneous current output by the grid-type converter mentioned above with the three-phase voltage at the point of common coupling.

[0052] In this embodiment, by setting the voltage reference value to 0 and adjusting the PI regulator based on the deviation between the negative sequence voltage and the reference negative sequence voltage, the negative sequence component can be actively suppressed to reduce the voltage distortion rate.

[0053] The first control output voltage and the second control output voltage are combined to obtain the control output voltage. It should be noted that after obtaining the control output voltage through the above method steps, a pulse width modulation (PWM) signal can be generated based on this control output voltage. For details, please refer to relevant existing technologies; these will not be elaborated here.

[0054] The control strategy provided in this embodiment, which integrates independent control of positive and negative sequence components and active suppression of negative sequence voltage, can not only ensure voltage stability and power transmission accuracy during normal operation, but also coordinate with the virtual impedance current limiting strategy when a grid asymmetry fault occurs. This can effectively maintain the voltage source characteristics of the VSG, effectively suppress negative sequence voltage and limit negative sequence current, and significantly improve the operational stability and power quality of the VSG under complex grid conditions.

[0055] Furthermore, to verify the effectiveness of the fault current limiting method for grid-connected converters provided by this invention, this embodiment also conducts simulation verification by building a simulation model in Simulink. Specifically, in the simulation verification, a single-phase short-circuit grounding is applied at the point of common coupling, and the existing fault current control scheme and the fault current limiting scheme for grid-connected converters provided by this invention are compared in multiple dimensions. This mainly includes comparing converter current and output voltage, negative sequence current and negative sequence voltage, and active power, and obtaining... Figures 3-9 The simulation results are shown below: By comparison Figure 3 and Figure 4 (Converter current) It can be observed that for both TVI current limiting control schemes, the phase current is limited to within 1.5 pu, and the phase current exhibits a sine wave pattern; through comparison... Figure 5 and Figure 6 (Output voltage) It can be seen that the existing fault current limiting scheme has a more serious output voltage distortion and slow recovery after the fault is eliminated, while the fault current limiting scheme provided by the present invention has a significantly reduced output voltage distortion rate and can quickly recover to the rated value. Depend on Figure 7 (Comparison of negative sequence current changes) shows that, compared to existing fault current limiting schemes, the fault current limiting scheme provided by this invention exhibits a significantly faster negative sequence current decay rate; from Figure 8 (Comparison of negative sequence voltage changes) shows that, compared with existing fault current limiting schemes, the fault current limiting scheme provided by this invention has a lower negative sequence voltage peak and a faster decay rate, which helps the three-phase voltage of the power grid to quickly return to balance; from Figure 9 (Comparison of active power changes) It can be seen that the active power oscillation of the existing fault current limiting scheme is severe, while the active power fluctuation of the fault current limiting scheme provided by the present invention is small, with no obvious high-frequency oscillation. After the fault is cleared, it can quickly recover to the rated active power, which can significantly ensure the stability of power transmission and reduce the power grid safety and stability problems caused by power fluctuations.

[0056] In summary, based on Figures 3-9 As shown, when encountering the same asymmetrical fault of single-phase short-circuit grounding, the VSG model built based on the control strategy provided by this invention and the VSG model built based on existing current control scheme technology have different effects. In this case, the VSG model in the scheme provided by this invention has smaller output phase voltage distortion, faster decay of negative sequence current and negative sequence voltage, and almost no oscillation of active power. However, the negative sequence output voltage of the existing TVI control does not immediately return to zero after the fault is cleared, which will cause oscillation of output active power.

[0057] The present invention provides a technical solution for acquiring the three-phase current signal of a converter in a three-phase stationary coordinate system, extracting the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal to obtain the positive and negative sequence current components, performing positive and negative sequence virtual impedance voltage drop analysis based on the obtained positive and negative sequence current reference values ​​and angle difference values ​​controlled by the outer loop voltage to obtain the positive and negative sequence impedance voltage drops, and performing voltage and current dual closed-loop control based on the positive and negative sequence impedance voltage drops, the positive and negative sequence current components to obtain the control output voltage in the three-phase stationary coordinate system, and performing pulse width modulation based on the control output voltage. This solution, based on the decoupling of positive and negative sequence current components in the synchronous rotating coordinate system and combined with a current-limiting control mechanism using real-time positive and negative sequence virtual impedance voltage drop analysis, not only dynamically generates virtual impedance based on the real-time calculated maximum phase current reference value, reducing reliance on current saturation limiters, but also allows the virtual impedance to intervene in advance when the current approaches the limit. This invention provides continuous control, strictly limiting the converter current within a safe range throughout both symmetrical and asymmetrical fault processes, and maintaining the voltage source characteristics of the VSG. It effectively overcomes the fundamental flaw of existing technologies that only take effect after current saturation and cannot maintain normal operating characteristics. Furthermore, it features a key innovation: precise extraction of positive and negative sequence electrical components based on the Fortescue matrix delay elimination method, and independent calculation of virtual impedance and voltage drop synthesis in synchronously rotating coordinate systems for positive and negative sequences. This effectively decouples the positive and negative sequence components, eliminates oscillations in current amplitude calculation, and generates a stable and accurate virtual voltage drop. This allows for effective suppression of fault current under both symmetrical and asymmetrical faults, effectively solving the critical problem of poor adaptability of traditional methods under asymmetrical conditions. In other words, this invention improves the stability of VSG operation and the ability to maintain voltage source characteristics under asymmetrical faults, while enhancing the uniformity and effectiveness of TVI current limiting control in both symmetrical and asymmetrical fault scenarios, thereby effectively enhancing system stability.

[0058] It should be noted that although the steps in the flowchart above are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order requirement for the execution of these steps, and they can be executed in other orders.

[0059] In one embodiment, such as Figure 10 As shown, a fault current limiting system for a grid-type converter is provided, the system comprising: The positive and negative sequence component extraction module 1 is used to acquire the three-phase current signal of the converter in the three-phase stationary coordinate system, and extract the positive and negative sequence current components in the two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. Impedance drop analysis module 2 is used to obtain the positive sequence current reference value, negative sequence current reference value and angle difference value of the outer loop voltage control output, and to perform positive and negative sequence virtual impedance drop analysis based on the positive sequence current reference value, the negative sequence current reference value and the angle difference value to obtain the positive sequence impedance drop and the negative sequence impedance drop. The dual closed-loop control module 3 is used to perform voltage and current dual closed-loop control based on the positive sequence impedance voltage drop, the negative sequence impedance voltage drop, the positive sequence current component and the negative sequence current component to obtain the control output voltage of the three-phase stationary coordinate system, and to perform pulse width modulation based on the control output voltage.

[0060] Specific limitations regarding the fault current limiting system for grid-type converters can be found in the above description of the fault current limiting method for grid-type converters, and the corresponding technical effects are equivalent, so they will not be repeated here. Each module in the aforementioned fault current limiting system for grid-type converters can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0061] Figure 11 An internal structural diagram of a computer device is shown in one embodiment. This computer device may specifically be a terminal or a server. Figure 11As shown, the computer device includes a processor, memory, network interface, display, camera, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it can implement a fault current limiting method for grid-type converters. The display screen can be an LCD screen or an e-ink display screen. The input device can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device casing, or an external keyboard, touchpad, or mouse.

[0062] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. Specific computing devices may include more or fewer components than those shown in the figure, or combine certain components, or have the same component arrangement.

[0063] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described above.

[0064] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0065] In summary, the fault current limiting method, system, computer device, and storage medium provided by this invention not only dynamically generate virtual impedance based on the real-time calculated maximum phase current reference value, reducing reliance on current saturation limiters, but also allow the virtual impedance to intervene early and continue to act when the current approaches the limit. This strictly limits the converter current within a safe range throughout the entire process of symmetrical and asymmetrical faults, while maintaining the voltage source characteristics of the VSG. This effectively overcomes the fundamental defect of existing technologies that only take effect after current saturation and cannot maintain normal operating characteristics. Furthermore, it can perform positive and negative current limiting based on the Fortescue matrix delay elimination method. The key innovations of accurately extracting the sequence electrical components and independently calculating the virtual impedance and synthesizing the voltage drop in the synchronously rotating coordinate systems of positive and negative sequence effectively decouple the positive and negative sequence components, eliminate the oscillation problem in the current amplitude calculation, and generate a stable and accurate virtual voltage drop. This enables effective suppression of fault current under both symmetrical and asymmetrical fault conditions, effectively solving the key problem of poor adaptability of traditional methods under asymmetrical operating conditions. In other words, this invention can improve the stability of VSG operation and the ability to maintain voltage source characteristics under asymmetrical fault conditions, while improving the uniformity and effectiveness of TVI current limiting control under symmetrical and asymmetrical fault scenarios, thereby effectively enhancing system stability.

[0066] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of the embodiments, refer to each other. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0067] The above-described embodiments are merely preferred embodiments of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A fault current limiting method for a grid-type converter, characterized in that, The method includes: The three-phase current signal of the converter in the three-phase stationary coordinate system is obtained, and the positive and negative sequence current components in the two-phase synchronous rotating coordinate system are extracted based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. Obtain the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer loop voltage control output, and perform positive and negative sequence virtual impedance voltage drop analysis based on the positive-sequence current reference value, the negative-sequence current reference value, and the angle difference value to obtain the positive-sequence impedance voltage drop and the negative-sequence impedance voltage drop. Based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component, voltage and current dual closed-loop control is performed to obtain the control output voltage of the three-phase stationary coordinate system, and pulse width modulation is performed based on the control output voltage.

2. The fault current limiting method for a grid-type converter as described in claim 1, characterized in that, The step of extracting the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component includes: The three-phase current signal of the converter is subjected to Clarke transformation to obtain the first current signal in the two-phase stationary coordinate system. The first current signal is delayed by a quarter cycle to obtain the second current signal; Based on the second current signal and the first current signal, a transformation process is performed based on a preset symmetric component matrix to obtain the first positive sequence current component and the first negative sequence current component in the two-phase stationary coordinate system. The first positive-sequence current component and the first negative-sequence current component are subjected to Park transformation to obtain the positive-sequence current component and the negative-sequence current component in the two-phase synchronous rotating coordinate system.

3. The fault current limiting method for a grid-type converter as described in claim 1, characterized in that, The steps for obtaining the positive-sequence current reference value, negative-sequence current reference value, and angle difference value of the outer loop voltage control output include: Obtain the positive-sequence current reference component and the negative-sequence current reference component of the outer loop voltage control output; The positive sequence current reference value is obtained by combining the d-axis positive sequence current reference value and the q-axis positive sequence current reference value in the positive sequence current reference component. The negative sequence current reference value is obtained by combining the d-axis negative sequence current reference value and the q-axis negative sequence current reference value in the negative sequence current reference component. The positive sequence phase angle is obtained by the ratio of the q-axis positive sequence current reference value to the d-axis positive sequence current reference value in the positive sequence current reference component. The negative sequence phase angle is obtained by the ratio of the q-axis negative sequence current reference value to the d-axis negative sequence current reference value in the negative sequence current reference component. The angle difference is obtained based on the difference between the negative phase angle and the positive phase angle.

4. The fault current limiting method for a grid-type converter as described in claim 1, characterized in that, The step of performing positive and negative sequence virtual impedance voltage drop analysis based on the positive sequence current reference value, the negative sequence current reference value, and the angle difference to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop includes: Based on the positive sequence current reference value, the negative sequence current reference value and the angle difference, the three-phase current reference amplitude is compared and analyzed to obtain the maximum current reference amplitude. The virtual resistance value is obtained based on the difference between the maximum current reference amplitude and the rated current, using a preset virtual resistance gain coefficient. Based on the virtual resistance value and the preset virtual impedance ratio, the corresponding virtual reactance value is obtained; The impedance voltage drop is calculated based on the virtual resistance value, the virtual reactance value, the positive sequence current component, and the negative sequence current component to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop.

5. The fault current limiting method for a grid-type converter as described in claim 1, characterized in that, The step of performing voltage and current dual closed-loop control based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component to obtain the control output voltage of the three-phase stationary coordinate system includes: Obtain the voltage compensation amount and virtual rotor angle of the virtual synchronous generator control output; Based on the voltage compensation amount, the virtual rotor angle, the positive sequence impedance voltage drop, and the positive sequence current component, perform positive sequence voltage and current dual closed-loop control to obtain the first control output voltage; Based on the negative sequence impedance voltage drop, the virtual rotor angle, and the negative sequence current component, a negative sequence voltage and current dual closed-loop control is performed to obtain the second control output voltage. The first control output voltage and the second control output voltage are combined to obtain the control output voltage.

6. The fault current limiting method for a grid-type converter as described in claim 5, characterized in that, The step of performing positive-sequence voltage and current dual closed-loop control based on the voltage compensation amount, the virtual rotor angle, the positive-sequence impedance voltage drop, and the positive-sequence current component to obtain the first control output voltage includes: The voltage control is performed based on the voltage compensation amount, the d-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop, the positive sequence voltage at the common coupling point and the d-axis positive sequence current at the common coupling point to obtain the reference value of the converter output d-axis positive sequence current. The converter output d-axis positive sequence voltage is obtained by current control based on the reference value of the converter output d-axis positive sequence current, the positive sequence current component, and the d-axis positive sequence voltage at the common connection point. Voltage control is performed based on the q-axis positive sequence impedance voltage drop in the positive sequence impedance voltage drop, the positive sequence voltage at the common connection point, and the q-axis positive sequence current at the common connection point to obtain the reference value of the converter output q-axis positive sequence current. Current control is performed based on the reference value of the q-axis positive sequence current output of the converter, the positive sequence current component, and the q-axis positive sequence voltage at the common connection point to obtain the q-axis positive sequence voltage output of the converter. The first control output voltage is generated based on the d-axis positive sequence voltage output by the converter, the q-axis positive sequence voltage output by the converter, and the virtual rotor angle.

7. The fault current limiting method for a grid-type converter as described in claim 5, characterized in that, The step of performing negative-sequence voltage and current dual closed-loop control based on the negative-sequence impedance voltage drop, the virtual rotor angle, and the negative-sequence current component to obtain the second control output voltage includes: The reference value of the converter output d-axis negative sequence current is obtained by voltage control based on the d-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common connection point and the d-axis negative sequence current at the common connection point. The converter output d-axis negative sequence voltage is obtained by current control based on the converter output d-axis negative sequence current reference value, the negative sequence current component, and the d-axis negative sequence voltage at the common connection point. Voltage control is performed based on the q-axis negative sequence impedance voltage drop in the negative sequence impedance voltage drop, the negative sequence voltage at the common connection point, and the q-axis negative sequence current at the common connection point to obtain the reference value of the converter output q-axis negative sequence current. Current control is performed based on the reference value of the q-axis negative sequence current output of the converter, the negative sequence current component, and the q-axis negative sequence voltage at the common connection point to obtain the q-axis negative sequence voltage output of the converter. The second control output voltage is generated based on the d-axis negative sequence voltage of the converter output, the q-axis negative sequence voltage of the converter output, and the virtual rotor angle.

8. A fault current limiting system for a grid-type converter, characterized in that, The system includes: The positive and negative sequence component extraction module is used to acquire the three-phase current signal of the converter in a three-phase stationary coordinate system, and extract the positive and negative sequence current components in a two-phase synchronous rotating coordinate system based on the three-phase current signal of the converter to obtain the positive sequence current component and the negative sequence current component. The impedance voltage drop analysis module is used to obtain the positive sequence current reference value, negative sequence current reference value and angle difference value of the outer loop voltage control output, and to perform positive and negative sequence virtual impedance voltage drop analysis based on the positive sequence current reference value, the negative sequence current reference value and the angle difference value to obtain the positive sequence impedance voltage drop and the negative sequence impedance voltage drop. The dual closed-loop control module is used to perform voltage and current dual closed-loop control based on the positive-sequence impedance voltage drop, the negative-sequence impedance voltage drop, the positive-sequence current component, and the negative-sequence current component to obtain the control output voltage of the three-phase stationary coordinate system, and to perform pulse width modulation based on the control output voltage.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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