Switched capacitor converter and method of controlling the same

Abstract

The application discloses a switched capacitor converter and a control method thereof. The switched capacitor converter comprises first and second conversion units connected in parallel between an input terminal and a ground terminal. The first conversion unit comprises first to third transistors and a first capacitor, and the second conversion unit comprises fourth to sixth transistors and a second capacitor. The second conversion unit further comprises a plurality of paired transistors, a first paired capacitor and a second paired capacitor. In a first working mode, the first and second capacitors and the first and second paired capacitors can all be flying capacitors in a switching cycle by controlling the switching sequence of the transistors, so as to realize a two-to-one conversion between the input and the output. The current branch is increased without adding extra transistors, the current effective value during switching is reduced, the loss is reduced, and the converter efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, specifically to a switched capacitor converter and its control method. Background Technology

[0002] With the rapid development of electronic systems, wired or wireless fast charging of terminal devices such as mobile phones, watches, and tablets is mostly achieved by outputting a voltage that is 2 or 4 times higher than the battery voltage through a power adapter or wireless charging circuit, and then reducing the high voltage to 1 / 2 or 1 / 4 of the voltage through a switched capacitor converter in the terminal device before charging the battery.

[0003] To save costs, when using a switched capacitor converter with an input-output voltage ratio of 4:1, it is desirable to achieve a 2:1 mode through a simple topology transformation. Figure 1 A schematic circuit connection diagram of a prior art switched-capacitor converter in its first operating mode is shown. Figure 1 As shown, the switched capacitor converter 110 includes two identical converter phases. The left-hand converter includes a transistor Q1a with its first terminal connected to the input terminal and its second terminal connected to the first terminal of capacitor C1A; a transistor Q2a connected between the second terminal of capacitor C1A and ground; transistors Q3a, Q8a, Q9a, and Q10a connected in series between the second terminal of capacitor C1A and ground; and transistors Q7a, Q4a, Q5a, and Q6a connected in series between the second terminal of transistor Q1a and ground. Capacitor C2A is connected in parallel across transistors Q4a and Q5a, and capacitor C4A is connected in parallel across transistors Q8a and Q9a. The transistor and capacitor connections of the right-hand converter are the same as those of the left-hand converter.

[0004] The first operating mode is the input-output voltage ratio mode of 2:1. In this mode, such as Figure 1 Capacitors C1A and C1B are effectively connected between the input terminal and the ground terminal, serving as input filter capacitors. The branches containing transistors Q3a and Q3b are disconnected, shown in gray in the diagram. Transistors Q7a (Q7b), Q4a (Q4b), Q5a (Q5b), and Q6a (Q6b) conduct complementaryly in the first and second halves of a switching cycle. Figure 1 The solid coil represents the transistor that needs to be turned on in the first half of the cycle, and the dashed coil represents the transistor that needs to be turned on in the second half of the cycle. Calculations show that VIN = 2VOA = 2VOB, achieving a 2:1 conversion.

[0005] but Figure 1In this configuration, only capacitors C2A and C2B act as flying capacitors, resulting in fewer current branches and excessively high effective current during switching, leading to low converter efficiency. Adding more current branches necessitates additional transistors, increasing chip area and cost. Therefore, current switched-capacitor converters struggle to simultaneously balance chip area and effective current. Summary of the Invention

[0006] This application provides a switched capacitor converter and its control method to solve the problems in the prior art.

[0007] According to one aspect of the present invention, a switched-capacitor converter is provided, comprising: a first conversion unit and a second conversion unit having the same circuit connection structure connected in parallel between an input terminal and a ground terminal; wherein, the first conversion unit includes a first energy storage unit and a second energy storage unit, the first energy storage unit including a first transistor, a first capacitor and a second transistor connected in series between the input terminal and the ground terminal, and a third transistor connected between a first terminal of the first capacitor and a common node of the second transistor and a first output node; the second energy storage unit includes a fourth transistor, a fifth transistor and a sixth transistor connected in series between a second terminal of the first capacitor and the ground terminal, and a second capacitor connected in parallel across the fourth transistor and the fifth transistor, the common node of the fourth transistor and the fifth transistor being a second output node; the second conversion unit includes a first paired energy storage unit and a second paired energy storage unit, the first paired energy storage unit correspondingly including a first paired transistor, a first capacitor, a second capacitor, a third transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in series between a second terminal of the first capacitor and the ground terminal, and a second capacitor connected in parallel across the fourth transistor and the fifth transistor, the common node of the fourth transistor and the fifth transistor being a second output node; the second conversion unit includes a first paired energy storage unit and a second paired energy storage unit, the first paired energy storage unit correspondingly including a first paired transistor, a first paired transistor, a second paired transistor, a third transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in series between the input terminal and the ground terminal, and a second capacitor connected in parallel across the fourth transistor and the fifth transistor, the common node of the fourth transistor and the fifth transistor being a second output node; the second energy storage unit includes a first paired energy storage unit and a second paired energy storage unit, the first paired energy storage unit correspondingly including a first paired transistor, a second paired energy storage unit, a third paired energy storage unit, a fourth paired energy storage unit, a fifth paired energy storage unit, and a sixth paired energy storage unit, the first paired energy storage unit including a first paired transistor, a third paired energy storage unit, a fifth paired energy storage unit, and a sixth paired energy storage unit, The system comprises a first paired capacitor, a second paired transistor, a third paired transistor, and a third output node; the second paired energy storage unit includes a fourth paired transistor, a fifth paired transistor, a sixth paired transistor, a second paired capacitor, and a fourth output node; in the first operating mode, by controlling the switching sequence of each transistor, in the first half of a switching cycle, the first capacitor is equivalently connected between the input terminal and the first output node, the second capacitor is equivalently connected between the input terminal and the second output node, and the first paired capacitor and the second paired capacitor are respectively equivalently connected between the ground terminal and the fourth output node; while in the second half of a switching cycle, the first capacitor and the second capacitor are respectively equivalently connected between the ground terminal and the second output node, the first paired capacitor is equivalently connected between the input terminal and the third output node, and the second paired capacitor is equivalently connected between the input terminal and the fourth output node.

[0008] Optionally, in the first operating mode, the second output node is connected to the first output terminal, the fourth output node is connected to the second output terminal, the first output node is connected to one of the first output terminal and the second output terminal, and the third output node is connected to the other of the first output terminal and the second output terminal.

[0009] Optionally, in the first operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal, and the ratio of the voltage at the input terminal to the voltage at the second output terminal, are both 2:1.

[0010] Optionally, in the first operating mode, during the first half-cycle, the first transistor, the third transistor, the fifth transistor, the second paired transistor, the fourth paired transistor, and the sixth paired transistor are all in the on state, while the second transistor, the fourth transistor, the sixth transistor, the first paired transistor, the third paired transistor, and the fifth paired transistor are all in the off state; during the second half-cycle, the on states of the first transistor to the sixth transistor and the first paired transistor to the sixth paired transistor are opposite to their respective on states during the first half-cycle.

[0011] Optionally, the second energy storage unit further includes a seventh transistor connected between the common node of the fourth transistor and the second capacitor and the second terminal of the first capacitor. The second paired energy storage unit correspondingly includes a seventh paired transistor, and in the first operating mode, the seventh transistor and the seventh paired transistor are in a normally-on state throughout the entire switching cycle. The first energy storage unit further includes an eighth transistor connected between the third transistor and the first output node. The first paired energy storage unit correspondingly includes an eighth paired transistor, and in the first operating mode, in the first half-cycle, the eighth transistor is in a conducting state and the eighth paired transistor is in a turning-off state; while in the second half-cycle, the eighth transistor is in a turning-off state and the eighth paired transistor is in a conducting state.

[0012] Optionally, the first energy storage unit further includes a third capacitor, which is equivalently connected between the first output node and the common node of the fifth paired transistor and the sixth paired transistor during the first half-cycle; the first paired energy storage unit correspondingly includes a third paired capacitor, which is equivalently connected between the common node of the fifth transistor and the sixth transistor and the third output node during the second half-cycle, and both the third capacitor and the third paired capacitor are output filter capacitors.

[0013] Optionally, the first conversion unit further includes a third energy storage unit, which includes a ninth transistor and a tenth transistor connected between the first output node and the ground terminal, and a fourth capacitor connected between the common node of the ninth transistor and the tenth transistor and the common node of the third transistor and the eighth transistor; the second conversion unit correspondingly includes a third paired energy storage unit, which correspondingly includes a ninth paired transistor, a tenth paired transistor and a fourth paired capacitor. In the first operating mode, the ninth transistor, the tenth transistor, the ninth paired transistor and the tenth paired transistor are in a normally off state throughout the entire operating cycle.

[0014] Optionally, in the second operating mode, the first output node and the second output node are connected to the first output terminal, and the third output node and the fourth output node are connected to the second output terminal; or, the second output node and the third output node are connected to the first output terminal, and the first output node and the fourth output node are connected to the second output terminal; or, the first output node to the fourth output node are all connected to the same output terminal. In the first half of a switching cycle, the first transistor, the third transistor, the fourth transistor, the sixth transistor, the ninth transistor, the second paired transistor, the fifth paired transistor, the seventh paired transistor, the eighth paired transistor, and the tenth paired transistor are all in the on state, while the first paired transistor, the third paired transistor, the fourth paired transistor, the sixth paired transistor, the ninth paired transistor, the second transistor, the fifth transistor, the seventh transistor, the eighth transistor, and the tenth transistor are all in the off state. In the second half of a switching cycle, the on states of the first transistor to the tenth transistor and the first paired transistor to the tenth paired transistor are opposite to their respective on states in the first half of the cycle.

[0015] Optionally, in the second operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal, and the ratio of the voltage at the input terminal to the voltage at the second output terminal, are both 4:1.

[0016] Optionally, in the second operating mode, the fifth paired transistor and the sixth paired transistor are multiplexed as the ninth transistor and the tenth transistor, respectively, and the fifth transistor and the sixth transistor are multiplexed as the ninth paired transistor and the tenth paired transistor, respectively.

[0017] According to another aspect of the present invention, a control method for a switched-capacitor converter is provided, applied to the aforementioned switched-capacitor converter, wherein, in the first operating mode, the control method includes: controlling the first transistor, the third transistor, the fifth transistor, the second paired transistor, the fourth paired transistor, and the sixth paired transistor to be turned on during the first half-cycle of a switching cycle; controlling the second transistor, the fourth transistor, the sixth transistor, the first paired transistor, the third paired transistor, and the fifth paired transistor to be turned on during the second half-cycle of a switching cycle; alternately repeating the switching actions of the first half-cycle and the second half-cycle, such that the first capacitor, the second capacitor, the first paired capacitor, and the second paired capacitor all act as flying capacitors.

[0018] The embodiments of the present invention have at least the following beneficial effects:

[0019] The switched-capacitor converter and its control method provided by this invention control the conduction timing of each transistor in a first operating mode. This ensures that in the first half of a switching cycle, both the first and second capacitors are equivalently connected between the input and output terminals, and the first and second paired capacitors are equivalently connected between the ground and output terminals. In the second half of the cycle, the first and second capacitors are equivalently connected between the ground and output terminals, and the first and second paired capacitors are equivalently connected between the input and output terminals. Therefore, in this mode, the first, second, first, and second paired capacitors can all act as flying capacitors, increasing the current branch, reducing the effective current value during circuit switching, and minimizing losses. This improves the converter efficiency without adding additional components.

[0020] Furthermore, by matching the four output nodes with the two output terminals, the switched capacitor converter can be split into independent two-phase converters or combined into a single-phase converter, achieving an input-output ratio of 2:1 under different circuit structures.

[0021] Furthermore, by changing the connection method between the four output nodes and the two output terminals, all output nodes of the same phase converter are connected to the same output terminal. By adjusting the transistor turn-on timing, the switched-capacitor converter can also operate in a second operating mode. In this second mode, the circuit can have three pairs of flying capacitors, achieving a 4:1 input-output ratio. Thus, without changing the circuit topology, multiple operating modes can be accommodated while maintaining a small device area.

[0022] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0023] Figure 1 A schematic circuit connection diagram of a prior art switched capacitor converter in a first operating mode is shown;

[0024] Figure 2 A schematic circuit connection diagram of the improved switched-capacitor converter in the first operating mode is shown.

[0025] Figure 3 It shows Figure 2 Timing waveform diagram of the switched capacitor converter in the first operating mode;

[0026] Figure 4 A schematic circuit connection diagram of a switched capacitor converter according to a first embodiment of the present invention in a first operating mode is shown.

[0027] Figure 5 It shows Figure 4 Timing waveform diagram of the switched capacitor converter in the first operating mode;

[0028] Figure 6 It shows Figure 4 The equivalent circuit diagram of the switched capacitor converter in the first half of a switching cycle in the first operating mode.

[0029] Figure 7 It shows Figure 4 The equivalent circuit diagram of the switched capacitor converter in the second half of a switching cycle in the first operating mode.

[0030] Figure 8 A schematic circuit connection diagram of a switched capacitor converter according to a second embodiment of the present invention in a first operating mode is shown;

[0031] Figure 9 A schematic circuit connection diagram of a switched capacitor converter according to a third embodiment of the present invention in a first operating mode is shown;

[0032] Figure 10 A schematic circuit connection diagram of a switched capacitor converter according to a first embodiment of the present invention in a second operating mode is shown;

[0033] Figure 11 It shows Figure 10 Timing waveform diagram of the switched capacitor converter in the second operating mode;

[0034] Figure 12 A schematic circuit connection diagram of a switched capacitor converter according to a second embodiment of the present invention in a second operating mode is shown;

[0035] Figure 13A schematic circuit connection diagram of a switched capacitor converter in a second operating mode according to a third embodiment of the present invention is shown. Detailed Implementation

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0037] Figure 2 A schematic circuit connection diagram of the improved switched-capacitor converter in the first operating mode is shown. Figure 3 It shows Figure 2 Timing waveform diagram of switched capacitor converter 120 in the first operating mode.

[0038] To increase the flying capacitor in the circuit Figure 2 The switched capacitor converter 120 in the embodiment is in Figure 1 Based on the switched capacitor converter 110, two transistors, namely transistor Qadd1 and transistor Qadd2, are added. For example... Figure 2 As shown, one end of transistor Qadd1 is connected to the first terminal of capacitor C1A in the left-hand phase converter, and the other end is connected to the common node of capacitor C4A and transistor Q3a. The drain of transistor Qadd2 is connected to the first terminal of capacitor C1B in the right-hand phase converter, and the other end is connected to the common node of capacitor C4B and transistor Q3b. Figure 2 In the diagram, transistors Q1a, Q1b, Q2a, and Q2b are all normally on, while transistors Q3a and Q3b are normally off. This allows capacitors C1A and C1B to be effectively connected between the input terminal and ground, acting as input filter capacitors. The remaining transistors perform switching operations. Solid coils in the diagram represent transistors that are on during the first half of a switching cycle, while dashed coils represent transistors that need to be on during the second half of a switching cycle.

[0039] Combination Figure 3Taking the example of transistors being on when high and off when low, in the first half-cycle T1 of a switching cycle T, transistors Q5a, Q7a, Q8a, Q10a, Q4b, Q6b, Q9b, and Qadd2 are on, while the remaining transistors Q4a, Q6a, Q9a, Q5b, Q7b, Q8b, Q10b, and Qadd1 remain off. At this time, capacitor C2A is equivalently connected between the input terminal VIN and the output terminal VOA, capacitor C4A is equivalently connected between the output terminal VOA and ground, capacitor C4B is equivalently connected between the input terminal VIN and the output terminal VOB, and capacitor C2B is equivalently connected between the output terminal VOB and ground. In the second half of cycle T2, transistors Q5b, Q7b, Q8b, Q10b, Q4a, Q6a, Q9a, and Qadd1 are in the on state, while the remaining transistors Q4b, Q6b, Q9b, Q5a, Q7a, Q8a, Q10a, and Qadd2 remain off. At this time, capacitor C4A is equivalently connected between the input terminal VIN and the output terminal VOA, capacitor C2A is equivalently connected between the output terminal VOA and ground, capacitor C2B is equivalently connected between the input terminal VIN and the output terminal VOB, and capacitor C4B is equivalently connected between the output terminal VOB and ground. Based on the voltage conversion across the capacitors, VIN = 2VOA = 2VOB, thus achieving a 2:1 voltage ratio conversion.

[0040] In the switched capacitor converter 120, each phase has two flying capacitors. While this improves the converter's efficiency, it is achieved by adding two transistors, Qadd1 and Qadd2, increasing chip area and cost. Therefore, this application improves upon the existing technology by increasing the number of flying capacitors without adding additional transistors, thereby increasing the current branch. The following is combined with... Figures 4-13 Detailed introduction.

[0041] Figure 4 A schematic circuit connection diagram of a switched-capacitor converter according to a first embodiment of the present invention in a first operating mode is shown. Figure 5 It shows Figure 4 Timing waveform diagram of the switched capacitor converter in the first operating mode.

[0042] like Figure 4 As shown, the switched capacitor converter 200 of this embodiment includes a first conversion unit 210 and a second conversion unit 220 connected in parallel between the input terminal VIN (receiving the input voltage VIN) and the ground terminal, having the same circuit connection structure. It can be seen that the circuit elements contained in the first conversion unit 210 and the second conversion unit 220, and the connection relationships between these elements, are completely identical, forming a mutually symmetrical structure.

[0043] The first conversion unit 210 includes a first energy storage unit 211 and a second energy storage unit 212. The first energy storage unit 211 includes a first transistor Q1a, a first capacitor C1A, and a second transistor Q2a connected in series between the input terminal and the ground terminal, and a third transistor Q3a connected between the first terminal of the first capacitor C1A, the common node of the second transistor Q2a, and the first output node. The second energy storage unit 212 includes a fourth transistor Q4a, a fifth transistor Q5a, and a sixth transistor Q6a connected in series between the second terminal of the first capacitor C1A and the ground terminal, and a second capacitor C2A connected in parallel across the series structure of the fourth transistor Q4a and the fifth transistor Q5a. The common node of the fourth transistor Q4a and the fifth transistor Q5a is the second output node.

[0044] Accordingly, the second conversion unit 220 includes a first paired energy storage unit 221 and a second paired energy storage unit 222. The first paired energy storage unit 221 includes a first paired transistor Q1b, a first paired capacitor C1B, a second paired transistor Q2b, a third paired transistor Q3b, and a third output node. The second paired energy storage unit 222 includes a fourth paired transistor Q4b, a fifth paired transistor Q5b, a sixth paired transistor Q6b, a second paired capacitor C2B, and a fourth output node. The component positions and connection methods of the first paired transistors Q1b to the sixth paired transistor Q6b, the first paired capacitor C1B, and the second paired capacitor C2B are the same as those of the first conversion unit 210, and will not be described again here.

[0045] In this embodiment, the switched capacitor converter 200 operates in the first operating mode, and both the first and second output nodes are connected to the first output terminal VOA, while the third and fourth output nodes are both connected to the second output terminal VOB. Therefore, the first conversion unit 210 and the second conversion unit 220 can be considered as two independent converters.

[0046] The switched-capacitor converter 200 of this embodiment may also include a control circuit (not shown in the figure), which is used to control the on and off states of each transistor in the first conversion unit 210 and the second conversion unit 220. In the first operating mode, during one switching cycle, the first transistor Q1a to the sixth transistor Q6a and the first paired transistor Q1b to the sixth paired transistor Q6b are all in a switching state. Furthermore, the switching timing of the first transistor Q1a to the sixth transistor Q6a is complementary to the switching timing of the first paired transistor Q1b to the sixth paired transistor Q6b. Figure 4In the diagram, a solid coil represents a transistor that is turned on during the first half of a switching cycle, T1, and a dashed coil represents a transistor that is turned on during the second half of a switching cycle, T2. Furthermore, in the various embodiments of this application, the transistor is described as being in the on state when the control signal is at a logic high level, and in the off state when the control signal is at a logic low level.

[0047] like Figure 5 As shown, in the first operating mode, during the first half-cycle T1, the first transistor Q1a, the third transistor Q3a, the fifth transistor Q5a, the second paired transistor Q2b, the fourth paired transistor Q4b, and the sixth paired transistor Q6b are all in the on state, while the second transistor Q2a, the fourth transistor Q4a, the sixth transistor Q6a, the first paired transistor Q1b, the third paired transistor Q3b, and the fifth paired transistor Q5b are all in the off state. Figure 6 It shows Figure 4 The equivalent circuit diagram of the switched capacitor converter in the first operating mode during the first half-cycle T1 of a switching cycle T.

[0048] Combination Figure 5 and Figure 6 In the first operating mode, during the first half-cycle T1 of a switching cycle T, the circuit connection can be equivalently represented as follows: the first capacitor C1A is equivalently connected between the input terminal and the first output node; the second capacitor C2A is equivalently connected between the input terminal and the second output node; and the first paired capacitor C1B and the second paired capacitor C2B are equivalently connected between the ground terminal and the fourth output node, respectively. That is, the first capacitor C1A and the second capacitor C2A are equivalently connected in parallel between the input terminal VIN and the first output terminal VOA, resulting in: VIN = VC1A + VOA, VIN = VC2A + VOA. Similarly, the first paired capacitor C1B and the second paired capacitor C2B are connected in parallel between the second output terminal VOB and the ground terminal, resulting in: VC1B = VOB, VC2B = VOB. VC1A, VC2A, VC1B, and VC2B represent the voltages across the first capacitor, the second capacitor, the first paired capacitor, and the second paired capacitor, respectively.

[0049] See also Figure 5In the second half of a switching cycle T2, the conduction states of transistors Q1a to Q6a and the first paired transistors Q1b to Q6b are opposite to their respective conduction states in the first half of the cycle T1. That is, transistors Q1a, Q3a, Q5a, Q2b, Q4b, and Q6b are all off, while transistors Q2a, Q4a, Q6a, Q1b, Q3b, and Q5b are all on. Figure 7 It shows Figure 4 The equivalent circuit diagram of the switched capacitor converter in the second half of a switching cycle T2 during the first operating mode.

[0050] Combination Figure 5 and Figure 7 In the latter half of a switching cycle T, T2, the circuit connection can be equivalently represented as follows: the first capacitor C1A and the second capacitor C2A are equivalently connected between the ground terminal and the second output node, respectively; the first paired capacitor C1B is equivalently connected between the input terminal and the third output node; and the second paired capacitor C2B is equivalently connected between the input terminal and the fourth output node. That is, the first capacitor C1A and the second capacitor C2A are connected in parallel between the ground terminal and the first output terminal VOA, so we have: VC1A = VOA, VC2A = VOA. Similarly, the first paired capacitor C1B and the second paired capacitor C2B are connected in parallel between the input terminal VIN and the second output terminal VOB, so we have: VIN = VC1B + VOB, VIN = VC2B + VOB.

[0051] according to Figure 6 and Figure 7 From the obtained formulas, we can derive: VIN = 2VOA = 2VOB. That is, in the first operating mode, the ratio of the input voltage to the first output voltage VOA, and the ratio of the input voltage to the second output voltage VOB, are both 2:1. It can be seen that in this embodiment, the first capacitor C1A, the second capacitor C2A, the first paired capacitor C1B, and the second paired capacitor C2B all serve as flying capacitors, meaning each phase converter has two flying capacitors. Compared to... Figure 1 Compared with existing technologies, this embodiment adds a flying capacitor and a current branch, which can reduce the effective value of the current during switching, reduce losses, and improve converter efficiency without adding transistors or other components, while taking into account chip area and effective current value.

[0052] See you again Figure 4 and Figure 5In this embodiment, the second energy storage unit 212 may further include a seventh transistor Q7a, which is connected between the common node of the fourth transistor Q4a and the second capacitor C2A and the second terminal of the first capacitor C1A. The second paired energy storage unit 222 correspondingly includes a seventh paired transistor Q7b, which is connected between the fourth paired transistor Q4b and the second terminal of the second paired capacitor C2B and the first paired capacitor C1B. Furthermore, in the first operating mode, the seventh transistor Q7a and the seventh paired transistor Q7b are normally on throughout the entire switching cycle T, equivalent to being connected by a wire.

[0053] Furthermore, the first energy storage unit 211 may also include an eighth transistor Q8a, which is connected between the third transistor Q3a and the first output node. The first paired energy storage unit 221 correspondingly includes an eighth paired transistor Q8b. In the first operating mode, during the first half-cycle T1, the eighth transistor Q8a is in the on state, and the eighth paired transistor Q8b is in the off state; while during the second half-cycle T2, the eighth transistor Q8a is in the off state, and the eighth paired transistor Q8b is in the on state. That is, the on state of the eighth transistor Q8a is the same as the on state of the third transistor Q3a, and it will not affect the connection between the third transistor Q3a and the first output node. The same applies to the eighth paired transistor Q8b.

[0054] In a further embodiment, the first conversion unit 210 further includes a third energy storage unit 213, which includes a ninth transistor Q9a and a tenth transistor Q10a connected between the first output node and the ground terminal, and a fourth capacitor C4A connected between the common node of the ninth transistor Q9a and the tenth transistor Q10a and the common node of the third transistor Q3a and the eighth transistor Q8a. Correspondingly, the second conversion unit 220 includes a third paired energy storage unit 223, which includes a ninth paired transistor Q9b, a tenth paired transistor Q10b, and a fourth paired capacitor C4B. In the first operating mode, the ninth transistor Q9a, the tenth transistor Q10a, the ninth paired transistor Q9b, and the tenth paired transistor Q10b are in a normally off state throughout the entire operating cycle. Figure 4 The gray area indicates that, in the first operating mode, neither the fourth capacitor C4A nor the fourth paired capacitor C4B is connected in the circuit.

[0055] Figure 8 A schematic circuit connection diagram of a switched capacitor converter according to a second embodiment of the present invention in a first operating mode is shown.

[0056] like Figure 8As shown, the switched capacitor converter 200 of this embodiment includes the same circuit structure and circuit components as the first embodiment, and the similarities will not be repeated. The difference is that, in this embodiment, in the first operating mode, the second output node and the third output node are both connected to the first output terminal VOA, while the first output node and the fourth output node are both connected to the second output terminal VOB. That is, the connection method of the four output nodes and two output terminals is different from that of the first embodiment.

[0057] In this embodiment, due to the crossover of the two output terminals, it cannot be directly regarded as an independent two-phase converter. However, Figure 8 The timing sequence of each transistor in the circuit still refers to... Figure 5 The operating timing is shown. In the first operating mode, during the first half-cycle T1 of a switching cycle T, the circuit connection can be equivalently represented as follows: the first capacitor C1A is equivalently connected between the input terminal and the second output terminal VOB; the second capacitor C2A is equivalently connected between the input terminal and the first output terminal VOA; and the first paired capacitor C1B and the second paired capacitor C2B are equivalently connected in parallel between the ground terminal and the second output node VOB. Therefore, VIN = VC1A + VOB, VIN = VC2A + VOA, VC1B = VOB, and VC2B = VOB. During the second half-cycle T2 of a switching cycle T, the circuit connection can be equivalently represented as follows: the first capacitor C1A and the second capacitor C2A are equivalently connected in parallel between the ground terminal and the first output terminal VOA; the first paired capacitor C1B is equivalently connected between the input terminal and the first output terminal VOA; and the second paired capacitor C2B is equivalently connected between the input terminal and the second output terminal VOB. We can obtain: VC1A=VOA, VC2A=VOA, VIN=VC1B+VOA, VIN=VC2B+VOB. From this, we can deduce that VIN=2VOA=2VOB. That is, in the first operating mode, the ratio of the input voltage to the voltage at the first output terminal VOA, and the ratio of the input voltage to the voltage at the second output terminal VOB, are both 2:1.

[0058] Figure 9 A schematic circuit connection diagram of a switched capacitor converter according to a third embodiment of the present invention in a first operating mode is shown.

[0059] like Figure 9 As shown, the switched capacitor converter 200 in this embodiment and Figure 8 Similar to the embodiment, in this embodiment, the switched-capacitor converter 200 includes first transistors Q1a to eighth transistors Q8a and first paired transistors Q1b to eighth paired transistors Q8b, but does not include the third energy storage unit 213 and the third paired energy storage unit 223. The connection method of each transistor and capacitor is described in [reference needed]. Figure 8 This will not be elaborated upon here.

[0060] The difference lies in this embodiment: the first energy storage unit 211 further includes a third capacitor C3A, which is connected between the first output node and the common node of the fifth paired transistor Q5b and the sixth paired transistor Q6b. The first paired energy storage unit 221 correspondingly includes a third paired capacitor C3B, which is connected between the common node of the fifth transistor Q5a and the sixth transistor Q6a and the third output node. It can be seen that in the first half-cycle T1 of a switching cycle T, the third capacitor C3A acts as the output filter capacitor, while in the second half-cycle T2, the third paired capacitor C3B acts as the output filter capacitor.

[0061] The equivalent circuit in the first operating mode of this embodiment is... Figure 8 As described in the embodiments, in the first operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal VOA, and the ratio of the voltage at the input terminal to the voltage at the second output terminal VOB, are both 2:1.

[0062] Furthermore, in Figure 8 In a corresponding embodiment, if the ninth transistor Q9a and the tenth transistor Q10a reuse the fifth paired transistor Q5b and the sixth paired transistor Q6b, the switching timing is based on the fifth paired transistor Q5b and the sixth paired transistor Q6b; and if the ninth paired transistor Q9b and the tenth paired transistor Q10b reuse the fifth transistor Q5a and the sixth paired transistor Q6a, the switching timing is based on the fifth transistor Q5a and the sixth paired transistor Q6a. In this case, the fourth capacitor C4A becomes the third capacitor C3A, and the fourth paired capacitor C4B correspondingly becomes the third paired capacitor C3B.

[0063] Figure 10 A schematic circuit connection diagram of a switched-capacitor converter according to a first embodiment of the present invention in a second operating mode is shown. Figure 11 It shows Figure 10 The timing waveform diagram of the switched capacitor converter in the second operating mode.

[0064] like Figure 10 As shown, the switched capacitor converter 200 in this embodiment and Figure 4 The structure is the same in the embodiment, and the components and their corresponding connections will not be described again here. In this embodiment, the switched capacitor converter 200 operates in the second operating mode. In the second operating mode, the first output node and the second output node are connected to the first output terminal VOA, and the third output node and the fourth output node are connected to the second output terminal VOB.

[0065] Let's still use a solid coil to represent a transistor that is turned on during the first half of a switching cycle, T1, and a dashed coil to represent a transistor that is turned on during the second half of a switching cycle, T2. Then, referring to... Figure 11In the second operating mode, during the first half-cycle T1 of a switching cycle T, transistors Q1a, Q3a, Q4a, Q6a, Q9a, Q2b, Q5b, Q7b, Q8b, and Q10b are all in the on state, while transistors Q1b, Q3b, Q4b, Q6b, Q9b, Q2a, Q5a, Q7a, Q8a, and Q10a are all in the off state. During the second half-cycle T2 of the switching cycle T, the on states of transistors Q1a through Q10a and transistors Q1b through Q10b are the opposite of their on states in the first half-cycle T1, which will not be elaborated further here.

[0066] At this point, within the first half of cycle T1, the circuit can be equivalently represented as follows: the first capacitor C1A and the fourth capacitor C4A are equivalently connected in series between the input terminal VIN and the first output terminal VOA; the second capacitor C2A is equivalently connected between the ground terminal and the first output terminal VOA; the first paired capacitor C1B and the second paired capacitor C2B are equivalently connected in series between the ground terminal and the second output terminal VOB; and the fourth paired capacitor C4B is equivalently connected between the output terminal and the second output terminal VOB. Correspondingly, we can obtain: VIN = VC1A + VC4A + VOA, VC2A = VOA, VC1B = VC2B + VOB, VC4B = VOB. During the latter half of cycle T2, the circuit is equivalent to: the first capacitor C1A and the second capacitor C2A are equivalently connected in series between the ground terminal and the first output terminal VOA; the fourth capacitor C4A is equivalently connected between the ground terminal and the first output terminal VOA; the first paired capacitor C1B and the fourth paired capacitor C4B are equivalently connected in series between the input terminal VIN and the second output terminal VOB; and the second paired capacitor C2B is equivalently connected between the ground terminal and the second output terminal VOB. Correspondingly, we can obtain: VCA1 = VC2A + VOA, VOA = VC4A, VIN = VC1B + VC4B + VOB, VC2B = VOB. Further derivation yields: VIN = 4VOA, VIN = 4VOB. That is, in the second operating mode, the ratio of the input voltage to the voltage of the first output terminal VOA, and the ratio of the input voltage to the voltage of the second output terminal VOB, are both 4:1.

[0067] Of course, in this embodiment, the first output terminal VOA and the second output terminal VOB can also be connected together, and the input-output ratio is still 4:1.

[0068] Figure 12A schematic circuit connection diagram of a switched capacitor converter according to a second embodiment of the present invention in a second operating mode is shown.

[0069] like Figure 12 As shown, this embodiment and Figure 8 The circuit structure of the switched capacitor converter 200 corresponding to the embodiment is the same, and will not be described again here. In this embodiment, in the second operating mode, the first output node to the fourth output node can be connected to the same output terminal, that is, the first output terminal VOA and the second output terminal VOB are connected and regarded as the same output terminal.

[0070] See the timing diagram of each transistor. Figure 11 Therefore, in the first half of a switching cycle T1, according to the equivalent circuit, we can obtain: VIN = VC1A + VC4A + VOB, VC1B = VC2B + VOB, VC2A = VOA, VC4B = VOA. In the second half of the cycle T2, according to the equivalent circuit, we can obtain: VC4A = VOB, VC2B = VOB, VC1A = VC2A + VOA, VIN = VC1B + VC4B + VOA. Derivation shows: VIN = 2VOA + 2VOB. Since the first output terminal VOA and the second output terminal VOB are connected in this embodiment, VOA = VOB, so we can obtain: VIN = 4VOA = 4VOB. That is, in the second operating mode, the ratio of the input voltage to the voltage of the first output terminal VOA, and the ratio of the input voltage to the voltage of the second output terminal VOB are both 4:1. Alternatively, the first output terminal VOA and the second output terminal VOB can also be unconnected, i.e., still following the... Figure 8 The connection method connects the second and third output nodes to the first output terminal VOA, and the first and fourth output nodes to the second output terminal VOB. Since the first and second conversion units have the same circuit structure, VOA is essentially equal to VOB, meaning a 4:1 ratio between the input and output terminals can be achieved.

[0071] Figure 13 A schematic circuit connection diagram of a switched capacitor converter in a second operating mode according to a third embodiment of the present invention is shown.

[0072] like Figure 13 As shown, the switched capacitor circuit 200 in this embodiment is to... Figure 12In this embodiment, the ninth transistor Q9a and the tenth transistor Q10a reuse the fifth paired transistor Q5b and the sixth paired transistor Q6b, with the switching timing based on the fifth paired transistor Q5b and the sixth paired transistor Q6b; conversely, the ninth paired transistor Q9b and the tenth paired transistor Q10b reuse the fifth transistor Q5a and the sixth paired transistor Q6a, with the switching timing based on the fifth transistor Q5a and the sixth paired transistor Q6a. The connection relationships of other transistors and capacitors are not described further.

[0073] In this embodiment, in the second operating mode, four output nodes can be connected to the same output terminal, i.e., the first output terminal VOA and the second output terminal VOB are connected. A solid coil still represents a transistor conducting during the first half-cycle T1 of a switching cycle, and a dashed coil represents a transistor conducting during the second half-cycle T2 of a switching cycle. Therefore, in the second operating mode, the relationship between the input voltage and the output voltage in one switching cycle is as follows: Figure 12 The same implementation applies, meaning that in the second operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal VOA, and the ratio of the voltage at the input terminal to the voltage at the second output terminal VOB, are both 4:1.

[0074] Therefore, the switched capacitor converters of various embodiments of the present invention can switch between two operating modes: an input-output ratio of 2:1 and an input-output ratio of 4:1 by changing the connection relationship of the output terminal, the connection of the transistors, and the switching timing of the transistors.

[0075] Furthermore, in this application, the first to tenth transistors and their corresponding first to tenth paired transistors are of the same type and size in each pair, and the capacitors and their corresponding paired capacitors have the same capacitance value and type.

[0076] Furthermore, the present invention also provides a control method for a switched capacitor converter, which is applied to the above-mentioned... Figures 4-9 In the switched-capacitor converter shown in the embodiment, the operation is applied in the first operating mode. Specifically, the control method of this embodiment includes, for example, the following steps:

[0077] In step S101, during the first half of a switching cycle, the first transistor, the third transistor, the fifth transistor, the second paired transistor, the fourth paired transistor, and the sixth paired transistor are turned on.

[0078] In step S102, during the second half of a switching cycle, the second transistor, the fourth transistor, the sixth transistor, the first paired transistor, the third paired transistor, and the fifth paired transistor are turned on.

[0079] In step S103, the switching action of the first half cycle and the second half cycle are repeated alternately, so that the first capacitor, the second capacitor, the first paired capacitor and the second paired capacitor all act as flying capacitors.

[0080] The control method in this embodiment is based on the above. Figures 4-9 The switched capacitor converter implemented in the embodiment has been described in the above embodiment description in terms of its specific circuit structure, principle and working process, and will not be repeated here.

[0081] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of the present invention, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and the present invention does not limit them.

[0082] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0083] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A switched capacitor converter, comprising: A first conversion unit and a second conversion unit with the same circuit connection structure are connected in parallel between the input terminal and the ground terminal; The first conversion unit includes a first energy storage unit and a second energy storage unit. The first energy storage unit includes a first transistor, a first capacitor, and a second transistor connected in series between the input terminal and the ground terminal, and a third transistor connected between the first terminal of the first capacitor and the common node of the second transistor and the first output node. The second energy storage unit includes a fourth transistor, a fifth transistor, and a sixth transistor connected in series between the second terminal of the first capacitor and the ground terminal, and a second capacitor connected in parallel across the fourth transistor and the fifth transistor. The common node of the fourth transistor and the fifth transistor is the second output node. The second conversion unit includes a first paired energy storage unit and a second paired energy storage unit. The first paired energy storage unit includes a first paired transistor, a first paired capacitor, a second paired transistor, a third paired transistor, and a third output node. The second paired energy storage unit includes a fourth paired transistor, a fifth paired transistor, a sixth paired transistor, a second paired capacitor, and a fourth output node. In the first operating mode, by controlling the switching timing of each transistor, in the first half of a switching cycle, the first capacitor is equivalently connected between the input terminal and the first output node, the second capacitor is equivalently connected between the input terminal and the second output node, and the first paired capacitor and the second paired capacitor are equivalently connected between the ground terminal and the fourth output node, respectively; while in the second half of a switching cycle, the first capacitor and the second capacitor are equivalently connected between the ground terminal and the second output node, respectively, the first paired capacitor is equivalently connected between the input terminal and the third output node, and the second paired capacitor is equivalently connected between the input terminal and the fourth output node.

2. The switched capacitor converter according to claim 1, wherein, In the first operating mode, the second output node is connected to the first output terminal, the fourth output node is connected to the second output terminal, the first output node is connected to one of the first output terminal and the second output terminal, and the third output node is connected to the other of the first output terminal and the second output terminal.

3. The switched capacitor converter according to claim 2, wherein, In the first operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal, and the ratio of the voltage at the input terminal to the voltage at the second output terminal, are both 2:

1.

4. The switched capacitor converter according to claim 1, wherein, In the first operating mode, during the first half-cycle, the first transistor, the third transistor, the fifth transistor, the second paired transistor, the fourth paired transistor, and the sixth paired transistor are all in the on state, while the second transistor, the fourth transistor, the sixth transistor, the first paired transistor, the third paired transistor, and the fifth paired transistor are all in the off state; during the second half-cycle, the on states of the first transistor to the sixth transistor and the first paired transistor to the sixth paired transistor are opposite to their respective on states during the first half-cycle.

5. The switched capacitor converter according to any one of claims 1-4, wherein, The second energy storage unit further includes a seventh transistor, which is connected between the common node of the fourth transistor and the second capacitor and the second terminal of the first capacitor. The second paired energy storage unit includes a seventh paired transistor, and in the first operating mode, the seventh transistor and the seventh paired transistor are in a normally on state throughout the entire switching cycle. The first energy storage unit further includes an eighth transistor, which is connected between the third transistor and the first output node. The first paired energy storage unit includes an eighth paired transistor. In the first operating mode, the eighth transistor is in the on state and the eighth paired transistor is in the off state during the first half-cycle; while in the second half-cycle, the eighth transistor is in the off state and the eighth paired transistor is in the on state.

6. The switched capacitor converter according to claim 5, wherein, The first energy storage unit also includes a third capacitor, which is equivalently connected between the first output node and the common node of the fifth paired transistor and the sixth paired transistor during the first half-cycle. The first paired energy storage unit includes a third paired capacitor, which, in the second half of the cycle, is equivalently connected between the common node of the fifth and sixth transistors and the third output node. Both the third capacitor and the third paired capacitor are output filter capacitors.

7. The switched capacitor converter according to claim 5, wherein, The first conversion unit further includes a third energy storage unit, which includes a ninth transistor and a tenth transistor connected between the first output node and the ground terminal, and a fourth capacitor connected between the common node of the ninth transistor and the tenth transistor and the common node of the third transistor and the eighth transistor. The second conversion unit includes a third paired energy storage unit, which includes a ninth paired transistor, a tenth paired transistor, and a fourth paired capacitor. In the first operating mode, the ninth transistor, the tenth transistor, the ninth paired transistor, and the tenth paired transistor are in a normally off state throughout the entire operating cycle.

8. The switched capacitor converter according to claim 7, wherein, In the second operating mode, the first output node and the second output node are connected to the first output terminal, and the third output node and the fourth output node are connected to the second output terminal; alternatively, the second output node and the third output node are connected to the first output terminal, and the first output node and the fourth output node are connected to the second output terminal; or, all four output nodes are connected to the same output terminal. Furthermore, during the first half of a switching cycle, the first transistor, the third transistor, the fourth transistor, the sixth transistor, the ninth transistor, the second paired transistor, the fifth paired transistor, the seventh paired transistor, the eighth paired transistor, and the tenth paired transistor are all in the on state, while the first paired transistor, the third paired transistor, the fourth paired transistor, the sixth paired transistor, the ninth paired transistor, the second transistor, the fifth transistor, the seventh transistor, the eighth transistor, and the tenth transistor are all in the off state. In the second half of a switching cycle, the conduction states of the first transistor to the tenth transistor and the first paired transistor to the tenth paired transistor are all opposite to their respective conduction states in the first half of the cycle.

9. The switched capacitor converter according to claim 8, wherein, In the second operating mode, the ratio of the voltage at the input terminal to the voltage at the first output terminal, and the ratio of the voltage at the input terminal to the voltage at the second output terminal, are both 4:

1.

10. The switched-capacitor converter according to claim 8, wherein, In the second operating mode, the fifth paired transistor and the sixth paired transistor are multiplexed as the ninth transistor and the tenth transistor, respectively, and the fifth transistor and the sixth transistor are multiplexed as the ninth paired transistor and the tenth paired transistor, respectively.

11. A control method for a switched capacitor converter, applied in the switched capacitor converter according to any one of claims 1-10, wherein, In the first operating mode, the control method includes: During the first half of a switching cycle, the first transistor, the third transistor, the fifth transistor, the second paired transistor, the fourth paired transistor, and the sixth paired transistor are turned on. In the second half of a switching cycle, the second transistor, the fourth transistor, the sixth transistor, the first paired transistor, the third paired transistor, and the fifth paired transistor are turned on. The switching action of the first half-cycle and the second half-cycle is repeated alternately, so that the first capacitor, the second capacitor, the first paired capacitor and the second paired capacitor all act as flying capacitors.

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