A four-dimensional chaotic circuit based on fractional-order memristor

Abstract

The application discloses a four-dimensional chaotic circuit based on a fractional-order memristor, and comprises a fractional-order memristor equivalent circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit and a fourth fractional-order chaotic circuit; the four fractional-order chaotic circuits generate corresponding four chaotic sequences respectively. The application combines the fractional-order memristor circuit with the fractional-order chaotic circuit, and the circuit can exhibit rich dynamic characteristics by adjusting the parameter value of the corresponding resistance, so that the application has higher security and adaptability in engineering applications such as chaotic system encryption.

Description

Technical Field

[0001] This invention belongs to the field of chaotic circuit technology, specifically relating to a four-dimensional chaotic circuit based on a fractional memristor. Background Technology

[0002] Memristors are a novel type of nonlinear two-port circuit device with characteristics such as memory, nonlinearity, and nonvolatility. Therefore, memristors have broad application prospects in many fields of next-generation information technology, including chaotic encryption, neural networks, and volatile data storage. Numerous studies have shown that using fractional calculus to model memory-based components can more accurately describe their actual physical characteristics. With the development of fractional calculus theory, researchers have begun to explore combining fractional calculus with memristors in their research.

[0003] Chaos is a pseudo-random phenomenon generated by deterministic nonlinear systems, exhibiting sensitivity to initial conditions. Because simple nonlinear dynamic systems can produce complex dynamic behaviors, chaos has wide applications in engineering fields such as information encryption and secure communication. In recent years, researchers have constructed many chaotic systems and studied their chaotic characteristics. Patent CN112073170B discloses a piecewise smooth memristor chaotic circuit with multiple attractors, allowing the observation of multiple chaotic attractors coexisting. Patent CN108632016B discloses an autonomous memristor chaotic circuit with multiple attractors; compared to general memristor chaotic circuits, this system can generate multiple uncertain and more topologically complex attractors. However, the memristor chaotic systems described above are all of integer order, resulting in insufficient memory and poor adaptability. Currently, various application scenarios exist in the field of chaotic encryption. Designing systems with multiple chaotic attractor structures and transient dynamic behaviors to adapt to different application scenarios while ensuring strong memory and flexibility has become an urgent problem to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a four-dimensional chaotic circuit based on a fractional-order memristor. This circuit can generate a variety of chaotic attractors with different topologies and exhibit rich dynamic behaviors such as transient chaos. By adjusting parameters, switching between different topological attractors can be achieved, significantly improving the randomness and unpredictability of the chaotic signal. In secure communication, this greatly enhances the anti-cracking capability of information encryption and allows the system to adapt to different application scenarios. Furthermore, because the system is fractional-order, it better describes real-world systems and possesses strong memory. This invention has high reference value for research on the application of fractional-order memristor chaotic systems in the field of chaotic encryption.

[0005] To achieve the above objectives, the present invention provides the following solution: A four-dimensional chaotic circuit based on a fractional-order memristor includes: a fractional-order memristor circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit, and a fourth fractional-order chaotic circuit: the fractional-order memristor circuit is used to generate a signal M, the first fractional-order chaotic circuit is used to generate a chaotic sequence x, the second fractional-order chaotic circuit is used to generate a chaotic sequence y, the third fractional-order chaotic circuit is used to generate a chaotic sequence z, and the fourth fractional-order chaotic circuit is used to generate a chaotic sequence w; The model of the four-dimensional chaotic circuit is as follows: in, q represents the order of the fractional derivative in the system equation, and a, b, and c are system parameters. In the first fractional chaotic circuit, the ratio of the fourth resistor R4 to the first resistor R1 is R4 / R1, denoted by parameter a. In the second fractional chaotic circuit, the ratio of the fourth resistor R4 to the second resistor R2 is R4 / R2, denoted by parameter b. In the third fractional chaotic circuit, the ratio of the thirteenth resistor R13 to the eleventh resistor R11 is R13 / R11, denoted by parameter c.

[0006] Preferably, the fractional-order memristor circuit includes a first multiplier A1. Both inputs of the first multiplier A1 are connected to the output y of the second fractional-order chaotic circuit. The output of the first multiplier A1 is connected to the inverting input of the first inverting adder U1 via resistor RA. The non-inverting input of the first inverting adder U1 is grounded. The negative terminal of power supply V1 is grounded, and the positive terminal of power supply V1 is connected to the inverting input of the first inverting adder U1 via resistor RB. The two ends of resistor RC are connected to the inverting input and output of the first inverting adder U1, respectively. One end of resistor RD is connected to the output of the first inverting adder U1, and the other end of resistor RD is connected to the inverting input of the first inverter U2. The non-inverting input of the first inverter U2 is grounded. The two ends of resistor RE are connected to the first inverting adder U1, U2, U3, U4, U5, U6, U7, U8, U9, U1, U1, U2, U1, U2, U3, U4, U5, U6, U7, U8, U9, U1, U2, U1, U2, U3, U4, U5, U6, U7, U8, U9, U1, U6, U7, U8, U9, U1, U6, U7, U8, U9, U1, U6, U9, U1, U6, U7, U8, U9, U1, U9, U1, U6, U9, U1, U1, U2 ... The inverter U2 has an inverting input and an output. One end of resistor RF is connected to the output of the first inverter U2, and the other end of resistor RF is connected to the inverting input of the square root U3. The non-inverting input of the square root U3 is grounded. One end of resistor RG is connected to the inverting input of the square root U3, and the other end of resistor RG is connected to the output of the second inverter U4. The two ends of resistor RH are connected to the inverting input and the output of the second inverter U4, respectively. The non-inverting input of the second inverter U4 is grounded. One end of resistor RI is connected to the inverting input of the second inverter U4, and the other end of resistor RI is connected to the output of the second multiplier A2. Both inputs of the second multiplier A2 are connected to the output M of the square root U3, and the output of the square root U3 serves as the output of the fractional memristor circuit, outputting the signal M.

[0007] Preferably, the first fractional-order chaotic circuit includes a third multiplier A3, both inputs of which are connected to the output y of the second fractional-order chaotic circuit. The output of the third multiplier A3 is connected to the inverting input of the second inverting adder U5 via a second resistor R2. The input of the first resistor R1 is connected to the first output z of the third fractional-order chaotic circuit, and the other end of the first resistor R1 is connected to the inverting input of the second inverting adder U5. The positive terminal of the power supply V2 is grounded, and the negative terminal of the power supply V2 is connected to the inverting input of the second inverting adder U5 via a third resistor R3. The two ends of the fourth resistor R4 are connected to the inverting input and output of the second inverting adder U5, respectively. The non-inverting input of the second inverting adder U5 is grounded. The output of the second inverting adder U5 is connected to the inverting input of the first inverting integrator U6 via a fifth resistor R5. A 0-coil connection is established between the inverting input and output of the first inverting integrator U6. In the .8th order unit circuit, the non-inverting input of the first inverting integrator U6 is grounded; the output of the first inverting integrator U6 serves as the first output of the first fractional-order chaotic circuit, outputting a positive signal x; the output of the first inverting integrator U6 is connected to the inverting input of the third inverter U7 via the sixth resistor R6, and the non-inverting input of the third inverter U7 is grounded; a seventh resistor R7 is connected between the inverting input and output of the third inverter U7, and the output of the third inverter U3 serves as the second output of the first fractional-order chaotic circuit, outputting an inverted signal. x; Preferably, the second fractional-order chaotic circuit includes an eighth resistor R8, the input of which is connected to the first output w of the fourth fractional-order chaotic circuit, and the other end of which is connected to the inverting input of an inverting amplifier U8, the non-inverting input of which is grounded; the two ends of a ninth resistor R9 are connected to the inverting input and output of the inverting amplifier U8, respectively; the output of the inverting amplifier U8 is connected to the inverting input of a second inverting integrator U9 via a tenth resistor R10; a 0.8-order unit circuit is connected between the inverting input and output of the second inverting integrator U9, the non-inverting input of which is grounded; the output of the second inverting integrator U9 serves as the output of the second fractional-order chaotic circuit, outputting the signal y; Preferably, the third fractional-order chaotic circuit includes an eleventh resistor R11, the input of which is connected to the second output terminal -x of the first fractional-order chaotic circuit, and the other end of which is connected to the inverting input terminal of the third inverting adder U10; the non-inverting input terminal of the third inverting adder U10 is grounded; the input of a twelfth resistor R12 is connected to the second output terminal -z of the third fractional-order chaotic circuit, and the other end of which is connected to the inverting input terminal of the third inverting adder U10; the two ends of a thirteenth resistor R13 are respectively connected to the inverting input terminal and the output terminal of the third inverting adder U10; the output terminal of the third inverting adder U10 is connected to the third inverting adder U10 via a fourteenth resistor R14. The inverting input of the third inverting integrator U11 is connected to the inverting input and output of the third inverting integrator U11 via a 0.8th order unit circuit. The non-inverting input of the third inverting integrator U11 is grounded. The output of the third inverting integrator U11 serves as the first output of the third fractional-order chaotic circuit, outputting a positive signal z. The output of the third inverting integrator U11 is connected to the inverting input of the fourth inverter U12 via the fifteenth resistor R15. The non-inverting input of the fourth inverter U12 is grounded. The sixteenth resistor R16 connects the inverting input and output of the fourth inverter U12. The output of the fourth inverter U12 serves as the second output of the third fractional-order chaotic circuit, outputting an inverted signal. z; Preferably, the fourth fractional chaotic circuit includes a fourth multiplier A4, the two input terminals of which are respectively connected to the output terminal M of the fractional memristor circuit and the second output terminal of the fourth fractional chaotic circuit. w, the output of the fourth multiplier A4 is connected to the inverting input of the fourth inverting adder U13 via the seventeenth resistor R17; the non-inverting input of the fourth inverting adder U13 is grounded; the two inputs of the fifth multiplier A5 are connected to the first output y of the second fractional chaotic circuit and the first output z of the third fractional chaotic circuit, respectively; the output of the fifth multiplier A5 is connected to the inverting input of the fourth inverting adder U13 via the eighteenth resistor R18; the two ends of the nineteenth resistor R19 are connected to the inverting input and output of the fourth inverting adder U13, respectively; the output of the fourth inverting adder U13 is connected to the fourth inverting integrator U14 via the twentieth resistor R20. The inverting input terminal of the fourth inverting integrator U14 is connected to the non-inverting input terminal, which is grounded. A 0.8th order unit circuit is connected between the inverting input terminal and the output terminal of the fourth inverting integrator U14. The output terminal of the fourth inverting integrator U14 serves as the first output terminal of the fourth fractional-order chaotic circuit, outputting a positive signal w. The output terminal of the fourth inverting integrator U14 is connected to the inverting input terminal of the fifth inverter U15 via the twenty-first resistor R21, and the non-inverting input terminal of the fifth inverter U15 is grounded. A twenty-second resistor R22 is connected between the inverting input terminal and the output terminal of the fifth inverter U15, and the output terminal of the fifth inverter U15 serves as the second output terminal of the fourth fractional-order chaotic circuit, outputting an inverted signal. w; Preferably, the 0.8th order unit circuit one includes a capacitor CC1 connected in series with a resistor RC1 and then in parallel with a capacitor CB1, and a capacitor CB1 connected in series with a resistor RB1 and then in parallel with a capacitor CA1, and a resistor RA1 connected in parallel with a capacitor CA1; the 0.8th order unit circuit two includes a capacitor CC2 connected in series with a resistor RC2 and then in parallel with a capacitor CB2, and a capacitor CB2 connected in series with a resistor RB2 and then in parallel with a capacitor CA2, and a resistor RA2 connected in parallel with a capacitor CA2; the 0.8th order unit circuit three includes a capacitor CC3 connected in series with a resistor RC3 and then in parallel with a capacitor CB3, and a capacitor CB3 connected in series with a resistor RB3 and then in parallel with a capacitor CA3, and a resistor RA3 connected in parallel with a capacitor CA3; the 0.8th order unit circuit four includes a capacitor CC4 connected in series with a resistor RC4 and then in parallel with a capacitor CB4, and a capacitor CB4 connected in series with a resistor RB4 and then in parallel with a capacitor CA4, and a resistor RA4 connected in parallel with a capacitor CA4; Preferably, the resistance values ​​of resistors RA, RB, RC, RD, RE, RF, RG, RH, and RI in the fractional-order memristor circuit satisfy the following relationships: RC / RA=1, RC / RB=1, RE / RD=1, RG / RF=1, and RI / RH=1; the resistance values ​​of the first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, sixth resistor R6, and seventh resistor R7 in the first fractional-order chaotic circuit satisfy the following relationships: R4 / R1=1.89, R4 / R2=1, R4 / R3=1, and R7 / R6=1; the eighth resistor R in the second fractional-order chaotic circuit... The resistance values ​​of resistors 8 and 9 satisfy the relationship R9 / R8=4; the resistance values ​​of resistors 11, 12, 13, 15, and 16 in the third fractional-order chaotic circuit satisfy the relationships R13 / R11=0.85, R13 / R12=1, and R16 / R15=1; the resistance values ​​of resistors 17, 18, 19, 21, and 22 in the fourth fractional-order chaotic circuit satisfy the relationships R19 / R17=1, R19 / R18=1, and R22 / R21=1. Preferably, the component parameter values ​​in the 0.8th order unit circuit are as follows: resistor RA1 = resistor RA2 = resistor RA3 = resistor RA4 = 782kΩ; resistor RB1 = resistor RB2 = resistor RB3 = resistor RB4 = 196 kΩ; resistor RC1 = resistor RC2 = resistor RC3 = resistor RC4 = 21 kΩ; capacitor CA1 = capacitor CA2 = capacitor CA3 = capacitor CA4 = 0.437μF; capacitor CB1 = capacitor CB2 = capacitor CB3 = capacitor CB4 = 0.219μF; capacitor CC1 = capacitor CC2 = capacitor CC3 = capacitor CC4 = 0.237μF.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention combines a fractional memristor (fractional-order memristor circuit) with a first, second, third, and fourth fractional-order chaotic circuit to construct a four-dimensional chaotic circuit based on a fractional memristor. This fractional-order memristor chaotic circuit contains chaotic attractors with various topologies, as well as rich dynamic characteristics such as offset enhancement and transient chaos. By adjusting system parameters, the system can exhibit chaotic attractors with various structures and transient characteristics to adapt to different application scenarios. It has higher security and adaptability in engineering applications such as chaotic system encryption. Attached Figure Description To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 The present invention provides an overall circuit schematic diagram of a four-dimensional chaotic circuit based on a fractional memristor; Figure 2 This invention relates to a chaotic attractor in y when q = 0.8, a = 1.89, b = 1, and c = 0.85. Numerical simulation phase diagram in the z-direction; Figure 3 This invention relates to a chaotic attractor in y when q = 0.8, a = 1.99, b = 1, and c = 0.85. Numerical simulation phase diagram in the z-direction; Figure 4 This invention relates to a chaotic attractor in y when q = 0.8, a = 2.18, b = 1, and c = 0.85. Numerical simulation phase diagram in the z-direction; Figure 5 This invention relates to a chaotic attractor in y when q = 0.8, a = 3.15, b = 1, and c = 0.85. Numerical simulation phase diagram in the z-direction; Figure 6 This invention relates to a chaotic attractor in y when q = 0.8, a = 3.35, b = 1, and c = 0.85. Numerical simulation phase diagram in the z-direction; Figure 7 The present invention is a numerical simulation phase diagram showing a transition behavior from a chaotic state to a periodic state when q=0.8, a=3.145, b=1, c=0.85. Figure 8 This is the time series diagram of the state variable x when q = 0.8, a = 3.145, b = 1, c = 0.85. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Example 1 like Figure 1 As shown, this embodiment of the invention provides a four-dimensional chaotic circuit based on a fractional-order memristor, including: a fractional-order memristor circuit, a first fractional-order chaotic circuit, a second fractional-order chaotic circuit, a third fractional-order chaotic circuit, and a fourth fractional-order chaotic circuit. The four-dimensional chaotic circuit generates four different chaotic sequences, which correspond to the first fractional-order chaotic circuit, the second fractional-order chaotic circuit, the third fractional-order chaotic circuit, and the fourth fractional-order chaotic circuit, respectively. The fractional-order memristor circuit is used to generate signal M, the first fractional-order chaotic circuit is used to generate chaotic sequence x, the second fractional-order chaotic circuit is used to generate chaotic sequence y, the third fractional-order chaotic circuit is used to generate chaotic sequence z, and the fourth fractional-order chaotic circuit is used to generate chaotic sequence w.

[0013] The fractional-order memristor circuit includes a first multiplier A1. Both inputs of the first multiplier A1 are connected to the output y of the second fractional-order chaotic circuit. The output of the first multiplier A1 is connected to the inverting input of the first inverting adder U1 via resistor RA. The non-inverting input of the first inverting adder U1 is grounded. The negative terminal of power supply V1 is grounded, and the positive terminal of power supply V1 is connected to the inverting input of the first inverting adder U1 via resistor RB. Resistor RC is connected to the inverting input and output of the first inverting adder U1, respectively. One end of resistor RD is connected to the output of the first inverting adder U1, and the other end of resistor RD is connected to the inverting input of the first inverter U2. The non-inverting input of the first inverter U2 is grounded. Resistor RE is connected to the first inverter U2... The inverting input and output terminals of the first inverter U2 are connected as follows: one end of resistor RF is connected to the output terminal of the first inverter U2, and the other end of resistor RF is connected to the inverting input terminal of the square root U3; the non-inverting input terminal of the square root U3 is grounded; one end of resistor RG is connected to the inverting input terminal of the square root U3, and the other end of resistor RG is connected to the output terminal of the second inverter U4; the two ends of resistor RH are connected to the inverting input terminal and the output terminal of the second inverter U4, respectively; the non-inverting input terminal of the second inverter U4 is grounded; one end of resistor RI is connected to the inverting input terminal of the second inverter U4, and the other end of resistor RI is connected to the output terminal of the second multiplier A2; both input terminals of the second multiplier A2 are connected to the output terminal M of the square root U3, and the output terminal of the square root U3 serves as the output terminal of the fractional memristor circuit, outputting the signal M; The first fractional-order chaotic circuit includes a third multiplier A3. Both inputs of the third multiplier A3 are connected to the output y of the second fractional-order chaotic circuit. The output of the third multiplier A3 is connected to the inverting input of the second inverting adder U5 via a second resistor R2. The input of the first resistor R1 is connected to the first output z of the third fractional-order chaotic circuit, and the other end of the first resistor R1 is connected to the inverting input of the second inverting adder U5. The positive terminal of power supply V2 is grounded, and the negative terminal of power supply V2 is connected to the inverting input of the second inverting adder U5 via a third resistor R3. The two ends of the fourth resistor R4 are connected to the inverting input and output of the second inverting adder U5, respectively. The non-inverting input of the second inverting adder U5 is grounded. The output of the second inverting adder U5 is connected to the inverting input of the first inverting integrator U6 via a fifth resistor R5. A 0-coil connection is established between the inverting input and output of the first inverting integrator U6. In the .8th order unit circuit, the non-inverting input of the first inverting integrator U6 is grounded; the output of the first inverting integrator U6 serves as the first output of the first fractional-order chaotic circuit, outputting a positive signal x; the output of the first inverting integrator U6 is connected to the inverting input of the third inverter U7 via the sixth resistor R6, and the non-inverting input of the third inverter U7 is grounded; a seventh resistor R7 is connected between the inverting input and output of the third inverter U7, and the output of the third inverter U3 serves as the second output of the first fractional-order chaotic circuit, outputting an inverted signal. x; The second fractional-order chaotic circuit includes an eighth resistor R8. The input terminal of the eighth resistor R8 is connected to the first output terminal w of the fourth fractional-order chaotic circuit, and the other end of the eighth resistor R8 is connected to the inverting input terminal of the inverting amplifier U8. The non-inverting input terminal of the inverting amplifier U8 is grounded. The two ends of the ninth resistor R9 are connected to the inverting input terminal and the output terminal of the inverting amplifier U8, respectively. The output terminal of the inverting amplifier U8 is connected to the inverting input terminal of the second inverting integrator U9 via the tenth resistor R10. A 0.8-order unit circuit is connected between the inverting input terminal and the output terminal of the second inverting integrator U9. The non-inverting input terminal of the second inverting integrator U9 is grounded. The output terminal of the second inverting integrator U9 serves as the output terminal of the second fractional-order chaotic circuit, outputting the signal y. The third fractional-order chaotic circuit includes an eleventh resistor R11. The input of the eleventh resistor R11 is connected to the second output terminal -x of the first fractional-order chaotic circuit, and the other end of the eleventh resistor R11 is connected to the inverting input terminal of the third inverting adder U10. The non-inverting input terminal of the third inverting adder U10 is grounded. The input of the twelfth resistor R12 is connected to the second output terminal -z of the third fractional-order chaotic circuit, and the other end of the twelfth resistor R12 is connected to the inverting input terminal of the third inverting adder U10. The two ends of the thirteenth resistor R13 are respectively connected to the inverting input terminal and the output terminal of the third inverting adder U10. The output terminal of the third inverting adder U10 is connected to the third inverting adder U10 via the fourteenth resistor R14. The inverting input of the third inverting integrator U11 is connected to the inverting input and output of the third inverting integrator U11 via a 0.8th order unit circuit. The non-inverting input of the third inverting integrator U11 is grounded. The output of the third inverting integrator U11 serves as the first output of the third fractional-order chaotic circuit, outputting a positive signal z. The output of the third inverting integrator U11 is connected to the inverting input of the fourth inverter U12 via the fifteenth resistor R15. The non-inverting input of the fourth inverter U12 is grounded. The sixteenth resistor R16 connects the inverting input and output of the fourth inverter U12. The output of the fourth inverter U12 serves as the second output of the third fractional-order chaotic circuit, outputting an inverted signal. z; The fourth fractional-order chaotic circuit includes a fourth multiplier A4, the two input terminals of which are respectively connected to the output terminal M of the fractional-order memristor circuit and the second output terminal of the fourth fractional-order chaotic circuit. w, the output of the fourth multiplier A4 is connected to the inverting input of the fourth inverting adder U13 via the seventeenth resistor R17; the non-inverting input of the fourth inverting adder U13 is grounded; the two inputs of the fifth multiplier A5 are connected to the first output y of the second fractional chaotic circuit and the first output z of the third fractional chaotic circuit, respectively; the output of the fifth multiplier A5 is connected to the inverting input of the fourth inverting adder U13 via the eighteenth resistor R18; the two ends of the nineteenth resistor R19 are connected to the inverting input and output of the fourth inverting adder U13, respectively; the output of the fourth inverting adder U13 is connected to the fourth inverting integrator U14 via the twentieth resistor R20. The inverting input terminal of the fourth inverting integrator U14 is connected to the non-inverting input terminal, which is grounded. A 0.8th order unit circuit is connected between the inverting input terminal and the output terminal of the fourth inverting integrator U14. The output terminal of the fourth inverting integrator U14 serves as the first output terminal of the fourth fractional-order chaotic circuit, outputting a positive signal w. The output terminal of the fourth inverting integrator U14 is connected to the inverting input terminal of the fifth inverter U15 via the twenty-first resistor R21, and the non-inverting input terminal of the fifth inverter U15 is grounded. A twenty-second resistor R22 is connected between the inverting input terminal and the output terminal of the fifth inverter U15, and the output terminal of the fifth inverter U15 serves as the second output terminal of the fourth fractional-order chaotic circuit, outputting an inverted signal. w; The 0.8th order unit circuit one includes a capacitor CC1 connected in series with a resistor RC1 and then in parallel with a capacitor CB1, and a capacitor CB1 connected in series with a resistor RB1 and then in parallel with a capacitor CA1, and a resistor RA1 connected in parallel with a capacitor CA1; the 0.8th order unit circuit two includes a capacitor CC2 connected in series with a resistor RC2 and then in parallel with a capacitor CB2, and a capacitor CB2 connected in series with a resistor RB2 and then in parallel with a capacitor CA2, and a resistor RA2 connected in parallel with a capacitor CA2; the 0.8th order unit circuit three includes a capacitor CC3 connected in series with a resistor RC3 and then in parallel with a capacitor CB3, and a capacitor CB3 connected in series with a resistor RB3 and then in parallel with a capacitor CA3, and a resistor RA3 connected in parallel with a capacitor CA3; the 0.8th order unit circuit four includes a capacitor CC4 connected in series with a resistor RC4 and then in parallel with a capacitor CB4, and a capacitor CB4 connected in series with a resistor RB4 and then in parallel with a capacitor CA4, and a resistor RA4 connected in parallel with a capacitor CA4; The resistance values ​​of resistors RA, RB, RC, RD, RE, RF, RG, RH, and RI in the fractional-order memristor circuit satisfy the following relationships: RC / RA=1, RC / RB=1, RE / RD=1, RG / RF=1, and RI / RH=1; the resistance values ​​of the first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, sixth resistor R6, and seventh resistor R7 in the first fractional-order chaotic circuit satisfy the following relationships: R4 / R1=1.89, R4 / R2=1, R4 / R3=1, and R7 / R6=1; the eighth resistor R in the second fractional-order chaotic circuit... The resistance values ​​of resistors 8 and 9 satisfy the relationship R9 / R8=4; the resistance values ​​of resistors 11, 12, 13, 15, and 16 in the third fractional-order chaotic circuit satisfy the relationships R13 / R11=0.85, R13 / R12=1, and R16 / R15=1; the resistance values ​​of resistors 17, 18, 19, 21, and 22 in the fourth fractional-order chaotic circuit satisfy the relationships R19 / R17=1, R19 / R18=1, and R22 / R21=1. Since unit circuits one, two, three, and four are all fractional-order (0.8th order) circuits, resistors RA1, RA2, RA3, and RA4 have a fixed resistance of 782 kΩ; resistors RB1, RB2, RB3, and RB4 have a fixed resistance of 196 kΩ; resistors RC1, RC2, RC3, and RC4 have a fixed resistance of 21 kΩ; capacitors CA1, CA2, CA3, and CA4 have a fixed capacitance of 0.437 μF; capacitors CB1, CB2, CB3, and CB4 have a fixed capacitance of 0.219 μF; and capacitors CC1, CC2, CC3, and CC4 have a fixed capacitance of 0.237 μF.

[0014] The fractional-order memristor circuit is a fractional-order magnetically controlled memristor model, and its mathematical expression is: Where v(t) represents the input voltage of the memristor, i(t) represents the output current of the memristor, and M( (t) represents the memconductance value of the memristor. (t) represents the internal state variables of the memristor, and k is the parameter of the memristor, expressed as the value of R9 / R8. Let represent a q-order Caputo-type fractional differential operator, and [0,t] represent the range of values ​​for the differential variable.

[0015] The mathematical expression for the four-dimensional chaotic circuit based on fractional memristors is: Where x, y, z, and w are state variables. q represents the order of the fractional derivative in the system equation, and a, b, and c are system parameters. In the first fractional-order chaotic circuit, the ratio of the fourth resistor R4 to the first resistor R1 is R4 / R1, denoted by parameter a. In the second fractional-order chaotic circuit, the ratio of the fourth resistor R4 to the second resistor R2 is R4 / R2, denoted by parameter b. In the third fractional-order chaotic circuit, the ratio of the thirteenth resistor R13 to the eleventh resistor R11 is R13 / R11, denoted by parameter c. The first inverting adder U1, the first inverter U2, the square root extractor U3, the second inverter U4, the second inverting adder U5, the first inverting integrator U6, the third inverter U7, the inverting proportional amplifier U8, the second inverting integrator U9, the third inverting adder U10, the third inverting integrator U11, the fourth inverter U12, the fourth inverting adder U13, the fourth inverting integrator U14, and the fifth inverter U15 are all of model TL082CD; the first multiplier A1, the second multiplier A2, the third multiplier A3, the fourth multiplier A4, and the fifth multiplier A5 are all of model AD633.

[0016] like Figures 2 to 8 As shown, this embodiment represents the simulation results of the circuit of the present invention. The system parameters q = 0.8, b = 1, and c = 0.85 remain unchanged, while only parameter a (i.e., ...) is changed. Figure 1 The value of the ratio (R4 / R1) of the fourth resistor R4 to the first resistor R1 in the first fractional-order chaotic circuit shown in the overall circuit diagram can generate chaotic attractors with various different structures. Figure 2 Two-dimensional phase diagrams of the chaotic attractors of the second and third fractional-order chaotic circuits when a=1.89; Figure 3 Two-dimensional phase diagrams of the chaotic attractors of the second and third fractional-order chaotic circuits when a=1.99; Figure 4 The two-dimensional phase diagrams of the chaotic attractors of the second and third fractional-order chaotic circuits when a=2.18 are shown. Figure 5 Two-dimensional phase diagrams of the chaotic attractors of the second and third fractional-order chaotic circuits when a=3.15; Figure 6 Two-dimensional phase diagrams of the chaotic attractors of the second and third fractional-order chaotic circuits when a=3.35; Figure 7 The three-dimensional phase diagrams of the transient chaotic attractors of the first, second, and third fractional-order chaotic circuits when a=3.145 are shown. Figure 8 The time series diagram of the chaotic sequence generated by the first fractional-order chaotic circuit when a=3.145 shows that the system instantly changes from a chaotic state to a periodic state at time t=222.9s.

[0017] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A four-dimensional chaotic circuit based on a fractional-order memristor, characterized in that, include: Fractional-order memristor circuit, first fractional-order chaotic circuit, second fractional-order chaotic circuit, third fractional-order chaotic circuit and fourth fractional-order chaotic circuit: The fractional-order memristor circuit is used to generate signal M, the first fractional-order chaotic circuit is used to generate chaotic sequence x, the second fractional-order chaotic circuit is used to generate chaotic sequence y, the third fractional-order chaotic circuit is used to generate chaotic sequence z, and the fourth fractional-order chaotic circuit is used to generate chaotic sequence w. The model of the four-dimensional chaotic circuit is as follows: in, q represents the order of the fractional derivative in the system equation, and a, b, and c are system parameters. In the first fractional chaotic circuit, the ratio of the fourth resistor R4 to the first resistor R1 is R4 / R1, denoted by parameter a. In the second fractional chaotic circuit, the ratio of the fourth resistor R4 to the second resistor R2 is R4 / R2, denoted by parameter b. In the third fractional chaotic circuit, the ratio of the thirteenth resistor R13 to the eleventh resistor R11 is R13 / R11, denoted by parameter c.

2. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 1, characterized in that, The fractional-order memristor circuit includes a first multiplier A1. Both inputs of the first multiplier A1 are connected to the output y of the second fractional-order chaotic circuit. The output of the first multiplier A1 is connected to the inverting input of the first inverting adder U1 via resistor RA. The non-inverting input of the first inverting adder U1 is grounded. The negative terminal of power supply V1 is grounded, and the positive terminal of power supply V1 is connected to the inverting input of the first inverting adder U1 via resistor RB. The two ends of resistor RC are connected to the inverting input and output of the first inverting adder U1, respectively. One end of resistor RD is connected to the output of the first inverting adder U1. One end of resistor RD is connected to the inverting input of the first inverter U2; the non-inverting input of the first inverter U2 is grounded; the two ends of resistor RE are connected to the inverting input and output of the first inverter U2, respectively; one end of resistor RF is connected to the output of the first inverter U2, and the other end of resistor RF is connected to the inverting input of the square root U3; the non-inverting input of the square root U3 is grounded; one end of resistor RG is connected to the inverting input of the square root U3, and the other end of resistor RG is connected to the output of the second inverter U4; the two ends of resistor RH are connected to the inverting input and output of the second inverter U4, respectively. The non-inverting input of the second inverter U4 is grounded; one end of the resistor RI is connected to the inverting input of the second inverter U4, and the other end of the resistor RI is connected to the output of the second multiplier A2. Both inputs of the second multiplier A2 are connected to the output M of the square root U3, and the output of the square root U3 serves as the output signal M of the fractional memristor circuit.

3. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 2, characterized in that, The first fractional-order chaotic circuit includes a third multiplier A3. Both inputs of the third multiplier A3 are connected to the output y of the second fractional-order chaotic circuit. The output of the third multiplier A3 is connected to the inverting input of the second inverting adder U5 via a second resistor R2. The input of the first resistor R1 is connected to the first output z of the third fractional-order chaotic circuit, and the other end of the first resistor R1 is connected to the inverting input of the second inverting adder U5. The positive terminal of the power supply V2 is grounded, and the negative terminal of the power supply V2 is connected to the inverting input of the second inverting adder U5 via a third resistor R3. The two ends of the fourth resistor R4 are connected to the inverting input and output of the second inverting adder U5, respectively. The non-inverting input of the second inverting adder U5 is grounded. The output of the second inverting adder U5 is connected to the inverting input of the first inverting integrator U6 via the fifth resistor R5; a 0.8 order unit circuit is connected between the inverting input and output of the first inverting integrator U6, and the non-inverting input of the first inverting integrator U6 is grounded. The output of the first inverting integrator U6 serves as the first output of the first fractional-order chaotic circuit, outputting a positive signal x. The output of the first inverting integrator U6 is connected to the inverting input of the third inverter U7 via a sixth resistor R6, and the non-inverting input of the third inverter U7 is grounded. A seventh resistor R7 connects the inverting input and output of the third inverter U7, and the output of the third inverter U3 serves as the second output of the first fractional-order chaotic circuit, outputting an inverted signal. x.

4. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 3, characterized in that, The second fractional-order chaotic circuit includes an eighth resistor R8. The input terminal of the eighth resistor R8 is connected to the first output terminal w of the fourth fractional-order chaotic circuit. The other end of the eighth resistor R8 is connected to the inverting input terminal of the inverting amplifier U8. The non-inverting input terminal of the inverting amplifier U8 is grounded. The two ends of the ninth resistor R9 are connected to the inverting input and output terminals of the inverting proportional amplifier U8, respectively. The output of the inverting amplifier U8 is connected to the inverting input of the second inverting integrator U9 via the tenth resistor R10; a 0.8th order unit circuit is connected between the inverting input and output of the second inverting integrator U9, and the non-inverting input of the second inverting integrator U9 is grounded. The output of the second inverting integrator U9 serves as the output of the second fractional-order chaotic circuit, outputting the signal y.

5. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 4, characterized in that, The third fractional-order chaotic circuit includes an eleventh resistor R11. The input of the eleventh resistor R11 is connected to the second output terminal -x of the first fractional-order chaotic circuit, and the other end of the eleventh resistor R11 is connected to the inverting input terminal of the third inverting adder U10. The non-inverting input terminal of the third inverting adder U10 is grounded. The input of the twelfth resistor R12 is connected to the second output terminal -z of the third fractional-order chaotic circuit, and the other end of the twelfth resistor R12 is connected to the inverting input terminal of the third inverting adder U10. The two ends of the thirteenth resistor R13 are respectively connected to the inverting input terminal and the output terminal of the third inverting adder U10. The output terminal of the third inverting adder U10 is connected to the third inverting adder U10 via the fourteenth resistor R14. The inverting input of the third inverting integrator U11 is connected to the inverting input and output of the third inverting integrator U11 via a 0.8th order unit circuit. The non-inverting input of the third inverting integrator U11 is grounded. The output of the third inverting integrator U11 serves as the first output of the third fractional-order chaotic circuit, outputting a positive signal z. The output of the third inverting integrator U11 is connected to the inverting input of the fourth inverter U12 via the fifteenth resistor R15. The non-inverting input of the fourth inverter U12 is grounded. The sixteenth resistor R16 connects the inverting input and output of the fourth inverter U12. The output of the fourth inverter U12 serves as the second output of the third fractional-order chaotic circuit, outputting an inverted signal. z.

6. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 5, characterized in that, The fourth fractional chaotic circuit includes a fourth multiplier A4, whose two input terminals are respectively connected to the output terminal M of the fractional memristor circuit and the second output terminal of the fourth fractional chaotic circuit. w, the output of the fourth multiplier A4 is connected to the inverting input of the fourth inverting adder U13 via the seventeenth resistor R17; The non-inverting input of the fourth inverting adder U13 is grounded; the two inputs of the fifth multiplier A5 are connected to the first output y of the second fractional chaotic circuit and the first output z of the third fractional chaotic circuit, respectively; the output of the fifth multiplier A5 is connected to the inverting input of the fourth inverting adder U13 via the eighteenth resistor R18; the two ends of the nineteenth resistor R19 are connected to the inverting input and output of the fourth inverting adder U13, respectively; the output of the fourth inverting adder U13 is connected to the twentieth resistor R20. The inverting input of the fourth inverting integrator U14 is connected, and the non-inverting input of the fourth inverting integrator U14 is grounded; a 0.8th order unit circuit is connected between the inverting input and output of the fourth inverting integrator U14; the output of the fourth inverting integrator U14 serves as the first output of the fourth fractional chaotic circuit, outputting a positive signal w; the output of the fourth inverting integrator U14 is connected to the inverting input of the fifth inverter U15 via the twenty-first resistor R21, and the non-inverting input of the fifth inverter U15 is grounded; A 22-year resistor R22 is connected between the inverting input and output of the fifth inverter U15. The output of the fifth inverter U15 serves as the second output of the fourth fractional-order chaotic circuit, outputting an inverted signal. w.

7. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 6, characterized in that, The 0.8th order unit circuit includes a capacitor CC1 connected in series with a resistor RC1 and then in parallel with a capacitor CB1, and a capacitor CB1 connected in series with a resistor RB1 and then in parallel with a capacitor CA1, and a resistor RA1 connected in parallel with a capacitor CA1. The second 0.8th order unit circuit includes a capacitor CC2 connected in series with a resistor RC2 and then in parallel with a capacitor CB2, and a capacitor CB2 connected in series with a resistor RB2 and then in parallel with a capacitor CA2, with a resistor RA2 connected in parallel with the capacitor CA2; the third 0.8th order unit circuit includes a capacitor CC3 connected in series with a resistor RC3 and then in parallel with a capacitor CB3, and a capacitor CB3 connected in series with a resistor RB3 and then in parallel with the capacitor CA3, with a resistor RA3 connected in parallel with the capacitor CA3; the fourth 0.8th order unit circuit includes a capacitor CC4 connected in series with a resistor RC4 and then in parallel with a capacitor CB4, and a capacitor CB4 connected in series with a resistor RB4 and then in parallel with the capacitor CA4, with a resistor RA4 connected in parallel with the capacitor CA4.

8. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 7, characterized in that, The resistance values ​​of resistors RA, RB, RC, RD, RE, RF, RG, RH, and RI in the fractional-order memristor circuit satisfy the following relationships: RC / RA=1, RC / RB=1, RE / RD=1, RG / RF=1, and RI / RH=1; the resistance values ​​of the first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, sixth resistor R6, and seventh resistor R7 in the first fractional-order chaotic circuit satisfy the following relationships: R4 / R1=1.89, R4 / R2=1, R4 / R3=1, and R7 / R6=1; the eighth resistor R in the second fractional-order chaotic circuit... The resistance values ​​of resistors 8 and 9 satisfy the relationship R9 / R8=4; the resistance values ​​of resistors 11, 12, 13, 15, and 16 in the third fractional-order chaotic circuit satisfy the relationships R13 / R11=0.85, R13 / R12=1, and R16 / R15=1; the resistance values ​​of resistors 17, 18, 19, 21, and 22 in the fourth fractional-order chaotic circuit satisfy the relationships R19 / R17=1, R19 / R18=1, and R22 / R21=1.

9. The four-dimensional chaotic circuit based on a fractional-order memristor as described in claim 8, characterized in that, The component parameter values ​​in the 0.8th order unit circuit are as follows: Resistor RA1 = Resistor RA2 = Resistor RA3 = Resistor RA4 = 782kΩ; Resistor RB1 = Resistor RB2 = Resistor RB3 = Resistor RB4 = 196 kΩ; Resistor RC1 = Resistor RC2 = Resistor RC3 = Resistor RC4 = 21 kΩ; Capacitor CA1 = Capacitor CA2 = Capacitor CA3 = Capacitor CA4 = 0.437μF; Capacitor CB1 = Capacitor CB2 = Capacitor CB3 = Capacitor CB4 = 0.219μF; Capacitor CC1 = Capacitor CC2 = Capacitor CC3 = Capacitor CC4 = 0.237μF.

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