High-performance message batch pushing method and device based on ring buffer and compare-and-swap atomic operation and electronic equipment

Abstract

The application provides a high-performance message batch pushing method and device based on a ring buffer and a compare-and-swap atomic operation and electronic equipment. A recyclable lock-free object pool is generated based on the ring buffer, an atomic serial number generator is initialized, and bit and addressing conversion logic is configured. When multiple hardware processor cores concurrently access the messages to be pushed, the ready message events marked as consumable states are generated in the ring buffer based on the lock-free object pool and the bit and addressing conversion logic. The upper limit of the published serial number of the ring buffer is polled and listened to, so as to extract the target channel identifiers corresponding to the service payloads in each ready message event, and then generate the aggregated refresh data packets pushed based on the multiple service payloads sent to the same network connection. The application solves the technical defects of serious lock competition, large GC pressure and low network IO efficiency in the prior art, and realizes robust pushing under extreme load.

Description

Technical Field

[0001] This application relates to the field of instant messaging push technology, and more specifically, to a high-performance message batch push method, apparatus, and electronic device based on a circular buffer and compare-and-swap atomic operations. Background Technology

[0002] In high-concurrency instant messaging systems, the real-time distribution of massive amounts of messages places extremely high demands on the throughput and real-time performance of the message push system. The system needs to support extremely high-frequency message injection and efficiently complete batch pushes to clients to reduce system response latency and save server resources.

[0003] In existing message push solutions, a producer-consumer model based on blocking queues is typically used. This solution first uses a system-defined blocking queue as a relay station. After receiving business messages, multiple producer threads compete for the queue's mutex lock to push message objects into the queue one by one. Subsequently, consumer threads continuously retrieve messages from the queue and call the network sending interface to execute the network transmission of a single message.

[0004] However, this push solution based on blocking queues has significant technical drawbacks. First, lock contention is severe; traditional blocking queues experience extensive lock contention during concurrent access, leading to frequent thread context switching and low utilization of the hardware processing core. Second, garbage collection is under heavy pressure; each message requires the creation of an independent event object, and in scenarios with massive message volumes, the high frequency of object creation and recycling can easily cause garbage collection pauses, affecting push real-time performance. Finally, network input / output efficiency is low; sending messages independently results in excessively frequent system calls, failing to leverage the batch transmission advantages of the network protocol stack. Existing technologies struggle to meet the real-time, robust processing requirements for extreme concurrent loads in high-performance scenarios. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a high-performance message batch push method, apparatus, and electronic device based on a circular buffer and comparison-and-exchange atomic operations.

[0006] A high-performance message batch push method based on a circular buffer and compare-and-swap atomic operations includes: Step 1: Generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator and configure bit and address conversion logic for it; Step 2: When the multiple hardware processor cores concurrently access the message to be pushed, a ready message event marked as consuming is generated in the circular buffer based on the lock-free object pool and the bit-address conversion logic. Step 3: Perform polling and listening on the upper limit of the published sequence number of the circular buffer to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate an aggregated refresh data packet for push based on multiple service payloads sent to the same network connection.

[0007] Optionally, it also includes: step 4, performing push processing on the aggregated refresh data packet based on preset degradation protection rules, and performing adaptive backpressure adjustment according to the load pressure of the ring buffer to limit the injection rate of the multiple hardware processor cores to the ring buffer.

[0008] Optionally, a fixed-capacity message event object grid is pre-allocated within the contiguous physical memory space of the circular buffer to generate a lock-free object pool that can be reused repeatedly.

[0009] Optionally, an atomic sequence number generator is initialized to encapsulate a core sequence number variable that represents the production progress within the atomic sequence number generator. The core sequence number variable serves as a globally unique sequence number locking flag, which can be accessed concurrently by the multiple hardware processor cores when executing multiple producer threads in parallel to receive messages to be pushed.

[0010] Optionally, bit-and-address conversion logic is configured for the atomic number generator.

[0011] Optionally, cache line padding is performed on the core sequence number variable to pad placeholder bytes before and after the core sequence number variable so that it occupies a hardware cache line independently, thereby eliminating hardware-level pseudo-sharing interference caused by multiple variables sharing the same hardware cache line when multiple hardware processor cores concurrently request enqueue sequence numbers.

[0012] Optionally, a globally monotonically increasing logical sequence number is generated based on the core sequence number variable.

[0013] Optionally, when the multiple hardware processor cores concurrently access the message to be pushed, each hardware processor core uses the bit-AND addressing conversion logic to map the target incremental sequence number to the corresponding physical storage index in real time in order to locate the message event object in the lock-free object pool in the memory space.

[0014] Optionally, the service payload carried by the message to be pushed is overwritten and filled into the message event object cell pointed to by the physical storage index.

[0015] Optionally, the filled message event object is transitioned from the request pre-occupancy state to the release ready state, and then a ready message event marked as consuming is generated in the circular buffer.

[0016] Optionally, each of the hardware processor cores reads the current logical sequence number from the atomic sequence number generator as the expected value, and attempts to perform a numerical update on the core sequence number variable using hardware instruction-level comparison and exchange atomic logic to lock the target incremental sequence number.

[0017] Optionally, an event handler is invoked to poll the upper limit of the published sequence number of the circular buffer and pull multiple ready message events injected and accumulated in parallel by the multiple hardware processor cores at once.

[0018] Optionally, the target channel identifier corresponding to the service payload in each ready message event is extracted, and aggregation and classification logic based on the channel dimension is executed to group and assemble multiple service payloads sent to the same network connection into a physical layer aggregate refresh data packet.

[0019] Optionally, the aggregated refresh data packet is subjected to batch refresh processing to form a pushable aggregated refresh data packet.

[0020] Optionally, the aggregated refresh data packet is delivered to the asynchronous execution engine to perform the first-level push; the resource monitoring plugin is synchronously invoked to collect the idle rate of the circular buffer in real time and match the degradation protection rules: in response to the system load exceeding the first-level warning threshold, the push task is diverted; in response to the system load triggering the second-level critical point, the caller running strategy is automatically activated to force the push task to be directly and synchronously executed by the hardware processor core currently executing the production release in step 2, and the injection rate of the multiple hardware processor cores to the circular buffer is limited by introducing a self-disciplined backpressure transmission mechanism.

[0021] A high-performance message batch push device based on a circular buffer and compare-and-swap atomic operations, comprising: The first program unit is used to generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator and configure bit and address conversion logic for it. The second program unit is used to generate ready message events marked as consuming in the circular buffer based on the lock-free object pool and the bit-address conversion logic when the multiple hardware processor cores concurrently access the message to be pushed. The third program unit is used to perform polling and listening on the upper limit of the published sequence number of the circular buffer, so as to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate a push aggregate refresh data packet based on multiple service payloads sent to the same network connection.

[0022] An electronic device includes a memory and a processor, wherein the memory stores a computer-executable program, and the processor is configured to run the computer-executable program to implement the high-performance message batch push method based on a circular buffer and compare-and-swap atomic operations as described in any one of the claims.

[0023] The technical advantages of the technical solution provided in this application are: This application presents a high-performance batch message push method that addresses the technical shortcomings of traditional blocking queue-based solutions, such as severe lock contention, high garbage collection pressure, and low network I / O efficiency. By constructing a lock-free object pool based on a circular buffer and introducing CAS atomic operations, it solves the problem of frequent thread switching caused by traditional mutex locks. Compared to traditional blocking queues, this application utilizes an atomic sequence number generator and bitwise AND addressing logic to achieve lock-free contention, enabling multiple hardware processor cores to complete sequence number preemption at instruction-level efficiency and eliminating kernel-mode lock contention. Through a pre-allocation mechanism for object grid bits, it achieves overlay filling of message payloads, significantly reducing the frequency of object creation in massive message scenarios, greatly reducing garbage collection pressure, and ensuring the real-time performance of the push process.

[0024] This application, based on a circular buffer-based ready state transition and batch aggregation mechanism, solves the problem of low IO efficiency caused by traditional message-by-message push methods. Traditional methods rely on triggering the sending of individual messages, while this application uses an event handler to poll the upper limit of published sequence numbers and groups messages destined for the same network connection into aggregated refresh packets based on the target channel identifier. Compared to traditional methods, this batch refresh processing can transform high-frequency system calls into low-frequency large-packet refreshes, significantly improving network input / output utilization and greatly enhancing system throughput while maintaining high response speed.

[0025] Furthermore, by employing degradation protection rules and an adaptive backpressure adjustment mechanism, a complete closed-loop optimization chain is formed, resolving the issue of system resource exhaustion under extreme loads. Compared to traditional fixed-capacity queues, this application monitors the idle rate of the circular buffer and flexibly enables traffic splitting and caller execution strategies when the load triggers a first- or second-level threshold. This mechanism directly feeds pressure back to the production end, forcing the hardware processor cores executing production releases to participate in the push action, thereby spontaneously limiting the injection rate. This design ensures that the system maintains real-time availability of the push chain even under extreme load scenarios, preventing memory overflow and exhibiting strong industrial-grade robustness. Attached Figure Description

[0026] Figure 1 This is a flowchart of a high-performance message batch push method based on a circular buffer and comparison and exchange atomic operations, according to an embodiment of this application.

[0027] Figure 2This is a schematic diagram of a high-performance message batch push device based on a circular buffer and comparison and exchange atomic operations, according to an embodiment of this application.

[0028] Figure 3 This is a structural diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0029] like Figure 1 As shown in the figure, this application provides a high-performance message batch push method based on a circular buffer and compare-and-swap atomic operations, comprising: Step 1: Generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator and configure bit and address conversion logic for it; Step 2: When the multiple hardware processor cores concurrently access the message to be pushed, a ready message event marked as consuming is generated in the circular buffer based on the lock-free object pool and the bit-address conversion logic. Step 3: Perform polling and listening on the upper limit of the published sequence number of the circular buffer to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate an aggregated refresh data packet for push based on multiple service payloads sent to the same network connection.

[0030] Optionally, it also includes: step 4, performing push processing on the aggregated refresh data packet based on preset degradation protection rules, and performing adaptive backpressure adjustment according to the load pressure of the ring buffer to limit the injection rate of the multiple hardware processor cores to the ring buffer.

[0031] Preferably, the specific implementation process of step 4 is as follows: First, a three-level gradient degradation guarantee rule linked to the running status of the ring buffer is constructed, clarifying the load threshold triggered by each level of degradation, the corresponding push execution path, and the adaptation processing logic with the aggregated refresh data packets generated in the previous steps. This three-level gradient degradation guarantee rule is set progressively according to the performance priority and reliability priority of push processing. Each level of rule corresponds to a specific ring buffer load state. The failure of the previous level rule will directly trigger the start of the next level rule, thus forming a continuous, uninterrupted push processing chain, ensuring that the aggregated refresh data packets can obtain the corresponding push execution resources under different load scenarios. Specifically, the first-level rule corresponds to the high-performance push path under normal ring buffer load scenarios, the second-level rule corresponds to the offloading push path under high ring buffer load scenarios, and the third-level rule corresponds to the reliable push path under overload ring buffer scenarios. The third-level rule synchronously carries the core execution logic of adaptive backpressure adjustment.

[0032] Preferably, in the specific technical implementation of step 4, the first-level push processing path in the degradation protection rule is executed first, delivering the aggregated refresh data packets generated in the previous steps to the event processing thread bound to the circular buffer. The event processing thread then completes the network push operation of the aggregated refresh data packets according to the preset batch refresh logic. This event processing thread is directly linked to the consumption progress of the circular buffer. The event processing thread processes the aggregated refresh data packets associated with the corresponding sequence number in ascending order of the published sequence number in the circular buffer. During the push process, the consumer fence sequence number of the circular buffer is updated synchronously, thereby releasing the slot resources of the corresponding sequence number in the circular buffer for reuse in subsequent message production. Among them, the consumer fence sequence number is a global variable representing the progress of message consumption completion. It is used to identify the maximum sequence number that has completed the entire push process in the circular buffer, providing a benchmark for subsequent slot availability judgment.

[0033] Preferably, in one scenario, when implementing step 4, the resource monitoring plugin is invoked synchronously to collect the number of free slots in the circular buffer in real time. Based on the ratio of the number of free slots to the total capacity of the circular buffer, the idle rate of the circular buffer is calculated. The calculated idle rate is then compared in real time with the preset first-level warning threshold in the degradation protection rules. When the idle rate of the circular buffer is lower than the first-level warning threshold, it is determined that the system load exceeds the first-level warning threshold. At this time, for newly generated aggregated refresh data packets, the push task is diverted. Instead of delivering the aggregated refresh data packets to the event processing thread bound to the circular buffer, they are submitted to a preset backup thread pool. The idle threads in the backup thread pool then perform the push operation of the aggregated refresh data packets. The number of core threads in this backup thread pool corresponds to the number of hardware computing cores of the device, and the maximum number of threads is twice the number of core threads. A fixed-capacity waiting queue is also set up to store aggregated refresh data packets that cannot be processed by threads temporarily. After the push operation of the backup thread pool is completed, the corresponding push completion count is updated synchronously to achieve observability of the entire push process.

[0034] Preferably, in the specific technical implementation of step 4, when the idle rate of the circular buffer collected by the resource monitoring plugin is lower than the preset secondary critical point in the degradation guarantee rule, it is determined that the system load has triggered the secondary critical point. At this time, the caller execution strategy is automatically activated, and for newly generated aggregate refresh data packets, the thread currently executing production release in step 2 is forced to directly and synchronously execute the push task. This caller execution strategy differs from the traditional handling method of discarding tasks or blocking and waiting. The thread originally used for producing messages is temporarily used to execute the push task. Before the push task is completed, the thread cannot continue to inject new messages to be pushed into the circular buffer. In this way, by introducing a self-disciplined backpressure transmission mechanism, the message injection rate of multiple hardware computing cores into the circular buffer is spontaneously limited. This processing logic directly transmits the pressure of system overload to the message production end, avoiding the problem of the circular buffer being full and memory resources being exhausted due to the message production speed continuously exceeding the consumption push speed. It adapts to the sudden traffic handling needs in high-concurrency instant messaging scenarios.

[0035] Preferably, the specific implementation process of adaptive backpressure adjustment in step 4 is as follows: Based on the execution status of each level of the degradation guarantee rule, the production admission judgment logic of the circular buffer is updated synchronously. Before each message to be pushed is injected into the circular buffer, the availability of the target slot is checked based on the current consumer fence sequence number, the total capacity of the circular buffer, and the current publishing cursor value. The publishing cursor is a global variable representing the progress of message production and publishing, used to identify the largest sequence number that has been published in the circular buffer. The availability check logic is as follows: first, the target incremental sequence number to be applied for is calculated based on the current publishing cursor value; then, the wraparound position sequence number is obtained by the difference between the target incremental sequence number and the total capacity of the circular buffer; the wraparound position sequence number is compared with the current consumer fence sequence number; if the wraparound position sequence number is greater than the consumer fence sequence number, it is determined that the message corresponding to the target slot has not yet been consumed and pushed. At this time, the message injection request is directly rejected, and the corresponding level of degradation processing is triggered. This achieves adaptive backpressure adjustment based on the real-time load of the circular buffer, preventing unconsumed messages from being overwritten and avoiding unlimited expansion of the circular buffer.

[0036] Preferably, in the specific technical implementation of step 4, during the execution of each level of degradation protection rule, the number of times the corresponding degradation action is triggered, the push processing time of the corresponding aggregated refresh data packet, and the push processing result are recorded synchronously to form a complete degradation execution log. Based on the continuously collected degradation execution log, the first-level warning threshold and the second-level critical point in the degradation protection rule are dynamically adapted and adjusted. The adjustment logic is as follows: when the number of triggers of the first-level degradation exceeds the set threshold within a unit time, the idle rate of the ring buffer corresponding to the first-level warning threshold is appropriately increased to initiate traffic diversion processing in advance and reduce the load pressure on the ring buffer; when the number of triggers of the second-level degradation exceeds the set threshold within a unit time, the idle rate of the ring buffer corresponding to the second-level critical point is appropriately increased to initiate the back pressure transmission mechanism in advance and prevent the system load from continuously increasing. The dynamically adjusted thresholds are synchronously updated in the comparison logic of the resource monitoring plugin, so that the degradation protection rule can adapt to the load fluctuations under different business scenarios and improve the environmental adaptability of the push processing link.

[0037] Preferably, in the specific technical implementation of step 4, after the push processing of the aggregated refresh data packet is completed, a cleanup operation of the corresponding message event object is performed synchronously. The channel reference and message body reference stored in the message event object are cleared to release the corresponding reference resources. At the same time, the circular buffer slot where the message event object is located is marked as reusable for subsequent message production. The push processing result is synchronously updated to a preset statistical counter, which includes the number of submitted messages, the number of completed pushes, the number of failed pushes, and the number of downgrade executions. The values ​​of these statistical counters can be read in real time to achieve observability of the entire push process. At the same time, the values ​​of the statistical counters also serve as an auxiliary reference for adaptive backpressure adjustment. When the proportion of failed pushes exceeds a set ratio, the message injection admission conditions of the circular buffer are tightened synchronously to further reduce the message injection rate and maintain the stable operation of the system.

[0038] Optionally, a fixed-capacity message event object grid is pre-allocated within the contiguous physical memory space of the circular buffer to generate a lock-free object pool that can be reused repeatedly.

[0039] Preferably, the dynamic calculation process of the fixed capacity of the circular buffer in step 1 is as follows: First, the available memory size of the current operating environment is obtained. Based on the available memory size, a preset capacity gradient rule is matched to calculate the fixed total capacity of the circular buffer. This fixed total capacity directly corresponds to the total number of message event object slots to be pre-allocated subsequently. The logic for setting the capacity gradient rule is that the larger the available memory size, the higher the matched fixed total capacity value, thus achieving an adaptive balance between memory usage and burst traffic handling capacity. This fixed total capacity setting provides a basic numerical basis for the continuous memory allocation of message event object slots and the implementation of bit-address conversion logic, adapting to the deployment requirements of different operating environments in high-concurrency instant messaging scenarios.

[0040] Preferably, the constraint verification process for the fixed capacity of the circular buffer in step 1 is as follows: A power-of-2 compliance verification is performed on the calculated fixed total capacity of the circular buffer. The verification logic is to determine whether the binary representation of the fixed total capacity contains only one bit with a value of 1. If the verification fails, the initialization process is terminated and an exception is thrown. If the verification passes, the corresponding index mask is calculated based on the fixed total capacity. This index mask is used in subsequent bit-addressing conversion logic to achieve fast conversion from logical sequence number to physical storage index. The core function of this constraint verification is to ensure that the fixed total capacity of the circular buffer can adapt to the operational requirements of the bit-addressing conversion logic, providing a prerequisite for lock-free fast location of message event object cells, and ensuring that the number of pre-allocated message event object cells precisely matches the addressing logic, avoiding addressing out-of-bounds issues.

[0041] Preferably, the contiguous memory allocation process for message event object cells in step 1 is as follows: Based on the fixed total capacity of the validated circular buffer, a number of message event object cells, matching the fixed total capacity, are created within contiguous physical memory space. All message event object cells are arranged sequentially and continuously to form a fixed-length array structure, with each position in the array corresponding to an independent message event object cell. This contiguous physical memory allocation method effectively improves CPU cache hit rate, reduces runtime memory access overhead, and provides a continuous and stable memory addressing foundation for subsequent multi-threaded concurrent access in a lock-free environment. Each message event object cell is used to hold a pre-created message event object instance, serving as the basic storage unit for generating a reusable lock-free object pool.

[0042] Preferably, the pre-creation and cell filling process of message event objects in step 1 is as follows: Based on a preset event object factory, an independent message event object instance is created for each message event object cell in the array structure. The created message event object instance is then completely filled into the corresponding message event object cell until all message event object cells are filled with message event object instances. This pre-creation and filling operation is completed once during system startup, and no new message event object creation operation is performed during runtime. This differs from the traditional approach of creating a new object for each message, reducing runtime object creation overhead from the root. Simultaneously, each message event object instance is equipped with a corresponding channel reference field, message body reference field, and placeholder fields for adapting cache line filling, ensuring that a single message event object instance can independently occupy a hardware cache line, eliminating false sharing interference in multi-core concurrent scenarios, and providing a foundation for the high-performance operation of the lock-free object pool.

[0043] Preferably, the construction process of the reusable mechanism for message event objects in step 1 is as follows: For each pre-created message event object instance, a corresponding field update method and reference cleanup method are defined. Simultaneously, the state transition rules of the message event object instance throughout the entire message production and consumption process are clarified, thus forming a complete object reusability logic. Specifically, the field update method is used during the message production phase to update the channel information and business payload corresponding to the message to be pushed to the corresponding fields of the corresponding message event object instance. The entire process only modifies field references and does not trigger the creation of new objects. The reference cleanup method is used after message consumption and push are completed to clear all reference fields in the message event object instance, allowing the message event object instance to return to its initial reusable state, and its corresponding message event object cell is also synchronously restored to a writable state. This reusable mechanism allows pre-allocated message event object instances to be reused multiple times along with the circular buffer's sequence number, thereby achieving the reusable capability of a lock-free object pool, effectively reducing runtime garbage collection pressure, and adapting to the processing needs of massive messages in high-concurrency instant messaging scenarios.

[0044] Preferably, the lock-free access addressing adaptation process of the lock-free object pool in step 1 is as follows: The lock-free object pool, after being populated with message event objects, is mapped and bound to a pre-calculated index mask and a globally monotonically increasing logical sequence number generated by the atomic sequence number generator. Based on bitwise AND addressing conversion logic, a conversion rule is established to transform the logical sequence number into the physical storage index of the message event object cell. This forms a lock-free access mechanism that can quickly locate the message event object instance in the corresponding cell using the logical sequence number. The operation logic of this conversion rule is as follows: Based on the target incremental sequence number obtained by the atomic sequence number generator, a bitwise AND operation is performed with the index mask to directly obtain the physical storage index of the message event object cell corresponding to the target incremental sequence number, thereby locating the pre-allocated message event object instance in that cell. The entire addressing process does not require traversal or lock contention; it can be completed through a single-step operation, effectively improving the object access efficiency in multi-threaded concurrent scenarios. At the same time, it provides accurate object location capabilities for subsequent concurrent message publishing based on comparison and exchange atomic operations, allowing multiple hardware processor cores to quickly access the target message event object cell in a lock-free environment.

[0045] Preferably, the construction process of the secure reuse verification mechanism for the lock-free object pool in step 1 is as follows: For each message event object cell in the lock-free object pool, a corresponding sequence number status flag is bound. Simultaneously, a linkage verification rule is established between cell availability and the consumer fence sequence number and publishing cursor sequence number in the circular buffer, thus forming a secure reuse mechanism for the object pool in a lock-free environment. Specifically, the consumer fence sequence number identifies the largest logical sequence number in the circular buffer that has completed full-process consumption and push, and the publishing cursor sequence number identifies the largest logical sequence number in the circular buffer that has completed message publishing. The linkage verification rule is that only when the sequence number associated with the message event object cell corresponding to the target logical sequence number has been fully processed by the consumer is the message event object instance in that cell marked as reusable and allowed to be used by new message production operations. This secure reuse verification mechanism can avoid the problem of unconsumed message event objects being overwritten by new messages in lock-free concurrent scenarios, ensuring the integrity of message processing. It also provides a preliminary state judgment basis for subsequent adaptive backpressure adjustment, allowing the lock-free object pool to operate stably and securely in high-concurrency scenarios.

[0046] Preferably, the initialization completion verification and ready state confirmation process of the lock-free object pool in step 1 is as follows: For the reusable lock-free object pool that has completed the full-process pre-allocation and mechanism construction, a full-cell initialization integrity verification is performed. The verification content includes the integrity of message event object instances in each message event object cell, the continuity of the contiguous memory space arrangement, the correctness of the mapping relationship between logical sequence numbers and physical storage indexes, and the availability of object reuse methods. If any item is found to be inconsistent with the preset requirements during the verification process, the initialization process is terminated and the corresponding exception information is thrown; if all full verifications pass, the lock-free object pool is marked as ready, completing the full-process generation of the reusable lock-free object pool. The lock-free object pool marked as ready can directly provide a lock-free, reusable message storage carrier for subsequent concurrent message publishing operations of multiple hardware processor cores. No object creation operation needs to be performed during system operation, thereby achieving zero object allocation at runtime, effectively reducing the impact of garbage collection pauses on the real-time performance of message push, and adapting to the core requirement of real-time distribution of massive messages in high-concurrency instant messaging systems.

[0047] Optionally, an atomic sequence number generator is initialized to encapsulate a core sequence number variable that represents the production progress within the atomic sequence number generator. The core sequence number variable serves as a globally unique sequence number locking flag, which can be accessed concurrently by the multiple hardware processor cores when executing multiple producer threads in parallel to receive messages to be pushed.

[0048] Preferably, the initialization preconditions and basic encapsulation structure construction process of the atomic sequence number generator in step 1 are as follows: The initialization operation of the atomic sequence number generator is performed after the fixed total capacity of the circular buffer has completed a power-of-2 compliance check and the continuous memory space of the lock-free object pool has been allocated. First, an independent encapsulation structure for the atomic sequence number generator is constructed, and the core sequence number variable used to represent the production progress is completely encapsulated in this structure, so that the core sequence number variable cannot be directly modified by external business logic, and can only be read and updated through the standardized interface preset by the atomic sequence number generator. Among them, the core sequence number variable serves as a globally unique sequence number locking flag, and its value directly corresponds to the maximum logical sequence number of messages that have been published in the circular buffer. When all producer threads executing in parallel apply for message event object slots, they must perform sequence number locking operations based on the current value of the core sequence number variable, thereby ensuring the global uniqueness and orderliness of sequence number allocation throughout the entire system, and providing a unified sequence number benchmark for concurrent message production of multiple hardware processor cores.

[0049] Preferably, the implementation process of memory model optimization and cache line filling for the core sequence number variable in step 1 is as follows: For the core sequence number variable encapsulated inside the atomic sequence number generator, memory isolation processing based on hardware cache lines is performed. A preset number of placeholder bytes are filled before and after the memory address of the core sequence number variable, so that the core sequence number variable can independently occupy a complete hardware cache line. Among them, the placeholder bytes are only used for spatial isolation of memory address and do not participate in any business logic operation or value update operation. The core function of the filling process is to eliminate the false sharing interference caused by multiple variables sharing the same hardware cache line when multiple hardware processor cores concurrently request enqueue sequence numbers. This avoids the cache synchronization overhead and performance loss caused by frequent hardware cache line invalidation in multi-core concurrent modification scenarios, allowing the read and update operations of the core sequence number variable to maintain a low access latency in multi-core concurrent scenarios, and providing a stable memory access foundation for high-concurrency access to the globally unique sequence number locking flag.

[0050] Preferably, the initial value setting and value update rule definition process for the core sequence number variable in step 1 is as follows: After completing the memory isolation processing of the core sequence number variable, an initial value is set for the core sequence number variable. This initial value is set to a negative number, representing that at the initial stage of system startup, there are no published message events or locked message event object slots in the circular buffer. At the same time, a strict value update rule is defined for the core sequence number variable. The rule clearly states that the value of the core sequence number variable can only monotonically increase with a fixed step size, and there can be no value rollback. In the single message publishing scenario, the value of the core sequence number variable increases by 1 fixed step size for each successfully locked available message event object slot; in the batch message publishing scenario, the increment step size is consistent with the number of slots requested for locking. This value update rule allows the value of the core sequence number variable to accurately represent the message production progress of the circular buffer, while providing a continuous and monotonically increasing logical sequence number source for subsequent bit and address conversion logic, ensuring that a stable mapping relationship is formed between the logical sequence number and the physical storage index of the message event object slot.

[0051] Preferably, the concurrent access interface definition and permission control process of the atomic sequence number generator in step 1 is as follows: For the atomic sequence number generator that encapsulates the core sequence number variable, two sets of mutually isolated standardized access interfaces are defined: a read-only access interface and an atomic update interface, thereby realizing permission control for concurrent access to the core sequence number variable. The read-only access interface is open to producer threads running on all hardware processor cores, as well as event handlers that subsequently execute message consumption. It only supports reading operations on the current value of the core sequence number variable, and the read operation follows memory visibility rules, ensuring that any update to the core sequence number variable completed by any hardware processor core can be observed instantly by all other hardware processor cores through the read-only access interface. The atomic update interface is only open to the preset compare-and-swap atomic logic, and only supports updating the value of the core sequence number variable through hardware instruction-level atomic operations. Any other business logic is prohibited from modifying the value of the core sequence number variable through this interface. This interface design not only ensures the global visibility of the core sequence number variable as a globally unique sequence number locking flag, but also structurally avoids the risk of the core sequence number variable being mistakenly modified in concurrent scenarios, ensuring the uniqueness and accuracy of the sequence number locking operation.

[0052] Preferably, the linkage adaptation process between the core sequence number variable and the availability verification logic of the circular buffer slot in step 1 is as follows: During the initialization process of the atomic sequence number generator, a linkage verification rule is simultaneously established between the core sequence number variable, the consumer fence sequence number of the circular buffer, and the fixed total capacity of the circular buffer. This rule is used to complete the availability verification of the target message event object slot when multiple hardware processor cores concurrently request sequence numbers, thus preventing unconsumed message events from being overwritten by new messages. The consumer fence sequence number is used to represent the maximum logical sequence number in the circular buffer that has completed the entire process of consumption and push. The execution logic of the linkage verification rule is as follows: After the producer thread calculates the target incremental sequence number based on the current value of the core sequence number variable, it first calculates the wraparound position sequence number by the difference between the target incremental sequence number and the fixed total capacity of the circular buffer. Then, it compares the wraparound position sequence number with the consumer fence sequence number. Only when the wraparound position sequence number is less than or equal to the consumer fence sequence number is the slot corresponding to the target incremental sequence number determined to be in an available state, and only then is the atomic update operation of the core sequence number variable allowed. This linkage adaptation ensures that the value update of the core sequence number variable is always linked to the actual consumption progress of the circular buffer, which not only guarantees the integrity of message processing, but also provides a preliminary state judgment basis for subsequent adaptive backpressure adjustment.

[0053] Preferably, the initialization process of the spin strategy for sequence number contention based on the core sequence number variable in step 1 is as follows: During the initialization phase of the atomic sequence number generator, a corresponding spin retry strategy is configured for the lock-free sequence number contention process based on the core sequence number variable. This strategy defines the processing logic after the failure of the comparison and exchange atomic operation when multiple hardware processor cores concurrently request sequence numbers. The specific rules of the spin retry strategy are as follows: when a hardware processor core fails to update the value of the core sequence number variable after performing a comparison and exchange atomic operation, it will immediately reread the latest current value of the core sequence number variable through the read-only access interface, recalculate the target incremental sequence number based on the latest value, and perform the comparison and exchange atomic operation again, thus forming a spin loop; at the same time, an upper limit threshold for the number of consecutive retries is set for the spin loop. When the number of consecutive spin retries exceeds the upper limit threshold during a single sequence number request, a thread yielding operation will be triggered, allowing the thread currently executing the sequence number request to temporarily yield hardware computing resources, avoiding the problem of a single thread occupying hardware computing resources for a long time in extreme concurrency scenarios, causing other producer threads to wait for a long time in their sequence number request operations. The initialization of this strategy makes the core sequence number variable a globally unique sequence number lock flag, which can support high-concurrency sequence number request operations of multiple hardware processor cores in a completely lock-free environment, while ensuring the orderliness and relative fairness of the sequence number allocation process.

[0054] Preferably, the initialization completion verification and ready state confirmation process of the atomic sequence number generator in step 1 is as follows: After completing the encapsulation of the core sequence number variable, memory isolation processing, initial value setting, access interface definition, linkage verification rule adaptation, and spin retry strategy configuration, a full-process initialization integrity verification is performed on the atomic sequence number generator to ensure that all functions of the atomic sequence number generator meet the preset operating requirements. The verification content includes whether the memory layout of the core sequence number variable meets the hardware cache line exclusive requirement, whether the permission control of the read-only access interface and atomic update interface is effective, whether the value update rule of the core sequence number variable meets the global monotonically increasing requirement, and whether the linkage verification logic with the slot availability of the circular buffer is running normally. If any item is found to be inconsistent with the preset requirements during the verification process, the initialization process is terminated and the corresponding exception information is thrown; if all verification items pass, the atomic sequence number generator is marked as ready, and the entire initialization process of the atomic sequence number generator is completed. The atomic sequence number generator marked as ready can provide a globally unique, lock-free concurrent sequence number locking service for producer threads that are executed in parallel by multiple hardware processor cores. At the same time, it provides a stable and continuous source of logical sequence numbers for bit and address conversion logic. Together with the pre-generated reusable lock-free object pool, it forms a complete lock-free message production basic environment, supporting message event generation and publishing operations in subsequent high-concurrency scenarios.

[0055] Optionally, bit-and-address conversion logic is configured for the atomic number generator.

[0056] Preferably, the pre-configuration verification and basic parameter binding process for the bit-and addressing conversion logic in step 1 is as follows: The configuration operation of the bit-and addressing conversion logic is executed after the atomic sequence number generator is initialized and the fixed total capacity of the circular buffer has passed the power of 2 compliance verification. First, the input parameter source of the bit-and addressing conversion logic is bound to the globally monotonically increasing logical sequence number generated by the atomic sequence number generator. The output mapping target of the bit-and addressing conversion logic is bound to the physical storage index of the message event object cell in the lock-free object pool within the circular buffer. At the same time, the fixed total capacity of the circular buffer is verified again to ensure that it meets the power of 2 requirement. Only after the verification passes will the subsequent conversion rule configuration operation be executed. This pre-configuration verification and parameter binding ensures that the input and output of the bit-and addressing conversion logic can accurately match the sequence number generation rules of the atomic sequence number generator and the storage structure of the lock-free object pool. This provides a compliant basic operating environment for the subsequent lock-free fast conversion from logical sequence number to physical storage index, avoiding addressing errors caused by mismatched basic parameters.

[0057] Preferably, the core index mask generation process of the bitwise AND addressing conversion logic in step 1 is as follows: Based on the fixed total capacity of the circular buffer after compliance verification, a corresponding index mask is calculated and generated. This index mask is the core baseline parameter for the bitwise AND addressing conversion logic to perform operations. The value of the index mask is the fixed total capacity of the circular buffer minus 1. The core principle of this value setting is that when the fixed total capacity of the circular buffer is a power of 2, the value of the fixed total capacity minus 1 has all low bits set to 1 and all high bits set to 0 in its binary representation. This provides accurate value truncation capability for subsequent bitwise AND operations, ensuring that the operation result falls within the effective physical storage index range of the circular buffer. The generated index mask is completely encapsulated within the bitwise AND addressing conversion logic and can only participate in addressing operations through the standardized interface of the conversion logic. It cannot be modified by external business logic, thereby ensuring the stability and uniqueness of the addressing operation baseline.

[0058] Preferably, the core operation rule definition process of the bitwise AND addressing conversion logic in step 1 is as follows: To complete the bitwise AND addressing conversion logic for parameter binding and index mask generation, a standardized sequence number-index conversion operation rule is defined. This rule clearly states that when the target increment sequence number output by the atomic sequence number generator is received, a bitwise AND operation is performed between the target increment sequence number and the pre-generated index mask. The result of the operation is the physical storage index corresponding to the target increment sequence number. This physical storage index directly corresponds to a unique message event object cell in the lock-free object pool. This operation rule differs from the traditional modulo operation rule. The bitwise AND operation can be completed in only one clock cycle, while the traditional modulo operation requires multiple clock cycles of processing overhead. This can significantly improve the conversion efficiency from sequence number to index. At the same time, this operation rule does not require traversal or lock contention, and can achieve lock-free fast addressing operation in multi-threaded concurrent scenarios, adapting to the high-frequency message production needs of high-concurrency instant messaging scenarios.

[0059] Preferably, the configuration process of the circular wraparound adaptation mechanism for the bitwise AND addressing conversion logic in step 1 is as follows: A circular wraparound adaptation rule matching the circular buffer's cyclic reuse characteristics is configured for the bitwise AND addressing conversion logic. This rule clearly states that no matter how large the logical sequence number generated by the atomic sequence number generator increases, the physical storage index obtained through the bitwise AND operation will always be limited to a valid range of 0 to the fixed total capacity of the circular buffer minus 1. When the value of the logical sequence number exceeds the fixed total capacity of the circular buffer, the bitwise AND operation will automatically complete the sequence number wraparound processing, remapping the out-of-range logical sequence number to a valid physical storage index at the beginning of the circular buffer. This circular wraparound adaptation mechanism allows the globally monotonically increasing logical sequence number to form a long-term stable mapping relationship with the fixed-capacity circular buffer. Combined with the lock-free object pool's message event object cyclic reuse mechanism, it achieves the cyclic utilization of the circular buffer slots, while avoiding the sequence number out-of-bounds problem in traditional array addressing, ensuring the continuity and stability of addressing operations throughout the entire message production process.

[0060] Preferably, the configuration process of the multi-concurrent access adaptation mechanism for the bit-AND addressing conversion logic in step 1 is as follows: A lock-free concurrency adaptation rule matching the concurrent access scenario of multiple hardware processor cores is configured for the bit-AND addressing conversion logic. This rule clearly states that the operation process of the bit-AND addressing conversion logic is a stateless pure operation, which does not modify any global variables during the operation. It only performs the operation based on the input target increment sequence number and a fixed index mask. Producer threads running on multiple hardware processor cores can simultaneously call the bit-AND addressing conversion logic to perform addressing operations without generating race conditions or requiring concurrency control through lock mechanisms. This concurrency adaptation mechanism, combined with the comparison and exchange atomic operations of the atomic sequence number generator, forms a complete lock-free sequence number allocation and addressing chain. After each producer thread locks a unique target increment sequence number through the comparison and exchange atomic operations, it can locate the corresponding message event object cell without locks or conflicts through the bit-AND addressing conversion logic, completely eliminating the lock contention overhead in the concurrent addressing process and significantly improving message production efficiency in multi-concurrency scenarios.

[0061] Preferably, the boundary verification and exception protection mechanism configuration process for the bit-AND addressing conversion logic in step 1 is as follows: A two-layer boundary verification rule is configured for the bit-AND addressing conversion logic. The first layer of verification is the validity check of the sequence number before the operation. Before performing the bit-AND operation, it is checked whether the input target increment sequence number is greater than or equal to the initial value of the atomic sequence number generator. If it does not meet the requirement, it is determined to be an illegal sequence number, the addressing operation is terminated, and an exception message is returned. The second layer of verification is the index range check after the operation. After completing the bit-AND operation and obtaining the physical storage index, it is checked whether the physical storage index is within the valid range of 0 to the fixed total capacity of the circular buffer minus 1. If it exceeds the range, the addressing operation is terminated, and an exception message is returned. Simultaneously, an exception log recording rule is configured for the bit-AND addressing conversion logic. For all illegal sequence numbers and index out-of-bounds exceptions, the corresponding sequence number value, triggering thread, and time information are recorded synchronously to facilitate subsequent problem location and investigation. This boundary verification and exception protection mechanism can effectively avoid addressing out-of-bounds problems caused by abnormal sequence number input, prevent illegal access to message event object grids, and ensure the security and integrity of lock-free object pool data storage.

[0062] Preferably, the end-to-end linkage adaptation configuration process of the bit and addressing conversion logic in step 1 is as follows: The configured bit and addressing conversion logic is linked and adapted with the upstream and downstream links of the entire message production process. Upstream, it is linked with the atomic number generator's comparison and exchange atomic operation to ensure that the target incremental sequence number locked by the comparison and exchange atomic operation can be directly input to the bit and addressing conversion logic, completing the rapid location of the physical storage index. Downstream, it is linked with the message event object filling operation of the lock-free object pool to ensure that the physical storage index obtained through the conversion logic can directly locate the corresponding message event object cell, providing an accurate memory address for the business payload coverage filling of the message to be pushed. Simultaneously, it is linked with the message consumption link of the downstream event processor. The event processor can quickly locate the corresponding message event object cell based on the consumption sequence number through the same bit and addressing conversion logic, completing the reading and processing of ready message events. This end-to-end linkage adaptation makes the bit and addressing conversion logic the core addressing foundation connecting the entire process of sequence number generation, message production, and message consumption, realizing lock-free fast memory access throughout the entire chain, providing core support for the high-performance operation of the entire batch message push method.

[0063] Preferably, the initialization completion verification and ready state confirmation process of the bit and addressing conversion logic in step 1 is as follows: After completing the definition of the operation rules, the configuration of the adaptation mechanism, and the binding of the full-link linkage, a full-process functional integrity verification is performed on the bit and addressing conversion logic. The verification content includes the matching of the index mask value with the fixed total capacity of the circular buffer, the accuracy of the sequence number-index conversion operation result, the effectiveness of the circular wraparound adaptation, the consistency of operation under concurrent access scenarios, and the triggering effectiveness of the boundary verification rules. If any item is found to be inconsistent with the preset requirements during the verification process, the configuration process is terminated and the corresponding exception information is thrown; if all verification items pass, the bit and addressing conversion logic is marked as ready, and the entire configuration process of the bit and addressing conversion logic is completed. The bit and addressing conversion logic marked as ready can provide high-concurrency, lock-free, and high-accuracy sequence number-to-index conversion services for producer threads running in parallel on multiple hardware processor cores. Together with the atomic sequence number generator and the lock-free object pool, it constitutes a complete lock-free message production basic environment, supporting the generation and publication of ready message events in subsequent high-concurrency scenarios.

[0064] Optionally, cache line padding is performed on the core sequence number variable to pad placeholder bytes before and after the core sequence number variable so that it occupies a hardware cache line independently, thereby eliminating hardware-level pseudo-sharing interference caused by multiple variables sharing the same hardware cache line when multiple hardware processor cores concurrently request enqueue sequence numbers.

[0065] Preferably, the pre-scenario adaptation and hardware principle anchoring process for the cache line filling process of the core sequence number variable in step 1 is as follows: the cache line filling process is executed after the atomic sequence number generator completes the encapsulation definition of the core sequence number variable and before the initial value setting of the core sequence number variable. The design of the processing action is anchored to the characteristics of multiple hardware processor cores executing producer threads in parallel and concurrently requesting enqueue numbers in high-concurrency instant messaging scenarios, combined with the cache read / write mechanism of the CPU hardware. The CPU hardware loads data from main memory into the cache in units of fixed-size cache lines to perform read / write operations. When multiple independent variables are stored in the same hardware cache line, if any hardware processor core performs a modification operation on one of the variables, it will cause all copies of that hardware cache line on other hardware processor cores to become invalid, and the latest data needs to be reloaded from main memory. This phenomenon is the hardware-level pseudo-shared interference. The core sequence number variable, as a globally unique sequence number locking flag, is the variable accessed most frequently by all producer threads. In high-concurrency scenarios, it will be frequently read and modified. If it shares the same hardware cache line with other variables, it will generate extremely high frequency of cache line invalidation and main memory reload operations, which will seriously affect the execution efficiency of sequence number allocation. Therefore, it is necessary to build an independent hardware cache line isolation environment for the core sequence number variable through cache line filling.

[0066] Preferably, the design and layout rule definition process for the placeholder byte parameters in step 1 of the cache line filling process is as follows: First, based on the standard cache line size of general-purpose CPU hardware, the total number of placeholder bytes to be filled is determined. Then, the placeholder bytes are divided into two groups: a pre-fill byte group and a post-fill byte group, which are respectively placed before and after the memory address of the core sequence number variable. The placeholder bytes are invalid data that does not participate in any business logic operations and does not carry any business data. Their only function is to occupy memory address space to achieve memory address isolation between the core sequence number variable and other business variables. The layout rule is clear: the total memory size of the pre-fill byte group and the total memory size of the post-fill byte group are not less than the total size of a single hardware cache line. This ensures that no matter how the starting address of the core sequence number variable in memory is aligned with the boundary of the hardware cache line, the complete data of the core sequence number variable will not fall into the same hardware cache line as any other business variable. This completely severs the cache line association between the core sequence number variable and other variables from the memory layout level, providing basic memory structure support for eliminating false sharing interference.

[0067] Preferably, the specific implementation process of cache line filling for the core sequence number variable in step 1 is as follows: Within the encapsulation structure of the atomic sequence number generator, the allocation and data layout of contiguous memory space are completed in the order of pre-padding byte group, core sequence number variable, and post-padding byte group. First, a pre-padding byte group of the corresponding memory size is allocated to complete the pre-isolation of memory addresses; then, the memory space for the core sequence number variable is allocated at the end of the contiguous memory address of the pre-padding byte group. The core sequence number variable adopts a modification rule that supports multi-threaded memory visibility, ensuring that any modification to the core sequence number variable by any hardware processor core can be observed by all other hardware processor cores in real time; finally, a post-padding byte group of the corresponding memory size is allocated at the end of the contiguous memory address of the core sequence number variable to complete the post-isolation of memory addresses. Throughout the entire memory layout process, the pre-padding byte group, core sequence number variable, and post-padding byte group occupy contiguous physical memory space, without inserting any other business variables, thereby ensuring that the core sequence number variable is completely wrapped by the two sets of padding bytes, forming an independent memory isolation interval.

[0068] Preferably, the principle and technical effect of eliminating false sharing interference in step 1 through cache line filling are as follows: After completing the cache line filling process, the core sequence number variable is completely isolated in memory layout by two sets of filling bytes, allowing it to independently occupy a complete hardware cache line, fundamentally eliminating the conditions for the generation of false sharing interference. In scenarios where multiple hardware processor cores concurrently request enqueue numbers, when a hardware processor core performs a comparison and swap atomic operation on the core sequence number variable and completes the value modification, it only causes the copy of the hardware cache line containing the core sequence number variable on other hardware processor cores to become invalid, without affecting the hardware cache lines containing other business variables; at the same time, modification operations of adjacent business variables by other hardware processor cores will not cause the hardware cache line containing the core sequence number variable to become invalid, and the value of the core sequence number variable can reside stably in the cache of each hardware processor core for a long time. This approach significantly reduces the number of cache line failures, main memory reload operations, and cache synchronization overhead between multiple cores in high-concurrency scenarios. It avoids the cache ping-pong effect caused by false sharing interference in traditional solutions, allowing the read and write operations of core sequence number variables to maintain stable low latency and adapt to the high-frequency sequence number application and update requirements in high-concurrency scenarios.

[0069] Preferably, the core sequence number variable that completes the cache line filling process in step 1 forms a deep performance linkage and adaptation relationship with the compare-and-swap atomic logic, providing an efficient hardware access foundation for lock-free sequence number contention. When performing sequence number locking operations, the compare-and-swap atomic logic needs to repeatedly execute three core actions: reading the core sequence number variable, comparing the expected value, and updating the value. Each sequence number locking operation requires multiple accesses to the core sequence number variable, and the access speed of the core sequence number variable directly determines the execution efficiency of the compare-and-swap atomic logic. After completing the cache line filling process, the cache hit rate of the core sequence number variable is significantly improved. Most read and write operations can be completed directly in the high-speed cache of the hardware processor core, without accessing main memory, greatly reducing the execution time of a single compare-and-swap atomic operation. Simultaneously, the elimination of false sharing interference reduces the cache synchronization waiting overhead in multi-core concurrent scenarios, lowers the failure probability of the compare-and-swap atomic operation, reduces the number of spin retries, and further improves the sequence number locking efficiency in multi-threaded concurrent scenarios, allowing multiple hardware processor cores to complete sequence number contention with higher concurrency, thus improving the throughput of the entire message production process.

[0070] Preferably, the cache line filling process for the core sequence number variable in step 1 forms a full-link functional support relationship with the bit and address conversion logic and the lock-free object pool, ensuring the stable and efficient operation of the entire message production process. The core sequence number variable is the only data source for generating globally monotonically increasing logical sequence numbers. The cache line filling process ensures low latency and high stability in the logical sequence number generation process, allowing the bit and address conversion logic to obtain the target incremental sequence number in real time and accurately, thereby quickly completing the conversion operation from logical sequence number to physical storage index. The accurate and rapid generation of the physical storage index allows the producer thread to accurately and efficiently locate the corresponding message event object cell in the lock-free object pool, completing the business payload overlay and filling operation of the message to be pushed. In the entire chain, the cache line filling process eliminates the access performance bottleneck of the core sequence number variable from the lowest-level hardware memory access level, providing a stable performance foundation for the entire process of logical sequence number generation, address conversion, object location, and data filling. It avoids performance fluctuations in the entire message production process caused by access latency fluctuations of the core sequence number variable, adapting to the real-time requirements of high-concurrency instant messaging systems for message push.

[0071] Preferably, the integrity verification and cross-architecture adaptation optimization process for the core sequence number variable cache line filling process in step 1 is as follows: After completing the memory layout and filling process, a cache line exclusivity verification is performed. The verification logic is to detect the start and end addresses of the memory of the core sequence number variable, confirm that the memory range in which it is located does not contain any other business variables, and that the total size of the memory range is not less than the size of a single hardware cache line, thereby verifying that the core sequence number variable can independently occupy a complete hardware cache line. If the verification fails, the size of the filling byte group is readjusted until the cache line exclusivity requirement is met. At the same time, for the differences in cache line size of different CPU hardware architectures, an adaptable filling byte quantity adjustment rule is configured. When the system starts, the hardware cache line size of the current running environment is automatically identified, and the total size of the pre-filling byte group and the post-filling byte group is dynamically adjusted to ensure that the cache line filling process can effectively eliminate false sharing interference under different hardware architectures. In addition, during system operation, the cache hit count, cache line miss count, and average time and success rate of comparison and swap atomic operations of the core sequence number variable are collected synchronously to continuously verify the running effect of cache line filling processing and ensure that the access performance of the core sequence number variable remains stable under high concurrency load scenarios.

[0072] Optionally, a globally monotonically increasing logical sequence number is generated based on the core sequence number variable.

[0073] Preferably, the pre-initialization and initial state definition process for generating globally monotonically increasing logical sequences based on the core sequence number variable in step 1 is as follows: The generation of logical sequences is initiated after the core sequence number variable completes cache line filling and initial value setting. First, the source of logical sequence number generation is strongly bound to the core sequence number variable encapsulated inside the atomic sequence number generator. This ensures that the value of the logical sequence number is entirely determined by the current value of the core sequence number variable, forming a one-to-one mapping relationship between the two, with no value modification path independent of the core sequence number variable. Simultaneously, an initial value is set for the logical sequence number, which is consistent with the initial value of the core sequence number variable and is set to a negative number. This represents the initial stage of system startup, where there are no published message events or locked message event object slots in the circular buffer, establishing a unified numerical benchmark for subsequent monotonically increasing rules. This strong binding design ensures that the generation of logical sequences is completely controlled by the core sequence number variable, avoiding problems such as sequence number value confusion and duplicate allocation, and providing a basic guarantee for globally unique sequence number allocation in multi-concurrency scenarios.

[0074] Preferably, the definition process of the core generation rule and atomic update linkage mechanism of the globally monotonically increasing logical sequence number in step 1 is as follows: First, the globally monotonically increasing rule of the logical sequence number is clarified. The rule restricts the value of the logical sequence number to only increase unidirectionally with a fixed step size, and there should be no value rollback, jump, or repetition. In the single message publishing scenario, the fixed step size is set to 1. In the batch message publishing scenario, the fixed step size is consistent with the number of message event object slots requested for locking. At the same time, the increment action of the logical sequence number is deeply linked with the execution result of the comparison and exchange atomic logic at the hardware instruction level. Only when the producer thread successfully completes the value update of the core sequence number variable through the comparison and exchange atomic logic will the corresponding target increment sequence number be generated based on the updated core sequence number variable value. This target increment sequence number is the globally monotonically increasing logical sequence number corresponding to this message publishing. If the comparison and exchange atomic logic fails to execute and the value of the core sequence number variable does not change, no new logical sequence number will be generated, and no change in the value of the original logical sequence number will be triggered. This linkage mechanism ensures the global uniqueness and strict monotonically increasing characteristics of logical sequence numbers in scenarios with concurrent access from multiple hardware processor cores at the hardware instruction level. It avoids sequence number conflicts and duplicate allocation problems in multi-threaded concurrent scenarios and adapts to the sequence number allocation requirements for the concurrent publication of massive messages in high-concurrency instant messaging systems.

[0075] Preferably, the implementation process of the global visibility guarantee mechanism for the globally monotonically increasing logical sequence number in step 1 is as follows: Based on the memory visibility rules preset by the core sequence number variable, a global real-time visibility capability is established across hardware processor cores for the generated logical sequence number. This ensures that after any hardware processor core completes the update of the core sequence number variable and generates a new logical sequence number, all producer threads and consumer threads running on other hardware processor cores can immediately read the latest logical sequence number value. Specifically, the producer thread obtains the message production progress of the current circular buffer by reading the latest logical sequence number value, and uses this as a benchmark to perform subsequent atomic operations of sequence number allocation, comparison, and exchange. The consumer thread obtains the upper limit of published message events in the current circular buffer by reading the latest logical sequence number value, and uses this as a benchmark to determine whether there are any ready message events to consume, and performs the corresponding message retrieval and processing operations. This global visibility guarantee mechanism allows the globally monotonically increasing logical sequence number to simultaneously serve as the production progress benchmark for the producer thread and the consumption progress benchmark for the consumer thread, establishing a lock-free progress synchronization mechanism between producers and consumers, avoiding the performance overhead caused by synchronizing production and consumption progress through locking mechanisms in traditional solutions.

[0076] Preferably, the adaptation mechanism between the globally monotonically increasing logical sequence number and the circular buffer storage structure in step 1 is implemented as follows: Taking into account the circular reuse characteristic of the fixed capacity of the circular buffer, a corresponding circular addressing adaptation rule is configured for the globally monotonically increasing logical sequence number. The rule clearly states that the value of the logical sequence number can increase infinitely with the continuous publication of messages, without being limited by the fixed total capacity of the circular buffer. Through bitwise AND addressing conversion logic, the infinitely increasing logical sequence number is mapped to the physical storage index within a fixed range of the circular buffer. Simultaneously, a complete lifecycle flow rule is defined for the logical sequence number. From its generation, the logical sequence number sequentially goes through four lifecycle stages: application pre-occupancy, data filling, publication readiness, and consumption completion. When the message event corresponding to the logical sequence number completes the full process of consumption and push, the circular buffer slot corresponding to that logical sequence number is marked as reusable. Newly generated logical sequence numbers can be remapped to this slot through bitwise AND addressing conversion logic, achieving circular reuse of the slot. This adaptation mechanism allows the globally monotonically increasing logical sequence number to form a long-term stable adaptation relationship with the fixed-capacity circular buffer. It ensures the global uniqueness of the sequence number and the orderliness of message publishing through the infinitely increasing characteristic, and adapts to the circular reuse characteristic of the circular buffer through bitwise addressing conversion logic. This solves the problems of limited sequence number range and easy sequence number conflict in circular reuse in traditional sequence number allocation schemes.

[0077] Preferably, the linkage between the globally monotonically increasing logical sequence number and the slot availability verification and backpressure control mechanism in step 1 is implemented as follows: Before generating a new logical sequence number, the availability of the target slot is verified based on the latest logical sequence number value. The availability verification is based on the consumer fence sequence number, which represents the maximum logical sequence number that has completed the entire consumption push in the circular buffer. The verification logic is as follows: First, the target incremental sequence number to be generated is calculated based on the latest logical sequence number value and the requested step size. Then, the wraparound position sequence number is calculated by the difference between the target incremental sequence number and the fixed total capacity of the circular buffer. The wraparound position sequence number is compared with the consumer fence sequence number. Only when the wraparound position sequence number is less than or equal to the consumer fence sequence number is the target slot determined to be available, allowing subsequent comparisons and the exchange of atomic operations and the generation of a new logical sequence number to be performed. If the wraparound position sequence number is greater than the consumer fence sequence number, the target slot is determined to be unavailable, the current sequence number application process is terminated, no new logical sequence number is generated, and the corresponding degradation processing process is triggered. This linkage mechanism makes the globally monotonically increasing logical sequence number the core carrier of backpressure control. By verifying the availability before the sequence number is generated, it avoids the problem of unconsumed message events being overwritten by new messages from the root. At the same time, it provides a precise sequence number benchmark for the system's adaptive backpressure adjustment, ensuring the integrity of message processing and the stability of the system in high-concurrency scenarios.

[0078] Preferably, the batch publishing adaptation mechanism for globally monotonically increasing logical sequence numbers in step 1 is implemented as follows: For batch message publishing needs in high-concurrency scenarios, a corresponding batch increment rule is configured for the generation of logical sequence numbers. The rule specifies that when a producer thread needs to publish multiple messages at once, it can apply for an increment step consistent with the number of messages to be published. Through a single comparison and exchange atomic operation, the core sequence number variable is updated in batches, thereby generating a continuous, globally monotonically increasing logical sequence number range. All sequence numbers within this range maintain a strict monotonically increasing characteristic, and the sequence numbers within the range are globally unique, without overlapping or conflicting with logical sequence numbers generated by other producer threads. The producer thread can use this continuous sequence number range to complete slot positioning and data filling operations for multiple messages at once. This batch adaptation mechanism significantly reduces the number of comparison and exchange atomic operations executed in high-concurrency batch publishing scenarios, reduces the overall overhead of sequence number application, and ensures the consistency of the publishing order and consumption order of batch messages through the continuous logical sequence number range, adapting to the ordered distribution requirements of batch messages in instant messaging systems.

[0079] Preferably, the implementation process of the consistency guarantee and operation status monitoring mechanism for the globally monotonically increasing logical sequence number in step 1 is as follows: For abnormal scenarios such as thread interruption and spin retry exceeding limits that may occur during the sequence number application process, corresponding consistency guarantee rules are configured for the generation of logical sequence numbers. The rules clearly state that a corresponding logical sequence number will only be generated after the comparison and exchange atomic operation is successfully executed and the core sequence number variable has completed a deterministic numerical update. In any abnormal scenario, as long as the value of the core sequence number variable has not been successfully updated, a new logical sequence number will not be generated, nor will the value of the already generated logical sequence number be modified. This ensures that the globally monotonically increasing characteristic of the logical sequence number is not destroyed in abnormal scenarios, avoiding problems such as sequence number confusion, duplication, and loss. Simultaneously, based on the numerical change of the globally monotonically increasing logical sequence number, a monitoring benchmark for the system's operation status is established. The message production throughput of the system is statistically analyzed through the increment rate of the logical sequence number, and the number of messages waiting to be consumed in the circular buffer is statistically analyzed through the difference between the latest logical sequence number and the consumer barrier sequence number, providing accurate numerical basis for system performance monitoring, load warning, and optimization adjustments.

[0080] Optionally, when the multiple hardware processor cores concurrently access the message to be pushed, each hardware processor core uses the bit-AND addressing conversion logic to map the target incremental sequence number to the corresponding physical storage index in real time in order to locate the message event object in the lock-free object pool in the memory space.

[0081] Preferably, the pre-triggering condition and input benchmark binding process for the mapping operation from the target incremental sequence number to the physical storage index in step 2 is as follows: The execution timing of this mapping operation is strictly limited to after the corresponding hardware processor core has successfully completed the numerical update of the core sequence number variable and locked the globally unique target incremental sequence number through hardware instruction-level comparison and exchange atomic logic, and before the service payload filling operation of the message to be pushed. The input benchmark for the mapping operation is the locked target incremental sequence number, which is generated entirely based on the update result of the core sequence number variable, possessing global uniqueness and strict monotonically increasing characteristics, and there is no duplication or overlap with the sequence number locked by other hardware processor cores; the execution carrier of the mapping operation is the bit-address conversion logic configured in step 1, which has been pre-adapted to the fixed total capacity of the circular buffer and has a built-in index mask corresponding to the fixed total capacity of the circular buffer, providing a stable and unified operation benchmark for the entire mapping process, ensuring that the mapping operations executed by different hardware processor cores follow completely consistent operation rules.

[0082] Preferably, the core mapping operation of the bitwise AND addressing conversion logic for the target increment number in step 2 is as follows: After receiving the target increment number, the bitwise AND addressing conversion logic performs a bitwise AND operation on the target increment number and the pre-generated index mask. The result of the operation is the physical storage index corresponding to the target increment number. The index mask value is the fixed total capacity of the circular buffer minus 1. Because the fixed total capacity of the circular buffer strictly follows the power of 2 rule, the binary representation of the index mask is all low bits set to 1 and all high bits set to 0. The core function of the bitwise AND operation is to retain the low-order effective bits of the target increment number, directly obtaining the physical storage index falling within the effective index range of the circular buffer. This operation process differs from the traditional modulo operation, requiring only a single clock cycle to complete all operations, eliminating the overhead of complex division operations. Furthermore, the entire operation is a stateless, pure numerical operation, without modifying any global variables or generating race conditions between threads, providing a lock-free, low-latency operational foundation for the concurrent execution of multiple hardware processor cores.

[0083] Preferably, the linkage positioning process between the physical storage index and the lock-free object pool storage structure in step 2 is as follows: After obtaining the physical storage index through bitwise AND operations, based on the continuous physical memory array structure of the lock-free object pool, the physical storage index is directly mapped to the array subscript position. This subscript position uniquely corresponds to a message event object cell within the lock-free object pool. During the initialization phase, the lock-free object pool has created message event object cells in the continuous physical memory space, with the number of cells matching the fixed total capacity of the circular buffer. All cells are arranged continuously according to the order of the physical storage index, forming a fixed-length array structure. The array subscript and the physical storage index form a one-to-one mapping relationship, with no misalignment or offset. The process of locating the message event object cell through the physical storage index only requires a single direct access to the memory address through the array subscript, without traversal or search operations. The access time is fixed and unaffected by the size of the circular buffer. At the same time, the continuous physical memory arrangement can significantly improve the CPU cache hit rate, further reducing memory access overhead in concurrent scenarios.

[0084] Preferably, the conflict-free security mechanism in step 2 for concurrent addressing scenarios involving multiple hardware processor cores is implemented as follows: In scenarios where multiple hardware processor cores execute producer threads in parallel and concurrently access messages to be pushed, the sequence number locking and mapping operations performed by each hardware processor core inherently possess the characteristic of being globally conflict-free. The core basis of this characteristic lies in the fact that the target incremental sequence number used for mapping by each hardware processor core is globally uniquely locked through comparison and exchange atomic logic. Different hardware processor cores cannot lock the same target incremental sequence number, and the operation rules of the bit and address conversion logic have global consistency. Different target incremental sequence numbers are either mapped to different physical storage indices or mapped to physical storage indices that have been consumed and are in a reusable state during sequence number wrap-around. There will be no situation where multiple hardware processor cores simultaneously map to the same message event object cell that is in use. Meanwhile, the bitwise addressing conversion logic does not involve any modification of shared variables. Multiple hardware processor cores can execute mapping operations in parallel without any interference between them. There is no need for concurrency control through lock mechanisms, which completely eliminates lock contention and thread context switching overhead in the concurrent addressing process, making it suitable for the concurrent injection of massive messages in high-concurrency instant messaging scenarios.

[0085] Preferably, the address wraparound adaptation and availability linkage mechanism in the circular buffer cyclic reuse scenario in step 2 is implemented as follows: The bitwise AND addressing conversion logic, through the characteristics of bitwise AND operations, naturally adapts to the cyclic reuse characteristics of the circular buffer, and can stably map the globally monotonically infinitely increasing target increment sequence number to the physical storage index within a fixed range of the circular buffer. When the value of the target increment sequence number exceeds the fixed total capacity of the circular buffer, the bitwise AND operation automatically truncates the high-order bits of the target increment sequence number, retaining only the low-order valid bits, and remaps the out-of-range sequence number to the valid physical storage index at the beginning of the circular buffer, realizing automatic sequence number wraparound and preventing the index out-of-bounds problem. Meanwhile, this mapping process forms a complete functional linkage with the pre-set slot availability verification mechanism. Before the hardware processor core locks the target incremental sequence number, the availability verification of the target slot has been completed through the consumer fence sequence number. This ensures that the message event object slot corresponding to the physical storage index mapped by the target incremental sequence number has completed the full-process consumption push and is in a reusable state. There will be no problem of new messages overwriting unconsumed messages. This achieves both the cyclic reuse of the circular buffer slot and ensures the integrity of message processing.

[0086] Preferably, the final location and status verification process of the message event object in step 2 is as follows: After locating the corresponding message event object cell through the physical storage index, the pre-allocated message event object within that cell is directly extracted. Simultaneously, a status validity verification is performed on the message event object. The verification includes whether the object is a valid instance pre-allocated during the initialization phase, whether the object is in a populateable initial state, and whether the object's reference fields have undergone post-consumption cleanup. Only when the status validity verification passes is the message event object determined as the target for filling the business payload of the message to be pushed, for use in subsequent business payload overlay filling operations. If the verification fails, the message publishing process is terminated, the corresponding exception log is recorded, and the corresponding sequence number release and retry process is triggered. This location and verification process, together with the pre-allocation and circular reuse mechanism of the lock-free object pool, forms a complete functional closed loop, ensuring that the located message event object is always valid and reusable. Furthermore, it eliminates the need to create new object instances at runtime; message filling can be completed simply by modifying the field references within the object, fundamentally reducing runtime object creation overhead and lowering garbage collection pressure.

[0087] Preferably, the continuous addressing adaptation optimization process in step 2 for batch message publishing scenarios is as follows: For batch message publishing requirements in high-concurrency scenarios, the bit-AND addressing conversion logic supports batch mapping processing of continuous target incremental sequence number intervals. When the hardware processor core locks a continuous target incremental sequence number interval through a single comparison and swap atomic operation, the bit-AND addressing conversion logic can complete the mapping operation of the entire interval sequence number in one go based on the starting value and length of the sequence number interval, obtaining the corresponding physical storage index interval. If the sequence number interval does not wrap around, a continuous physical storage index interval is obtained; if the sequence number interval wraps around, it is split into two continuous physical storage index intervals. Based on the physical storage index obtained from the batch mapping, multiple consecutive message event object cells can be located at once, completing the batch message filling operation, significantly reducing the number of mapping operations. Simultaneously, the continuous physical storage index can fully utilize the spatial locality characteristic of the CPU cache, improving the memory access efficiency of the batch message filling process, and further enhancing the system's throughput in batch message publishing scenarios.

[0088] Preferably, the addressing fault tolerance and boundary protection mechanism in step 2 under abnormal scenarios is implemented as follows: Before and after the bitwise addressing conversion logic performs the mapping operation, a two-layer boundary verification rule is set to ensure the security and stability of the addressing process. The first layer is the input validity verification before the operation, verifying whether the target increment sequence number is a valid sequence number successfully locked through the comparison and swap atomic operation, and verifying whether the sequence number value conforms to the globally monotonically increasing rule. If the input sequence number is invalid, the mapping operation is terminated directly, and an abnormal result is returned. The second layer is the index range verification after the operation, verifying whether the physical storage index obtained by mapping is within the valid range of 0 to the fixed total capacity of the circular buffer minus 1. If the index exceeds the valid range, the subsequent object location operation is terminated, and the abnormal information is recorded. Simultaneously, a corresponding fault isolation mechanism is set up for abnormal situations occurring during the addressing process. An addressing abnormality in a single hardware processor core will not affect the normal operation of other producer threads, nor will it damage the storage structure of the lock-free object pool, ensuring the stable operation of the system under high concurrency scenarios.

[0089] Optionally, the service payload carried by the message to be pushed is overwritten and filled into the message event object cell pointed to by the physical storage index.

[0090] Preferably, the pre-triggering condition and input benchmark binding process for the business payload coverage filling operation in step 2 is as follows: the execution timing of this filling operation is strictly limited to after the corresponding hardware processor core completes the accurate positioning of the message event object through bit and address conversion logic and completes the state validity verification of the message event object, and before the state transition operation of the message event object. The core input benchmark for the filling operation includes three parts: first, the business payload carried by the message to be pushed, which covers the complete content such as the core data of the message body, the target receiving end information, and the message timing metadata; second, the message event object cell located by the physical storage index and in a fillable state, which contains the message event object instance pre-allocated during the initialization phase; and third, a globally unique target incremental sequence number bound to this message publication, which forms a one-to-one mapping relationship with the message event object cell. Through the strong binding of the input benchmark, it is ensured that the target object of the filling operation is completely matched with the message to be published, and there will be no problems of sequence number misalignment or object mismatch, thus establishing an accurate data foundation for subsequent message publication and consumption.

[0091] Preferably, the core execution logic and object field adaptation process of the business payload overwrite and filling in step 2 are as follows: The message event object pre-allocated in the message event object grid has a standardized field storage structure preset during the initialization phase. This structure includes four core modules: business payload storage field, target channel identifier field, message sequence number association field, and lifecycle status flag field. All fields are repeatedly writable reference type fields, and the memory address and overall structure of the object will not change due to repeated writing. The core execution logic of the overwrite and filling operation is to directly write the business payload carried by the message to be pushed into the business payload storage field of the message event object, and at the same time, write the metadata such as the target channel identifier and the bound target incremental sequence number corresponding to the message into the corresponding association field. The whole process only modifies the field references inside the message event object, does not create new object instances, and does not change the memory arrangement of the message event object in the lock-free object pool. This filling method is different from the traditional solution's processing mode of creating a new object for each message, fundamentally reducing the runtime object creation overhead, reducing the garbage collection frequency and pause time, and adapting to the continuous injection requirements of massive messages in high-concurrency instant messaging scenarios.

[0092] Preferably, the conflict-free security mechanism in step 2 for concurrent filling scenarios involving multiple hardware processor cores is implemented as follows: In scenarios where multiple hardware processor cores execute producer threads in parallel and concurrently access messages to be pushed, the filling operation inherently possesses a globally conflict-free security characteristic. The core basis of this characteristic lies in the fact that the target increment sequence number corresponding to each filling operation is globally uniquely locked through hardware instruction-level comparison and exchange atomic logic. Different hardware processor cores cannot lock the same target increment sequence number, and the corresponding physical storage index and message event object cell also possess global uniqueness. This prevents multiple threads from simultaneously operating on the same message event object cell in a pre-allocated state. Furthermore, the execution scope of the filling operation is strictly limited to the cell corresponding to the sequence number locked by the current producer thread. It only modifies the internal fields of the message event object within the current cell, without modifying the content of other cells or any globally shared variables. The entire filling process does not require concurrent control through a locking mechanism, avoiding thread race conditions and context switching overhead, thus completely eliminating the lock contention bottleneck in concurrent filling scenarios.

[0093] Preferably, the linkage and adaptation process between the business payload overwrite operation and the lock-free object pool cyclic reuse mechanism in step 2 is as follows: The target message event object of the overwrite operation is a reusable object in the lock-free object pool that has completed the previous round of full-process consumption and push and performed a reference cleanup operation. All field references in this object have been completely cleared, and it is in an initial fillable state with no residual data from the previous round of messages. After the overwrite operation is completed, the message event object will transition from the fillable state to the pre-reservation completed state. After the subsequent release ready mark is completed, it will enter the consumption processing flow. When the message event corresponding to this message event object completes the full-process consumption and push, the field reference cleanup operation will be performed again to clear all the content written in this overwrite, returning to the reusable state and waiting for the next round of overwrite. This linkage mechanism of overlay filling and circular reuse allows a single message event object to be reused an infinite number of times along with the sequence number of the circular buffer. It is created only once during the system initialization phase throughout its entire lifecycle, and no new object instance needs to be created during runtime. This completely solves the garbage collection pressure problem caused by high-frequency object creation in traditional solutions, and ensures low latency and high stability of message push in high-concurrency scenarios.

[0094] Preferably, the continuous overwrite and fill optimization mechanism in step 2 for batch message publishing scenarios is implemented as follows: For batch message publishing requirements in high-concurrency scenarios, the fill operation supports batch overwrite and fill processing for messages with consecutive sequence number ranges. When the producer thread locks a continuous target incremental sequence number range through a single comparison and exchange atomic operation, and obtains the corresponding continuous physical storage index range through bitwise AND addressing conversion logic, it can perform a batch fill operation. Following the monotonically increasing sequence number order, the business payload and corresponding metadata of the batch messages to be pushed are sequentially filled into the corresponding sequence number message event object cells. Continuous physical storage indexes can fully utilize the spatial locality characteristic of CPU cache, allowing consecutively arranged message event objects to be loaded into the CPU cache in batches, significantly reducing the number of memory accesses and latency. Simultaneously, the batch fill operation only needs to perform a unified state verification and metadata association operation once, reducing the repetitive overhead of filling a single message and significantly improving the system's throughput in batch message publishing scenarios.

[0095] Preferably, the integrity verification and data consistency guarantee mechanism for business payload overlay filling in step 2 is implemented as follows: After the overlay filling operation is completed, the filling integrity and consistency verification will be performed immediately. The verification content includes three core dimensions: First, business payload write integrity verification, confirming that the content in the business payload storage field is completely consistent with the original business payload of the message to be pushed, without any data truncation, disorder, or loss; Second, metadata matching verification, confirming that the content in the target channel identifier and message sequence number association fields is completely matched with the current message to be pushed and the locked target incremental sequence number, ensuring a one-to-one correspondence between the message, sequence number, and object; Third, field format compliance verification, confirming that the format of all written content conforms to the preset specification requirements and will not have an abnormal impact on the subsequent consumption processing flow. Only when all validation items pass is the filling operation officially confirmed as complete, allowing subsequent state transition operations to proceed. If validation fails, a field rollback operation is immediately executed, clearing all field references written this time, restoring the message event object to its reusable state before filling, recording an exception log, and triggering the corresponding message retry process. This fundamentally eliminates the problems of message data corruption and sequence number mismatch, ensuring the accuracy of message distribution.

[0096] Preferably, the fault tolerance and isolation mechanism for abnormal scenarios in step 2 of business payload overlay filling is implemented as follows: Complete fault tolerance and isolation rules are set up to address various abnormal scenarios that may occur during the filling process, such as abnormal business payload format, abnormal object memory access, and thread interruption. When an abnormal situation is detected during the filling process, the current filling operation is immediately terminated, and field cleanup and state rollback operations are performed immediately to ensure that the target message event object cell is not contaminated by abnormal data and always maintains a reusable clean state. Simultaneously, the currently locked target incremental sequence number is released, and the cell corresponding to that sequence number is re-included in the available resource pool, allowing other producer threads to re-apply for its use. This mechanism ensures that a single thread's filling anomaly will not affect the normal operation of other producer threads, nor will it disrupt the overall storage structure of the lock-free object pool and the sequence number allocation rules of the circular buffer. It achieves fault isolation under abnormal scenarios, ensuring the stable operation of the system in high-concurrency scenarios and preventing the entire message production process from being interrupted due to a single message's filling anomaly.

[0097] Optionally, the filled message event object is transitioned from the request pre-occupancy state to the release ready state, and then a ready message event marked as consuming is generated in the circular buffer.

[0098] Preferably, the pre-triggering conditions and full lifecycle state rule definition process for the state transition operation of the message event object in step 2 are as follows: the execution timing of this state transition operation is strictly limited to after the business payload of the message to be pushed has been fully covered and filled, and all filling integrity and data consistency checks have passed, but before the ready message event is generated. First, standardized state transition rules are defined for the message event object throughout its lifecycle, clarifying that the message event object includes four mutually exclusive lifecycle states: reusable state, application pre-occupancy state, release ready state, and consumption completed state. The reusable state is the initial state after the object has completed consumption cleanup, representing that the object slot can be re-applied for; the application pre-occupancy state is the state entered after the target incremental sequence number is locked and the message event object is located, and the business payload coverage and filling operation can only be performed in this state; the release ready state is the state entered after the filling check is completed, representing that the message data in the object has completed all pre-release preparations; the consumption completed state is the state entered after the message has been consumed and processed, waiting to return to the reusable state after cleanup. This state rule defines a one-way, irreversible flow path, ensuring that each state transition has clear preconditions and corresponding business actions, thus establishing a rigorous execution benchmark for subsequent state transitions and the generation of ready message events.

[0099] Preferably, the core flow execution and atomicity guarantee mechanism implementation process of the message event object from the request pre-occupancy state to the release ready state in step 2 is as follows: The core execution action of the state flow is to update the lifecycle state flag field encapsulated inside the message event object, changing the field value from the flag corresponding to the request pre-occupancy state to the flag corresponding to the release ready state. This state update operation must be executed through hardware instruction-level comparison and exchange atomic logic. Before execution, it is first checked whether the current state flag field is the expected request pre-occupancy state. The state update is only executed if the check passes; if the check fails, the flow operation is terminated, thereby ensuring the atomicity and uniqueness of the state update operation. The entire state update process is a single-instruction atomic operation, which will not be interrupted by thread scheduling and will not cause race conditions due to concurrent modification by multiple threads. This completely avoids the problems of state confusion and repeated updates in concurrent scenarios. At the same time, the state update operation only modifies the state flag field within the current message event object and will not change the object's memory address or business payload data, ensuring the integrity and consistency of message data during the state flow process.

[0100] Preferably, the conflict-free security mechanism for state transition in multi-hardware processor core concurrent scenarios in step 2 is implemented as follows: In scenarios where multiple hardware processor cores execute producer threads in parallel and concurrently process messages to be pushed, state transition operations naturally possess the global conflict-free security characteristic. The core basis of this characteristic lies in the fact that each message event object is strongly bound to a globally unique target increment sequence number. This target increment sequence number can only be globally locked through atomic logic of comparison and exchange. Only the producer thread that successfully locks this sequence number has the permission to execute the state update operation of the corresponding message event object; other threads cannot modify the state flag field of this object. Simultaneously, the scope of each producer thread's state transition operation is strictly limited to the message event object corresponding to its locked sequence number. It will not modify the state of other objects or any globally shared variables. The entire transition process does not require concurrency control through mutex locks, and will not generate race conditions or context switching overhead between threads. This completely eliminates the lock contention bottleneck in state transitions under high concurrency scenarios, adapting to the business scenario requirements of massive message concurrent injection.

[0101] Preferably, the process of transitioning from the publish-ready state to the consumeable state and the final generation of ready message events in step 2 is as follows: After a message event object completes its state transition and enters the publish-ready state, the marking of the consumeable state and the generation of ready message events are completed synchronously based on the sequence number ordering rules of the circular buffer. First, a publishable sequence number upper limit marker linked to the core sequence number variable is maintained for the circular buffer. This marker represents the maximum logical sequence number within the current circular buffer that has completed all publish preparations and can be read by consumers. Only when all consecutive sequence numbers corresponding to message event objects before the target incremental sequence number have completed the transition from the request pre-occupancy state to the publish-ready state will the publishable sequence number upper limit marker be updated to the current maximum ready sequence number, thereby avoiding sequence number gaps and ensuring the orderliness of message consumption. After the publishable sequence number upper limit marker is updated, all message event objects within the upper limit range that are in the publish-ready state officially become ready message events marked as consumeable, completing the entire ready message event generation process. The generated ready message events are fully visible to downstream event handlers and can be batch-fetched and consumed.

[0102] Preferably, the implementation process of the global visibility guarantee and event handler listening linkage mechanism for ready message events in step 2 is as follows: During the generation of ready message events, the updates of all status flag fields and the updates of the published sequence number upper limit flag follow the multi-threaded memory visibility rules, ensuring that the status update and sequence number upper limit update completed by any hardware processor core can be observed in real time by all other hardware processor cores, especially the core running the event handler. This mechanism forms a complete functional linkage with the event handler polling and listening logic in the downstream step 3. The event handler continuously polls and reads the published sequence number upper limit flag, compares it with the currently consumed sequence number, and when it finds that the published sequence number upper limit is greater than the consumed sequence number, it can determine that there is a newly generated ready message event, and then pull all ready message events within the sequence number range in batches. At the same time, the business payload, target channel identifier, and status flag in the generated ready message event are all in a read-only state. The event handler can only perform read operations and cannot modify the content, ensuring the data consistency of the ready message event during the consumption process and preventing secondary modification by the producer thread.

[0103] Preferably, the optimization mechanism for state transition and batch generation of ready message events in the batch message publishing scenario in step 2 is implemented as follows: For batch message publishing requirements in high-concurrency scenarios, state transition and ready message event generation support a batch optimization processing mode. When the producer thread locks a continuous target incremental sequence number range through a single comparison and exchange atomic operation, and completes the business load coverage filling and integrity verification of all message event objects within the range, it will sequentially execute the state transition operation of each message event object according to the monotonically increasing logical sequence number, uniformly transitioning it from the request pre-occupancy state to the publish ready state. The core optimization in the batch scenario lies in the fact that only after all message event objects within the entire continuous sequence number range have completed their state transitions will the published sequence number upper limit marker be updated all at once, generating all ready message events within the corresponding range at once. This significantly reduces the number of updates to the published sequence number upper limit marker and lowers the cache synchronization overhead between multiple cores. Meanwhile, the message event objects corresponding to consecutive sequence numbers are arranged in a continuous physical memory within the lock-free object pool. Batch state transition operations can make full use of the spatial locality characteristics of CPU cache, loading consecutive objects into the high-speed cache in batches, which significantly improves the execution efficiency of batch processing. Furthermore, the batch-generated ready message events maintain a strict sequence number increment order, ensuring message timing consistency during consumption and adapting to the orderly distribution requirements of batch messages in instant messaging scenarios.

[0104] Preferably, the fault tolerance and isolation mechanism for abnormal scenarios in the state transition and ready message event generation process in step 2 is implemented as follows: Complete fault tolerance and isolation rules are set up to address various abnormal scenarios that may occur during the state transition process, such as atomic operation failures, thread interruptions, and data verification anomalies. When an abnormal situation is detected during the state transition, the current state transition and ready message event generation operation will be immediately terminated. State rollback processing will be performed immediately, rolling the target message event object from the pre-reservation state to the reusable state. Simultaneously, all business payloads and metadata currently filled into the object will be cleared to ensure that the object's cell is not contaminated by abnormal data. The locked target incremental sequence number will be released synchronously, and the cell corresponding to that sequence number will be re-included in the available resource pool, allowing other producer threads to re-request its use. This mechanism ensures that an abnormal state transition of a single message will not affect the normal operation of other producer threads, nor will it disrupt the sequence number allocation rules of the circular buffer or the overall storage structure of the lock-free object pool. It achieves fault isolation in abnormal scenarios, preventing the entire message production process from being interrupted due to an abnormal processing of a single message. At the same time, all abnormal situations will be recorded synchronously with their corresponding sequence number, triggering thread, and exception type, which will facilitate subsequent problem location and investigation, and trigger the corresponding message retry process to ensure that message data is not lost.

[0105] Optionally, each of the hardware processor cores reads the current logical sequence number from the atomic sequence number generator as the expected value, and attempts to perform a numerical update on the core sequence number variable using hardware instruction-level comparison and exchange atomic logic to lock the target incremental sequence number.

[0106] Preferably, the pre-triggering condition and execution benchmark binding process of the sequence number locking operation based on the comparison and exchange atomic logic in step 2 is as follows: the execution timing of this sequence number locking operation is strictly limited to after the producer thread running on the corresponding hardware processor core receives the message to be pushed and completes the pre-slot availability check, and before the message event object positioning and business payload filling operations. The core execution benchmark of the operation is strongly bound to the core sequence number variable encapsulated inside the atomic sequence number generator. The core sequence number variable has completed the cache line filling process and can independently occupy a complete hardware cache line, eliminating the access latency caused by false sharing interference and providing a stable hardware access foundation for high-frequency concurrent read and update operations. At the same time, the pre-slot availability check needs to be completed before the operation is executed. Based on the consumer fence sequence number and the fixed total capacity of the circular buffer, it is confirmed that the message event object slot corresponding to the sequence number to be applied for is in a reusable state. Only after the check passes will the subsequent sequence number reading and atomic update operations be started, thus avoiding invalid sequence number applications and resource occupation from the root.

[0107] Preferably, the process of reading the current logical sequence number and determining the expected value benchmark in step 2 is as follows: The hardware processor core reads the current value of the core sequence number variable through the read-only access interface preset by the atomic sequence number generator. This value is the current globally monotonically increasing logical sequence number. Simultaneously, the read logical sequence number is determined as the expected value benchmark for subsequent comparison and exchange atomic operations. The core sequence number variable follows the multi-threaded memory visibility rules, ensuring that any update to the core sequence number variable by any hardware processor core can be observed instantly by all other hardware processor cores through the read-only access interface. This guarantees that the read logical sequence number is always the latest global value, preventing the reading of outdated values. Furthermore, the read operation can only be performed through the standardized read-only interface of the atomic sequence number generator, and the value of the core sequence number variable cannot be directly modified, ensuring the readability and accuracy of the expected value benchmark and providing a reliable numerical benchmark for subsequent atomic comparison operations.

[0108] Preferably, the core execution mechanism and atomicity guarantee process of the hardware instruction-level comparison and exchange atomic logic in step 2 are as follows: the comparison and exchange atomic logic is a native atomic operation at the hardware instruction level. The entire operation process is directly guaranteed to be atomic by the CPU hardware instruction, and will not be interrupted by the thread scheduling mechanism, nor will there be race conditions for concurrent modification by multiple threads. Concurrency control through mutex locks at the operating system level is not required. This atomic operation contains three core execution elements: first, the memory address corresponding to the core sequence number variable, which serves as the target memory location of the operation; second, the pre-read current logical sequence number, which serves as the expected value for numerical comparison; and third, the update target value calculated based on the expected value. In the scenario of a single message publication, the update target value is the expected value plus 1, which is the target increment sequence number to be locked. The core execution logic of the operation is: atomically compare the current actual value in the memory address of the core sequence number variable with the expected value. If the two are completely equal, the value of the core sequence number variable is atomically updated to the target value, and the operation is judged to be successful; if the two are not equal, no numerical update operation is performed, and the operation is judged to be unsuccessful. This mechanism completely eliminates the overhead of kernel-mode and user-mode switching, thread context switching, and lock contention bottlenecks caused by traditional mutex locks, and is suitable for the concurrent sequence number application requirements of massive messages in high-concurrency instant messaging scenarios.

[0109] Preferably, the target increment sequence number locking and state binding process after the successful execution of the comparison and exchange atomic operation in step 2 is as follows: After the successful execution of the comparison and exchange atomic operation, the value of the core sequence number variable has been atomically updated, and the expected value before the update is the globally unique target increment sequence number successfully locked this time. The target increment sequence number forms a one-to-one strong binding relationship with the message to be pushed this time, and at the same time forms a unique mapping with the corresponding message event object cell in the circular buffer. The producer thread changes the life cycle state of the message event object corresponding to the sequence number from the reusable state to the request pre-occupancy state, marking that the cell has been locked by the current thread, and other threads can no longer perform request or modification operations on the cell corresponding to the sequence number. At the same time, the locked target increment sequence number will serve as the unique input benchmark for subsequent bit and address conversion logic, used to map to obtain the corresponding physical storage index, complete the subsequent message event object positioning and business payload filling operations, and form a complete closed loop from sequence number locking to message filling.

[0110] Preferably, the conflict-free guarantee and spin retry optimization mechanism in step 2 for concurrent sequence number application scenarios of multiple hardware processor cores is implemented as follows: In scenarios where multiple hardware processor cores execute producer threads in parallel and concurrently apply for sequence numbers, the comparison and exchange atomic logic naturally possesses the safety characteristic of global conflict-free operation. Since the value update of the core sequence number variable is an atomic operation, only one hardware processor core's comparison and exchange operation can be successfully executed at any given time, completing the sequence number locking. All other concurrently executed operations will fail due to the mismatch between the expected value and the actual value, preventing multiple threads from locking the same target incremental sequence number. This ensures the global uniqueness and conflict-free nature of sequence number allocation at the hardware level. For scenarios where operations fail, a corresponding spin retry optimization mechanism is configured. After an operation fails, the thread will immediately reread the latest current value of the core sequence number variable through the read-only access interface, update the expected value, and then perform the comparison and swap atomic operation again, forming a spin loop. At the same time, an upper limit threshold is set for the number of consecutive retries in the spin loop. When the number of consecutive spin retries in a single sequence number application exceeds this upper limit threshold, a thread yielding operation will be triggered, allowing the current thread to temporarily relinquish hardware computing resources. This avoids the problem of a single thread occupying hardware resources for a long time in extreme concurrency scenarios, causing other producer threads to wait for a long time in sequence number applications. This balances the efficiency of sequence number application in high-concurrency scenarios with the relative fairness of thread scheduling.

[0111] Preferably, the sequence number locking adaptation optimization mechanism in step 2 for batch message publishing scenarios is implemented as follows: For batch message publishing requirements in high-concurrency scenarios, the comparison and exchange atomic logic supports batch locking adaptation for continuous sequence number ranges. When the producer thread needs to publish multiple messages at once, it can determine the sequence number increment step based on the number of messages to be published, set the update target value to the expected value read plus the number of messages to be published, and complete the batch update of the core sequence number variable through a single comparison and exchange atomic operation, thereby locking a continuous, globally unique target increment sequence number range. All sequence numbers within this range maintain a strict monotonically increasing characteristic, and the range is globally unique, without overlapping or conflicting with sequence numbers locked by other threads. Based on this continuous sequence number range, the producer thread can complete the message event object grid locking, address mapping, and business payload filling operations for multiple messages at once. This batch adaptation mechanism significantly reduces the number of comparison and exchange atomic operations in high-concurrency batch publishing scenarios, reduces the overall overhead of sequence number allocation, and at the same time, continuous target incremental sequence numbers can make full use of the spatial locality characteristics of CPU cache, improve the memory access efficiency of subsequent batch message filling processes, and further enhance the system's throughput in batch message publishing scenarios.

[0112] Preferably, the fault tolerance and isolation mechanism for the sequence number locking operation in step 2 is implemented as follows: Complete fault tolerance and isolation rules are set up to address various abnormal scenarios that may occur during the sequence number locking process, such as spin retry exceeding limits, thread interruption, and slot availability status changes. When an abnormal condition is triggered during the sequence number application process, the current sequence number locking operation is immediately terminated. If the sequence number locking has been completed through a comparison and exchange operation, the corresponding sequence number release operation is executed, atomically rolling back the value of the core sequence number variable to its state before the operation. Simultaneously, the message event object slot corresponding to the sequence number is rolled back from the pre-reserved state to the reusable state, ensuring that the sequence number resource and object slot are not abnormally occupied and are reinstated into the available resource pool, allowing other producer threads to re-apply for use. This mechanism ensures that a sequence number locking anomaly in a single thread will not affect the normal operation of other producer threads, nor will it disrupt the numerical consistency of the core sequence number variable or the sequence number allocation rules of the circular buffer. It achieves fault isolation under abnormal scenarios, preventing the entire message production process from being interrupted due to a single message's sequence number application anomaly. At the same time, all abnormal situations will be recorded synchronously with their corresponding sequence number, triggering thread, and exception type, which will facilitate subsequent problem location and investigation, and trigger the corresponding message retry process to ensure that message data is not lost.

[0113] Preferably, the implementation process of the sequence number locking operation and the linkage adaptation mechanism of the entire business process in step 2 is as follows: As the core link of the entire message production process, the sequence number locking operation forms a deep linkage adaptation with the upstream and downstream business links. Upward, it links with the upstream slot availability verification and backpressure control mechanism. When the number of messages to be consumed in the circular buffer reaches a preset threshold, the execution frequency of the sequence number application operation will be limited, triggering the corresponding backpressure rate limiting strategy. The message injection rate is controlled from the sequence number allocation stage to avoid the overflow problem of the circular buffer. Downward, it links with the bit and address conversion logic, business payload filling, and state transition stages. The target incremental sequence number after locking is directly used as the input of the bit and address conversion logic to complete the accurate positioning of the message event object. At the same time, it serves as the globally unique identifier of the message, running through the entire lifecycle of message filling, publishing, consumption, and push, providing a unified identification benchmark for the orderly distribution of messages, anomaly tracing, and duplicate data filtering. This full-link linkage adaptation makes the sequence number locking operation the core hub connecting the entire process of message production, consumption, and push, ensuring the orderliness, accuracy, and stability of the entire batch message push method.

[0114] Optionally, an event handler is invoked to poll the upper limit of the published sequence number of the circular buffer and pull multiple ready message events injected and accumulated in parallel by the multiple hardware processor cores at once.

[0115] Preferably, the initialization of the event handler and the pre-baseline binding process for the polling listening operation in step 3 are as follows: The event handler is an asynchronous consumption processing execution unit independent of the producer thread. The start time of its polling listening operation is strictly limited to after the circular buffer, lock-free object pool, and atomic sequence number generator have completed full initialization, and the producer thread has started the ready message event generation process. The core baseline of the polling listening is strongly bound to the upper limit flag of the published sequence number maintained by the circular buffer. This upper limit flag is synchronously updated by the ready message event generation process in step 2 upstream, representing the maximum logical sequence number in the current circular buffer that has completed all publishing preparations and can be consumed and read. Simultaneously, the event handler maintains an independent consumed sequence number flag as the baseline value for polling comparison, thereby determining whether there are any newly added ready message events. This baseline binding mechanism ensures that the polling listening operation is executed entirely based on the upstream message publishing progress, preventing invalid empty polling and ensuring that generated ready message events are not missed, thus establishing a rigorous execution baseline for subsequent batch retrieval operations.

[0116] Preferably, the core execution mechanism for polling the upper limit of published sequence numbers in step 3 is implemented as follows: The event processor adopts a fixed-period circular polling mode, continuously reading the upper limit of published sequence numbers flag in the circular buffer, and simultaneously comparing the read upper limit of published sequence numbers with the internally maintained consumed sequence numbers in real time. The upper limit of published sequence numbers flag follows the multi-threaded memory visibility rules, ensuring that every update of the flag by the upstream producer thread can be observed by the event processor in real time during the polling process, without the problem of reading expired values. At the same time, an adaptive adjustment mechanism is configured for the polling mode. When multiple consecutive polling comparison results show no new ready message events, the polling cycle will be appropriately extended to reduce the ineffective occupation of CPU computing resources; when a new ready message event is detected and the number of message backlogs continues to rise, the polling cycle will be automatically shortened to improve the listening response speed, balancing resource utilization in low-load scenarios and message processing real-time performance in high-load scenarios, and adapting to the traffic fluctuation characteristics of instant messaging systems.

[0117] Preferably, the triggering condition and pull interval determination process for batch retrieval of ready message events in step 3 are as follows: When the event processor detects during the polling and comparison process that the upper limit of the published sequence number in the circular buffer is greater than the internally maintained consumed sequence number, it determines that there are newly added, consumeable ready message events and formally triggers the batch retrieval operation. The sequence number interval for batch retrieval is formed by taking the consumed sequence number as the starting boundary and the upper limit of the published sequence number as the ending boundary, forming a continuous, globally monotonically increasing logical sequence number interval. All message event objects corresponding to the sequence numbers within this interval have completed the transition from the request pre-occupancy state to the published ready state and have formally become ready message events marked as consumeable. This interval determination mechanism ensures that all ready message events retrieved in batches are valid data that have completed the publication preparation and will not retrieve messages that are not fully filled or whose state is not ready. At the same time, the continuous sequence number interval can make full use of the continuous memory arrangement characteristics of the circular buffer, providing the optimal execution basis for subsequent batch memory access and data reading.

[0118] Preferably, the core execution process of the one-time batch retrieval of ready message events in step 3 is as follows: Based on a defined continuous logical sequence number range, the event processor, following a monotonically increasing sequence number order, uses bitwise AND addressing conversion logic shared with the producer thread to map each logical sequence number within the range to its corresponding physical storage index in real time, thereby locating the corresponding message event object cell in the lock-free object pool. After locating, the event processor reads the complete content of all message event objects within the range, including business payload, target channel identifier, and sequence number associated metadata, in a batch, completing the batch retrieval of ready message events. During the retrieval process, the event processor only has read-only access to all ready message events and cannot modify the business data and status flags within the message event objects, completely avoiding the data race problem between the consumer thread and the producer thread. The entire batch retrieval process does not require concurrency control through mutex locks and does not generate thread context switching overhead, completely eliminating the lock contention bottleneck in the traditional consumption model and significantly improving message consumption efficiency in high-concurrency scenarios.

[0119] Preferably, the implementation process of the orderliness and conflict-free security guarantee mechanism for batch retrieval in the multi-hardware processor core parallel injection scenario in step 3 is as follows: For the scenario where multiple hardware processor cores run producer threads in parallel and concurrently inject messages to be pushed, the update of the upper limit of the published sequence number strictly follows the consecutive sequence number rule. Only after all message events corresponding to consecutive sequence numbers before the target incremental sequence number have completed the ready state transition will the upper limit of the published sequence number be updated to the current maximum value. This fundamentally avoids the problem of empty sequence numbers and ensures that the ready message events retrieved in batches always maintain a strict sequence number increment order, consistent with the global timing of message injection. At the same time, each ready message event is strongly bound to a globally unique logical sequence number. Ready message events generated by different producer threads will not have overlapping or conflicting sequence numbers. The batch retrieval operation of the event handler is only executed based on the globally unified sequence number range, and will not compete for resources with any producer thread, nor will it affect the message injection process of the producer thread. This achieves completely lock-free parallel execution of the production and consumption links, adapting to high-load business scenarios with massive concurrent message injection.

[0120] Preferably, the implementation process of the state update and full-link business linkage mechanism after the batch retrieval operation in step 3 is as follows: After the event handler completes the one-time batch retrieval of ready message events, it atomically updates the internally maintained consumed completion sequence number to the end boundary of the sequence number range of this retrieval, completing the state loop of this consumption retrieval process. The updated consumed completion sequence number is synchronously fed back to the slot reuse management module of the circular buffer, which is used to mark that the message event object with the corresponding sequence number has been consumed and read. After the reference cleanup is completed, it can be re-transferred to the reusable state for the producer thread to re-apply for use, realizing the circular reuse and full life cycle management of the circular buffer slots. At the same time, the ready message events obtained by batch retrieval are directly input into the downstream channel-based aggregation and classification logic, providing a complete data source for subsequent aggregation refresh data packet generation and message push operations, forming a full-link business loop from message production, consumption retrieval to aggregation push, ensuring the orderliness and continuity of the entire message batch push process.

[0121] Preferably, the fault tolerance and isolation mechanism for abnormal scenarios in step 3 during polling and batch retrieval is implemented as follows: Complete fault tolerance rules are set for various abnormal scenarios that may occur during polling, such as sequence number reading errors, object location failures, data reading errors, and thread interruptions during retrieval. When an error is detected during polling when the upper limit of published sequence numbers is read, the current polling comparison will be immediately terminated, the current consumed sequence number baseline will be retained, and the system will wait for the next polling cycle to reread the sequence number. Abnormal batch retrieval operations will not be executed. When an object location or data reading error is detected during batch retrieval, the message corresponding to the abnormal sequence number will be skipped, and the retrieval operation of other normal messages within the interval will continue. Simultaneously, the abnormal sequence number and error information will be recorded, preventing the entire batch retrieval process from being interrupted due to an error in a single message. This mechanism ensures that a single abnormal event will not affect the overall operation of the event handler, nor will it disrupt the sequence number management rules of the circular buffer or the storage structure of the lock-free object pool. It achieves fault isolation under abnormal scenarios, ensuring the continuous and stable operation of the system under high concurrency scenarios. Furthermore, the recording of the abnormal log provides complete data support for subsequent problem localization and investigation.

[0122] Optionally, the target channel identifier corresponding to the service payload in each ready message event is extracted, and aggregation and classification logic based on the channel dimension is executed to group and assemble multiple service payloads sent to the same network connection into a physical layer aggregate refresh data packet.

[0123] Preferably, the pre-triggering conditions and input benchmark binding process for the target channel identifier extraction and channel dimension aggregation and classification operations in step 3 are as follows: the execution timing of this series of operations is strictly limited to after the event processor completes a one-time batch retrieval of ready message events and all data integrity checks are passed, and before the aggregation and refresh data packet assembly operation. The core input benchmark for the operation is the complete set of ready message events in a consumable state obtained by the event processor in batch retrieval. Each ready message event contains four core data types: business payload bound to the message, target channel identifier, globally unique logical sequence number, and message time-series metadata. Among them, the target channel identifier forms a one-to-one strong binding relationship with the receiving end network connection, serving as the sole benchmark for subsequent aggregation and classification operations. At the same time, before the operation is executed, a pre-compliance check is performed on the batch-retrieved set of ready message events to filter out abnormal message events with abnormal status, missing business payloads, or invalid target channel identifiers. Only compliant and valid ready message events are retained to enter the subsequent identifier extraction and aggregation and classification process, ensuring the accuracy and validity of the data source for the aggregation operation from the root.

[0124] Preferably, the extraction and compliance verification process of the target channel identifier corresponding to the service payload in a ready message event is as follows: For each ready message event that passes the pre-verification, the target channel identifier strongly bound to the message service payload is extracted from the target channel identifier storage field of the message event object through a standardized read-only access interface. The extraction process has only read-only permissions and will not modify any data within the message event object, completely avoiding interference from the consumption stage to the production stage data. After extraction, multi-level compliance verification is performed on each target channel identifier. The first level is format compliance verification, confirming that the identifier conforms to the preset encoding specifications and there are no issues of format errors, truncation, or garbled characters. The second level is validity verification, confirming that the network connection corresponding to the identifier is in an active and available state and there are no cases of disconnection or failure. The third level is binding relationship verification, confirming that the target channel identifier and the receiving end information of the corresponding service payload are completely matched and there are no issues of identifier and payload mismatch. Only after all three layers of verification pass will the target channel identifier be bound to the corresponding business payload and global logical sequence number to form an aggregation unit, and enter the subsequent aggregation and classification process; message events that fail verification will be isolated separately, and after recording the abnormal information, they will enter the corresponding abnormal handling process, and will not participate in the normal aggregation and classification operation, thus ensuring the accuracy of the aggregation benchmark.

[0125] Preferably, the aggregation and classification logic based on the channel dimension adopts a key-value mapping classification execution mechanism. The verified target channel identifier is used as the unique classification key, and the aggregation unit, composed of the corresponding bound business payload, global logical sequence number, and time-series metadata, is used as the classification value to construct an aggregation mapping table at the channel dimension. The aggregation and classification operation is executed sequentially in a monotonically increasing order of the global logical sequence number of ready message events. For each aggregation unit, it first checks whether a classification key corresponding to the target channel identifier already exists in the aggregation mapping table. If not, a new classification entry corresponding to the target channel identifier is created in the aggregation mapping table, and the current aggregation unit is stored in the payload set of that entry. If it already exists, the current aggregation unit is directly appended to the end of the payload set of the corresponding classification entry. This ensures that all business payloads corresponding to the same target channel identifier are always arranged in an increasing order of the global logical sequence number, maintaining complete consistency with the global time sequence of message injection. This completely avoids the problem of message out-of-order delivery during the aggregation process, adapting to the core requirement of message time sequence consistency in instant messaging scenarios. Meanwhile, the aggregation and classification operation is executed entirely in the local memory of the event handler, without needing to access shared global variables or use mutex locks for concurrency control. It will not cause resource contention with the upstream producer thread or the downstream push execution thread, thus ensuring the execution efficiency of the aggregation and classification operation in high-concurrency scenarios.

[0126] Preferably, standardized grouping rules and batch optimization mechanisms are set for multiple service payloads with the same target channel identifier (i.e., destined for the same network connection). The grouping operation is performed independently on a per-category basis for each target channel identifier in the aggregation mapping table. The grouping rules are clear: all service payloads under the same category must be grouped in strictly ascending order of the global logical sequence number, and the order of the payloads cannot be adjusted. A continuity check is performed on the grouped service payloads; if a sequence number is discontinuous, a sequence number gap is marked and the corresponding missing sequence number information is recorded to ensure the temporal integrity of the grouped payload set. An adaptive batch threshold is set for the grouping operation. When the number of service payloads corresponding to the same target channel identifier reaches the preset batch threshold, the grouping operation for that entry is immediately completed, generating the corresponding payload grouping set. When the number of service payloads has not reached the batch threshold, but all ready message events retrieved in that batch have been aggregated and categorized, a final grouping operation is performed on all ungrouped category entries to ensure that all valid service payloads are grouped accordingly, preventing payload omissions. This grouping mechanism reduces the number of subsequent data packet assembly and network transmissions by batch grouping, solving the problem of excessively frequent system calls and low network I / O efficiency caused by sending data packet by packet in the background technology. It also takes into account the real-time nature of message push by adaptive threshold, avoiding message delays caused by waiting for batch thresholds in low-traffic scenarios.

[0127] Preferably, for each payload grouping set that has completed the grouping operation, a standardized assembly and encapsulation operation of the physical layer aggregated refresh data packet is performed. Each target channel identifier corresponds to an independent aggregated refresh data packet, and a one-to-one mapping relationship is formed between the data packet and the receiving end network connection. The assembly of the data packet strictly follows a preset standardized structure, consisting of three core parts: packet header, payload aggregate, and packet tail. The packet header encapsulates core metadata such as the target channel identifier, globally unique identifier of the data packet, payload quantity, timing interval, and data length, providing complete baseline information for downstream push execution and receiving end parsing. The payload aggregate is an ordered aggregate of all service payloads corresponding to the same network connection, which is continuously encapsulated in the order after grouping, retaining the complete content and corresponding sequence number of each service payload to ensure that the receiving end can accurately parse each independent message. The packet tail encapsulates data checksum, end identifier, and other content for downstream data integrity verification, preventing data packet tampering or truncation during transmission. After assembly, the aggregated refresh data packet undergoes integrity and compliance checks to confirm that the data packet structure is complete, the metadata and payload aggregate are fully matched, and the checksum verification is successful. Only when all checks pass will the data packet be marked as pushable and enter the subsequent batch refresh and push process. Data packets that fail the checks will be isolated and discarded, and the corresponding reassembly process will be triggered to record the abnormal information, ensuring the accuracy and availability of the assembled aggregated refresh data packet.

[0128] Preferably, for high-concurrency, high-traffic scenarios where the number of ready message events fetched in a single batch is enormous and the target channel identifiers have multiple dimensions, a multi-channel parallel aggregation optimization mechanism is configured. This mechanism breaks down the aggregation and data packet assembly operations into multiple parallel subtasks. Each subtask is responsible for processing a set of non-overlapping target channel identifiers corresponding to aggregation and assembly operations. These parallel subtasks are scheduled and executed based on the asynchronous execution pool of the event handler. The data processing scope of each subtask is completely isolated, preventing multiple subtasks from operating on the same target channel identifier simultaneously. This completely avoids data races and resource contention issues during parallel execution, eliminating the need for lock mechanisms for concurrency control and significantly improving the overall execution efficiency of aggregation operations in high-traffic scenarios. Meanwhile, dynamic scheduling rules are set for the parallel aggregation mechanism. Based on the total number of ready message events fetched in a single batch, the number of target channel identifiers, and the current system load, the number of parallel subtasks and the processing scope of each subtask are dynamically adjusted. When the system load is low and the total number of messages is large, the number of parallel subtasks is increased to improve processing speed; when the system load is high, the number of parallel subtasks is reduced to avoid excessive consumption of system computing resources, balancing processing efficiency and system stability. Furthermore, the aggregated refresh data packets assembled in parallel are uniformly collected according to the dimension of the target channel identifier, preventing data packet corruption or loss and ensuring data consistency after parallel processing.

[0129] Preferably, a complete fault tolerance and isolation mechanism is set up to address various abnormal scenarios that may occur throughout the entire process of identifier extraction, aggregation and classification, and data packet assembly, while forming a deep end-to-end linkage with upstream and downstream business links. For single-message anomalies such as target channel identifier verification failure or missing business payload, a single-message isolation mechanism is adopted to isolate and process the abnormal message separately, without affecting the aggregation and classification process of other normal messages in the same batch. At the same time, complete information such as the global logical sequence number and anomaly type of the abnormal message is recorded for subsequent anomaly tracing and retry processing. For single-channel anomalies such as aggregation operation anomalies corresponding to a single target channel identifier or data packet assembly failure, a single-channel isolation mechanism is adopted to terminate the aggregation and assembly process of the current batch of that channel, retain all message events corresponding to that channel, and re-execute the aggregation operation after the next batch is pulled, without affecting the aggregation and assembly process of other normal channels. This achieves fault isolation in abnormal scenarios and prevents the aggregation process of the entire batch from being interrupted due to a single channel anomaly. Meanwhile, the aggregated and assembled pushable status refresh data packets are directly synchronized to the downstream batch refresh processing stage, providing a standardized batch data source for message push. The statistical data such as channel activity, message quantity, and aggregation efficiency generated during the aggregation process are synchronously fed back to the upstream backpressure adjustment stage, providing data support for the adjustment of adaptive backpressure strategies. This forms a closed-loop business process from message production and consumption aggregation to push execution and backpressure adjustment, ensuring the orderly, stable, and efficient operation of the entire batch message push system.

[0130] Optionally, the aggregated refresh data packet is subjected to batch refresh processing to form a pushable aggregated refresh data packet.

[0131] Preferably, the pre-triggering condition and input benchmark binding process for the batch refresh processing operation of aggregated refresh data packets in step 3 is as follows: the execution timing of this batch refresh processing operation is strictly limited to after the aggregation and classification based on the channel dimension is completed, the standardized assembly and compliance verification of the aggregated refresh data packets are all passed, and before the push status flag and downstream push execution are implemented. The core input benchmark for batch refresh processing is the set of aggregated refresh data packets that have been standardized and assembled. Each aggregated refresh data packet forms a strong one-to-one binding relationship with a unique target channel identifier and the corresponding active network connection. The data packet encapsulates a complete packet header, ordered payload aggregate, and packet tail verification structure, and carries the global logical sequence number range and timing metadata of the corresponding business payload, providing a complete and compliant data source for batch refresh processing. Before the operation is executed, a second pre-verification is performed on the input set of aggregated refresh data packets to filter out abnormal data packets with invalid target channel identifiers, disconnected network connections, or failed data verification. Only compliant and valid aggregated refresh data packets are retained to enter the subsequent batch refresh processing flow, ensuring the accuracy and validity of the data source for refresh processing from the root.

[0132] Preferably, the core network transmission adaptation optimization process in step 3 of the batch refresh processing is as follows: For each compliant and valid aggregate refresh data packet, transmission adaptation optimization processing oriented towards the network protocol stack is performed to adapt to the characteristics and requirements of the underlying network transmission, solving the problems of frequent system calls and low network I / O efficiency caused by sending messages one by one in the background technology. The transmission adaptation optimization processing first performs maximum transmission unit adaptation calculation. Based on the maximum transmission unit value of the link corresponding to the target network connection, the fixed length overhead of the network protocol header and transmission protocol header is deducted to calculate the maximum effective payload length of a single packet corresponding to the network connection. Then, the overall length of the aggregate refresh data packet is compared with the maximum effective payload length. If the overall length of the data packet does not exceed the maximum effective payload length, the complete structure of the data packet is retained, and no splitting processing is performed. If the overall length of the data packet exceeds the maximum effective payload length, the aggregate refresh data packet is split into multiple consecutive sub-data packets in ascending order of the global logical sequence number. The length of each sub-data packet does not exceed the maximum effective payload length, and each sub-data packet retains the complete packet header structure, timing identifier, and check information to ensure that the receiving end can accurately complete the reassembly of sub-data packets and message parsing. This adaptation avoids the problems of decreased transmission efficiency and increased packet loss rate caused by forced fragmentation of data packets by link devices during network transmission. At the same time, it maximizes the use of the network protocol stack's batch transmission capabilities and improves the utilization of network I / O.

[0133] Preferably, the implementation process of the multi-channel parallel refresh scheduling and order guarantee mechanism in step 3 for batch refresh processing is as follows: For the aggregated refresh data packet set that has completed transmission adaptation optimization, multi-channel parallel batch refresh scheduling is performed on a per-target channel identifier basis. The refresh tasks corresponding to each target channel identifier are independent of each other and the data range is completely isolated. There will be no situation where multiple scheduling tasks operate on the data packets corresponding to the same target channel identifier at the same time, which completely avoids the data race and resource competition problems in the parallel scheduling process. There is no need to use mutex locks for concurrency control, which greatly improves the refresh processing efficiency in high-traffic, multi-connection scenarios. At the same time, for all aggregated refresh data packets corresponding to the same target channel identifier, the refresh sorting is strictly performed in a monotonically increasing order of the global logical sequence number to ensure that the data packets corresponding to the same network connection are always refreshed in accordance with the global timing of message injection, and there will be no problem of data packet out-of-order, which adapts to the core requirement of message timing consistency in real-time communication scenarios. During the parallel refresh scheduling process, the number of refresh tasks executed in parallel is dynamically adjusted based on the current system computing resource load and network I / O busyness. When system resources are sufficient and network I / O is idle, the number of parallel tasks is increased to improve refresh processing speed; when system load is high and network I / O is busy, the number of parallel tasks is reduced to avoid excessive consumption of system resources and network bandwidth, thus balancing refresh processing efficiency and system operation stability.

[0134] Preferably, the protocol stack optimization and system call aggregation process in step 3 for batch refresh processing is as follows: For aggregate refresh data packets that have completed sorting and scheduling, batch submission optimization processing for the operating system network protocol stack is performed. Multiple aggregate refresh data packets corresponding to different network connections within the same batch are submitted to the network protocol stack buffer of the operating system kernel through a single batch system call, replacing the multiple independent system calls corresponding to each message in the traditional solution. This batch submission processing is implemented through the batch network sending interface provided by the operating system, which transmits data packets, connection handles, and sending parameters corresponding to multiple target network connections to the kernel space in batches at one time, reducing the number of context switches between user mode and kernel mode and reducing the CPU overhead caused by system calls. At the same time, for multiple consecutive aggregate refresh data packets corresponding to the same network connection, batch writing optimization of the kernel buffer is performed, which continuously writes multiple data packets to the kernel sending buffer of the corresponding network connection. This fully utilizes the sliding window mechanism and congestion control mechanism of the network protocol stack, maximizes the use of available bandwidth of the network link, reduces the number of interrupt interactions between the kernel and the network card, further improves the overall efficiency of network transmission, and solves the technical defects of excessively frequent system calls and low network I / O efficiency caused by sending one message at a time in the traditional solution.

[0135] Preferably, the adaptive flow control and link status linkage mechanism for batch refresh processing in step 3 is implemented as follows: During batch refresh processing, real-time link status data for each target network connection is collected synchronously, including core indicators such as link round-trip latency, packet loss rate, kernel send buffer idle rate, and available sliding window size. Based on the collected link status data, adaptive flow control is performed on the aggregate refresh data packets of the corresponding network connection. When an increase in network link round-trip latency or packet loss rate is detected, the length and refresh frequency of the single refresh data packet for the corresponding network connection are automatically reduced to avoid network congestion caused by the sending rate exceeding the link's carrying capacity. When a good network link status and sufficient kernel send buffer idleness are detected, the length and refresh frequency of the single refresh data packet for the corresponding network connection are automatically increased to fully utilize the available bandwidth of the link and improve the real-time performance of message push. At the same time, this adaptive flow control mechanism is linked with the preset degradation protection rules. When a large number of network connections are found to be congested or have accumulated data packets, the link status and accumulated data are fed back to the downstream back pressure adjustment stage, providing data support for the execution of the adaptive back pressure strategy, thus realizing full-link linkage optimization from network transmission status to message injection rate.

[0136] Preferably, the pushable status marking and standardized encapsulation process after the batch refresh processing in step 3 is as follows: After the aggregated refresh data packet completes all transmission adaptation optimization, batch scheduling, and protocol stack submission preprocessing, the standardized marking and final encapsulation process for the pushable status is performed to form a formal pushable aggregated refresh data packet. The pushable status marking is implemented through the status identifier field in the data packet header. Updating the field value to the pushable status indicates that the data packet has completed the entire refresh processing flow and can directly enter the downstream push execution stage without performing any additional preprocessing operations. The final encapsulation process supplements each pushable aggregated refresh data packet with all the metadata required for push execution, including the kernel handle of the target network connection, data packet sending priority, timeout retransmission rules, maximum number of retries, callback identifier after sending, etc., ensuring that the downstream asynchronous execution engine can directly complete the push execution of the data packet based on the encapsulated metadata without performing additional metadata query and processing operations, further improving the efficiency of push execution. Meanwhile, each pushable aggregate refresh data packet retains a complete global logical sequence number range and target channel identifier, providing accurate baseline data for subsequent consumption progress updates and slot reuse management after push completion.

[0137] Preferably, the fault tolerance and fault isolation mechanism for abnormal scenarios in the batch refresh process in step 3 is implemented as follows: hierarchical fault tolerance and fault isolation rules are set for various abnormal scenarios that may occur in the entire refresh process to ensure that a single abnormal event will not affect the entire batch refresh process or disrupt the processing logic of other normal data packets. For single-packet anomalies such as transmission adaptation failure, length exceeding limits, and verification failure, a single-packet isolation mechanism is adopted. This removes the abnormal packet from the current refresh batch, stores it separately in an anomaly handling queue, and records complete information such as the corresponding target channel identifier, global logical sequence number range, and anomaly type, awaiting subsequent retry processing. This does not affect the refresh processing flow of other normal packets in the same batch. For single-channel anomalies such as network connection loss or link failure corresponding to a single target channel identifier, a single-channel isolation mechanism is adopted. This terminates the refresh processing of all packets in the current batch for that channel, stores all corresponding packets in the channel anomaly queue, and synchronously updates the channel's active status identifier. This does not affect the refresh processing flow of other normal active channels. For global anomalies such as batch system call failures and kernel buffer overflows, a batch rollback mechanism is adopted. This rolls back all packets in the current batch that have not yet been submitted to their state before refresh processing, awaiting re-execution in the next refresh cycle. This prevents packet loss and duplicate processing. This hierarchical fault tolerance mechanism achieves fault isolation in abnormal scenarios, ensuring the continuous and stable operation of the refresh processing flow under high concurrency and high traffic scenarios.

[0138] Preferably, the full-process statistics and upstream-downstream linkage feedback mechanism for batch refresh processing in step 3 are implemented as follows: Throughout the entire batch refresh processing process, comprehensive statistical data is collected synchronously, including core indicators such as the total number of data packets processed in a single batch, the number of channels, processing latency, system call count, the number of sub-packets to be adapted and split, and the number of abnormal data packets. Simultaneously, data such as the refresh success rate, average data packet length, and link transmission status corresponding to each target channel identifier are also collected. The collected statistical data is stored in the system's monitoring and statistics module for observing system operation status and troubleshooting. It is also synchronously fed back to the upstream channel dimension aggregation and classification stage and the downstream backpressure adjustment stage, forming a full-process linkage optimization. For the upstream aggregation and classification stage, the aggregation batch threshold for different channels is dynamically adjusted based on the refresh processing statistical data. For channels with good link status and sufficient bandwidth, the aggregation batch threshold is increased to further reduce the number of system calls; for channels with poor link status and high latency, the aggregation batch threshold is decreased to improve the real-time performance of message pushes. For the downstream back pressure adjustment process, the backlog of refresh processing and network transmission pressure data are synchronized to the degradation protection rule matching module, providing accurate decision-making basis for adaptive back pressure adjustment. This achieves end-to-end collaborative optimization from message aggregation and refresh processing to push execution and rate control, further improving the system's throughput performance and operational stability in high-concurrency scenarios.

[0139] Optionally, the aggregated refresh data packet is delivered to the asynchronous execution engine to perform the first-level push; the resource monitoring plugin is synchronously invoked to collect the idle rate of the circular buffer in real time and match the degradation protection rules: in response to the system load exceeding the first-level warning threshold, the push task is diverted; in response to the system load triggering the second-level critical point, the caller running strategy is automatically activated to force the push task to be directly and synchronously executed by the hardware processor core currently executing the production release in step 2, and the injection rate of the multiple hardware processor cores to the circular buffer is limited by introducing a self-disciplined backpressure transmission mechanism.

[0140] Preferably, the delivery and first-level push execution process of the aggregated refresh data packet to the asynchronous execution engine in step 4 is as follows: the timing of this delivery and push operation is strictly limited to after the aggregated refresh data packet has completed batch refresh processing and is officially marked as pushable. Degradation guarantee rule matching and backpressure adjustment operations are executed synchronously and in parallel. The core execution carrier of the first-level push is the asynchronous execution engine, independent of the message production and message aggregation processes. This engine has multiple built-in independent asynchronous execution thread pools, with a one-to-one mapping between the thread pools and the priority dimensions of the target network connection. Differentiated scheduling strategies can be executed for aggregated refresh data packets of different priorities. The aggregated refresh data packet that has completed batch refresh processing is delivered to the corresponding level of the execution thread pool within the asynchronous execution engine according to the priority corresponding to the target channel identifier. The thread pool executes the first-level push operation for the corresponding network connection in ascending order of the global logical sequence number of the data packet, submitting the data packet to the operating system network protocol stack to complete the final network transmission. After the push operation is completed, the consumed sequence number maintained internally by the event handler will be updated synchronously. The sequence number will be pushed to the end boundary of the logical sequence number range covered by the corresponding data packet. Simultaneously, the reference cleanup and state rollback operation of the corresponding message event object cell in the circular buffer will be triggered, so that the corresponding cell will be re-transferred to a reusable state for the upstream message production process to re-apply for use. This realizes the seamless connection from message push to slot reuse.

[0141] Preferably, the real-time collection and status synchronization mechanism of the circular buffer idle rate by the resource monitoring plugin in step 4 is implemented as follows: This collection operation is executed synchronously and in parallel with the first-level push operation of the aggregated refresh data packet. The execution body of the collection operation is an independent resource monitoring plugin. The entire collection process adopts a lock-free read-only access mode, only reading the relevant status flags in the circular buffer, atomic sequence number generator, and event handler, without modifying any business data or status fields, thus completely avoiding performance interference to the entire message production, aggregation, and push process. The resource monitoring plugin first reads the fixed total capacity value of the circular buffer, then reads the current value of the core sequence number variable in the atomic sequence number generator, and simultaneously reads the current value of the consumed sequence number in the event handler. By using the fixed total capacity and the length of the published but unconsumed sequence number interval, the number of currently available idle slots in the circular buffer is calculated, and then the proportion of the number of idle slots to the fixed total capacity is calculated, which is the real-time idle rate of the circular buffer. The resource monitoring plugin adaptively adjusts the idle rate collection frequency based on the message accumulation speed of the circular buffer and the push execution latency. When the idle rate continues to decrease and the message accumulation speed accelerates, it automatically shortens the collection interval to improve the real-time performance of status collection. When the idle rate is within the normal range and message push is stable, it automatically extends the collection interval to reduce the ineffective use of system computing resources. The collected real-time idle rate data is synchronously updated to the matching module of the degradation protection rules, serving as the core decision-making benchmark for triggering degradation strategies.

[0142] Preferably, the hierarchical definition and real-time matching execution logic of the preset degradation protection rules in step 4 are as follows: The degradation protection rules adopt a two-level tiered strategy definition mode, which is divided into two levels: the first-level warning threshold and the second-level critical point. Each level takes the real-time idle rate of the circular buffer as the core trigger benchmark, and combines four auxiliary dimensions of indicators: average push execution latency, maximum message backlog duration, system computing resource load, and network IO busyness, to form a multi-dimensional comprehensive trigger judgment logic, so as to avoid the false triggering of degradation strategies caused by fluctuations in a single indicator. The first-level warning threshold is the warning line for system load, corresponding to the first lower limit of the ring buffer idle rate. When the real-time idle rate is lower than this lower limit, and two or more auxiliary dimension indicators meet the warning conditions, the system load is determined to exceed the first-level warning threshold, triggering the corresponding push task diversion processing strategy. The second-level critical point is the safety critical line for system load, corresponding to the second lower limit of the ring buffer idle rate. This lower limit is lower than the lower limit corresponding to the first-level warning threshold. When the real-time idle rate is lower than this critical lower limit, and three or more auxiliary dimension indicators meet the critical conditions, the system load is determined to trigger the second-level critical point, automatically activating the corresponding caller execution strategy. All thresholds and triggering conditions within the degradation protection rules support dynamic configuration based on business scenario requirements, adapting to instant messaging push scenarios of different scales and real-time requirements. Furthermore, rule matching and execution are completed entirely in memory, without accessing persistent storage, ensuring low latency and high real-time performance of strategy triggering.

[0143] Preferably, the push task diversion processing in step 4 after the system load exceeds the first-level warning threshold is as follows: When the matching module of the degradation protection rule determines that the system load exceeds the first-level warning threshold, it will immediately trigger the push task diversion processing strategy. The core objective of this strategy is to improve the overall throughput of push execution, alleviate message backlog pressure, and prevent the system load from further deteriorating and triggering the second-level critical point through multi-pool diversion scheduling of push tasks. The diversion processing strategy first classifies the push tasks currently to be executed in the asynchronous execution engine according to the priority of the target channel identifier and the real-time requirements of the message type. The push tasks are divided into two categories: core real-time tasks and non-core non-real-time tasks. Core real-time tasks include tasks with high push latency requirements, such as one-on-one chat and group chat real-time messages, which are retained in the main execution thread pool of the asynchronous execution engine to continue execution, ensuring the real-time push of core businesses. Non-core non-real-time tasks include tasks with relatively low push latency requirements, such as offline notifications and operational messages, which are diverted to the pre-initialized standby asynchronous execution thread pool for execution. During the task distribution process, the proportion of tasks and the number of execution threads are dynamically adjusted based on the real-time load of the main execution thread pool and the backup execution thread pool. When the load of the main execution thread pool remains high, the distribution range of non-core tasks is appropriately expanded. When the load of the main execution thread pool drops and the idle rate of the circular buffer returns to the normal range, the task distribution is gradually stopped and the tasks are returned to the main execution thread pool. This achieves adaptive task distribution scheduling for push tasks, which effectively improves the system's push processing capabilities while ensuring the core business experience.

[0144] Preferably, the automatic activation and forced execution process of the caller execution strategy after the system load triggers the secondary critical point in step 4 is as follows: When the matching module of the degradation protection rule determines that the system load has triggered the secondary critical point, it means that all execution thread pools of the asynchronous execution engine are fully loaded, the push execution capacity has reached its limit, and the message backlog in the circular buffer has reached a critical state. At this time, the caller execution strategy will be automatically activated immediately. The core execution logic of this strategy is to force the push task originally handled by the asynchronous execution engine to be rolled back to the hardware computing core currently executing production and release in step 2, and the corresponding producer thread will synchronously execute the push task. After the caller execution strategy is activated, all producer threads currently executing message production and release, after completing the entire process of filling the business payload of the message to be pushed, the state transition of the message event object, and the generation of the ready message event, cannot continue to process the next message to be pushed. They must first synchronously execute the push task of the aggregate refresh data packet to which the corresponding message belongs. Only after the push task is completed can the production and release operation of the next message continue. During the execution of this strategy, priority will be given to ensuring the push of core real-time messages. The producer thread will prioritize the synchronous execution of push tasks corresponding to high-priority channels, while push tasks for low-priority channels will be processed after the core tasks are completed. At the same time, the activation and execution status of the strategy will be synchronously notified to all producer threads to ensure that all producer threads follow the same execution rules and avoid the problem of some threads continuing to inject messages at high speed, which could lead to further accumulation and deterioration.

[0145] Preferably, the construction of the self-regulating backpressure transmission mechanism and the execution process of limiting the message injection rate in step 4 are as follows: This backpressure transmission mechanism takes the caller's running strategy as the core execution carrier and the dynamic balance between push execution capability and message production rate as the core objective. Through the reverse transmission of push execution pressure, it achieves spontaneous limitation on the rate at which multiple hardware computing cores inject messages into the circular buffer. This avoids the performance bottlenecks and thread race conditions caused by centralized control, as it does not require centralized flow control components and global lock mechanisms. When the caller's running strategy is activated, the total processing time of a single message by the producer thread increases the execution time of the synchronous push task on top of the original production and release operation. The processing cycle of a single message is significantly extended, causing a spontaneous decrease in the number of messages that a single producer thread can process and inject into the circular buffer per unit time, directly limiting the message injection rate from the execution level. Meanwhile, the real-time idle rate data of the circular buffer is synchronized to the sequence number request module of all producer threads. When the idle rate is in the secondary critical range, the sequence number request module will automatically adjust the spin retry parameters of the comparison and exchange atomic operations, extend the thread yielding interval after consecutive retry failures, reduce the frequency of sequence number requests, and further limit the message injection rate. When the idle rate of the circular buffer gradually recovers and the push backlog pressure is relieved, the spin retry parameters will be gradually restored to improve the message injection rate, thus achieving a dynamic adaptive balance between message production rate and push consumption capacity.

[0146] Preferably, the implementation process of the fault tolerance and end-to-end collaborative optimization mechanism for the entire push processing and backpressure adjustment process in step 4 is as follows: For various abnormal scenarios that may occur during the push execution, degradation strategy triggering, and backpressure adjustment processes, hierarchical fault tolerance and fault isolation rules are set to ensure that a single abnormal event will not affect the stable operation of the entire push process or cause a cascading failure effect. For single-packet push anomalies such as network connection anomalies, data packet sending timeouts, and protocol stack submission failures during the asynchronous execution engine push process, a single-packet retry and fault isolation mechanism is adopted. A limited number of timeout retransmissions are performed on abnormal data packets. If the retransmission still fails, the corresponding data packet is stored in the anomaly handling queue, recording the corresponding channel information and sequence number range, without affecting the push execution of other normal data packets in the same batch. For single-channel anomalies such as network connection disconnection or link failure of a single target channel, a channel isolation mechanism is adopted to terminate the push operation of the corresponding data packet for that channel and update the channel's active status, without affecting the push process of other normal channels. To address strategy-level anomalies such as mismatched degradation protection rules or abnormal execution of caller-driven strategies, a rapid failure rollback mechanism is employed. This immediately terminates the execution of the currently abnormal degradation strategy, reverting the push process to normal asynchronous execution mode. Simultaneously, anomaly information is recorded to prevent push process interruptions caused by strategy anomalies. Furthermore, push execution success rate, latency data, degradation strategy trigger status, and backpressure adjustment effectiveness data are synchronously fed back to upstream message aggregation and batch refresh stages. This dynamically adjusts the batch threshold for channel aggregation and the frequency and length of data packet refreshes, forming end-to-end collaborative optimization from push execution to message production. This ensures the system maintains high operational stability and message push performance under different load scenarios.

[0147] like Figure 2 As shown in the figure, a high-performance message batch push device based on a circular buffer and compare-and-swap atomic operations is provided in this application embodiment, comprising: The first program unit is used to generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator, and configure bit and address conversion logic for it.

[0148] The second program unit is used to generate ready message events marked as consumable in the circular buffer based on the lock-free object pool and the bit-address conversion logic when the multiple hardware processor cores concurrently access the message to be pushed.

[0149] The third program unit is used to perform polling and listening on the upper limit of the published sequence number of the circular buffer, so as to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate a push aggregate refresh data packet based on multiple service payloads sent to the same network connection.

[0150] The fourth program unit is used to perform push processing on the aggregated refresh data packet based on preset degradation protection rules, and to perform adaptive back pressure adjustment according to the load pressure of the ring buffer to limit the injection rate of the multiple hardware processor cores to the ring buffer.

[0151] like Figure 3 As shown, an electronic device according to an embodiment of this application includes a processor and a memory; The memory is used to store computer programs; When the processor executes the program stored in the memory, it implements the functions of each module of the aforementioned high-performance message batch push device based on circular buffer and comparison and exchange atomic operations, or implements the steps of the aforementioned high-performance message batch push method based on circular buffer and comparison and exchange atomic operations.

[0152] Figures 2-3 For an exemplary description, please refer to the above. Figure 1 .

Claims

1. A high-performance message batch push method based on a circular buffer and compare-and-swap atomic operations, characterized in that, include: Step 1: Generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator and configure bit and address conversion logic for it; Step 2: When the multiple hardware processor cores concurrently access the message to be pushed, a ready message event marked as consuming is generated in the circular buffer based on the lock-free object pool and the bit-address conversion logic. Step 3: Perform polling and listening on the upper limit of the published sequence number of the circular buffer to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate an aggregated refresh data packet for push based on multiple service payloads sent to the same network connection.

2. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations as described in claim 1, characterized in that, It also includes: Step 4, based on preset degradation protection rules, performing push processing on the aggregated refresh data packet, and performing adaptive backpressure adjustment according to the load pressure of the ring buffer to limit the injection rate of the multiple hardware processor cores to the ring buffer.

3. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations as described in claim 1, characterized in that, Step 1 specifically includes: A fixed-capacity message event object grid is pre-allocated within the contiguous physical memory space of the circular buffer to generate a lock-free object pool that can be reused repeatedly. Initialize the atomic sequence number generator so that a core sequence number variable for representing the production progress is encapsulated inside the atomic sequence number generator. The core sequence number variable serves as a globally unique sequence number locking flag, which can be accessed concurrently by the multiple hardware processor cores when executing multiple producer threads in parallel to receive messages to be pushed. Configure bit and address conversion logic for the atomic number generator.

4. The high-performance message batch push method based on a circular buffer and comparison-and-swap atomic operations as described in claim 3, characterized in that, Step 1 also specifically includes: The core sequence number variable is processed by cache line padding to fill placeholder bytes before and after the core sequence number variable so that it occupies a hardware cache line independently, thereby eliminating the hardware-level pseudo-sharing interference caused by multiple variables sharing the same hardware cache line when multiple hardware processor cores concurrently request enqueue sequence numbers. A globally monotonically increasing logical sequence number is generated based on the core sequence number variable.

5. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations according to claim 1, characterized in that, Step 2 specifically includes: When the multiple hardware processor cores concurrently access the message to be pushed, each hardware processor core uses the bit-address conversion logic to map the target incremental sequence number to the corresponding physical storage index in real time to locate the message event object in the lock-free object pool in the memory space, and fills the service payload carried by the message to be pushed into the cell of the message event object pointed to by the physical storage index. The filled message event object is transitioned from the request pre-occupancy state to the publish ready state, and then a ready message event marked as consuming is generated in the circular buffer.

6. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations as described in claim 1, characterized in that, Step 2 also specifically includes: Each of the hardware processor cores reads the current logical sequence number from the atomic sequence number generator as the expected value, and uses hardware instruction-level comparison and exchange atomic logic to attempt to update the core sequence number variable in order to lock the target incremental sequence number.

7. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations according to claim 1, characterized in that, Step 3 specifically includes: The event handler is invoked, which performs polling and listening to the upper limit of the published sequence number of the circular buffer, and pulls multiple ready message events that are injected and accumulated in parallel by the multiple hardware processor cores in one batch. Extract the target channel identifier corresponding to the service payload in each ready message event, and execute the aggregation and classification logic based on the channel dimension to group and assemble multiple service payloads sent to the same network connection into physical layer aggregate refresh data packets; perform batch refresh processing on the aggregate refresh data packets to form pushable aggregate refresh data packets.

8. The high-performance message batch push method based on circular buffer and compare-and-swap atomic operations as described in claim 1, characterized in that, Step 4 specifically includes: The aggregated refresh data packet is delivered to the asynchronous execution engine to perform the first-level push; the resource monitoring plugin is synchronously invoked to collect the idle rate of the circular buffer in real time and match the degradation protection rules: in response to the system load exceeding the first-level warning threshold, the push task is diverted; in response to the system load triggering the second-level critical point, the caller running strategy is automatically activated to force the push task to be directly and synchronously executed by the hardware processor core currently executing the production release in step 2, and the injection rate of the multiple hardware processor cores to the circular buffer is limited by introducing a self-disciplined backpressure transmission mechanism.

9. A high-performance message batch push device based on a circular buffer and compare-and-swap atomic operations, characterized in that, include: The first program unit is used to generate a reusable lock-free object pool based on the circular buffer, initialize the atomic number generator and configure bit and address conversion logic for it. The second program unit is used to generate ready message events marked as consuming in the circular buffer based on the lock-free object pool and the bit-address conversion logic when the multiple hardware processor cores concurrently access the message to be pushed. The third program unit is used to perform polling and listening on the upper limit of the published sequence number of the circular buffer, so as to extract the target channel identifier corresponding to the service payload in each ready message event, and then generate a push aggregate refresh data packet based on multiple service payloads sent to the same network connection.

10. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer-executable program, and the processor is used to run the computer-executable program to implement the high-performance message batch push method based on a circular buffer and compare-and-swap atomic operations as described in any one of claims 1-8.

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