FPGA-based infrared image data parallel processing method and circuit

Abstract

This invention relates to the field of infrared imaging and low-level hardware processing technology, and discloses a parallel processing method and circuit for infrared image data based on FPGA. The method includes: establishing a pixel spatiotemporal mapping coordinate system and extracting pixel mapping point coordinate pairs; performing hardware topology sensing and spatial decoupling to output a spatial topology matrix; performing real-time pixel-level non-uniformity correction; implementing phase-locked noise reduction through a virtual offset field to obtain an equalized corrected bitstream; generating a quantization mapping curve based on saliency sensing; and performing real-time video reconstruction combined with adaptive power consumption control to output a video signal. This invention solves the problems of latency and instantaneous heat accumulation in large-area infrared data processing, achieving high-fidelity restoration of spatial topology and suppression of non-uniform noise; closed-loop energy management eliminates image blurring caused by thermal drift, comprehensively improving the system's imaging clarity and hardware operating efficiency.

Description

Technical Field

[0001] This invention relates to the field of infrared imaging and underlying hardware processing technology, and more specifically, to a method and circuit for parallel processing of infrared image data based on FPGA. Background Technology

[0002] With the rapid development of infrared imaging technology, large-area, high-resolution infrared detectors are increasingly widely used in precision guidance, complex background monitoring, and industrial non-destructive testing. However, traditional infrared image preprocessing schemes, such as macroscopic methods like increasing processor clock speed, expanding off-chip storage capacity, or optimizing discrete filtering operators, generally face performance bottlenecks when dealing with high-speed dynamic targets and extreme temperature difference environments. Existing technologies mostly remain at the level of line-by-line serial processing of the raw infrared bitstream or rely on statically preset correction parameters for gain compensation. This ignores the spatiotemporal coupling characteristics of infrared radiation data stream generation, as well as the topological congestion effect of underlying hardware resources under large-area data throughput. Specifically, the "detail trapping effect" is caused by the interplay of non-uniform noise and dynamic thermal drift, burying the features of targets with minute temperature differences within complex, unstable fringe interference. Furthermore, frequent handshakes and memory scheduling between multi-level processing logic modules lead to severe computational latency accumulation, causing hardware resources to experience dramatic instantaneous heat dissipation and heat buildup when dealing with high-throughput data streams. This results in a dynamic imbalance between image clarity and hardware stability. While traditional digital signal processing architectures can perform basic function mapping, their lack of deep perception of the hardware physical resource topology means their enormous computational and storage overhead cannot meet the demands of real-time, ultra-low latency imaging control. Therefore, how to shift from passive serial logic to active spatial topology perception, transforming macroscopic hardware computing power stacking into parallel decoupling and spatiotemporal alignment of key pixel data, thereby overcoming the contradiction between rigid hardware resource allocation and real-time performance, is a pressing technical challenge in this field.

[0003] In the prior art, Chinese invention patent CN103049879B discloses an FPGA-based infrared image preprocessing method. This method employs a monolithic FPGA architecture with an embedded programmable system-on-a-chip (SOPC), integrating a non-uniform correction module, a blind pixel replacement module, a histogram statistics module, and a grayscale transformation module. It eliminates the need for a digital signal processor (DSP) for calculations, acquires correction coefficients through image freezing, performs pixel correction row-by-row in a pipeline, completes blind pixel replacement using median filtering, and performs histogram statistics and linear grayscale transformation of the infrared image. This achieves system miniaturization and solves the problems of complex circuitry, high power consumption, and low image processing efficiency inherent in traditional FPGA+DSP architectures. Chinese patent CN207652564U discloses an FPGA-based uncooled infrared thermal imaging system. The system consists of an infrared detection module, a bias modulation module, an FPGA module, and a DDR3 storage module. It is equipped with a 640×480 uncooled infrared focal plane detector and uses a Cyclone V series FPGA chip as the core processing unit. The bias modulation module realizes adaptive correction coefficient adjustment, and the DDR3 and FLASH storage modules complete image data caching. Finally, the image is output through the VIDEO and LVDS interfaces. It features miniaturization, low power consumption, and high real-time performance, and can realize the acquisition, processing and synchronous display of infrared images.

[0004] However, while the two existing technologies mentioned above have some value in infrared image preprocessing and miniaturization of thermal imaging systems, they fail to address the core pain points of "detail trapping effect," hardware topology congestion, and heat accumulation in large-area scenarios. Specifically, the Chinese patent with authorization announcement number CN103049879B relies on static correction coefficients and employs a line-by-line serial processing mode, ignoring the spatiotemporal coupling characteristics of the infrared data stream. It lacks hardware topology awareness and pixel spatial decoupling design, making it prone to latency accumulation during large-area data processing. The Chinese patent with authorization announcement number CN207652564U only implements basic bias modulation and data buffering, lacking dynamic blind pixel filling, phase offset noise reduction mechanisms, and adaptive power consumption control design, thus failing to suppress nonlinear noise shift under extreme temperature differences. Neither of these technologies achieves pixel parallel decoupling and temporal phase alignment, failing to release the embedding characteristics of targets with small temperature differences and struggling to balance image clarity and hardware thermal stability, thus failing to meet the real-time imaging requirements of high-resolution infrared devices in high-speed, dynamic, and extreme environments. Summary of the Invention

[0005] This invention is applicable to large-area infrared detection systems of various specifications, such as high-resolution, high-frame-rate imaging scenarios. It can meet the requirements of efficient parallel scheduling and high-throughput data processing of FPGA underlying hardware resources. By establishing a pixel spatiotemporal mapping coordinate system, extracting pixel mapping point coordinate pairs, and performing hardware topology perception and spatial decoupling, the original infrared radiation data stream is transformed into a spatial topology matrix, realizing the accurate reconstruction of the processing architecture from passive time series to active parallel topology. The non-uniformity hardware compensation operator and phase-locked noise reduction logic implement physical interference through a virtual offset field, transforming traditional noise reduction into quantitative phase offsetting for process inhomogeneity and phase jitter, effectively suppressing the "curtain effect" and periodic interference, and obtaining an equalized corrected bitstream. Based on the saliency perception window, a quantization mapping curve is generated, and combined with power consumption constraint feedback control, a video quantization projection path is established to achieve closed-loop management of detail enhancement and thermal energy consumption. This invention can not only break through the latency bottleneck of large-area array processing, but also provide thermal stability support for extreme temperature difference environments, reduce hardware energy consumption, and comprehensively improve imaging quality and system energy efficiency ratio.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A parallel processing method for infrared image data based on FPGA includes: The original infrared radiation data stream characterizing the thermal radiation intensity distribution of the target scene is acquired, and a pixel spatiotemporal mapping coordinate system is constructed to extract features from the original infrared radiation data stream to obtain pixel mapping point coordinate pairs. Hardware topology awareness and spatial decoupling are performed on the pixel mapping point coordinate pairs to obtain preliminary decoupled pixel clusters. Parallel temporal analysis and phase synchronization alignment are performed on the preliminary decoupled pixel clusters to output a spatial topology matrix. Non-uniformity correction is performed on the spatial topology matrix to obtain a primary correction pixel set. Phase-locked denoising is then performed on the primary correction pixel set to obtain a denoised data stream. Real-time blind pixel filling and logical verification are then performed on the denoised data stream to output an equalized correction bit stream. Based on the equalization correction bitstream, a saliency-aware operation is performed to obtain the quantization mapping curve. Based on the quantization mapping curve, real-time video reconstruction and adaptive power consumption control are performed to output the video signal.

[0007] Furthermore, the method for obtaining the pixel mapping point coordinate pairs includes: Obtain the pixel sampling sequence number corresponding to each pixel in the raw infrared radiation data stream; Determine the origin of the coordinate system in the pixel spatiotemporal mapping coordinate system, and determine the total number of columns and rows according to the array specifications of the infrared detector; By performing modulo and floor operations on the pixel sampling sequence number using the total number of columns, preliminary column indices and preliminary row indices are obtained, respectively. The preliminary column index and preliminary row index are respectively subjected to centering offset processing to obtain the horizontal axis component and the vertical axis component. The horizontal axis component and the vertical axis component are combined to obtain the pixel mapping point coordinate pair.

[0008] Furthermore, the preliminary decoupled pixel cluster includes: Based on the pixel mapping point coordinate pairs, the original infrared radiation data stream is deconstructed into multiple parallel channels, and the physical layout center of each parallel channel in the hardware physical layer is defined to determine the physical transmission path of the parallel channels. Extract the wiring Manhattan distance of each physical layout center relative to the coordinate origin, and quantify the path background delay of each parallel channel on the physical transmission path based on the wiring Manhattan distance; The computational background delay generated by the execution data buffer and logical mapping of the registers in each parallel channel is obtained, and the path background delay and the computational background delay are accumulated to obtain the preliminary decoupled pixel cluster.

[0009] Furthermore, the spatial topology matrix includes: Configure an elastic buffer at the end of each parallel channel and set a target delay cycle number that represents the timing alignment reference of all parallel channels; The period difference between the target delay cycle number and the path background delay corresponding to the initial decoupled pixel cluster loaded in each parallel channel and the sum of the calculated background delay is calculated. The elastic buffer is used to perform delay alignment processing based on the period difference to eliminate the transmission phase difference between parallel channels. After each parallel channel meets the target delay period, each initially decoupled pixel cluster is controlled to output synchronously from the elastic buffer to obtain the spatial topology matrix.

[0010] Furthermore, the primary correction pixel set includes: The correction parameter matrix stored in the block random access memory is invoked, and the correction parameter matrix contains the gain coefficient and bias coefficient corresponding to each pixel position; Gain alignment and bias alignment are performed on each pixel in the spatial topology matrix using gain and bias coefficients, and a primary corrected pixel set is output.

[0011] Furthermore, the denoised data stream includes: Perform a discrete Fourier transform on the primary correction pixel set to obtain the dominant frequency characterizing the periodic sampling interference; A virtual hedging field with opposite phase and opposite polarity is constructed based on the dominant frequency; The virtual offset field and the primary correction pixel set are synchronously superimposed. The energy offset is performed on the energy fluctuation component induced by the dominant frequency in the primary correction pixel set by utilizing the destructive interference principle between the virtual offset field and the primary correction pixel set, and the denoised data stream is output.

[0012] Furthermore, the step of extracting the correction pixel to be detected and its 8 neighboring pixels from the denoised data stream, wherein the correction pixel is a discrete feature quantization unit in the primary correction pixel set, and the correction pixel carries a grayscale response value; Calculate the arithmetic mean of the grayscale response values ​​of the 8 neighboring pixels to obtain the background value of the reference neighborhood; The grayscale response value corresponding to the correction pixel to be detected is subtracted from the background value of the reference neighborhood to obtain the numerical deviation. The acute angle probability threshold and the number of judgment frames are set. If the absolute value of the numerical deviation is greater than the acute angle probability threshold in a continuous number of judgment frames, the current pixel mapping point coordinate pair is determined to be a dynamic blind cell. The nearest pixel with a numerical deviation less than the acute angle probability threshold is retrieved from the 8 neighboring pixels and used as the nearest neighbor effective pixel to cover the correction pixel at the dynamic blind cell in real time, thus obtaining the repair correction pixel. The repaired and corrected pixels are combined with the corrected pixels that are not identified as dynamic blind pixels to form a pixel sequence, and the grayscale response value is detected to be within the preset dynamic range range. Only when the grayscale response value is greater than the dynamic range range is the equalized correction bitstream output.

[0013] Furthermore, the quantization mapping curve includes: A saliency perception window is constructed with each pixel mapping point coordinate pair as the logical center point. The absolute value of the difference between the grayscale response values ​​of the logical center point and its surrounding pixels is calculated to obtain the local detail gradient value. Set a noise suppression baseline value. If the local detail gradient value is greater than the noise suppression baseline value, the pixel mapping point coordinate pair is determined to be in a non-smooth feature region. The local detail gradient value and the noise suppression baseline value are subtracted to obtain the effective gradient feature value. Based on the definition of multiple gray levels according to the gray response values, for each gray level, the effective gradient feature quantities belonging to that gray level and located in the non-smooth feature region are accumulated to obtain the feature weight operator. The feature weight operators are recursively accumulated to obtain the cumulative distribution value. The sum of the feature weight operators and the preset quantization upper limit are combined to perform normalization mapping to obtain the mapped quantization value. All mapped quantization values ​​are then combined to form a quantization mapping curve.

[0014] Furthermore, the video signal includes: Each mapped quantization value is stored in a block random access memory to construct a lookup table, and the grayscale response value in the equalization correction bitstream is used as an addressing signal to output the corresponding mapped quantization value from the lookup table to complete the video reconstruction. The power consumption status during hardware operation is acquired in real time, and the generation interval period, which represents the update frequency of the quantization mapping curve, is set. Only when the power consumption state value is greater than or equal to the power consumption safety threshold, the generation interval period is increased to reduce the logic flip frequency used to calculate the quantization mapping curve, and a video signal is generated based on the reconstructed mapping quantization value.

[0015] An FPGA-based parallel processing circuit for infrared image data is used to implement the aforementioned FPGA-based parallel processing method for infrared image data. The system includes: Topology mapping module: used to acquire raw infrared radiation data stream, generate pixel mapping point coordinate pairs by establishing a pixel spatiotemporal mapping coordinate system, and perform hardware topology awareness and spatial domain decoupling processing based on pixel mapping point coordinate pairs, outputting a spatial topology matrix representing the spatial geometric relationship of pixels; Response Alignment Module: Used to call non-uniformity hardware compensation operators using spatial topology matrix to perform pixel response alignment, obtain primary corrected pixel set, and construct virtual counter-current field based on primary corrected pixel set to perform phase-locked noise reduction processing, resulting in equalized corrected bitstream with response consistency. Video reconstruction module: It is used to perform feature extraction on the equalization correction bitstream using a saliency-aware window, obtain feature weight operators and generate quantization mapping curves, perform real-time video reconstruction based on quantization mapping curves, and simultaneously perform adaptive power consumption control to output high-fidelity thermal imaging video signals.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention reconstructs the original infrared radiation data stream into a spatial topology matrix by using a pixel spatiotemporal mapping coordinate system, hardware topology sensing, and spatial decoupling. This solves the problem of accumulated processing latency in traditional serial architectures and improves the energy efficiency of hardware parallel processing. Phase-locked denoising is performed using a non-uniformity hardware compensation operator and a virtual offset field. Phase offsetting suppresses detector non-uniformity noise and periodic sampling interference, resulting in a consistent, equalized correction bitstream that ensures image structural integrity. Furthermore, a quantization mapping curve is generated based on a saliency-sensing window, and the generation interval is dynamically adjusted using power consumption constraint feedback control. This avoids the surge in instantaneous heat consumption caused by excessively high logic flip rates and eliminates imaging nonlinear shifts caused by heat accumulation. This achieves high-fidelity enhancement of large-area images and closed-loop management of hardware energy efficiency, significantly improving imaging clarity and system operational stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating the parallel processing method for infrared image data based on FPGA provided in this embodiment of the invention; Figure 2 A schematic diagram illustrating the logical mapping relationship between an infrared detector photosensitive array and a pixel spatiotemporal mapping coordinate system, provided for an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the principle of a saliency-aware window and feature weight generation quantization mapping curve provided in an embodiment of the present invention. Figure 4 This is a functional block diagram of an FPGA-based parallel infrared image data processing circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1 Please see Figure 1 As shown, this embodiment provides a parallel processing method for infrared image data based on FPGA, including: Step S10: Obtain the original infrared radiation data stream characterizing the thermal radiation intensity distribution of the target scene, and construct a pixel spatiotemporal mapping coordinate system to extract features from the original infrared radiation data stream to obtain pixel mapping point coordinate pairs. Perform hardware topology awareness and spatial decoupling on the pixel mapping point coordinate pairs to obtain preliminary decoupled pixel clusters. Perform parallel temporal analysis and phase synchronization alignment on the preliminary decoupled pixel clusters to output the spatial topology matrix.

[0021] Further, step S10 includes: Step S11: Obtain the original infrared radiation data stream that characterizes the thermal radiation intensity distribution of the target scene, and construct a pixel spatiotemporal mapping coordinate system to extract features from the original infrared radiation data stream to obtain pixel mapping point coordinate pairs.

[0022] In the development of uncooled infrared imaging systems, the infrared imaging system is a precision optoelectronic device composed of an infrared optical lens, an infrared detector, a readout circuit, and a signal processing circuit. The infrared optical lens is an optical component that uses the principle of refraction to focus the far-infrared radiation energy of an external target onto a preset focal plane. The infrared detector, installed at the focal plane of the infrared optical lens, is a sensitive element that converts far-infrared radiation energy into a weak electrical signal by utilizing the physical property that the resistance of the vanadium oxide sensitive layer changes with radiant heat. The infrared detector internally contains a photosensitive array, which is a sensing physical layer composed of multiple pixel units arranged in a matrix, used for spatial sampling of the radiation energy focused by the infrared optical lens. The readout circuit, integrated inside the infrared detector, is an integrated circuit used to perform periodic current integration, voltage sampling, and analog-to-digital conversion operations on the weak electrical signal generated by each pixel unit in the photosensitive array. However, existing infrared image processing schemes typically treat the acquired signal as a one-dimensional time series, ignoring the geometric topological relationships of pixel units on the focal plane of the infrared detector. For example, when dealing with a high-resolution array specification of 604×512, due to the huge number of pixel units contained in each frame, the simple serial processing architecture leads to a linear accumulation of processing delays within the field-programmable gate array. Furthermore, in the initial period after startup, the inability to decouple spatial noise and thermal drift in real time results in non-stationary image blurring in the output signal. To eliminate the imaging processing distortion caused by model simplification, a reference frame capable of accurately mapping the original signal to the physical focal plane space is established, outputting a structured quantization benchmark. The aim is to transform the passive time series description into an active, high-fidelity digital spatial topological description.

[0023] The raw infrared radiation data stream refers to the digital serial response sequence generated by the photosensitive array of the infrared detector, characterizing the distribution of thermal radiation intensity of the target scene. Specifically, the radiation energy in the far-infrared band of the external target is focused by the infrared optical lens onto the photosensitive array of the infrared detector, causing a change in the resistance of the vanadium oxide sensitive layer in the photosensitive array. The readout circuit integrates and samples the weak electrical signal generated by the resistance change of the vanadium oxide sensitive layer, and converts the sampled analog quantity into a digital signal through analog-to-digital conversion. The digital signal is output through the digital output interface of the infrared detector and captured in real time by the general-purpose input / output port of the field-programmable gate array, thereby obtaining the raw infrared radiation data stream. The external target refers to a physical entity located within the object-side field of view of the infrared optical lens and with a temperature above absolute zero. In practical applications, this includes monitoring targets, search and rescue objects, vehicle-mounted road environment entities, and industrial detection equipment. The far-infrared band can penetrate the atmospheric window region and be effectively sensed by uncooled detectors; for example, the long-wave infrared spectrum region with wavelengths between 8 and 14 micrometers. The radiation energy refers to the electromagnetic wave energy continuously and spontaneously radiated into external space by the external target due to the thermal motion of molecules.

[0024] To accurately describe the physical position of each pixel unit in the raw infrared radiation data stream on the focal plane of the infrared detector, a fixed two-dimensional Cartesian coordinate system, namely the pixel spatiotemporal mapping coordinate system, is established with the projection point of the geometric center of the infrared detector's photosensitive array within the field-programmable gate array's logic mapping space as the origin O. The logic mapping space refers to a virtual resource array model composed of configurable logic blocks and distributed storage units within the field-programmable gate array. The horizontal axis X of the pixel spatiotemporal mapping coordinate system is defined as a straight line parallel to the row drive direction of the infrared detector, and the vertical axis Y is defined as a straight line perpendicular to the horizontal axis and parallel to the column drive direction of the infrared detector, ensuring a high degree of consistency between the pixel spatiotemporal mapping coordinate system and the internal physical array structure of the infrared detector. After establishing the pixel spatiotemporal mapping coordinate system, feature extraction is performed on the raw infrared radiation data stream using the pixel spatiotemporal mapping coordinate system to generate pixel mapping point coordinate pairs. The function of these pixel mapping point coordinate pairs is to transform the one-dimensional discrete pixel sampling sequence number into spatial position coordinates with physical directionality. Specifically, the pixel sampling sequence number n in the original infrared radiation data stream is obtained. This pixel sampling sequence number represents an increasing integer indicating the order of a single pixel unit within a single frame of the original infrared radiation data stream's time sequence. It is obtained by performing pulse accumulation counting on the effective pixel synchronization clock, which is synchronously input with the original infrared radiation data stream, using a pixel counter within the field-programmable gate array. The effective pixel synchronization clock refers to the synchronization pulse signal output by the infrared detector, indicating that the current data bit belongs to the effective pixel region of the photosensitive array. The horizontal axis component of the pixel mapping point coordinate pair is obtained by performing a modulo operation on the total number of rows P and the total number of columns Q in the array specification, and then a floor operation is performed to obtain the vertical axis component of the pixel mapping point coordinate pair. Specifically, the initial column index is obtained by performing a modulo operation on the pixel sampling sequence number using the total number of columns Q in the array specification, and then half of the total number of columns Q is subtracted from the initial column index to obtain the horizontal axis component.The pixel sampling number is rounded down using the total number of columns Q in the array specification to obtain the preliminary row index. Half of the total number of rows P is then subtracted from the preliminary row index to obtain the vertical component of the pixel mapping point coordinate pair. For example, taking a 640×512 array specification as an example, the horizontal and vertical components are explained. The total number of rows P and columns Q in the array specification are 512 and 640 respectively; the total number of pixel sampling numbers corresponding to the array specification is 640×512, or 327680. When the pixel sampling number is 3... When the pixel sampling number is 320640, the corresponding horizontal axis component is 0. Taking the modulo of 320640 with 640 gives 0; subtracting 320 from 0 gives -320. The corresponding vertical axis component is 501, obtained by rounding down 640 with 320640. Subtracting half of 512 from 501 gives 245. Therefore, for a 640×512 array, when the pixel sampling number is 320640, the horizontal axis component of the pixel mapping point coordinate pair is -320, and the vertical axis component is 245. See also. Figure 2 This is a schematic diagram illustrating the logical mapping relationship between the photosensitive array of an infrared detector and the spatiotemporal mapping coordinate system of pixels, provided by an embodiment of the present invention. Figure 2 The left side of the diagram illustrates the photosensitive array of a 640×512 infrared detector. The photosensitive array consists of multiple pixel units arranged in a matrix, with consecutive yellow progressive scan timing paths clearly marked to indicate the generation logic of the raw infrared radiation data stream. A solid black square illustrates pixel unit number 320640. The right side shows the pixel spatiotemporal mapping coordinate system established within the logic mapping space of the field-programmable gate array (FPGA), consisting of mutually perpendicular horizontal axes (X) and vertical axes (Y), with the origin O corresponding to the geometric center of the photosensitive array. The diagram specifically uses pixel sample number 320640 as an example, demonstrating its precise location in the pixel spatiotemporal mapping coordinate system after calculation, at a position with a horizontal component of -320 and a vertical component of 245.

[0025] Step S12: Based on the pixel mapping point coordinates, perform hardware topology awareness and spatial decoupling to obtain a preliminary decoupled pixel cluster.

[0026] After obtaining the pixel mapping point coordinate pairs, to ensure that the original infrared radiation data stream does not experience timing conflicts due to differences in the physical distribution of underlying hardware resources during parallel processing, an operation is performed to obtain the hardware topology of the field-programmable gate array (FPGA). The hardware topology refers to a set of quantified parameters reflecting the spatial distribution, resource idle ratio, and wiring path congestion characteristics of configurable logic blocks, multiply-accumulate units, and on-chip storage resources at each physical coordinate point within the logic mapping space relative to the pixel spatiotemporal mapping coordinate system. Since the wiring delay of hardware logic directly affects the image processing throughput in the software architecture design of uncooled infrared imaging systems, an evaluation model is established to quantify the carrying capacity of the hardware topology for pixel mapping point coordinate pairs.

[0027] Logical density evolution analysis is performed in the pixel spatiotemporal mapping coordinate system using hardware topology quantities. Specifically, the logical mapping space is divided into multiple logical resource grids according to the unit span of the pixel spatiotemporal mapping coordinate system, defined as coordinate units. The remaining number of lookup tables and registers in the configurable logic blocks contained in each coordinate unit, as well as the number of idle multiply-accumulate units, are counted. The lookup table refers to the basic logic unit used to implement combinational logic operations within the field-programmable gate array (FPGA); the register refers to the basic storage unit used to implement sequential logic storage within the FPGA. A weighted summation calculation is performed on the remaining number of lookup tables, the remaining number of registers, and the number of idle multiply-accumulate units using preset resource weight coefficients to obtain the static computing potential of each coordinate unit. The static computing potential represents the theoretical maximum computing task carrying capacity of the coordinate unit without considering signal wiring congestion. The resource weight coefficients are calibrated based on the consumption ratio of different hardware resources. For example, the weight coefficients for the remaining number of lookup tables, the remaining number of registers, and the number of idle multiply-accumulate units are set to 0.2, 0.1, and 0.7, respectively. The total number of wiring interconnection paths between a coordinate unit and its adjacent coordinate units is obtained. This total number of wiring interconnection paths refers to the maximum physical upper limit of metal interconnect segments used to connect physical logic blocks between coordinate units. Simultaneously, the number of occupied paths within the total number of wiring interconnection paths is obtained; this number refers to wiring resources that have already been pre-occupied. The ratio of the number of occupied paths to the total number of wiring interconnection paths is defined as the path congestion coefficient. This path congestion coefficient is used to normalize the static computing potential, yielding the wiring path capacity for each coordinate unit. The wiring path capacity represents the effective computing potential actually provided by each coordinate unit under communication bandwidth constraints. Normalization is achieved by subtracting the path congestion coefficient from 1 and then multiplying it by the static computing potential.

[0028] The data processing capacity of each coordinate unit is analyzed. Specifically, the routing path capacity is divided by a preset single-pixel processing overhead to obtain the maximum number of parallel pixel processing pipelines that each coordinate unit can accommodate under the premise of time convergence. This is defined as the logical capacity value. The single-pixel processing overhead is obtained by statistically analyzing the number of lookup tables, registers, and multiply-accumulate units required to perform logical operations on a single pixel unit, and obtaining the corresponding total resource consumption. For example, it is set to 150. The logical capacity value represents the quantized upper limit of the parallel processing capability of pixel units supported by each coordinate unit in the spatial dimension. Using the horizontal and vertical axes of the pixel spatiotemporal mapping coordinate system as physical index addresses, the logical capacity value corresponding to each coordinate unit is filled into the corresponding position of a two-dimensional data matrix as matrix elements. The numerical space between adjacent coordinate units is smoothed using a bilinear interpolation algorithm to form a digital mapping matrix with continuous numerical gradients, defined as a logical routing graph, which is used to characterize the hardware performance abundance of different regions within the logical mapping space.

[0029] Spatial decoupling processing is performed on the logical routing graph to obtain preliminary decoupled pixel clusters. Specifically, the preset number of parallel channels in the field-programmable gate array (FPGA) is obtained. A parallel channel refers to an independent logical path built at the hardware level capable of performing synchronous operations on the pixel data stream. The initial segmentation step size is obtained by dividing the array specifications of the infrared detector, such as the total number of columns, by the number of parallel channels. This initial segmentation step size refers to the coordinate span covered by each parallel channel in the pixel spatiotemporal mapping coordinate system without considering hardware resource congestion constraints. Based on the initial segmentation step size, the geometric region corresponding to each parallel channel is defined in the pixel spatiotemporal mapping coordinate system. This geometric region refers to a closed logical plane jointly defined by the horizontal and vertical coordinate ranges in the pixel spatiotemporal mapping coordinate system. Specifically: Taking the center of the pixel spatiotemporal mapping coordinate system as the origin, the system is divided at equal intervals along the horizontal axis according to the initial segmentation step size, resulting in several interconnected horizontal axis intervals. Simultaneously, the maximum coordinate span of the infrared detector along the vertical axis is obtained, defined as the full vertical axis interval. Specifically, each horizontal axis coordinate within a horizontal axis interval is exhaustively paired with each vertical axis coordinate within the full vertical axis interval, resulting in a point set composed of all coordinate points. The rectangular envelope space enclosed by this point set in the pixel spatiotemporal mapping coordinate system is defined as the geometric region. By extracting all elements covered by the geometric region in the logical routing graph and calculating the arithmetic mean of the corresponding logical carrying capacity values, the average logical carrying capacity value within the geometric region is obtained. The geometric region is mapped to the logical routing graph. The set of matrix elements corresponding to the coordinate points in the point set is retrieved. The matrix elements corresponding one-to-one with each index address in the set of matrix elements are extracted, that is, the logical carrying capacity value of all coordinate units within the geometric region is obtained. The extracted logical carrying capacity values ​​are accumulated to obtain the total capacity value. The total number of index addresses in the set of matrix elements is obtained. The total capacity value and the total number are divided to obtain the average logical carrying capacity value. The inclusion relationship is determined and the average logical carrying capacity value is compared with the preset load safety threshold.The load safety threshold represents the minimum remaining resource ratio required to maintain stable signal transmission timing; for example, it is set to 0.15. If the average logical capacity value is greater than or equal to the load safety threshold, the current geometric region is retained as the logical segmentation region. Conversely, if the average logical capacity value is less than the load safety threshold, displacement compensation is performed in the coordinate direction where the logical capacity value increases and is greater than or equal to the load safety threshold. By translating the start or end address of the horizontal axis interval, the rectangular envelope space enclosed by the point set is redefined, thereby excluding coordinate units with logical capacity values ​​less than the load safety threshold from the geometric region and including coordinate units with logical capacity values ​​greater than or equal to the load safety threshold, until the average logical capacity value within the adjusted geometric region is greater than or equal to the load safety threshold, thus obtaining the logical segmentation region. The pixel mapping point coordinate pairs within the logical segmentation region are logically archived to generate a preliminary decoupled pixel cluster.

[0030] Step S13: Perform parallel temporal analysis and phase synchronization alignment based on the initial decoupled pixel clusters, and output the spatial topology matrix.

[0031] After obtaining the initial decoupled pixel clusters, in order to eliminate the hardware link transmission time difference caused by the non-equal distribution of the logically segmented regions, a time-series correlation quantization analysis is performed for each of the parallel channels.

[0032] Specifically, based on the pixel spatiotemporal mapping coordinate system, the physical layout center of each initially decoupled pixel cluster in the logical mapping space is determined. The physical layout center refers to the logical centroid coordinates obtained by performing a weighted average calculation using the horizontal and vertical components of all coordinate units within the geometric region in the pixel spatiotemporal mapping coordinate system, with the corresponding logical carrying capacity value as the weight. The wiring Manhattan distance relative to the origin of each physical layout center is then obtained. The wiring Manhattan distance refers to the sum of the lengths of the metal interconnect segments traversed along the horizontal and vertical axes when each initially decoupled pixel cluster crosses interconnect resources within the field-programmable gate array (FPGA), used to characterize the physical path differences of each parallel channel on the underlying hardware.

[0033] The transmission delay of the electrical signal pulse corresponding to the Manhattan distance of each wiring is statistically analyzed and defined as the path-based latency. The electrical signal pulse refers to the electrical signal representation driven by the effective pixel synchronization clock when the initially decoupled pixel cluster is transmitted in the logic mapping space. Specifically, the unit delay constant determined by the hardware process characteristics of the field-programmable gate array (FPGA) is obtained. The unit delay constant refers to the inherent physical time required for the electrical signal pulse to traverse a unit length of metal interconnect resources within the FPGA. The Manhattan distance of the wiring is multiplied by the unit delay constant to obtain the path-based latency. Simultaneously, the total number of clock cycles generated by the digital computation logic required to realize the single-pixel processing overhead within each parallel channel is obtained and defined as the computation-based latency. The total number of clock cycles refers to the number of discrete clock pulses experienced in a single complete computation task, driven by the effective pixel synchronization clock, to extract the digital response features for a single pixel mapping point coordinate pair and output the initial feature value. The initial feature value refers to the quantized value obtained after performing radiation intensity quantization processing on the digital signal corresponding to each pixel unit through digital computation logic.

[0034] The path-based latency and the computation-based latency are summed to obtain the cumulative time cost of each parallel channel. Using the largest cumulative time cost among all parallel channels as a benchmark, the differences between the remaining parallel channels and the benchmark are calculated. A two-dimensional data matrix matching the logical mapping space in spatial dimension is constructed, defined as the parallel latency sensing matrix. Based on the horizontal and vertical components of the pixel spatiotemporal mapping coordinate system, the matrix index positions in the parallel latency sensing matrix are locked. All coordinate units covered by the point set within the logical segmentation region are obtained. The corresponding differences are used as time compensation components shared by each coordinate unit in the point set and filled into the matrix index positions corresponding to each coordinate unit in the parallel latency sensing matrix, ensuring a one-to-one correspondence between each matrix element in the parallel latency sensing matrix and its physical position in the pixel spatiotemporal mapping coordinate system. Based on the differences recorded in the parallel latency sensing matrix, a first-in-first-out (FIFO) storage queue of corresponding depth is opened at the output end of each parallel channel as an elastic buffer. The depth refers to the maximum number of effective pixel synchronization clock cycles that the elastic buffer can temporarily store. For any parallel channel whose cumulative time overhead is less than the reference value, a clock cycle-level delay suspension operation is performed on the parallel processing data stream output by the corresponding elastic buffer. The parallel processing data stream refers to the digitized serial pulse sequence of pixel mapping point coordinates and corresponding preliminary feature values ​​generated after the digital computing logic within each parallel channel performs a single complete computation task for each initially decoupled pixel cluster. Specifically, the difference corresponding to the parallel channel is extracted from the parallel delay sensing matrix. The difference is divided by the period span of the effective pixel synchronization clock and rounded up to obtain the target delay cycle number for the parallel channel. The target delay cycle number represents the number of additional clock pulses that the parallel channel needs to delay to reach the reference value. When the parallel channel outputs the parallel processing data stream, the starting edge of the effective pixel synchronization clock is monitored in real time. The parallel processing data stream is received using the elastic buffer and data is temporarily stored; simultaneously, a counting operator is configured at the read end of the elastic buffer, which performs pulse accumulation counting on the effective pixel synchronization clock to obtain a count value. During the period when the counter value of the counter operator is less than the target delay cycle number, the read enable signal is kept in an inactive state by logic level control, causing the parallel processing data stream to temporarily remain inside the elastic buffer. When the counter value of the counter operator is greater than or equal to the target delay cycle number, the counter operator triggers a logic transition, activating the read enable signal of the elastic buffer. The parallel processing data stream then begins to be popped from the elastic buffer according to the first-in, first-out (FIFO) logic.The status of the elastic buffers corresponding to each parallel channel is monitored in real time. When all parallel channels have completed the clock cycle-level delay suspension operation and are all in the read-read state, the global frame start pulse is used to synchronously drive each parallel processing data stream, resulting in a phase-aligned parallel data stream with high consistency in the temporal phase, defined as a phase-aligned pixel stream. In order to restore the phase-aligned pixel stream to global spatial topological features, a pixel coordinate remapping operation is performed. Specifically, a two-dimensional data set for carrying spatial topological information is constructed, defined as a topology reconstruction matrix. The preliminary feature values ​​of the phase-aligned pixel stream are obtained and synchronously extracted in the pixel spatiotemporal mapping coordinate system. Using the pixel spatiotemporal mapping coordinate system as the spatial reference, each preliminary feature value is filled point-to-point into the matrix index position determined by the corresponding horizontal and vertical components in the topology reconstruction matrix. Through the pixel coordinate remapping, a spatial topology matrix is ​​obtained. The spatial topology matrix is ​​a two-dimensional quantized feature array that restores the geometric topological relationship of the photosensitive array in the spatial dimension and has undergone hardware delay calibration in the temporal phase.

[0035] Step S10 solves the technical challenges of linear accumulation of processing delay and inability to decouple spatial noise and thermal drift in real time caused by traditional serial processing architectures under large-area infrared specifications through the pixel spatiotemporal mapping coordinate system, pixel mapping point coordinate pairs, logical routing diagram, and spatial topology matrix. It realizes the accurate conversion of infrared image data from passive time series to active, high-fidelity two-dimensional spatial topology description and hardware-level parallel acceleration. Among them, the pixel spatiotemporal mapping coordinate system breaks the strong coupling of the bitstream in the time dimension and establishes a spatial mapping benchmark; the pixel mapping point coordinate pairs transform the one-dimensional discrete pixel sampling sequence number into spatial position coordinates with physical topological orientation; the logical routing diagram quantifies the hardware performance abundance of different regions within the logical mapping space to provide a decision basis for spatial decoupling; the spatial topology matrix restores the geometric topology relationship of the photosensitive array in the spatial dimension and outputs a two-dimensional quantized feature array that has been hardware delay-calibrated and phase-synchronized.

[0036] Step S20: Perform non-uniformity correction on the spatial topology matrix to obtain a primary correction pixel set; perform phase-locked noise reduction on the primary correction pixel set to obtain a denoised data stream; perform real-time blind pixel filling and logic verification on the denoised data stream to output an equalized correction bit stream.

[0037] Further, step S20 includes: Step S21: Perform non-uniformity correction on the spatial topology matrix to obtain the primary corrected pixel set.

[0038] After obtaining the spatial topology matrix, in order to eliminate the inconsistency in the output response of each pixel unit in the infrared detector due to uneven manufacturing process, amplitude gain alignment and level bias compensation operations are performed for each preliminary feature value.

[0039] Specifically, the calibration parameter matrix is ​​obtained from the on-chip memory stored within the field-programmable gate array (FPGA). The on-chip memory is a hardware storage entity composed of distributed storage units within the logic mapping space. The calibration parameter matrix refers to a two-dimensional feature data set composed of preset gain coefficients and bias coefficients. The gain coefficient characterizes the difference in sensitivity gain of each pixel unit to incident radiation energy, and its setting is based on the response efficiency distribution range of the infrared detector under different ambient temperatures. For example, the value range of the gain coefficient is set to 0.5 to 2. The bias coefficient characterizes the background output bias of each pixel unit under no-radiation excitation, and its setting is based on the offset deviation of the readout circuit under reference blackbody radiation. For example, the value range of the bias coefficient is set to an integer between -8192 and 8192. Due to the physical characteristic that the resistance of each pixel unit in an uncooled infrared detector changes with the radiation energy, the amplitude of the digital signal generated by each pixel unit is linearly positively correlated with the incident radiation energy. Therefore, real-time correction is performed. Specifically, using a multiply-accumulate unit, the initial eigenvalues ​​and gain coefficients in the spatial topology matrix are multiplied to obtain the first addend, which is then added to the bias coefficient, which serves as the second addend, to obtain the primary correction pixel set. The primary correction pixel set refers to the set of digitally corrected pixels that has eliminated response inconsistency interference and retained the physical topological properties of the spatial topology matrix. To meet the requirements of low power consumption and high timeliness when dealing with high-throughput pixel streams, a two-stage pipelined processing architecture is constructed. This two-stage pipelined processing architecture deploys the multiplication and addition operations within different clock cycles of the effective pixel synchronization clock, and utilizes the register resources inside the field-programmable gate array to achieve time-domain segmentation of the computation link, thereby avoiding the linear accumulation of signal transmission delays caused by excessively long combinational logic paths. The two-stage pipelined processing architecture effectively reduces the logic path length within a single clock cycle, which helps the infrared imaging system maintain a stable logic flip rate under complex temperature variations.

[0040] Step S22: Perform phase-locked noise reduction processing on the primary correction pixel set to obtain a denoised data stream.

[0041] After obtaining the primary correction pixel set, a filtering operation based on physical phase offset is performed to address the periodic sampling interference caused by phase jitter between the detector readout circuit and the sampling clock of the field-programmable gate array during the development of the infrared core.

[0042] Specifically, each time compensation component stored in the parallel delay sensing matrix is ​​extracted, and the discrete Fourier transform operation is performed on the discrete time-domain data sequence composed of each time compensation component within the single-frame pixel range to obtain the frequency domain energy distribution spectrum. The point with the largest energy amplitude in the frequency domain energy distribution spectrum is retrieved and defined as the frequency peak. The frequency value corresponding to the frequency peak is defined as the dominant frequency. The dominant frequency characterizes the most significant noise periodic feature caused by the difference in hardware link wiring delay. The ratio of the time compensation component to the period span of the effective pixel synchronization clock is defined as the phase offset ratio. The phase offset ratio is multiplied by the constant 2π to obtain the instantaneous phase angle. The constant 2π is referenced based on the phase periodicity principle in simple harmonic motion. Since the complete physical cycle of the periodic signal in the time dimension corresponds to a 2π radian period in the phase space, by calculating the ratio of the time offset to the clock period and mapping it to the closed interval from 0 to 2π, a deterministic conversion from time domain delay to frequency domain phase deviation is achieved. The discrete values ​​of all time-compensated components within a single frame pixel range are statistically analyzed, and half the difference between the maximum and minimum values ​​is calculated to obtain an amplitude estimate. Based on the time-compensated components, a virtual offset field with opposite phase to the periodic sampling interference is generated inside the field-programmable gate array (FPGA). This virtual offset field consists of multiple compensation components V, each corresponding to a pixel sampling number. These compensation components are used to offset the periodic sampling interference at the corresponding coordinate point during signal superposition by using level characteristics with opposite polarities. The calculation formula for the compensation components is as follows: ,in, , , , , These represent the amplitude estimate, dominant frequency, pixel sampling number, effective pixel synchronization clock period span, and instantaneous phase angle, respectively, with 2π and π being constants. The term represents a sine function, and the calculation formula is based on the principle of destructive interference of physical waveforms. Among them, the term... The time-varying phase used to reconstruct the periodic sampling interference, wherein, , The angular frequency characteristics of the noise were determined. , The pixel spatial index is mapped back to the physical time axis. The amplitude estimate is used to match the energy intensity of the periodic sampling interference, ensuring that the offset signal and the noise signal achieve energy balance in the amplitude dimension. The instantaneous phase angle is used to characterize the fixed phase deviation between parallel channels caused by hardware wiring delay, ensuring that the starting point of the compensation signal is precisely aligned with the physical starting phase of the noise. The reference to π is based on the principle of destructive interference, representing a 180-degree phase flip, making the polarity of the compensation component completely opposite to that of the original noisy signal, thus achieving mutual cancellation of physical energy during time-domain superposition. For each correction pixel in the primary correction pixel set corresponding to the pixel sampling index, the correction pixel and the corresponding compensation component in the virtual offset field are added in real time to obtain the denoised data stream. Here, the correction pixel refers to the discrete feature quantization unit in the primary correction pixel set, used to characterize the correction result after performing amplitude gain alignment and level bias compensation for each preliminary feature value.

[0043] Step S23: Perform real-time blind cell filling and logical verification on the denoised data stream, and output the equalized correction bit stream.

[0044] After acquiring the denoised data stream, real-time detection and spatial domain repair operations are performed on dynamic dead pixels generated by the infrared detector during aging or wide temperature range changes. A dead pixel refers to a pixel unit in the photosensitive array whose response output remains fixed at a high or low level or does not change with radiation energy, indicating a response failure.

[0045] Specifically, based on the pixel spatiotemporal mapping coordinate system, the correlation between the currently detected correction pixel and its 8 neighboring pixels is extracted from the denoised data stream. The 8 neighboring pixels refer to the quantized feature set formed by the correction pixels corresponding to the 8 discrete pixel mapping point coordinate pairs surrounding the current pixel mapping point coordinate pair within the logical mapping space. To quantify the deviation between the correction pixel and its surrounding spatial environment, the arithmetic mean of the grayscale response values ​​corresponding to the 8 neighboring pixels is calculated to obtain the reference neighborhood background value. The grayscale response value refers to the quantized value of the digital radiometric intensity carried by the correction pixel. The reference neighborhood background value characterizes the local radiometric intensity benchmark surrounding the current pixel mapping point coordinate pair. Dynamic blind pixel localization and real-time filling are performed on the reference neighborhood background value. Specifically, the correction pixel of the current pixel mapping point coordinate pair is subtracted from the reference neighborhood background value to obtain the numerical deviation. The numerical deviation characterizes the digital feature displacement of a single pixel unit from its physical spatial neighborhood statistical mean. An acute angle probability threshold is set to define the numerical boundary for determining whether a pixel unit possesses spatial response consistency. This threshold is based on a multiple of the standard deviation of the infrared detector's response noise under a stable blackbody radiation source. The aim is to isolate blind pixels caused by hardware limitations and actual physical defects by defining an upper limit for the spatial grayscale gradient. For example, for an infrared imaging system with a quantization depth of 14 bits, the acute angle probability threshold is set to a range of 128 to 512. When the absolute value of the detected numerical deviation is greater than the acute angle probability threshold for w consecutive frames, the current pixel mapping point coordinate pair is determined to be a dynamic blind pixel. Here, w is the number of frames. The number of frames is determined by the ratio of the thermal equilibrium response time of the vanadium oxide sensitive layer of the infrared detector's photosensitive array after radiative excitation to the frame period required for the infrared detector to output a single frame image. This aims to eliminate non-continuous numerical jumps caused by transient fluctuations in the vanadium oxide sensitive layer during heat exchange, ensuring the physical authenticity of the blind pixel determination. For example, it is set to 8.

[0046] For the coordinates of a pixel identified as a dynamic blind pixel, a logical overlay command is triggered synchronously. Specifically, the nearest neighbor valid pixel is retrieved from the 8 neighboring pixels. The nearest neighbor valid pixel refers to the correction pixel that is closest to the dynamic blind pixel in the pixel spatiotemporal mapping coordinate system in terms of physical distance and whose numerical deviation is less than the acute angle probability threshold. The grayscale response value of the nearest neighbor valid pixel is used to overlay the correction pixel at the dynamic blind pixel in real time to obtain a repaired correction pixel. The repaired correction pixel refers to the digitized quantization value obtained by performing logical replacement on the response failure features identified in the denoised data stream using spatial domain topological correlation. The repaired correction pixel is combined with the correction pixels that were not identified as dynamic blind pixels to obtain a pixel sequence. Logical verification is performed on the pixel sequence. Specifically, it is checked whether each grayscale response value in the pixel sequence is within the preset dynamic range range of the infrared imaging system. The dynamic range range is the validity boundary of the value determined by the analog-to-digital conversion bit depth of the infrared detector. For example, the dynamic range range is set to 0 to 16383. If the grayscale response value is within the dynamic range range, the grayscale response value is determined to be valid data, retained, and output as the result. Conversely, if the grayscale response value exceeds the dynamic range of digitization, it is determined to be overflow data. A normalization truncation process is then performed using hardware saturation logic. For example, if the dynamic range is 0 to 16383, a grayscale response value greater than 16383 is forcibly reset to 16383; a grayscale response value less than 0 is forcibly reset to 0. Through logical verification, an equalization correction bitstream is output.

[0047] Step S20 addresses the technical challenges of the "curtain effect" caused by uneven infrared detector manufacturing processes, the periodic "ripple" interference caused by phase jitter in the readout circuit, and dynamic pixel failure under wide-temperature conditions by using a calibration parameter matrix, a primary calibration pixel set, a virtual offset field, and an equalized calibration bitstream. This achieves consistent alignment of the entire array pixel response and physical phase offset suppression of underlying hardware noise. Specifically, the calibration parameter matrix provides gain and bias references for response alignment at each pixel coordinate; the primary calibration pixel set eliminates response inconsistency interference and preserves spatial topology properties; the virtual offset field utilizes the principle of destructive interference to cancel the energy of periodic sampling interference; and the equalized calibration bitstream outputs a highly spatially consistent quantized calibration bitstream through blind cell logic overlay and digital dynamic range verification.

[0048] Step S30: Perform saliency sensing operation based on equalization correction bitstream to obtain quantization mapping curve, perform real-time video reconstruction and power consumption adaptive control based on quantization mapping curve, and output video signal.

[0049] Further, step S30 includes: Step S31: Perform a saliency-aware operation based on the equalization correction bitstream to obtain the quantization mapping curve. After acquiring the equalized and corrected bitstream, a saliency sensing operation based on spatial topological features is performed to address the contradiction between the extremely wide dynamic range of the original signal and the minimal difference in target radiation in uncooled infrared imaging systems. Background regions in infrared scenes, such as the sky and flat ground, occupy a large number of quantization orders and contain low information entropy, while real targets, such as distant pedestrians and industrial hotspots, are often hidden within extremely narrow quantization intervals. Existing global histogram alignment schemes often overstretch the low-entropy background, resulting in severe grainy noise in the output image (i.e., background noise amplification) and causing spatial folding loss of high-frequency details during quantization mapping. To suppress background noise while achieving accurate capture of targets with minute temperature differences, a dynamic evaluation index capable of quantifying local texture activity is established.

[0050] Specifically, a K×K saliency perception window is constructed using each pixel mapping point coordinate pair as the logical center point, where K is the window size, determined by the ratio between the diffraction-limited Airy disk diameter of the infrared optical lens and the pixel center distance of the infrared detector's photosensitive array; for example, K is set to 3. Spatial gradient distribution features are extracted within the saliency perception window. These features are digitized vector sets characterizing the degree of change in pixel response values ​​relative to spatial coordinates within a local area. Specifically, the remaining pixels within the saliency perception window, excluding the logical center point, are defined... For each surrounding pixel, the absolute value of the difference between the grayscale response value of the logical center point and the grayscale response value of each surrounding pixel is calculated. These absolute differences are then summed and divided by the total number of surrounding pixels to obtain the local detail gradient value. This local detail gradient value is physically equivalent to the average grayscale dispersion between the logical center point and its surrounding pixels, and is used to characterize the saliency of local details at the coordinates of the currently detected pixel mapping point. Simultaneously, a noise suppression benchmark value is set to eliminate the interference of residual hardware background noise on contrast extraction. This noise suppression benchmark value is set based on the corresponding response noise standard deviation in the correction parameter matrix. By comparing the numerical relationship between the local detail gradient value and the noise suppression benchmark value, effective gradient features are extracted. Specifically, if the local detail gradient value is greater than the noise suppression benchmark value, the current pixel mapping point coordinate pair is determined to be in a non-smooth feature region. A subtraction operation is performed between the local detail gradient value and the noise suppression benchmark value to obtain the effective gradient feature quantity. If the local detail gradient value is less than or equal to the noise suppression benchmark value, the current pixel mapping point coordinate pair is determined to be in a smooth background region, and the effective gradient feature quantity is forcibly reset to 0. The extraction of the effective gradient feature quantity is based on the principle of nonlinear maximum value operation in physical signal processing. This aims to nonlinearly limit the local detail gradient value, so that small fluctuations within the noise suppression benchmark value are judged as invalid interference and zeroed out, while signals exceeding the noise suppression benchmark value are judged as effective components containing the target feature. Logical aggregation is performed on the complete pixel coordinate point set formed by the array specifications. This complete pixel coordinate point set is a two-dimensional matrix point set enclosed by the total number of rows and columns of the array specifications. The gray level is defined as the discrete order representing the distribution of gray-level response values ​​in the quantization space. The total number of gray levels is determined by the bit depth of the analog-to-digital conversion of the infrared detector. For example, for a 14-bit quantization specification, the gray level index is a set of integers from 0 to 16383. For each gray level within the complete set of pixel coordinates, all pixel mapping point coordinate pairs with gray level response values ​​equal to the gray level are retrieved, and the effective gradient feature quantities corresponding to the pixel mapping point coordinate pairs are summed to obtain the feature weight operator corresponding to each gray level.

[0051] Integral operations and normalization are performed on each feature weight operator to generate a quantization mapping curve. Specifically, the feature weight operators are recursively accumulated from low to high grayscale index to obtain the cumulative distribution value corresponding to each grayscale level. The sum of the feature weight operators corresponding to all grayscale levels is obtained. Each cumulative distribution value is divided by this sum and then multiplied by a preset target visual display quantization upper limit to obtain the mapped quantization value corresponding to each grayscale index. A quantization mapping curve is generated using all mapped quantization values ​​arranged in the order of grayscale indexes. The quantization upper limit refers to the highest effective quantization order determined by the hardware bit depth of the backend display terminal. See also... Figure 3 This diagram illustrates the principle of a saliency-aware window and feature weight generation quantization mapping curve provided by an embodiment of the present invention. The left side of the diagram illustrates a 3×3 saliency-aware window using a matrix grid, where the solid black circle represents the logical center point. Arrowed vector lines radiating from the logical center point to surrounding pixels illustrate the hardware logic for extracting spatial features. The right side of the diagram shows the quantization transformation space composed of gray-level indices and mapped quantization values. The solid waveform represents the quantization mapping curve, demonstrating the nonlinear projection relationship driven by the feature weight operator. Gray shaded areas mark the non-smooth feature regions determined by the effective gradient feature quantities. The horizontal dashed line in the diagram indicates the upper limit of quantization.

[0052] Step S32: Perform real-time video reconstruction and adaptive power consumption control based on the quantization mapping curve, and output the video signal.

[0053] After generating the quantization mapping curve, a real-time video reconstruction operation based on hardware status feedback is performed to address the surge in instantaneous heat consumption caused by the excessively high logic flip rate during the large-area data stream processing of the field-programmable gate array, as well as the nonlinear offset problem caused by non-uniform noise under extreme temperature difference conditions.

[0054] A video quantization projection path is constructed, and the conversion from the original signal to the visualized signal is achieved through point-to-point mapping logic. Specifically, the mapped quantization values ​​in the quantization mapping curve are stored in storage units within the logic mapping space. These storage units are the built-in block random access memory (BRAM) within a field-programmable gate array (FPGA). During storage, the grayscale index is used as the physical write address of the BRAM, and the corresponding mapped quantization value is stored in the corresponding storage space. Each grayscale response value contained in the equalization correction bitstream is used as a read addressing enable signal input to the address of the BRAM, executing the point-to-point mapping logic. This directly overwrites and replaces the input grayscale response value with the mapped quantization value, achieving real-time updating of pixel values. Since this replacement process does not involve cache sorting, it ensures that the pixel's arrangement order in the temporal sequence and its spatial position in the pixel spatiotemporal mapping coordinate system remain unchanged.

[0055] Meanwhile, to address the image non-uniformity noise and nonlinear offset issues caused by internal heat accumulation, power consumption constraint feedback control is implemented. Specifically, the junction temperature sensor inside the field-programmable gate array (FPGA) and a current sampling circuit integrated on the hardware motherboard are used to acquire the power consumption status of the FPGA in real time. The current sampling circuit refers to a hardware monitoring link used to capture the real-time current amplitude of the FPGA. The power consumption status represents the quantitative characteristics of the thermal power consumption level of the hardware processing unit, and its calculation is based on the product of the real-time current amplitude and the supply voltage of the FPGA. A power consumption safety threshold is also set, which is determined based on the overall thermal balance design specifications of the infrared imaging system and the heat dissipation rate of the FPGA at extreme operating temperatures, thus defining the upper limit of hardware operation. For example, the power consumption safety threshold is set to 2. The power consumption state quantity is compared with the power consumption safety threshold in real time. Only when the power consumption state quantity is greater than or equal to the power consumption safety threshold is the power consumption constraint feedback logic triggered. By increasing the generation interval period of the quantization mapping curve, the frequency of performing feature weight statistics and curve reconstruction tasks for the equalization correction bitstream is adjusted from frame-by-frame triggering to cross-frame triggering, thereby reducing the instantaneous flip rate of the logic gates inside the hardware processing unit and obtaining power consumption reduction pixels. The power consumption reduction pixels refer to quantization pixel units with steady-state thermal noise suppression characteristics generated by reducing the feature calculation frequency while maintaining hardware thermal balance. The power consumption reduction pixels are encapsulated in a protocol format to obtain a video signal. The video signal is a digital video data stream that integrates radiation feature reconstruction and standardized display timing.

[0056] Step S30 addresses the challenges of detail masking by high-dynamic backgrounds in infrared scenes, the surge in instantaneous heat consumption caused by large-area data streams, and imaging distortion due to heat accumulation by using a saliency-aware window, quantization mapping curves, power consumption state variables, and power consumption-reduced pixels. This achieves a dynamic balance between adaptive enhancement of high-fidelity image edge textures and system thermal stability and computational overhead. Specifically, the saliency-aware window extracts spatial gradient distribution features characterizing the saliency of edge structure textures to quantify the visual contribution of each grayscale interval; the quantization mapping curve establishes an address lookup table model for nonlinear projection of radiation features onto visual features to eliminate computational latency; the power consumption state variable uses junction temperature and current sampling to quantify the thermal power consumption level of the hardware processing unit in real time; and the power consumption-reduced pixels generate digital pixel units with steady-state thermal noise suppression characteristics through a cross-frame triggering strategy while maintaining hardware thermal balance.

[0057] Example 2 This embodiment, based on Embodiment 1, provides an FPGA-based parallel processing circuit for infrared image data, such as... Figure 4 As shown, it includes: Topology mapping module: used to acquire raw infrared radiation data stream, generate pixel mapping point coordinate pairs by establishing a pixel spatiotemporal mapping coordinate system, and perform hardware topology awareness and spatial domain decoupling processing based on pixel mapping point coordinate pairs, outputting a spatial topology matrix representing the spatial geometric relationship of pixels; Response Alignment Module: Used to call non-uniformity hardware compensation operators using spatial topology matrix to perform pixel response alignment, obtain primary corrected pixel set, and construct virtual counter-current field based on primary corrected pixel set to perform phase-locked noise reduction processing, resulting in equalized corrected bitstream with response consistency. Video reconstruction module: It is used to perform feature extraction on the equalization correction bitstream using a saliency-aware window, obtain feature weight operators and generate quantization mapping curves, perform real-time video reconstruction based on quantization mapping curves, and simultaneously perform adaptive power consumption control to output high-fidelity thermal imaging video signals.

[0058] In the topology mapping module, the process of acquiring the raw infrared radiation data stream, generating pixel mapping point coordinate pairs by establishing a pixel spatiotemporal mapping coordinate system, and performing hardware topology awareness and spatial decoupling processing based on the pixel mapping point coordinate pairs to output a spatial topology matrix representing the spatial geometric relationships of pixels includes: Acquire the raw infrared radiation data stream and obtain the pixel sampling sequence number through a pixel counter; The pixel sampling sequence number is moduloed and rounded down using the total number of columns to obtain the preliminary column index and preliminary row index respectively. The preliminary column index and preliminary row index are then subtracted by half of the total number of columns and rows respectively to generate pixel mapping point coordinate pairs. Based on the pixel mapping point coordinates, the physical layout center of the parallel channel is defined in the logical mapping space. The wiring Manhattan distance of each physical layout center relative to the coordinate origin is calculated. Based on the wiring Manhattan distance, an elastic buffer is configured at the end of each parallel channel to perform phase synchronization alignment and output the spatial topology matrix.

[0059] In the response alignment module, the step of using a spatial topology matrix to call a non-uniformity hardware compensation operator to perform pixel response alignment, obtaining a primary corrected pixel set, and constructing a virtual offset field based on the primary corrected pixel set to perform phase-locked noise reduction processing, resulting in an equalized corrected bitstream with response consistency, includes: The correction parameter matrix stored in the block random access memory is called to perform gain and bias alignment on each pixel in the spatial topology matrix to obtain the primary correction pixel set. The discrete Fourier transform is performed based on the primary correction pixel set to extract the dominant frequency, and a virtual countercurrent field with opposite polarity is generated. The periodic sampling interference is canceled out by the principle of destructive interference to obtain a denoised data stream. The pixel spatial response consistency is determined by using an acute angle probability threshold, and overlay filling is performed on pixels determined to have failed response, outputting an equalized correction bitstream.

[0060] In the video reconstruction module, the step of performing feature extraction on the equalization correction bitstream using a saliency-aware window to obtain feature weight operators and generate a quantization mapping curve, performing real-time video reconstruction based on the quantization mapping curve, and simultaneously performing adaptive power consumption control to output a high-fidelity thermal imaging video signal includes: Construct a saliency-aware window, calculate the difference in grayscale response values ​​between the logical center point and surrounding pixels, extract spatial gradient distribution features, and statistically analyze the feature weight operators for each grayscale level. The feature weight operator is recursively accumulated and normalized to generate a quantization mapping curve, which is then stored in a block random access memory to construct a video quantization projection path. The power consumption state is quantified in real time by a junction temperature sensor and a current sampling circuit. When the power consumption state exceeds a preset threshold, the generation interval period is increased to reduce the logic flip rate, output power consumption reduction pixels, and output video signals through the video quantization projection path.

[0061] In addition, the parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of the corresponding technical solutions in the prior art have not been described in detail, so as to avoid excessive elaboration.

[0062] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A parallel processing method for infrared image data based on FPGA, characterized in that, The method includes: The original infrared radiation data stream characterizing the thermal radiation intensity distribution of the target scene is acquired, and a pixel spatiotemporal mapping coordinate system is constructed to extract features from the original infrared radiation data stream to obtain pixel mapping point coordinate pairs. Hardware topology awareness and spatial decoupling are performed on the pixel mapping point coordinate pairs to obtain preliminary decoupled pixel clusters. Parallel temporal analysis and phase synchronization alignment are performed on the preliminary decoupled pixel clusters to output a spatial topology matrix. Non-uniformity correction is performed on the spatial topology matrix to obtain a primary correction pixel set. Phase-locked denoising is then performed on the primary correction pixel set to obtain a denoised data stream. Real-time blind pixel filling and logical verification are then performed on the denoised data stream to output an equalized correction bit stream. Based on the equalization correction bitstream, a saliency-aware operation is performed to obtain the quantization mapping curve. Based on the quantization mapping curve, real-time video reconstruction and adaptive power consumption control are performed to output the video signal.

2. The FPGA-based parallel processing method for infrared image data according to claim 1, characterized in that, The method for obtaining the pixel mapping point coordinate pairs includes: Obtain the pixel sampling sequence number corresponding to each pixel in the raw infrared radiation data stream; Determine the origin of the coordinate system in the pixel spatiotemporal mapping coordinate system, and determine the total number of columns and rows according to the array specifications of the infrared detector; By performing modulo and floor operations on the pixel sampling sequence number using the total number of columns, preliminary column indices and preliminary row indices are obtained, respectively. The preliminary column index and preliminary row index are respectively subjected to centering offset processing to obtain the horizontal axis component and the vertical axis component. The horizontal axis component and the vertical axis component are combined to obtain the pixel mapping point coordinate pair.

3. The FPGA-based parallel processing method for infrared image data according to claim 2, characterized in that, The preliminary decoupled pixel cluster includes: Based on the pixel mapping point coordinate pairs, the original infrared radiation data stream is deconstructed into multiple parallel channels, and the physical layout center of each parallel channel in the hardware physical layer is defined to determine the physical transmission path of the parallel channels. Extract the wiring Manhattan distance of each physical layout center relative to the coordinate origin, and quantify the path background delay of each parallel channel on the physical transmission path based on the wiring Manhattan distance; The computational background delay generated by the execution data buffer and logical mapping of the registers in each parallel channel is obtained, and the path background delay and the computational background delay are accumulated to obtain the preliminary decoupled pixel cluster.

4. The FPGA-based parallel processing method for infrared image data according to claim 3, characterized in that, The spatial topology matrix includes: Configure an elastic buffer at the end of each parallel channel and set a target delay cycle number that represents the timing alignment reference of all parallel channels; The period difference between the target delay cycle number and the path background delay corresponding to the initial decoupled pixel cluster loaded in each parallel channel and the sum of the calculated background delay is calculated. The elastic buffer is used to perform delay alignment processing based on the period difference to eliminate the transmission phase difference between parallel channels. After each parallel channel meets the target delay period, each initially decoupled pixel cluster is controlled to output synchronously from the elastic buffer to obtain the spatial topology matrix.

5. The FPGA-based parallel processing method for infrared image data according to claim 4, characterized in that, The primary correction pixel set includes: The correction parameter matrix stored in the block random access memory is invoked, and the correction parameter matrix contains the gain coefficient and bias coefficient corresponding to each pixel position; Gain alignment and bias alignment are performed on each pixel in the spatial topology matrix using gain and bias coefficients, and a primary corrected pixel set is output.

6. The FPGA-based parallel processing method for infrared image data according to claim 5, characterized in that, The denoised data stream includes: Perform a discrete Fourier transform on the primary correction pixel set to obtain the dominant frequency characterizing the periodic sampling interference; A virtual hedging field with opposite phase and opposite polarity is constructed based on the dominant frequency; The virtual offset field and the primary correction pixel set are synchronously superimposed. The energy offset is performed on the energy fluctuation component induced by the dominant frequency in the primary correction pixel set by utilizing the destructive interference principle between the virtual offset field and the primary correction pixel set, and the denoised data stream is output.

7. The FPGA-based parallel processing method for infrared image data according to claim 6, characterized in that, The equalization correction bitstream includes: Extract the correction pixel to be detected and its 8 neighboring pixels from the denoised data stream. The correction pixel is a discrete feature quantization unit in the primary correction pixel set, and the correction pixel carries grayscale response values. Calculate the arithmetic mean of the grayscale response values ​​of the 8 neighboring pixels to obtain the background value of the reference neighborhood; The grayscale response value corresponding to the correction pixel to be detected is subtracted from the background value of the reference neighborhood to obtain the numerical deviation. The acute angle probability threshold and the number of judgment frames are set. If the absolute value of the numerical deviation is greater than the acute angle probability threshold in a continuous number of judgment frames, the current pixel mapping point coordinate pair is determined to be a dynamic blind cell. The nearest pixel with a numerical deviation less than the acute angle probability threshold is retrieved from the 8 neighboring pixels and used as the nearest neighbor effective pixel to cover the correction pixel at the dynamic blind cell in real time, thus obtaining the repair correction pixel. The repaired and corrected pixels are combined with the corrected pixels that are not identified as dynamic blind pixels to form a pixel sequence, and the grayscale response value is detected to be within the preset dynamic range range. Only when the grayscale response value is greater than the dynamic range range is the equalized correction bitstream output.

8. The FPGA-based parallel processing method for infrared image data according to claim 7, characterized in that, The quantization mapping curve includes: A saliency perception window is constructed with each pixel mapping point coordinate pair as the logical center point. The absolute value of the difference between the grayscale response values ​​of the logical center point and its surrounding pixels is calculated to obtain the local detail gradient value. Set a noise suppression baseline value. If the local detail gradient value is greater than the noise suppression baseline value, the pixel mapping point coordinate pair is determined to be in a non-smooth feature region. The local detail gradient value and the noise suppression baseline value are subtracted to obtain the effective gradient feature value. Based on the definition of multiple gray levels according to the gray response values, for each gray level, the effective gradient feature quantities belonging to that gray level and located in the non-smooth feature region are accumulated to obtain the feature weight operator. The feature weight operators are recursively accumulated to obtain the cumulative distribution value. The sum of the feature weight operators and the preset quantization upper limit are combined to perform normalization mapping to obtain the mapped quantization value. All mapped quantization values ​​are then combined to form a quantization mapping curve.

9. The FPGA-based parallel processing method for infrared image data according to claim 8, characterized in that, The video signal includes: Each mapped quantization value is stored in a block random access memory to construct a lookup table, and the grayscale response value in the equalization correction bitstream is used as an addressing signal to output the corresponding mapped quantization value from the lookup table to complete the video reconstruction. The power consumption status during hardware operation is acquired in real time, and the generation interval period, which represents the update frequency of the quantization mapping curve, is set. Only when the power consumption state value is greater than or equal to the power consumption safety threshold, the generation interval period is increased to reduce the logic flip frequency used to calculate the quantization mapping curve, and a video signal is generated based on the reconstructed mapping quantization value.

10. An FPGA-based parallel processing circuit for infrared image data, used to implement the FPGA-based parallel processing method for infrared image data according to any one of claims 1-9, characterized in that, The system includes: Topology mapping module: used to acquire raw infrared radiation data stream, generate pixel mapping point coordinate pairs by establishing a pixel spatiotemporal mapping coordinate system, and perform hardware topology awareness and spatial domain decoupling processing based on pixel mapping point coordinate pairs, outputting a spatial topology matrix representing the spatial geometric relationship of pixels; Response Alignment Module: Used to call non-uniformity hardware compensation operators using spatial topology matrix to perform pixel response alignment, obtain primary corrected pixel set, and construct virtual counter-current field based on primary corrected pixel set to perform phase-locked noise reduction processing, resulting in equalized corrected bitstream with response consistency. Video reconstruction module: It is used to perform feature extraction on the equalization correction bitstream using a saliency-aware window, obtain feature weight operators and generate quantization mapping curves, perform real-time video reconstruction based on quantization mapping curves, and simultaneously perform adaptive power consumption control to output high-fidelity thermal imaging video signals.

Images