Circuit board and method of manufacturing the same

Abstract

The present disclosure provides a circuit board and a manufacturing method thereof. The circuit board according to an embodiment includes an insulating layer, a primer layer disposed on the insulating layer and including a first uneven portion, and a conductive line disposed on the first uneven portion of the primer layer. The conductive line includes a first conductive line including a second uneven portion corresponding to the first uneven portion, and a second conductive line disposed on the first conductive line.

Description

Technical Field

[0001] This disclosure relates to a circuit board and a method for manufacturing the same. Background Technology

[0002] Circuit boards include an insulating layer and circuit patterns formed on the insulating layer using conductive materials. Due to the recent trend of miniaturization and weight reduction of electronic components, higher density and finer circuit patterns are required.

[0003] To create more refined circuit patterns, various fabrication methods can be used, such as the tenting method, the modified semi-additive process (MSAP) method, and the semi-additive process (SAP) method.

[0004] The sealing method involves etching away unnecessary parts, which is easy to process circuit patterns, but difficult to perform fine processing.

[0005] The MSAP method is a method of forming circuit patterns on the remaining thin seed layer after etching copper foil, and it is advantageous for forming circuit patterns with a specific pitch or larger pitch. However, it is difficult to form fine circuit patterns with a specific pitch or smaller pitch using the MSAP method.

[0006] Because the SAP method forms circuit patterns solely through plating, there is almost no difference between the linewidths at the top and bottom of the circuit pattern. This makes the SAP method suitable for creating fine circuit patterns, but it involves complex processes and requires special materials. In particular, the prepreg contained in the copper clad laminate (CCL), the core layer material used in the SAP method, is unsuitable for forming circuit patterns using the SAP method due to its low plating adhesion. Summary of the Invention

[0007] The embodiments aim to provide a circuit board and a method thereof that can improve the adhesion of conductive lines to easily realize fine circuits of conductive lines and improve manufacturing yield.

[0008] However, the problems to be solved by the embodiments are not limited to those described above, and various extensions can be made within the scope of the technical ideas included in the embodiments.

[0009] A circuit board according to an embodiment of the present disclosure includes: an insulating layer; a base layer disposed on the insulating layer and including a first uneven portion; and a conductive line disposed on the first uneven portion of the base layer. The conductive line includes: a first conductive line including a second uneven portion corresponding to the first uneven portion; and a second conductive line disposed on the first conductive line.

[0010] The first conductive line may include a copper foil layer, and the second conductive line may include a seed line and a plated line disposed on the seed line.

[0011] The surface roughness of the first uneven portion may be greater than the surface roughness of the portion of the base coating that does not overlap with the first conductive line.

[0012] The second thickness can be greater than the first thickness, where the second thickness is the thickness of the plated line and the first thickness is the thickness of the seed line.

[0013] The second uneven portion may be located at the boundary surface between the base coating and the first conductive line.

[0014] The first uneven portion may protrude from the surface of the base coating, and the second uneven portion may be recessed from the surface of the first conductive wire.

[0015] The first uneven portion and the second uneven portion can be interlocked with each other.

[0016] The insulating layer may include a composite material, which may include resin and fiber, and the base layer may include a polymer.

[0017] The polymer may include at least one selected from epoxy resin, polyimide resin, polyamide-imide resin, polyamide resin, liquid crystal polymer resin, and cycloolefin resin.

[0018] The surface roughness (Ra) of the first uneven portion can be from 0.05 μm to 0.4 μm.

[0019] The first conductive wire may include copper.

[0020] A method for manufacturing a circuit board according to an embodiment includes: preparing an insulating layer and sequentially stacking a base layer and a first conductive layer on the insulating layer, the base layer including a first uneven portion, the first conductive layer including a second uneven portion corresponding to the first uneven portion; forming a seed layer on the first conductive layer; forming a pattern mask on the seed layer that exposes a first portion of the seed layer and covers a second portion of the seed layer; forming a plating line on the first portion of the seed layer; removing the pattern mask; and forming a conductive line, the step of forming the conductive line including removing the second portion of the seed layer and the portion of the first conductive layer located below the second portion of the seed layer.

[0021] The step of removing the second portion of the seed layer and the portion of the first conductive layer located below the second portion of the seed layer may include: reducing the surface roughness of the portion of the base layer located below the second portion of the seed layer to less than the surface roughness of the first uneven portion of the base layer.

[0022] The process for forming the seed layer may include an electroless plating process, and the process for forming the plating line may include an electroplating process.

[0023] The steps of forming the pattern mask may include: forming a dry film resist on the seed layer; and exposing and developing the dry film resist.

[0024] The step of forming the conductive line may further include: using the plating line as an etching mask to etch the second portion of the seed layer to form a seed line, thereby completing the second conductive line; and forming the first conductive line by using the plating line as an etching mask to etch the exposed portion of the first conductive layer.

[0025] According to an embodiment, the first uneven portion of the base coating and the second uneven portion of the first conductive line (for forming a seed layer for the conductive line) can interlock with each other, thereby improving the adhesion of the conductive line including the first conductive line. Therefore, fine circuitry of the conductive line can be easily achieved, and the manufacturing yield of the circuit board can be improved.

[0026] However, the effects of the embodiments are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. Attached Figure Description

[0027] Figure 1 This is a cross-sectional view of the circuit board according to an embodiment.

[0028] Figure 2 This is a schematic flowchart of a method for manufacturing a circuit board according to an embodiment.

[0029] Figures 3 to 6 These are cross-sectional views showing a method for manufacturing a circuit board according to an embodiment.

[0030] Figure 7 This is a diagram illustrating a method for measuring the adhesion of conductive lines on a circuit board according to an embodiment. Detailed Implementation

[0031] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings, enabling those skilled in the art to readily implement the embodiments. This disclosure may be modified in various ways without departing from its spirit or scope.

[0032] For clarity of description, parts or components not related to the description have been omitted, and identical or similar constituent elements are indicated by the same reference numerals throughout the specification.

[0033] Furthermore, the accompanying drawings are provided only to facilitate understanding of the embodiments disclosed in this specification, and the drawings should not be construed as limiting the spirit of the disclosure in this specification. It should be understood that this disclosure includes all modifications, equivalents, and substitutions without departing from the scope and spirit of this disclosure.

[0034] In the accompanying drawings, the dimensions and thicknesses of each element are shown arbitrarily for ease of description, but this disclosure is not limited to those shown in the drawings. In the accompanying drawings, the thicknesses of some layers and regions have been enlarged for clarity and ease of description.

[0035] It should be understood that when an element such as a layer, membrane, region, or plate is referred to as being "on" or "above" another element, it may be directly on the other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, the terms "on" or "above" may mean being disposed on or below a reference portion, and do not necessarily mean being disposed above the reference portion based on the direction of gravity.

[0036] Unless expressly stated to the contrary, the words “including,” “comprising,” and “having” should be understood as implying the inclusion of the stated element but excluding any other element.

[0037] Throughout the instruction manual, the phrases “in plan view” or “on a plane” can refer to the view of a portion of the object when viewed from above, and the phrases “in section view” or “on a section” can refer to the view of a section taken by vertically cutting the portion of the object when viewed from the side.

[0038] Furthermore, throughout the specification, “connection” means not only when two or more elements are directly connected, but also when two or more elements are indirectly connected through other elements, and when they are physically and / or electrically connected. In addition, “connection” can also mean that two or more elements are integrated with each other, although they are referred to by different names according to their location or function.

[0039] The various embodiments and modifications will now be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a cross-sectional view of the circuit board according to an embodiment.

[0041] like Figure 1As shown, the circuit board according to the embodiment may include an insulating layer 100, a base coating 200, and conductive lines 300.

[0042] The insulating layer 100 may include a composite material of resin and fiber. For example, the insulating layer 100 may include a prepreg, an Ajinomoto deposited film (ABF), a photosensitive imageable dielectric (PID), etc.

[0043] A base coating 200 may be disposed on the insulating layer 100 and may improve the adhesion between the insulating layer 100 and the conductive wire 300. The base coating 200 may have a first uneven portion 200a on the surface facing the first conductive wire 310. The first uneven portion 200a may protrude from the surface of the base coating 200. The surface roughness (Ra) of the first uneven portion 200a may be from 0.05 μm to 0.4 μm. In this case, the surface roughness of the first uneven portion 200a may be higher than the surface roughness of the portion of the base coating 200 that does not overlap with the first conductive wire 310. That is, in this embodiment, although the first uneven portion 200a is shown as being formed only below the first conductive wire 310, the portion of the base coating 200 that does not overlap with the first conductive wire 310 may also be finely textured to have a surface roughness lower than that of the first uneven portion 200a. The surface roughness may be measured by a profilometer or a laser scanner. Other methods and / or tools understood by those skilled in the art may be used, even if not described in this disclosure. In this document, "the first uneven portion 200a protrudes from the surface of the base coating 200" can mean, for example, that the base coating 200 may include a plurality of protrusions relative to the upper surface of the portion of the base coating 200 excluding the first uneven portion 200a, to form the first uneven portion 200a with a surface roughness (Ra) in the range of 0.05 μm to 0.4 μm. However, this embodiment is not limited to this, and the first uneven portion 200a may also be a plurality of recesses that are recessed (or sunken) relative to the surface of the base coating 200.

[0044] The base coating 200 may include a polymer. For example, the base coating 200 may include at least one of epoxy resin, polyimide (PI) resin, polyamide-imide (PAI) resin, polyamide (PA) resin, liquid crystal polymer (LCP) resin, and cyclic olefin (COP) resin.

[0045] Conductive lines 300 can be disposed on the first uneven portion 200a of the base coating 200. Conductive lines 300 can be applied to peripheral bumps, signal lines, etc. on circuit boards that require a high level of adhesion.

[0046] The conductive line 300 may include a stacked first conductive line 310 and a second conductive line 320.

[0047] The first conductive line 310 may include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, the first conductive line 310 may include copper (Cu), for example, the first conductive line 310 may be a copper (Cu) foil layer.

[0048] The first conductive line 310 may have a second uneven portion 310a on its surface corresponding to the first uneven portion 200a. The second uneven portion 310a may be disposed at the boundary surface between the base coating 200 and the first conductive line 310, that is, the second uneven portion 310a may be disposed at the surface of the first conductive line 310 that contacts the base coating 200.

[0049] The second uneven portion 310a may be recessed (or recessed) from the surface of the first conductive line 310 to insert into the first uneven portion 200a of the base coating 200. That is, the first uneven portion 200a and the second uneven portion 310a may interlock with each other, where "interlock" may mean that their shapes are almost perfectly matched, so that there is almost no gap between their interfaces. The first uneven portion 200a and the second uneven portion 310a may together form the uneven portion UE. Here, "the surface of the first conductive line 310" may refer to the surface coplanar with "the upper surface of the portion of the base coating 200 other than the first uneven portion 200a", and "the second uneven portion 310a is recessed (or recessed) from the surface of the first conductive line 310" may mean, for example, that the first conductive line 310 may include a plurality of recesses that are recessed relative to the lower surface of the first conductive line 310 to form a second uneven portion 310a corresponding to the first uneven portion 200a. However, this embodiment is not limited to this. The second uneven portion 310a may also be a plurality of protrusions that protrude relative to the surface of the first conductive line 310, as long as they can interlock with the first uneven portion 200a.

[0050] Because the first uneven portion 200a of the base coating 200 and the second uneven portion 310a of the first conductive line 310 are in contact with each other and interlock, the adhesion of the conductive line 300 including the first conductive line 310 can be improved. Therefore, fine circuitry of the conductive line 300 can be easily realized, and the manufacturing yield of the circuit board can be improved.

[0051] The second conductive line 320 may have the same pattern as the first conductive line 310, and may be disposed on the first conductive line 310. That is, on a plane, the second conductive line 320 and the first conductive line 310 may overlap each other, and the boundary lines at both ends of the second conductive line 320 and the boundary lines at both ends of the first conductive line 310 may coincide with each other.

[0052] The second conductive line 320 may include a seed line 321 and a plated line 322.

[0053] Seed wire 321 can serve as a seed layer for forming plated wires through a plating process. Seed wire 321 may include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0054] The plating line 322 can be a plating layer plated using a seed line 321 as a seed layer. In this case, because the plating line 322 is a plating layer and the seed line 321 is a seed layer, the thickness of the plating line 322—the second thickness t2—can be greater than the thickness of the seed line 321—the first thickness t1. The first thickness t1 and the second thickness t2 can be measured by scanning electron microscopy. Other methods and / or tools understood by those skilled in the art may be used even if not described in this disclosure.

[0055] The plated line 322 may include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0056] Then, refer to Figures 2 to 6 Together Figure 1 A method for manufacturing a circuit board according to an embodiment is described in detail.

[0057] Figure 2 This is a schematic flowchart of a method for manufacturing a circuit board according to an embodiment. Figures 3 to 6 These are cross-sectional views showing a method for manufacturing a circuit board according to an embodiment.

[0058] like Figure 2 and Figure 3 As shown, an insulating layer 100 can be prepared, and a base layer 200 and a first conductive layer 30 are sequentially stacked on the insulating layer 100 (S100).

[0059] In this case, a base layer 200 can be formed on the insulating layer 100, and the first conductive layer 30 can be formed by applying pressure to the base layer 200, or the base layer 200 on which the first conductive layer 30 has been formed by applying pressure can be attached to the insulating layer 100 to form the first conductive layer 30.

[0060] Because the first conductive layer 30 has a second uneven portion 310a, by applying pressure to the first conductive layer 30, the shape of the second uneven portion 310a can be transferred onto the surface of the undercoating layer 200 that contacts the second uneven portion 310a, thereby forming the first uneven portion 200a on the surface of the undercoating layer 200. The first conductive layer 30 may include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first conductive layer 30 may be a copper (Cu) foil. The first uneven portion 200a and the second uneven portion 310a may be formed together to form the uneven portion UE.

[0061] Next, as Figure 2 and Figure 4 As shown, a seed layer 40 can be formed on the first conductive layer 30 by an electroless plating process (S200). The seed layer 40 may include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0062] Next, a pattern mask PM can be formed to expose the first portion 41 of the seed layer 40 (S300). In this case, the pattern mask PM can cover the remaining portion of the seed layer 40 other than the first portion 41—the second portion 42.

[0063] A pattern mask PM can be formed by forming a dry film resist (DFR) on the first conductive layer 30 and exposing and developing the dry film resist.

[0064] Next, as Figure 2 and Figure 5 As shown, plating lines 322 can be formed on the exposed first portion 41 of the seed layer 40 by an electroplating process (S400).

[0065] Next, as Figure 2 and Figure 6 As shown, the pattern mask PM can be removed (S500). Therefore, the second portion 42 of the seed layer 40, which is located below the pattern mask PM, can be exposed to the outside.

[0066] Next, as Figure 1 and Figure 2 As shown, the plating line 322 can be used as an etching mask to simultaneously etch the second portion 42 of the seed layer 40 and the second portion 32 of the first conductive layer 30. Figure 6 The portion of the first conductive layer 30 shown below the second portion 42 of the seed layer 40 is used to form the conductive line 300 (S600).

[0067] Specifically, because the plating line 322 is used as an etching mask to etch the second portion 42 of the seed layer 40, the first portion 41 of the seed layer 40 can retain the same pattern as the plating line 322 to form the seed line 321, thereby forming a second conductive line 320 including the seed line 321 and the plating line 322. Since the second portion 32 of the first conductive layer 30 (the portion of the first conductive layer 30 exposed using the plating line 322 as an etching mask) is successively etched, therefore... Figure 6 The first portion 31 of the first conductive layer 30 shown may retain the same pattern as the pattern of the second conductive line 320 to form the first conductive line 310. Therefore, a conductive line 300 including the second conductive line 320 and the first conductive line 310 can be formed.

[0068] In this case, while etching the second portion 32 of the first conductive layer 30, the surface roughness can be reduced by etching the surface of the undercoating layer 200 disposed below the second portion 32 of the first conductive layer 30. Therefore, the surface roughness of the first uneven portion 200a can be higher than the surface roughness of the portion of the undercoating layer 200 that does not overlap with the first conductive line 310.

[0069] Because the conductive line 300 is formed using the MSAP method, the linewidth of the conductive line 300 can be minimized. Furthermore, because the first uneven portion 200a of the base coating 200 and the second uneven portion 310a of the first conductive line 310 interlock with each other, the contact area between the base coating 200 and the first conductive line 310 can be increased, thereby improving the adhesion of the conductive line 300 including the first conductive line 310. Therefore, fine circuitry of the conductive line 300 can be easily achieved, and the manufacturing yield of the circuit board can be improved.

[0070] Because the conductive line 300 is formed using the base coating 200 via the MSAP method, the adhesion of the conductive line 300 is improved compared to the conventional SAP method or conventional MSAP method.

[0071] Figure 7 This is a diagram illustrating a method for measuring the adhesion of conductive lines on a circuit board according to an embodiment.

[0072] like Figure 7 As shown, the first sample S1 can be manufactured by conventional SAP method, the second sample S2 can be manufactured by conventional MSAP method, and the third sample S3 can be manufactured by MSAP method using the base coating 200 of this embodiment.

[0073] Specifically, a conventional SAP method can form a first sample S1 with conductive lines by the following steps: A base layer can be formed on an insulating layer of the sample, and a seed layer can be formed on the base layer by electroless plating. A pattern mask can then be formed on the seed layer, and a plating layer can be formed on the seed layer exposed by the pattern mask by electroplating. The pattern mask can then be removed, and the seed layer exposed by the removed pattern mask can be removed to form the conductive lines.

[0074] Alternatively, the conventional MSAP method can form a second sample S2 with conductive lines using the following method: A copper foil layer can be formed on the sample insulating layer, and a seed layer can be formed on the copper foil layer by electroless plating. Then, a pattern mask can be formed on the seed layer, and a plating layer can be formed on the seed layer exposed by the pattern mask by electroplating. The pattern mask can then be removed, and the seed layer and copper foil layer exposed by the removed pattern mask can be removed together by an etching process to form the conductive lines.

[0075] Additionally, it can be at multiple locations in each of the first sample S1, the second sample S2, and the third sample S3 (e.g., Figure 7 The adhesion of the conductive wire 300 is measured at the first position P1, the second position P2, the third position P3, the fourth position P4 and the fifth position P5 shown in the figure.

[0076] In this case, for the first sample S1, the second sample S2, and the third sample S3, the adhesion can be measured by separating the conductive wire 300 from the insulating layer 100.

[0077] Table 1 below shows the adhesion force of the conductive wire 300 measured at the first position P1, the second position P2, the third position P3, the fourth position P4, and the fifth position P5 for each of the first sample S1, the second sample S2, and the third sample S3.

[0078] (Table 1)

[0079] As shown in Table 1, the average adhesion force of the first sample S1 manufactured by the conventional SAP method can be 0.63 kgf / cm. 2 Furthermore, the average adhesion force of the second sample S2, manufactured using the conventional MSAP method, can be 0.72 kgf / cm². 2 However, the average adhesion force of the third sample S3 manufactured through this embodiment can be 1.2 kgf / cm. 2 Therefore, it can be seen that the adhesion strength of this embodiment is improved by more than 60% compared with the conventional MSAP method.

[0080] Although this disclosure has been described in conjunction with what are now considered to be actual embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims.

Claims

1. A circuit board, comprising: Insulating layer; A base coating layer is disposed on the insulating layer and includes a first uneven portion; as well as Conductive wires are disposed on the first uneven portion of the base coating. The conductive wire includes: A first conductive line, including a second uneven portion corresponding to the first uneven portion; and The second conductive wire is disposed on the first conductive wire.

2. The circuit board as claimed in claim 1, wherein, The first conductive line includes a copper foil layer, and the second conductive line includes a seed line and a plated line disposed on the seed line.

3. The circuit board as described in claim 2, wherein, The surface roughness of the first uneven portion is greater than the surface roughness of the portion of the base coating that does not overlap with the first conductive line.

4. The circuit board as described in claim 2, wherein, The second thickness is greater than the first thickness, where the second thickness is the thickness of the plated wire and the first thickness is the thickness of the seed wire.

5. The circuit board as described in claim 2, wherein, The second uneven portion is located at the boundary surface between the base coating and the first conductive line.

6. The circuit board as claimed in claim 5, wherein, The first uneven portion protrudes from the surface of the base coating, and the second uneven portion is recessed from the surface of the first conductive wire.

7. The circuit board as claimed in claim 6, wherein, The first uneven portion and the second uneven portion are interlocked with each other.

8. The circuit board as claimed in claim 1, wherein, The insulating layer comprises a composite material, which includes resin and fiber, and the base layer comprises a polymer.

9. The circuit board as claimed in claim 8, wherein, The polymer includes at least one selected from epoxy resin, polyimide resin, polyamide-imide resin, polyamide resin, liquid crystal polymer resin, and cyclic olefin resin.

10. The circuit board as claimed in claim 1, wherein, The surface roughness (Ra) of the first uneven portion is 0.05 μm to 0.4 μm.

11. The circuit board as claimed in claim 1, wherein, The first conductive wire comprises copper.

12. A method for manufacturing a circuit board, comprising: An insulating layer is prepared and a base layer and a first conductive layer are sequentially stacked on the insulating layer. The base layer includes a first uneven portion, and the first conductive layer includes a second uneven portion corresponding to the first uneven portion. A seed layer is formed on the first conductive layer; A pattern mask is formed on the seed layer that exposes a first portion of the seed layer and covers a second portion of the seed layer; A plating line is formed on the first portion of the seed layer; Remove the pattern mask; as well as The step of forming the conductive line includes removing the second portion of the seed layer and the portion of the first conductive layer located below the second portion of the seed layer.

13. The manufacturing method as described in claim 12, wherein, The step of removing the second portion of the seed layer and the portion of the first conductive layer located below the second portion of the seed layer includes: reducing the surface roughness of the portion of the base layer located below the second portion of the seed layer to less than the surface roughness of the first uneven portion of the base layer.

14. The manufacturing method as described in claim 12, wherein, The process for forming the seed layer includes an electroless plating process, and the process for forming the plating line includes an electroplating process.

15. The manufacturing method as described in claim 12, wherein, The steps for forming the pattern mask include: A dry film resist is formed on the seed layer; and The dry film resist is exposed and developed.

16. The manufacturing method as described in claim 12, wherein, The step of forming the conductive wire further includes: Using the plated line as an etching mask, the second portion of the seed layer is etched to form a seed line, thereby completing the second conductive line; and The first conductive line is formed by etching the exposed portion of the first conductive layer using the plating line as an etching mask.

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