Wiring substrate

Abstract

A wiring substrate with good connection quality to an external substrate. A wiring substrate (1) includes a first substrate (10) having a first surface (10F) and a second surface (10S), and having a first core substrate (100) and a first buildup portion (10B), and a second substrate (20) having a third surface (20F) and a fourth surface (20S), and having a second core substrate (200) and a second buildup portion (20B). The second surface (10S) of the first substrate (10) and the third surface (20F) of the second substrate (20) are connected via a conductive connection element (BP), the fourth surface (20S) of the second substrate (20) is configured as a component mounting surface, the first surface (10F) of the first substrate (10) is configured as a substrate connection surface, the second core substrate (200) includes a glass substrate (201), the first core substrate (100) includes a resin substrate (101), the thermal expansion rate of the first substrate (10) is greater than the thermal expansion rate of the second substrate (20), and the thermal expansion rate of the first substrate (10) is 7 ppm or more and 15 ppm or less.

Description

Technical Field

[0001] This invention relates to wiring substrates. Background Technology

[0002] Patent Document 1 discloses a wiring circuit board having a glass substrate, an insulating resin layer formed on the glass substrate, and wiring arrays stacked on the insulating resin layer. A semiconductor element is connected to one side of the wiring circuit board, and an external printed circuit board is connected to the other side via connection elements such as solder balls and conductive bumps.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-5174

[0004] In the wiring circuit board disclosed in Patent Document 1, it is believed that the following situation exists: poor connection caused by thermal stress occurs in the connection of the connection element via the printed circuit board, which is an external element, and sufficient connection quality cannot be obtained between it and the external element. Summary of the Invention

[0005] The wiring substrate of the present invention comprises: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate having a first core substrate and a first laminate portion, the first laminate portion comprising a first insulating layer and a first conductive layer alternately laminated on both surfaces of the first core substrate; and a second substrate having a third surface and a fourth surface opposite to the third surface, the second substrate having a second core substrate and a second laminate portion, the second laminate portion comprising a second insulating layer and a second conductive layer alternately laminated on both surfaces of the second core substrate. The second surface of the first substrate and the third surface of the second substrate are connected via conductive connecting elements, the fourth surface of the second substrate is configured as a component mounting surface, the first surface of the first substrate is configured as a substrate connecting surface, the second core substrate comprises a glass substrate, the first core substrate comprises a resin substrate, the thermal expansion coefficient of the first substrate is greater than the thermal expansion coefficient of the second substrate, and the thermal expansion coefficient of the first substrate is 7 ppm or more and 15 ppm or less.

[0006] According to embodiments of the present invention, a high-quality wiring substrate can be provided for connection with an external substrate. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view illustrating an example of a wiring substrate according to one embodiment of the present invention.

[0008] Figure 2A This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0009] Figure 2BThis is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0010] Figure 2C This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0011] Figure 3A This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0012] Figure 3B This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0013] Figure 3C This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0014] Figure 3D This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0015] Figure 4A This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0016] Figure 4B This is a cross-sectional view illustrating an example of the manufacturing process of a wiring substrate according to one embodiment.

[0017] Label Explanation

[0018] 1: Wiring substrate; 10: First substrate; 20: Second substrate; 10B: First stacked layer; 20B: Second stacked layer; 11: Insulating layer (first insulating layer); 21: Insulating layer (second insulating layer); 12: Conductor layer (first conductor layer); 22: Conductor layer (second conductor layer); 13: Via conductor (first via conductor); 23: Via conductor (second via conductor); 100: First core substrate; 101: Resin substrate; 102: First core conductor layer; 200: Second core substrate; 201: Glass substrate; 103: Through conductor (first through conductor); 203: Through conductor (second through conductor); 12fp: Conductor pad (substrate connection pad); 12sp, 22fp: Conductor pad; 22sp: Conductor pad (component mounting pad); BP: Connection element; EA: Component mounting area. Detailed Implementation

[0019] The wiring substrate of the present invention is described with reference to the accompanying drawings. Figure 1A cross-sectional view of wiring substrate 1, as an example of a wiring substrate according to an embodiment, is shown. However, wiring substrate 1 is merely one example of a wiring substrate according to an embodiment. For example, the layered structure of the wiring substrate of the embodiment and the number of conductor layers and insulating layers included in the wiring substrate of the embodiment are not limited to [specific details needed]. Figure 1 The layered structure of the wiring substrate 1 and the number of conductor layers and insulating layers included in the wiring substrate 1 are described. In addition, in the figures referred to in the following description, certain parts are sometimes depicted in enlarged form for easy understanding of the disclosed embodiments, and structural elements are sometimes not depicted in precise proportions to each other regarding size and length.

[0020] The wiring substrate of the embodiment includes two substrates (a first substrate and a second substrate). The first and second substrates are composed of a core substrate and a laminated portion, which is composed of insulating and conductive layers alternately stacked on both sides of the core substrate. The wiring substrate 1 of the illustrated example includes a first substrate 10 and a second substrate 20. The first substrate 10 has a first surface 10F and a second surface 10S opposite to the first surface 10F as two main surfaces perpendicular to its thickness direction. The second substrate 20 has a third surface 20F and a fourth surface 20S opposite to the third surface 20F as two main surfaces perpendicular to its thickness direction. The second substrate 20 is arranged such that the third surface 20F faces the second surface 10S of the first substrate 10, and is connected to the first substrate 10 via a connection element BP. Furthermore, in the wiring substrate 1 of the illustrated example, the first substrate 10 and the second substrate 20 have substantially equal shapes and dimensions in planar shape. Here, "planar shape" refers to the shape identified when the wiring substrate 1 is viewed from a line of sight parallel to its thickness direction (i.e., viewed from above).

[0021] In the wiring substrate 1, the first substrate 10 has a first core substrate 100, which has a resin substrate 101 and a first core conductor layer 102 formed in contact with two surfaces of the resin substrate 101 perpendicular to the thickness direction. The first core substrate 100 has a surface 100f and another surface 100s opposite to the surface 100f. A first insulating layer 11 and a first conductor layer 12 are respectively stacked on both surfaces (surface 100f and surface 100s) of the first core substrate 100, and a total of two first insulating layers 11 and two first conductor layers 12 constitute the first laminate portion 10B included in the first substrate 10.

[0022] The second substrate 20 has a second core substrate 200 made of a glass substrate 201. The second core substrate 200 has one surface 200f and another surface 200s opposite to the first surface 200f. Five layers of second insulating layer 21 and five layers of second conductor layer 22 are respectively stacked on both surfaces (one surface 200f and the other surface 200s) of the second core substrate 200, and the total of 10 layers of second insulating layer 21 and 10 layers of second conductor layer 22 constitute the second laminate portion 20B included in the second substrate 20.

[0023] Furthermore, regarding the description of the wiring substrate in the embodiment, in the description of the structural elements of the first substrate 10, the side of the first core substrate 100 closest to the resin substrate 101 is referred to as "lower," "inner," or "lower side," and the side furthest from the resin substrate 101 is referred to as "upper," "outer," or "upper side," and the side facing away from the resin substrate 101. The surface of each element constituting the first substrate 10 facing the resin substrate 101 is also referred to as the "lower surface," and the surface facing the opposite side to the resin substrate 101 is also referred to as the "upper surface." Similarly, in the description of the structural elements of the second substrate 20, the side closest to the glass substrate 201 constituting the second core substrate 200 is referred to as "lower" or "lower side," and the side furthest from the glass substrate 201 is referred to as "upper" or "upper side." Therefore, the surface of each element constituting the second substrate 20 facing the glass substrate 201 is referred to as the "lower surface," and the surface facing the opposite side to the glass substrate 201 is also referred to as the "upper surface."

[0024] The first core conductor layer 102 of the first core substrate 100 constituting the first substrate 10, which is grounded to both sides of the resin substrate 101, is connected by a through conductor 103 that penetrates the resin substrate 101 in the thickness direction. The first core substrate 100 may include a plurality of through conductors 103. Through-hole conductors 13 are formed in the first insulating layer 11 constituting the first substrate 10, and these through conductors 13 penetrate the first insulating layer 11 in the thickness direction, connecting conductors (first conductor layers 12 to each other, or first conductor layer 12 and first core conductor layer 102) that are facing each other across the first insulating layer 11. On the glass substrate 201 of the second core substrate 200 constituting the second substrate 20, a through conductor 203 that penetrates the glass substrate 201 in the thickness direction is formed. The second core substrate 200 may include a plurality of through conductors 203. Through-hole conductors 23 are formed in the second insulating layer 21 constituting the second substrate 20. These through-hole conductors 23 penetrate the second insulating layer 21 in the thickness direction, connecting conductors (second conductor layers 22 to each other, or second conductor layers 22 and through-hole conductors 203) that are separated by the second insulating layer 21. Furthermore, the through-hole conductor 103 included in the first core substrate 100 is also referred to as the first through-hole conductor 103, and the through-hole conductor 203 included in the second core substrate 200 is also referred to as the second through-hole conductor 203. Additionally, the through-hole conductor 13 formed in the first insulating layer 11 is also referred to as the first through-hole conductor 13, and the through-hole conductor 23 formed in the second insulating layer 21 is also referred to as the second through-hole conductor 23.

[0025] The first through conductor 103 includes: a conductive conductor film 113 covering the inner wall of the through hole 101a formed in the resin substrate 101; and a filler material 123 filling the area (void) defined by the conductor film 113, such as an insulating resin. That is, the first through conductor 103 includes a conductive conductor film 113 and a filler material 123 filling the inner side of the conductor film 113. The conductor film 113 constituting the first through conductor 103 is integrally formed with the first core conductor layer 102. The second through conductor 203 is formed by filling the through hole 201a formed in the glass substrate 201 with a conductor. In the illustrated example, the end face of the second through conductor 203 in the extending direction is formed to be substantially coplanar with the surface of the glass substrate 201, constituting one surface 200f and another surface 200s of the second core substrate 200.

[0026] The first via conductor 13 is formed by filling a through hole 11a formed in the first insulating layer 11 with a conductive material. The first via conductor 13 is integrally formed with the first conductor layer 12, which is in contact with the surface of the first insulating layer 11 through which the first via conductor 13 penetrates, opposite to the first core substrate 100. The second via conductor 23 is formed by filling a through hole 21a formed in the second insulating layer 21 with a conductive material. The second via conductor 23 is integrally formed with the second conductor layer 22, which is in contact with the surface of the second insulating layer 21 through which the second via conductor 23 penetrates, opposite to the second core substrate 200.

[0027] The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 are formed using any insulating resin. Examples of insulating resins include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, as well as thermoplastic resins such as fluoropolymers, liquid crystal polymers (LCP), fluorinated vinyl ester (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 may contain inorganic fillers (not shown) such as silica or alumina. The resin substrate 101, the first insulating layer 11, and the second insulating layer 21 may also contain reinforcing materials (core materials) such as glass fibers or aramid fibers. In the illustrated example, the resin substrate 101 contains reinforcing material 101s.

[0028] The glass material used for the glass substrate 201 constituting the second core substrate 200 can be, for example, soda lime glass, borosilicate glass, or alkali-free glass. These glasses may contain elements such as magnesium, calcium, manganese, aluminum, lead, iron, chromium, potassium, sulfur, antimony, and boron as additives. In the wiring substrate of this embodiment, the core substrate of the first substrate is made of an insulating resin with a relatively high coefficient of thermal expansion, while the core substrate of the second substrate is made of a glass material with a relatively low coefficient of thermal expansion.

[0029] As conductors constituting the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the second through conductor 203, the first through conductor 103, and the first core conductor layer 102, examples include copper and nickel, with copper being preferred. Figure 1In the example shown, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, the second through conductor 203, and the first core conductor layer 102 are each shown as a single layer, but can be constructed in a multilayer structure. For example, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, the second through conductor 203, and the first core conductor layer 102 can have a multilayer structure including any one of a metal foil layer (preferably copper foil), a metal film layer (preferably a copper film formed by chemical plating or sputtering), and a plating film layer (preferably an electroplated copper film). For example, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 113, and the second through conductor 203 can have a double-layer structure including a metal film layer and a plating film layer. The first core conductor layer 102 can have a five-layer structure including a metal foil layer, a metal film layer, and a plating film layer.

[0030] Each conductor layer (first conductor layer 12, second conductor layer 22, and first core conductor layer 102) constituting the wiring substrate 1 is patterned with a predetermined conductor pattern. The first conductor layer 12 constituting the first surface 10F of the first substrate 10 is formed with a pattern having multiple conductor pads 12fp. The first conductor layer 12 constituting the second surface 10S of the first substrate 10 is formed with a pattern having multiple conductor pads 12sp. The second conductor layer 22 constituting the third surface 20F of the second substrate 20 is formed with a pattern having multiple conductor pads 22fp. The second conductor layer 22 constituting the fourth surface 20S of the second substrate 20 is formed with a pattern having multiple conductor pads 22sp.

[0031] In the first substrate 10, a solder resist layer 10Rf, formed of, for example, photosensitive polyimide resin or epoxy resin, is stacked on the outermost first conductor layer 12 on one side 100f of the first core substrate 100. An opening 10Rfa is formed in the solder resist layer 10Rf, through which a conductor pad 12fp is exposed. That is, the first side 10F of the first substrate 10 includes the surface of the solder resist layer 10Rf and the surface of the conductor pad 12fp exposed from the opening 10Rfa. A solder resist layer 10Rs is stacked on the outermost first conductor layer 12 on the other side 100s of the first core substrate 100. An opening 10Rsa is formed in the solder resist layer 10Rs, through which a conductor pad 12sp is exposed. That is, the second side 10S of the first substrate 10 includes the surface of the solder resist layer 10Rs and the surface of the conductor pad 12sp exposed from the opening 10Rsa.

[0032] A solder resist layer 20Rf is stacked on the outermost second conductor layer 22 on one side 200f of the second core substrate 200. An opening 20Rfa is formed in the solder resist layer 20Rf, through which conductor pads 22fp are exposed. That is, the third side 20F of the second substrate 20 includes the surface of the solder resist layer 20Rf and the surface of the conductor pads 22fp exposed from the opening 20Rfa. A solder resist layer 20Rs is stacked on the outermost second conductor layer 22 on the other side 200s of the second core substrate 200. An opening 20Rsa is formed in the solder resist layer 20Rs, through which conductor pads 22sp are exposed. That is, the fourth side 20S of the second substrate 20 includes the surface of the solder resist layer 20Rs and the surface of the conductor pads 22sp exposed from the opening 20Rsa.

[0033] As described above, the first core substrate 100 constituting the first substrate 10 includes a resin substrate 101 made of an insulating resin with a relatively high coefficient of thermal expansion, and the second core substrate 200 constituting the second substrate 20 includes a resin substrate 101 made of a glass material with a relatively low coefficient of thermal expansion. Therefore, the coefficient of thermal expansion of the first substrate 10 as a whole differs from that of the second substrate 20 as a whole. Specifically, in the wiring substrate of the embodiment, the coefficient of thermal expansion of the first substrate 10 is greater than that of the second substrate 20.

[0034] The fourth surface 20S of the second substrate 20, which forms the outermost surface of the wiring substrate 1, is configured as a component mounting surface for connecting an external electronic component D. In the illustrated example, the second substrate 20 has a component mounting region EA, within which a conductor pad 22sp is formed. During use of the wiring substrate 1, the conductor pad 22sp is connected to the connection pad Dp of the external electronic component D. During the mounting of the external electronic component D onto the wiring substrate 1, a conductive bonding material SB, such as solder, is disposed on the upper surface of the exposed conductor pad 22sp. The conductor pad 22sp is electrically and mechanically connected to the connection pad Dp of the external electronic component D via this bonding material SB. Examples of electronic components D that can be mounted on the wiring substrate 1 include, for example, active components such as semiconductor integrated circuit devices and transistors.

[0035] On the opposite side of the fourth surface 20S of the second substrate 20, which serves as the component mounting surface in the wiring substrate 1, the first surface 10F of the first substrate 10 is, for example, the connection surface (substrate connection surface) that connects to the external substrate DD when the wiring substrate 1 is mounted on an external substrate DD, which is the motherboard of any electrical device. Therefore, in the use of the wiring substrate 1, the conductor pad 12fp is connected to the connection pad DDP of the external substrate DD. In the connection between the wiring substrate 1 and the external substrate DD, a conductive bonding element SBP, such as solder, is disposed on the surface of the exposed conductor pad 12sp. The conductor pad 12sp is electrically and mechanically connected to the connection pad DDP of the external substrate DD via this bonding element SBP.

[0036] The plurality of conductor pads 22sp exposed on the fourth surface 20S of the second substrate 20, which serves as a component mounting surface, are also referred to as component mounting pads 22sp. The plurality of conductor pads 12fp exposed on the first surface 10F of the first substrate 10, which serves as a substrate connection surface, are also referred to as substrate connection pads 12fp. In the illustrated example, in the second substrate 20, the minimum value of the spacing between the plurality of component mounting pads 22sp constituting the component mounting surface 20S (i.e., the distance between the centers of two adjacent component mounting pads 22sp) is less than the minimum value of the spacing between the plurality of conductor pads 22fp constituting the third surface 20F. In addition, in the first substrate 10, the minimum value of the spacing between the plurality of substrate connection pads 12fp constituting the substrate connection surface 10F is greater than the minimum value of the spacing between the plurality of conductor pads 12sp constituting the second surface 10S. That is, the wiring that may be included in the wiring substrate 1, in its use, can realize rewiring from the connecting pads Dp with relatively narrow spacing of the electronic component D mounted on the component mounting surface 20S to the connecting pads DDP with relatively wide spacing of the outer substrate DD. Therefore, there is a case where the spacing of the plurality of second through conductors 203 included in the second core substrate 200 is smaller than the spacing of the plurality of first through conductors 103 included in the first core substrate 100. In order to achieve a structure in which the spacing of the second through conductors 203 is smaller than the spacing of the first through conductors 103, there is a case where the diameter of the second through conductors 203 is smaller than the diameter of the first through conductors 103. In addition, here "diameter" refers to the straight-line distance between the two farthest points on the outer edges of the through conductors 103, 203 when viewed from above.

[0037] Regarding the prior art, as described above, when a substrate containing a glass substrate with a relatively low coefficient of thermal expansion is connected to an external substrate, poor connection may sometimes occur due to the difference in coefficients of thermal expansion between the two substrates. Specifically, when the coefficient of thermal expansion of the external substrate is relatively high, the difference between the coefficients of thermal expansion of the substrate containing the glass substrate and the external substrate is large, and poor connection may sometimes occur due to the concentration of thermal stress caused by this difference at the connection point. In contrast, in the wiring substrate of the embodiment, the second substrate 20, which has a second core substrate 200 including a glass substrate 201, has a structure that connects to the external substrate DD via the first substrate 10. As described above, the coefficient of thermal expansion of the second substrate 20 as a whole is different from the coefficient of thermal expansion of the first substrate 10 as a whole; the coefficient of thermal expansion of the first substrate 10 is greater than the coefficient of thermal expansion of the second substrate 20. Therefore, sometimes the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the first substrate 10 is smaller than the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the second substrate 20, and the difference between the thermal expansion coefficient of the second substrate 20 and the thermal expansion coefficient of the first substrate 10 is also smaller than the difference between the thermal expansion coefficient of the external substrate DD and the thermal expansion coefficient of the second substrate 20. In this case, compared with the case where the second substrate 20 is directly connected to the external substrate DD, the thermal stress that can be applied to the connection portion between the first substrate 10 and the external substrate DD, and the connection portion between the second substrate 20 and the first substrate 10, can be mitigated. It is believed that in the connection between the second substrate 20 and the external substrate DD, the occurrence of poor connection caused by thermal stress is suppressed.

[0038] The thermal expansion coefficient of the second substrate 20, which includes a second core substrate 200 made of a glass substrate 201, is, for example, 4 ppm or more and 12 ppm or less. The thermal expansion coefficient of the first substrate 10, which has a first core substrate 100 including a resin substrate 101, is 7 ppm or more and 15 ppm or less. From the viewpoint of avoiding poor connection caused by thermal stress due to the difference in thermal expansion coefficients of the connecting parts, the difference between the thermal expansion coefficients of the first substrate 10 and the second substrate 20 is preferably 2 ppm or more and 6 ppm or less.

[0039] Furthermore, the thickness dimension of the second laminate portion 20B in the second substrate 20 is preferably larger than the thickness dimension of the first laminate portion 10B in the first substrate 10. It is believed that the stress applied to the second substrate 20 when the external electronic component D is mounted on the component mounting surface 22sp is absorbed by the second substrate 20 before reaching the connection between the second substrate 20 and the first substrate 10, thereby suppressing the occurrence of defects at the connection between the second substrate 20 and the first substrate 10.

[0040] As described above, the conductors constituting the second substrate 20 (second conductor layer 22, second via conductor 23, second through conductor 203) sometimes form rewiring fan-out from the component mounting pad 22sp constituting the component mounting surface 20S to the conductor pad 22fp constituting the third surface 20F. Furthermore, the conductors constituting the first substrate 10 (first conductor layer 12, first via conductor 13, first through conductor 103) sometimes form rewiring fan-out from the conductor pad 12sp constituting the second surface 10S to the substrate connection pad 12fp constituting the first surface 10F. Accompanying this, the second via conductor 23 is sometimes formed with a finer pitch than the first via conductor 13; therefore, the thickness of the second insulating layer 21 constituting the second substrate 20 is sometimes less than the thickness of the first insulating layer 11 constituting the first substrate 10. In this case, in order to alleviate the stress when mounting the external electronic component D, from the viewpoint of increasing the thickness of the second laminate portion 20B of the second substrate 20, it is preferable that the number of the second insulating layer 21 constituting the second laminate portion 20B is greater than the number of the first insulating layer 11 constituting the first laminate portion 10B of the first substrate 10. Therefore, it is preferable that the number of the second conductor layer 22 constituting the second laminate portion 20B is greater than the number of the first conductor layer 12 constituting the first laminate portion 10B of the first substrate 10.

[0041] The conductor pad 22fp constituting the third surface 20F of the second substrate 20 is mechanically and electrically connected to the conductor pad 12sp constituting the second surface 10S of the first substrate 10 via a conductive connecting element BP. Alternatively, an underfill material such as epoxy resin or polyimide resin (not shown) may be filled between the third surface 20F of the second substrate 20 and the second surface 10S of the first substrate 10 (specifically, between the solder resist layer 20Rf and the solder resist layer 10Rs).

[0042] Next, refer to Figures 2A to 2C , Figures 3A to 3D as well as Figures 4A-4B This indicates the manufacturing process. Figure 1 The method for manufacturing the wiring substrate in the case of wiring substrate 1 shown is described below. Furthermore, the structural elements formed in the manufacturing method described below can be used in [the following text is incomplete and requires further context]. Figure 1 The material used as the material for the corresponding structural element in the description of the wiring substrate 1 is formed. Furthermore, in the following, the referenced... Figures 2A to 4B The text does not depict the metal foil layer, metal film layer, and coating layer, which are structural elements of each conductor layer. Figure 1 Similarly, each conductor layer is depicted as a single layer.

[0043] The steps of manufacturing the wiring substrate 1 include the following steps: manufacturing a first substrate 10, manufacturing a second substrate 20, and connecting the first substrate 10 and the second substrate 20. First, refer to... Figures 2A to 2CThe manufacturing process of the first substrate 10 will be described.

[0044] like Figure 2A As shown, a first core substrate 100 is formed. For example, a laminate (e.g., a double-sided copper-clad laminate) is prepared having a resin substrate 101 made of an insulating resin such as epoxy resin and metal foils (not shown) disposed on both sides of the resin substrate 101. Through holes 101a are formed on the prepared laminate, for example, by drilling. Next, a metal film layer (not shown) is formed on the inner wall surface of the through hole 101a and the upper surface of the metal foil by chemical plating, and a plating layer (not shown) is formed on the metal film layer by electroplating the metal film layer as a power supply layer. As a result, a conductor film 113 is formed having a metal film layer and a plating layer and covering the inner wall surface of the through hole 101a.

[0045] Next, the inner side of the conductor film 113 is filled with a filler material 123, such as epoxy resin, to form a first through conductor 103 composed of the conductor film 113 and the filler material 123. After the filler material 123 is cured, a metal film layer and a plating film layer are further formed over the entire area of ​​the exposed surfaces of the filler material 123 and the plating film layer, and a first core conductor layer 102 with a predetermined conductor pattern is formed by a subtractive process. A first core substrate 100 having one surface 100f and another surface 100s is obtained.

[0046] Next, as Figure 2B As shown, a first insulating layer 11 is formed covering the first core conductor layer 102 and the resin substrate 101 exposed from the pattern of the first core conductor layer 102. The first insulating layer 11 is formed, for example, by hot-pressing a film-like insulating resin containing epoxy resin, phenolic resin, etc., onto the surface of the first core substrate 100 (on one surface 100f and another surface 100s). Next, a first via conductor 13 penetrating the first insulating layer 11 and a first conductor layer 12 on the first insulating layer 11 are integrally formed. Specifically, a through hole 11a is formed in the first insulating layer 11 at the location where the first via conductor 13 should be formed, for example, by irradiation with a carbon dioxide laser. The first conductor layer 12 and the first via conductor 13 are formed by forming a metal film layer (not shown) on the inner surface of the through hole 11a and the upper surface of the first insulating layer 11 using chemical plating or sputtering, and by forming a plating film layer (not shown) using an anti-plating agent with appropriate openings and electroplating that uses the metal film layer as a power supply layer. The first conductor layer 12 on one side 100f of the first core substrate 100 is formed in a pattern including conductor pads 12fp. The first conductor layer 12 on the other side 100s of the first core substrate 100 is formed in a pattern including conductor pads 12sp.

[0047] Next, as Figure 2CAs shown, a solder resist layer 10Rf is formed on the outermost first conductor layer 12 and first insulating layer 11 on one side 100f of the first core substrate 100, having an opening 10Rfa that exposes the conductor pad 12fp. On the outermost first conductor layer 12 and first insulating layer 11 on the other side 100s of the first core substrate 100, a solder resist layer 10Rs is formed with an opening 10Rsa that exposes the conductor pad 12sp. The fabrication of the first substrate 10, having a first side 10F and a second side 10S opposite to the first side 10F, is completed. The thermal expansion coefficient of the manufactured first substrate 10 is, for example, 7 ppm or more and 15 ppm or less.

[0048] Next, refer to Figures 3A to 3D The manufacturing of the second substrate 20 will be described. First, as follows... Figure 3A As shown, a second core substrate 200 is formed. In forming the second core substrate 200, firstly, a glass substrate 201, such as one comprising soda lime glass, borosilicate glass, or alkali-free glass, is prepared, and a through-hole 201a is formed on the glass substrate 201. In forming the through-hole 201a, for example, a modified portion is formed at the location on the glass substrate 201 where the through-hole 201a is to be formed by laser irradiation, and the modified portion is removed, for example, by an etching solution containing an aqueous solution of hydrogen fluoride, thereby forming the through-hole 201a. As the laser for forming the modified portion, helium-neon lasers, argon ion lasers, excimer lasers, and various YAG lasers can be used.

[0049] Next, the interior of the formed through-hole 201a is completely filled with a conductor, which is then formed to completely cover both surfaces of the glass substrate 201 perpendicular to its thickness direction. During the formation of the conductor, a metal film layer (not shown) is formed, for example, by chemical plating, on the inner wall surface of the through-hole 201a and on both surfaces of the glass substrate 201. Then, by electroplating the metal film layer as a power supply layer, a plating layer (not shown) is formed on the metal film layer. A second through conductor 203 having both the metal film layer and the plating layer is formed, and both surfaces of the glass substrate 201 are covered by a layer of the conductor with a two-layer structure of the metal film layer and the plating layer. Next, the layer of the conductor covering both surfaces of the glass substrate 201 is removed, for example, by CMP (chemical mechanical polishing). Figure 3A As shown, a second core substrate 200 is formed, which is composed of the surface of the glass substrate 201 and the surface (end face) of the second through conductor 203, and has one surface 200f and another surface 200s.

[0050] Next, as Figure 3BAs shown, a second insulating layer 21 is formed covering one surface 200f and the other surface 200s of the second core substrate 200, and then a second conductor layer 22 is formed on the second insulating layer 21. Simultaneously with the formation of the second conductor layer 22, a second via conductor 23 is integrally formed with the second conductor layer 22.

[0051] The second insulating layer 21 is formed, for example, by hot-pressing a film-like insulating resin (e.g., epoxy resin) onto the surface (one side 200f and the other side 200s) of the second core substrate 200. A through-hole 21a is formed at the location in the second insulating layer 21 where the second via conductor 23 is to be formed, for example, by irradiation with a carbon dioxide laser. A second conductor layer 22 and a second via conductor 23 are formed by forming a metal film (not shown) on the inner surface of the through-hole 23a and the upper surface of the second insulating layer 21 using chemical plating or sputtering, and by forming a plating film (not shown) using an anti-plating agent with appropriate openings and employing the metal film as a power supply layer through electroplating.

[0052] Next, as Figure 3C As shown, on the upper sides of one surface 200f and the other surface 200s of the second core substrate 200, the same process as the formation of the second insulating layer 21 and the integral formation of the second via conductor 23 and the second conductor layer 22 described above is repeated a desired number of times. As shown, a second laminated portion 20B is formed, comprising a total of 10 layers of the second insulating layer 21 and a total of 10 layers of the second conductor layer 22. The outermost second conductor layer 22 on the side of one surface 200f is formed with a pattern including conductor pads 22fp. The outermost second conductor layer 22 on the side of the other surface 200s is formed with a pattern including conductor pads 22sp.

[0053] Next, as Figure 3D As shown, a solder resist layer 20Rf is formed on the outermost second conductor layer 22 and second insulating layer 21 on one side 200f of the second core substrate 200, having an opening 20Rfa that exposes the conductor pad 22fp. On the outermost second conductor layer 22 and second insulating layer 21 on the other side 200s of the second core substrate 200, a solder resist layer 20Rs is formed with an opening 20Rsa that exposes the conductor pad 22sp. The manufacturing of the second substrate 20, having a third side 20F and a fourth side 20S opposite to the third side 20F, is complete. The thermal expansion coefficient of the manufactured second substrate 20 is, for example, 4 ppm or more and 12 ppm or less.

[0054] Next, refer to Figures 4A-4B The connection between the first substrate 10 and the second substrate 20 will be described. First, as... Figure 4A As shown, a connection element BP, for example a solder protrusion, is formed on the conductor pad 12sp of the second surface 10S constituting the first substrate 10.

[0055] Next, as Figure 4B As shown, the second substrate 20 is connected to the first substrate 10 via a connection element BP. Specifically, the second substrate 20 is arranged such that its third surface 20F faces the second surface 10S of the first substrate 10, and the conductor pad 22fp exposed in the opening 20Rsa of the solder mask layer 20Rs constituting the third surface 20F is connected to the connection element BP. The fabrication of the wiring substrate 1 is complete. Alternatively, after the first substrate 10 and the second substrate 20 are connected, a bottom filler material (not shown) can be filled into the gap between the third surface 20F of the second substrate 20 and the second surface 10S of the first substrate 10, which are interconnected via the connection element BP.

Claims

1. A wiring substrate, comprising: A first substrate has a first side and a second side opposite to the first side. The first substrate has a first core substrate and a first laminate portion. The first laminate portion includes a first insulating layer and a first conductive layer alternately laminated on both sides of the first core substrate. A second substrate has a third surface and a fourth surface opposite to the third surface. The second substrate has a second core substrate and a second laminated portion. The second laminated portion includes a second insulating layer and a second conductive layer alternately laminated on both surfaces of the second core substrate. in, The second surface of the first substrate and the third surface of the second substrate are connected via a conductive connecting element. The fourth surface of the second substrate is configured as a component mounting surface. The first surface of the first substrate is configured as a substrate connection surface. The second core substrate includes a glass substrate. The first core substrate comprises a resin substrate. The thermal expansion coefficient of the first substrate is greater than that of the second substrate. The thermal expansion coefficient of the first substrate is above 7 ppm and below 15 ppm.

2. The wiring substrate according to claim 1, wherein, The difference between the thermal expansion coefficient of the first substrate and the thermal expansion coefficient of the second substrate is greater than 2 ppm and less than 6 ppm.

3. The wiring substrate according to claim 1, wherein, The thickness of the first lamination is less than the thickness of the second lamination.

4. The wiring substrate according to claim 1, wherein, The number of conductor layers constituting the second stacked portion is greater than the number of conductor layers constituting the first stacked portion.

5. The wiring substrate according to claim 1, wherein, The first substrate and the second substrate have approximately the same shape and size when viewed from above.

6. The wiring substrate according to claim 1, wherein, The first core substrate includes a first through conductor. The second core substrate includes a second through conductor. The diameter of the second through conductor is smaller than the diameter of the first through conductor.

7. The wiring substrate according to claim 1, wherein, The third surface includes multiple conductor pads. The fourth surface includes multiple components mounted with pads. The minimum spacing between the multiple components and the pads is less than the minimum spacing between the multiple conductor pads.

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