Integrated ic single photon avalanche diode and photon detection system

Abstract

This application provides an integrated IC single-photon avalanche diode and a photon detection system, relating to the field of semiconductor technology. The single-photon avalanche diode includes: a substrate; an epitaxial layer formed on the substrate; and a first P-type well, a first N-type well, and a second P-type well formed within the epitaxial layer; the first N-type well and the second P-type well are located on the side of the first P-type well facing away from the substrate and are in contact with the first P-type well; the second P-type well surrounds the first N-type well, and the second P-type well and the N-type well are spaced apart to form a protective ring structure; the first P-type well and the first N-type well form an avalanche PN junction; after incident photons are absorbed in the first P-type well, electron-hole pairs are generated, wherein electrons, as minority carriers, are accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication. This application provides a technical solution that uses electrons as avalanche trigger carriers, fundamentally improving the avalanche triggering probability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a single-photon avalanche diode and photon detection system with integrated IC. Background Technology

[0002] A single-photon avalanche diode (SPAD) is a high-sensitivity photodetector operating in Geiger mode. It boasts advantages such as fast response, high sensitivity, and single-photon detection capabilities, and is widely used in fields such as lidar, 3D imaging, fluorescence spectroscopy, and quantum communication. With the development of integrated circuit technology, monolithically integrating SPADs with CMOS (Complementary Metal-Oxide-Semiconductor) readout circuits has become the mainstream development direction for high-performance photodetector chips.

[0003] Traditional single-photon avalanche diode devices mostly use holes as avalanche trigger carriers, resulting in a low avalanche trigger probability, which directly limits further improvement in photon detection efficiency. Furthermore, when integrated with CMOS circuits, these structures also suffer from poor isolation, susceptibility to electrical crosstalk, high dark count, and insufficient process compatibility. Summary of the Invention

[0004] This application provides a single-photon avalanche diode and photon detection system with integrated IC, which provides a technical solution that can use electrons as avalanche trigger carriers to fundamentally improve the avalanche trigger probability, thereby optimizing photon detection efficiency, while taking into account integration compatibility with CMOS circuits.

[0005] In a first aspect, embodiments of this application provide a single-photon avalanche diode integrated with an IC, the single-photon avalanche diode comprising: Substrate; An epitaxial layer formed on the substrate; The epitaxial layer contains a first P-type well, a first N-type well, and a second P-type well; wherein, along the thickness direction of the substrate, the first N-type well and the second P-type well are located on the side of the first P-type well away from the substrate and are in contact with the first P-type well; along the thickness direction perpendicular to the substrate, the second P-type well surrounds the first N-type well, and the second P-type well and the N-type well are spaced apart to form a protective ring structure; The first P-type well and the first N-type well form an avalanche PN junction; after the incident photon is absorbed in the first P-type well, an electron-hole pair is generated, in which the electron, as a minority carrier, is accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication.

[0006] In one optional embodiment, the single-photon avalanche diode further includes: a second N-type well and a third N-type well formed in the epitaxial layer; Along the thickness direction of the substrate, the third N-type well is located on the side of the first P-type well that is away from the first N-type well; Along the thickness direction of the substrate, the second N-type well is located on the side of the third N-type well away from the substrate and is in contact with the third N-type well; Along a direction perpendicular to the thickness of the substrate, the second N-type well is disposed around the periphery of the second P-type well and the first P-type well.

[0007] In one alternative implementation, the third N-type well is a deep N-type well, which is formed using a standard CMOS process.

[0008] In one optional implementation, the second N-type well is connected to the third N-type well and a preset voltage is applied, so that the third N-type well forms a reverse-biased PN junction with the first P-type well and the epitaxial layer respectively, thereby achieving electrical isolation between the single-photon avalanche diode and the CMOS circuit in the integrated IC.

[0009] In one alternative embodiment, the single-photon avalanche diode further includes a quenching element for quenching the avalanche current generated by the single-photon avalanche diode.

[0010] In one optional embodiment, the single-photon avalanche diode further includes a first lead-out electrode and a second lead-out electrode; The first lead electrode is formed in the first N-type well, and the first lead electrode is flush with the surface of the first N-type well away from the first P-type well, for applying a reverse bias voltage; The second lead electrode is formed in the second P-type well, and the second lead electrode is flush with the side surface of the second P-type well opposite to the first P-type well, for grounding or providing a fixed potential.

[0011] In one optional implementation, the quenching element is a quenching MOS transistor or a high-resistance polysilicon resistor; When the quenching element is the quenching MOS transistor, the first terminal of the quenching MOS transistor is connected to the second lead electrode, the second terminal of the quenching MOS transistor is connected to a preset voltage, and the gate of the quenching MOS transistor is used to receive control signals. When the quenching element is the high-resistance polycrystalline silicon resistor, one end of the high-resistance polycrystalline silicon resistor is connected to the second lead electrode, and the other end is connected to a preset voltage.

[0012] In one alternative embodiment, the single-photon avalanche diode further includes an isolation structure formed between the second P-type well and the first N-type well.

[0013] In one alternative embodiment, the single-photon avalanche diode includes a third P-type well and a third lead-out electrode; Along the direction perpendicular to the substrate thickness, the third P-type well is located on the side of the second N-type well that is away from the second P-type well; The third lead electrode is formed in the third P-type well, and the third lead electrode is flush with the side surface of the third P-type well that is away from the substrate, for grounding or providing a fixed potential reference. A reverse-biased PN junction is formed between the third P-type well and the second N-type well. This is used to block the lateral diffusion of charge carriers in the photonic avalanche diode.

[0014] Secondly, embodiments of this application also provide a photon detection system, including a single-photon avalanche diode of the integrated IC described in the first aspect.

[0015] Thirdly, embodiments of this application provide a lidar system, the system including the single-photon avalanche diode of the integrated IC described in the first aspect.

[0016] Fourthly, embodiments of this application provide an imaging system that integrates a single-photon avalanche diode of the integrated IC described in any of the first aspects.

[0017] With the above technical solution adopted, embodiments of this application provide a single-photon avalanche diode, a photon detection system, a lidar system, and an imaging system integrated with an IC. The single-photon avalanche diode includes: a substrate; an epitaxial layer formed on the substrate; and a first P-type well, a first N-type well, and a second P-type well formed within the epitaxial layer. Along the thickness direction of the substrate, the first N-type well and the second P-type well are located on the side of the first P-type well facing away from the substrate and are in contact with the first P-type well. Along the thickness direction perpendicular to the substrate, the second P-type well surrounds the first N-type well, and the second P-type well and the N-type well are spaced apart to form a protective ring structure. The first P-type well and the first N-type well form an avalanche PN junction. After incident photons are absorbed in the first P-type well, electron-hole pairs are generated, wherein electrons, as minority carriers, are accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication.

[0018] Based on the above description, in this embodiment, after the incident photon is absorbed in the first P-type well, an electron-hole pair is generated. The electron, acting as the minority carrier, is accelerated by a strong electric field in the depletion region of the avalanche PN junction, triggering avalanche multiplication. Under the same electric field and process conditions, the avalanche triggering probability of electrons is twice or more than that of holes. Therefore, the avalanche triggering probability of a single-photon avalanche diode can be significantly increased, solving the technical problem of low avalanche triggering probability caused by the traditional use of holes as avalanche triggering carriers. It should be understood that the core influencing factor on photon detection efficiency includes the avalanche triggering probability. Under the premise that the quantum efficiency and fill factor remain essentially unchanged, increasing the avalanche triggering probability can directly drive the optimization of photon detection efficiency, fundamentally improving the single-photon detection sensitivity of the SPAD and meeting the application requirements of high-sensitivity photoelectric detection scenarios (such as lidar and quantum communication).

[0019] Furthermore, the second P-type well surrounds the first N-type well along a direction perpendicular to the substrate thickness. This protective ring structure effectively disperses the electric field intensity at the edge of the avalanche PN junction, preventing excessive electric field concentration and suppressing edge breakdown at its source. This results in a more uniform breakdown voltage for the single-photon avalanche diode, improving its stability and consistency. Edge breakdown is one of the main causes of high dark count rates in SPADs. The protective ring structure reduces non-photon-triggered avalanche events by suppressing edge breakdown, thereby lowering the dark count rate and improving the device's detection accuracy. Especially in low-light, single-photon detection scenarios, it effectively reduces noise interference and ensures the accuracy of the detection signal. Moreover, the protective ring structure is spaced apart from the first N-type well, ensuring that it does not affect the normal operation of the core avalanche region formed by the first P-type and N-type wells, while also protecting the core region from avalanche anomalies caused by external interference or structural defects, further improving the device's reliability and lifespan.

[0020] Finally, in this embodiment, the first P-type well is formed within the epitaxial layer and located below the first N-type well (along the substrate thickness direction). Incident photons can be fully absorbed in the first P-type well, effectively generating electron-hole pairs, reducing photon escape, improving photon utilization, and providing a sufficient source of charge carriers for subsequent avalanche multiplication. Furthermore, both the first N-type well and the second P-type well are in contact with the first P-type well, ensuring the stable formation of the avalanche PN junction. Simultaneously, the protective ring structure of the second P-type well prevents the lateral diffusion of avalanche current, concentrating the avalanche multiplication process in the core region, improving the stability and controllability of avalanche multiplication, and ensuring that the single-photon avalanche diode can respond stably and rapidly to single-photon signals. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] Figure 1 The present invention provides a structure of a single-photon avalanche diode integrated into an IC. Figure 1 ; Figure 2 The present invention provides a structure of a single-photon avalanche diode integrated into an IC. Figure 2 . Attached image description: 10-Substrate; 20-Epipolar layer; 301-First P-type well; 302-First N-type well; 303-Second P-type well; 304-Second N-type well; 305-Third N-type well; 306-Second lead-out electrode; 307-First lead-out electrode; 308-Third P-type well; 309-Third lead-out electrode; 3010-Isolation structure; 401-CMOS circuit; 402-Quenching element. Detailed Implementation

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various information or data, but these elements are not limited by these terms. These terms are only used to distinguish first information from another type of information. For example, without departing from the scope of this application, first action information may be referred to as second action information, and similarly, second action information may be referred to as first action information. Both first action information and second action information are action information, but they are not the same action information.

[0026] In this document, it should be understood that the terminology used is for convenience of understanding only and does not imply any limitation on its meaning. Furthermore, any number of elements in the accompanying drawings is for illustrative purposes only and not for limitation, and any naming is for distinction only and has no limiting meaning.

[0027] A single-photon avalanche diode (SPAD) is a high-sensitivity photodetector operating in Geiger mode. It boasts advantages such as fast response, high sensitivity, and single-photon detection capabilities, and is widely used in fields such as lidar, 3D imaging, fluorescence spectroscopy, and quantum communication. With the development of integrated circuit technology, monolithically integrating SPADs with CMOS (Complementary Metal-Oxide-Semiconductor) readout circuits has become the mainstream development direction for high-performance photodetector chips.

[0028] Traditional single-photon avalanche diode devices mostly use holes as avalanche trigger carriers, resulting in a low avalanche trigger probability, which directly limits further improvement in photon detection efficiency. Furthermore, when integrated with CMOS circuits, these structures also suffer from poor isolation, susceptibility to electrical crosstalk, high dark count, and insufficient process compatibility.

[0029] Based on this, the technical concept of this application embodiment is: by the synergy of electronically triggered avalanche and the protective ring isolation structure, the avalanche triggering probability is significantly improved without reducing the fill factor or increasing the process cost, thereby greatly optimizing the photon detection efficiency (PDE) of the device. At the same time, it solves the problems of easy edge breakdown and poor compatibility with CMOS integration of traditional SPAD, and meets the application requirements of high-performance optoelectronic detection scenarios such as lidar and imaging systems.

[0030] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for identical or similar content, the description will not be repeated in different embodiments.

[0031] First, let's explain integrated circuits (ICs) and their single-photon avalanche diodes: Integrated circuits (ICs) refer to the integration of multiple electronic components (such as transistors, resistors, capacitors, diodes, etc.) onto the same semiconductor chip (such as silicon wafer) through semiconductor processes (such as the standard CMOS process in this application) to form a complete and miniaturized electronic functional module. In essence, they are miniaturized collections of electronic circuits.

[0032] In this application, the integrated IC single-photon avalanche diode (SPAD) refers to a SPAD device integrated with CMOS readout circuits, bias circuits, and other electronic components on the same semiconductor chip using standard CMOS technology, rather than the SPAD existing as a separate independent device. This integrated design allows the SPAD to work seamlessly with peripheral circuits, reducing the overall chip size, integration difficulty, and manufacturing cost, while improving device stability and response speed, making it suitable for miniaturized, high-performance applications such as LiDAR and imaging systems.

[0033] Reference Figure 1 and Figure 2 This application provides an integrated IC single-photon avalanche diode, the single-photon avalanche diode comprising: Substrate 10; An epitaxial layer 20 is formed on the substrate 10; The epitaxial layer 20 includes a first P-type well 301, a first N-type well 302, and a second P-type well 303. Along the thickness direction of the substrate 10, the first N-type well 302 and the second P-type well 303 are located on the side of the first P-type well 301 facing away from the substrate 10 and are in contact with the first P-type well 301. Along the thickness direction perpendicular to the substrate 10, the second P-type well 303 surrounds the first N-type well 302, and the second P-type well 303 is spaced apart from the first N-type well 302 to form a protective ring structure. The first P-type well 301 and the first N-type well 302 form an avalanche PN junction; after the incident photon is absorbed in the first P-type well 301, an electron-hole pair is generated, wherein the electron, as a minority carrier, is accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication.

[0034] In this embodiment, the substrate 10 serves as the basic support carrier for the entire SPAD device, providing a stable substrate for the formation of the subsequent epitaxial layer 20 and various well structures. Typically, a P-type substrate 10 is used (to adapt to the subsequent doping layout of P-type wells and N-type wells), which is the basis for the realization of the electrical characteristics of the device.

[0035] The epitaxial layer 20 is formed on the surface of the substrate 10 and serves as the carrier region for various well structures (first P-type well 301, first N-type well 302, and second P-type well 303). It is formed through an epitaxial growth process, which allows for precise control of doping concentration and thickness, providing a suitable environment for the formation of avalanche PN junctions, photon absorption, and carrier transport, and avoiding interference from impurities in the substrate 10 on device performance.

[0036] The first P-type well 301 is formed inside the epitaxial layer 20 and is the core region for photon absorption and carrier generation. It also serves as the P-type terminal of the avalanche PN junction, providing the basis for subsequent electron-triggered avalanche. The first N-type well 302 is formed within the epitaxial layer 20, along the thickness direction of the substrate 10, located on the side of the first P-type well 301 away from the substrate 10, and in contact with the first P-type well 301. The first N-type well 302 serves as the N-type terminal of the avalanche PN junction, forming a reverse-biased PN junction with the first P-type well 301, providing a strong electric field environment for carrier acceleration and avalanche multiplication.

[0037] The second P-type well 303 is also formed within the epitaxial layer 20, located in the same layer as the first N-type well 302 (along the thickness direction of the substrate 10), and in contact with the first P-type well 301; along the direction perpendicular to the thickness of the substrate 10 (i.e., the horizontal direction), the second P-type well 303 is arranged in a ring around the periphery of the first N-type well 302, and maintains a certain distance from the first N-type well 302. This arrangement of surrounding and spacing constitutes the protective ring structure of the SPAD device, which is used to protect the core avalanche region and optimize the electric field distribution.

[0038] Specifically, the working principle of this single-photon avalanche diode is as follows: After an incident single photon irradiates the diode surface, it penetrates the epitaxial layer 20 and is finally absorbed in the first P-type well 301. The first P-type well 301 serves as the photon absorption region, and its doping concentration and thickness are optimized to ensure sufficient photon absorption, reduce photon escape, and improve photon utilization. After the photon is absorbed by the first P-type well 301, its energy is transferred to the electrons in the well, causing the electrons to jump from the valence band to the conduction band, thereby generating electron-hole pairs (i.e., photogenerated carriers), providing initial carriers for subsequent avalanche multiplication. The avalanche PN junction formed by the first P-type well 301 and the first N-type well 302, when operating, forms a strong electric field depletion region by applying a reverse bias voltage. In the generated electron-hole pairs, electrons, as minority carriers (the first P-type well 301 is P-type doped, and electrons are minority carriers), are rapidly accelerated under the strong electric field of the depletion region, gaining sufficient kinetic energy. The accelerated electrons collide with atoms in the well, generating more electron-hole pairs. These newly generated carriers are then accelerated in the strong electric field, triggering a chain reaction and forming an avalanche multiplication effect. Ultimately, the weak single-photon signal is converted into a detectable electrical signal, enabling single-photon detection.

[0039] Throughout the entire operation, the protective ring structure formed by the second P-type trap 303 is used to ensure the stability and controllability of the avalanche multiplication process and to avoid abnormal situations such as edge breakdown.

[0040] Based on the above description, in this embodiment, after the incident photon is absorbed in the first P-type well 301, an electron-hole pair is generated. The electron, as the minority carrier, is accelerated by a strong electric field in the depletion region of the avalanche PN junction, triggering avalanche multiplication. Under the same electric field and process conditions, the avalanche triggering probability of electrons is twice or more than that of holes. Therefore, the avalanche triggering probability of a single-photon avalanche diode can be significantly improved, solving the technical problem of low avalanche triggering probability caused by the traditional use of holes as avalanche triggering carriers. It should be understood that the core influencing factor on photon detection efficiency includes the avalanche triggering probability. Under the premise that the quantum efficiency and fill factor remain essentially unchanged, the improvement of the avalanche triggering probability can directly drive the optimization of photon detection efficiency, fundamentally improving the single-photon detection sensitivity of the SPAD and meeting the application requirements of high-sensitivity photoelectric detection scenarios (such as lidar and quantum communication).

[0041] Furthermore, the second P-type well 303 surrounds the first N-type well 302 along a direction perpendicular to the thickness of the substrate 10. The resulting protective ring structure effectively disperses the electric field intensity at the edge of the avalanche PN junction, preventing excessive electric field concentration and suppressing edge breakdown from the source. This results in a more uniform breakdown voltage for the single-photon avalanche diode, improving its stability and consistency. Edge breakdown is one of the main causes of high dark count rates in SPADs. The protective ring structure reduces non-photon-triggered avalanche events by suppressing edge breakdown, thereby lowering the dark count rate and improving the device's detection accuracy. Especially in low-light, single-photon detection scenarios, it effectively reduces noise interference and ensures the accuracy of the detection signal. Moreover, the protective ring structure is spaced apart from the first N-type well 302, ensuring that it does not affect the normal operation of the core avalanche region formed by the first P-type well 301 and the first N-type well 302, while also protecting the core region from avalanche anomalies caused by external interference or structural defects, further improving the device's reliability and lifespan.

[0042] Finally, in this embodiment, the first P-type well 301 is formed within the epitaxial layer 20 and located below the first N-type well 302 (along the thickness direction of the substrate 10). Incident photons can be fully absorbed in the first P-type well 301, effectively generating electron-hole pairs, reducing photon escape, improving photon utilization, and providing a sufficient source of charge carriers for subsequent avalanche multiplication. Furthermore, both the first N-type well 302 and the second P-type well 303 are in contact with the first P-type well 301, ensuring the stable formation of the avalanche PN junction. Simultaneously, the protective ring structure of the second P-type well 303 can prevent the lateral diffusion of avalanche current, concentrating the avalanche multiplication process in the core region, improving the stability and controllability of avalanche multiplication, and ensuring that the single-photon avalanche diode can respond stably and quickly to single-photon signals.

[0043] Furthermore, the single-photon avalanche diode also includes a second N-type well 304 and a third N-type well 305 formed in the epitaxial layer 20; Along the thickness direction of the substrate 10, the third N-type well 305 is located on the side of the first P-type well 301 that is away from the first N-type well 302. Along the thickness direction of the substrate 10, the second N-type well 304 is located on the side of the third N-type well 305 away from the substrate 10 and is in contact with the third N-type well 305; Along the thickness direction perpendicular to the substrate 10, the second N-type well 304 is disposed around the periphery of the second P-type well 303 and the first P-type well 301.

[0044] Optionally, the third N-type well 305 is a deep N-type well, which is formed using standard CMOS technology.

[0045] In this embodiment, the third N-type well 305 is formed inside the epitaxial layer 20 along the thickness direction (vertical direction) of the substrate 10. Its position is on the side of the first P-type well 301 away from the first N-type well 302, i.e., the first P-type well 301 is sandwiched between the first N-type well 302 (above) and the third N-type well 305 (below), and the third N-type well 305 is in contact with the first P-type well 301 (no gap is required, ensuring effective transmission of electrical effects). Based on the aforementioned structure, the third N-type well 305 is typically a deep N-type well (DNW), formed using standard CMOS technology, with a higher doping concentration than ordinary N-type wells, achieving superior isolation.

[0046] The second N-type well 304 is also formed inside the epitaxial layer 20, serving as the outer isolation ring of the single-photon avalanche diode. Along the thickness direction of the substrate 10, it is located on the side of the third N-type well 305 away from the substrate 10 and is in contact with the third N-type well 305, that is, the third N-type well 305 is sandwiched between the substrate 10 (indirectly) and the second N-type well 304 (above); along the direction perpendicular to the thickness of the substrate 10 (horizontal direction), the second N-type well 304 is arranged in a ring around the second P-type well 303 and the first P-type well 301, completely surrounding the core avalanche region (first P-type well 301 and first N-type well 302) and the protective ring region (second P-type well 303) of the SPAD, forming a fully enclosed isolation structure 3010.

[0047] In this embodiment, when the SPAD is working, a reverse bias voltage is applied to the first N-type well 302 (to form an avalanche electric field), while the second N-type well 304 and the third N-type well 305 are connected to a preset voltage (usually a high potential VDD). Since the third N-type well 305 is in contact with the first P-type well 301 and the second N-type well 304 surrounds the core region, after being connected to a high potential, the third N-type well 305 will form a reverse bias PN junction with the first P-type well 301 and the epitaxial layer 20 (usually P-type); the second N-type well 304 will form a reverse bias PN junction with the surrounding CMOS circuit 401 region.

[0048] The reverse-biased PN junction is in the cutoff state, which can effectively block the lateral diffusion and longitudinal transport of charge carriers (electrons and holes), thereby isolating the core avalanche region of the SPAD from the peripheral CMOS circuit 401, avoiding problems such as electrical crosstalk and substrate leakage between the two, and ensuring that the SPAD and CMOS circuit 401 work stably.

[0049] Based on the above description, the third N-type well 305 is located below the first P-type well 301, forming a reverse-biased PN junction with the first P-type well 301 and the epitaxial layer 20. This effectively blocks the diffusion of charge carriers from the SPAD core region towards the substrate 10, avoiding problems such as increased dark count rate and abnormal avalanche current caused by leakage current in the substrate 10, thus improving the device's operational stability. The third N-type well 305 is a deep N-type well with high doping concentration and deep vertical extension, which can help disperse the electric field of the avalanche PN junction formed by the first P-type well 301 and the first N-type well 302, further alleviating electric field concentration. Combined with the guard ring structure of the second P-type well 303, it provides dual suppression of edge breakdown, reduces the dark count rate, and improves the uniformity of the device's breakdown voltage. Furthermore, the third N-type well 305 is formed using standard CMOS technology, without the need for additional special doping steps, masks, or high-temperature processes. This process is consistent with the various well structures described above, allowing for direct monolithic integration with CMOS readout circuits, reducing integration difficulty and manufacturing costs, and meeting the development needs of integrated circuits.

[0050] Furthermore, the surrounding structure of the second N-type well 304 can block impurities and electric field interference from the peripheral CMOS circuit 401 from entering the core avalanche region of the SPAD, avoiding carrier abnormalities in the core region, reducing abnormal triggering of avalanche multiplication, and further improving the reliability and lifespan of the device. Specifically, the third N-type well 305 is responsible for bottom-layer vertical isolation, and the second N-type well 304 is responsible for peripheral horizontal isolation. The two are closely connected and work together to form a three-dimensional isolation structure 3010 that wraps around the top and bottom and surrounds the periphery. Compared with the traditional single isolation structure 3010, the isolation effect is more significant, which can completely solve the crosstalk and leakage problems when integrating the SPAD with the CMOS circuit 401.

[0051] In one optional embodiment, the second N-type well 304 is connected to the third N-type well 305 and a preset voltage is applied, so that the third N-type well 305 forms a reverse-biased PN junction with the first P-type well 301 and the epitaxial layer 20 respectively, thereby achieving electrical isolation between the single-photon avalanche diode and the CMOS circuit 401 in the integrated IC.

[0052] In this embodiment, the second N-type well 304 and the third N-type well 305 (deep N-type well) are electrically connected, forming a conductive electrical path between them. This ensures that both can be connected to the same preset voltage, forming a unified isolation potential layer. Considering the operating characteristics of SPADs and the requirements of CMOS integration, this preset voltage is typically a high potential (such as VDD), which is higher than the potential of the first P-type well 301 and the epitaxial layer 20 (typically P-type), providing a potential basis for the formation of a reverse-biased PN junction.

[0053] Specifically, based on the above technical solution, the principle of achieving electrical isolation between the single-photon avalanche diode and the CMOS circuit 401 in the integrated IC is as follows: After the second N-type well 304 and the third N-type well 305 are connected to a preset high potential, since the third N-type well 305 (N-type) is in contact with the first P-type well 301 (P-type) and the epitaxial layer 20 (P-type), according to the electrical characteristics of the PN junction, when the N-type semiconductor (third N-type well 305) is connected to a high potential and the P-type semiconductor (first P-type well 301, epitaxial layer 20) is connected to a low potential (or ground potential), a reverse-biased PN junction will be formed between them. The reverse-biased PN junction is in a cutoff state, and its depletion region will widen, which can effectively block the passage of charge carriers (electrons and holes). That is, it can block the diffusion of charge carriers in the SPAD core region (first P-type well 301, first N-type well 302) to the epitaxial layer 20 and the substrate 10, and it can also block the diffusion of charge carriers in the peripheral CMOS circuit 401 to the SPAD core region. In other words, through the blocking effect of the reverse bias PN junction, the core avalanche region of the SPAD is completely electrically isolated from the CMOS circuit 401 in the integrated IC, avoiding problems such as electrical crosstalk and substrate leakage between the two, and ensuring that the SPAD and CMOS circuit 401 can work stably without interfering with each other.

[0054] Based on the above description, the three-dimensional isolation system formed by connecting the second N-type well 304 and the third N-type well 305 can effectively block the lateral diffusion of avalanche carriers from the core region of the SPAD to the peripheral CMOS circuit 401, avoiding interference from avalanche current with the normal operation of the CMOS readout circuit; at the same time, it blocks the diffusion of carriers from the CMOS circuit 401 to the core region of the SPAD, preventing signal noise from the CMOS circuit 401 from affecting the single-photon detection accuracy of the SPAD, ensuring stable operation of both. Furthermore, the reverse-biased PN junction formed by the third N-type well 305, the first P-type well 301, and the epitaxial layer 20 can effectively block carrier diffusion towards the substrate 10, avoiding problems such as increased dark count rate, abnormal avalanche current, and increased device power consumption caused by leakage current in the substrate 10, thus improving the operational stability and energy efficiency of the SPAD device. Compared to a single isolation structure 3010 (which only provides lateral or longitudinal isolation), the three-dimensional isolation formed by the second N-type well 304 and the third N-type well 305 has no isolation breaks and can achieve all-round, dead-angle-free electrical isolation, solving the technical problem of incomplete isolation when integrating traditional SPADs with CMOS.

[0055] Optionally, the single-photon avalanche diode further includes a quenching element 402, which is used to quench the avalanche current generated by the single-photon avalanche diode.

[0056] In this embodiment, the quenching element 402 is an auxiliary electrical component integrated into the single-photon avalanche diode. It is connected in series with the core avalanche region of the SPAD (the avalanche PN junction formed by the first P-type well 301 and the first N-type well 302). Its function is to quench, that is, to quickly terminate the avalanche current generated by the SPAD after detecting a single photon, so that the SPAD can quickly recover from the avalanche state to the standby state, ensuring that the device can continuously and stably detect subsequent single-photon signals.

[0057] Specifically, when the SPAD operates in Geiger mode, its avalanche process and the function of the quenching element 402 are as follows: After the incident photon is absorbed in the first P-type well 301, an electron-hole pair is generated. The electron, as a minority carrier, is accelerated by a strong electric field in the depletion region of the avalanche PN junction, triggering the avalanche multiplication effect and forming a continuously increasing avalanche current (if this current is not terminated in time, it will cause the SPAD device to overheat, be damaged, or fail to respond to subsequent photons). When the avalanche current is generated, the quenching element 402 connected in series with the avalanche PN junction will immediately take effect. If it is a quenching MOSFET, its gate will receive a control signal and quickly turn off the device, cutting off the flow path of the avalanche current; if it is a high-resistivity polysilicon resistor, its high resistance characteristics will limit the increase of the avalanche current and reduce the bias voltage across the SPAD, thereby terminating the avalanche process. The bias voltage across the SPAD will quickly recover to the reverse bias voltage required for Geiger mode, and the device will reset from the avalanche state to the standby state, enabling it to continue absorbing subsequent incident photons, triggering avalanche multiplication, and achieving continuous single-photon detection.

[0058] Based on the above description, after a SPAD triggers avalanche, the avalanche current increases exponentially. If not quenched in time, the excessive current can cause overheating and burnout in the core area of ​​the device (avalanche PN junction), or even permanent device failure. The quenching element 402 can quickly cut off or limit the avalanche current, avoiding current overload, effectively protecting the SPAD device, and extending its lifespan. Furthermore, by terminating the avalanche current, the quenching element 402 can prevent the avalanche effect from continuing to spread in the core area of ​​the SPAD, preventing disordered electric field distribution, avoiding problems such as accelerated edge breakdown and abnormally high dark count rate, and ensuring the structural integrity and electrical stability of the device.

[0059] It should be understood that the quenching element 402, by terminating the avalanche current, prevents the avalanche effect from continuously spreading in the core region of the SPAD, prevents disordered electric field distribution, avoids problems such as accelerated edge breakdown and abnormally high dark count rate, and ensures the structural integrity and electrical stability of the device. Without the quenching element 402, the SPAD would fall into a continuous avalanche state after triggering an avalanche, making it unable to detect subsequent incident photons. The presence of the quenching element 402 allows the SPAD to quickly reset after each avalanche, achieving stable detection of continuously incident single photons and improving the practicality and detection efficiency of the device.

[0060] Optionally, the single-photon avalanche diode further includes a first lead-out electrode 307 and a second lead-out electrode 306; The first lead-out electrode 307 is formed in the first N-type well 302, and the first lead-out electrode 307 is flush with the side surface of the first N-type well 302 that is away from the first P-type well 301, for applying a reverse bias voltage. The second lead electrode 306 is formed in the second P-type well 303, and the second lead electrode 306 is flush with the side surface of the second P-type well 303 opposite to the first P-type well 301, for grounding or providing a fixed potential.

[0061] In this embodiment, the first lead-out electrode 307 is formed in the first N-type well 302, corresponding to the N-type end of the core avalanche region of the SPAD (the avalanche PN junction formed by the first P-type well 301 and the first N-type well 302), ensuring good electrical contact with the first N-type well 302 without excessive contact resistance. The first lead-out electrode 307 is flush with the surface of the first N-type well 302 away from the first P-type well 301, meaning that the first lead-out electrode 307 does not protrude from the surface of the first N-type well 302, nor is it recessed into the well structure; it remains at the same level as the well surface. This structural design avoids electric field concentration caused by electrode protrusion, reduces the chip area occupied by the electrode, does not affect the photosensitive area of ​​the SPAD core region, and facilitates subsequent chip packaging and external circuit connection.

[0062] The first lead-out electrode 307 is used to apply a reverse bias voltage to the core avalanche region of the SPAD. That is, the first lead-out electrode 307 applies a reverse bias voltage to the first N-type well 302, so that the avalanche PN junction formed by the first P-type well 301 and the first N-type well 302 is in a reverse bias state, providing a strong electric field environment for carrier acceleration and triggering avalanche multiplication, which is the basic condition for the SPAD to realize single photon detection.

[0063] The second lead electrode 306 is formed in the second P-type well 303, corresponding to the SPAD's guard ring structure (the second P-type well 303 surrounds the first N-type well 302). It achieves good electrical contact with the second P-type well 303, ensuring that the potential is uniformly transmitted throughout the entire second P-type well 303, guaranteeing the normal operation of the guard ring structure. Consistent with the first lead electrode 307, the second lead electrode 306 is flush with the surface of the second P-type well 303 on the side facing away from the first P-type well 301, avoiding structural defects and electric field interference caused by electrode protrusions or depressions. Simultaneously, it maintains structural consistency with the first lead electrode 307, facilitating mass production and chip layout optimization.

[0064] The second lead electrode 306 is used for grounding or providing a fixed potential reference. That is, the second P-type well 303 is grounded or connected to a fixed reference potential through the second lead electrode 306. On the one hand, it provides a stable potential reference for the avalanche PN junction to ensure the stability of the reverse bias voltage. On the other hand, it provides a connection node for the quenching element 402 (quenching MOS transistor or high-resistance polysilicon resistor), so that the quenching element 402 can form a series circuit with the SPAD core region to realize the quenching function of avalanche current.

[0065] In this embodiment, the first lead-out electrode 307 applies a reverse bias voltage to the first N-type well 302, providing conditions for avalanche multiplication; the second lead-out electrode 306 is grounded or provides a fixed potential, which, together with the protection ring structure, alleviates electric field concentration; in addition, both electrodes are fabricated using standard CMOS technology, which is compatible with the process of the second N-type well 304, the third N-type well 305 (deep N-type well), and the quenching element 402, and can be monolithically integrated with the SPAD core structure and CMOS readout circuit without affecting the overall compactness and isolation effect.

[0066] Furthermore, the quenching element 402 is a quenching MOS transistor or a high-resistance polysilicon resistor.

[0067] When the quenching element 402 is the quenching MOS transistor, the first end of the quenching MOS transistor is connected to the second lead electrode 306, the second end of the quenching MOS transistor is connected to a preset voltage, and the gate of the quenching MOS transistor is used to receive control signals.

[0068] When the quenching element 402 is the high-resistance polysilicon resistor, one end of the high-resistance polysilicon resistor is connected to the second lead electrode 306, and the other end is connected to a preset voltage.

[0069] When the quenching element 402 is a quenching MOS transistor, the first terminal of the quenching MOS transistor (which can be a PMOS transistor or an NMOS transistor, both of which are compatible with standard CMOS process) is connected to the second lead electrode 306, the second terminal of the quenching MOS transistor is connected to a preset voltage, and the gate of the quenching MOS transistor is used to receive control signals.

[0070] In this embodiment, the quenching MOS transistor can be either a PMOS transistor or an NMOS transistor, both of which are compatible with standard CMOS processes. The specific connection method is as follows: the first end of the quenching MOS transistor is connected to the second lead electrode 306, the second end of the quenching MOS transistor is connected to a preset voltage, and the gate of the quenching MOS transistor is used to receive control signals.

[0071] Based on the structure described above, the second lead-out electrode 306 is formed in the second P-type well 303 for grounding or providing a fixed potential reference. The quenching MOSFET is connected to the second lead-out electrode 306 through the first terminal, indirectly forming a series circuit with the core avalanche region of the SPAD (the avalanche PN junction formed by the first P-type well 301 and the first N-type well 302), providing a stable electrical path for quenching avalanche current. The preset voltage can be flexibly selected according to the type of quenching MOSFET (PMOS / NMOS) to select a fixed reference potential (such as ground potential GND or high potential VDD), ensuring that the MOSFET can normally realize the turn-off and turn-on functions, thereby completing the quenching of avalanche current and device reset.

[0072] In this embodiment, the high-resistance polysilicon resistor is formed using a standard CMOS process. Specifically, one end of the high-resistance polysilicon resistor is connected to the second lead electrode 306, and the other end is connected to a preset voltage (which is consistent with the preset voltage connected to the quenched MOS transistor to ensure stable circuit potential).

[0073] Similar to quenching MOSFETs, high-resistance polysilicon resistors are connected in series with the core avalanche region of SPAD via a second lead electrode 306 at one end. No additional control terminal is required; the avalanche current is quenched solely by the high resistance characteristics of the resistor itself. The connection method is simple and the operation is stable, making it suitable for cost-sensitive applications with low detection speed requirements.

[0074] In other words, both the quenched MOSFET and the high-resistance polysilicon resistor are connected in series with the SPAD core region through the second lead electrode 306, which does not interfere with the normal operation of the avalanche PN junction, nor does it affect the stability of the reverse bias voltage applied to the first lead electrode 307. At the same time, both components can be formed using standard CMOS processes, are compatible with the overall structure process, and can be monolithically integrated with the SPAD core structure and CMOS readout circuit without increasing additional manufacturing costs or affecting the overall compactness of the chip.

[0075] In some alternative embodiments, the single-photon avalanche diode further includes an isolation structure 3010 formed between the second P-type well 303 and the first N-type well 302.

[0076] In this embodiment, the isolation structure 3010 is formed between the second P-type well 303 and the first N-type well 302, and is distributed around the substrate 10 in a direction perpendicular to the thickness (horizontal direction). That is, it is located between the second P-type well 303 (protective ring structure) and the first N-type well 302, filling the gap between them, realizing physical and electrical isolation between the second P-type well 303 and the first N-type well 302, without affecting the contact relationship between the second P-type well 303, the first N-type well 302 and the first P-type well 301, and without destroying the structural integrity of the SPAD core avalanche region.

[0077] The isolation structure 3010 can be shallow trench isolation (STI). As a mature isolation method in standard CMOS processes, shallow trench isolation is highly compatible with the overall device process. Its core function is to achieve precise isolation between the second P-type well 303 and the first N-type well 302. Together with the three-dimensional isolation system formed by the second N-type well 304 and the third N-type well 305 mentioned above, it further optimizes the electric field distribution of the device, blocks abnormal carrier diffusion, and ensures stable operation of the SPAD core avalanche region.

[0078] The isolation structure 3010 employs a shallow trench isolation (STI) process, a standard isolation method in CMOS technology. Specifically, a shallow trench is etched within the epitaxial layer 20 between the second P-type well 303 and the first N-type well 302. The trench is filled with an insulating material (such as silicon dioxide). After planarization, it remains flush with the surfaces of the epitaxial layer 20, the second P-type well 303, and the first N-type well 302, without protrusion or depression. The trench depth and width are optimized to provide excellent electrical insulation without interfering with the electric field distribution in the SPAD core area, while maintaining a compact structure that does not occupy excessive chip area.

[0079] In this embodiment, the isolation structure 3010 is used to isolate the second P-type well 303 (protective ring) from the first N-type well 302 (N-type end of the avalanche PN junction). The insulating material in the trench blocks the lateral diffusion of charge carriers (electrons and holes) between the two, preventing the charge carriers of the second P-type well 303 from entering the first N-type well 302 and interfering with the avalanche multiplication process, thus preventing abnormal avalanche current and increased dark count rate. At the same time, the insulation characteristics of the shallow trench isolation can further alleviate the electric field concentration at the edge of the avalanche PN junction, assisting the protective ring structure of the second P-type well 303 to better suppress edge breakdown, and ensuring that the core avalanche region of the SPAD can achieve avalanche multiplication stably and controllably.

[0080] Optionally, the single-photon avalanche diode includes a third P-type well 308 and a third lead-out electrode 309; Along the direction perpendicular to the thickness of the substrate 10, the third P-type well 308 is located on the side of the second N-type well 304 that is away from the second P-type well 303; The third lead-out electrode 309 is formed in the third P-type well 308, and the third lead-out electrode 309 is flush with the side surface of the third P-type well 308 that is away from the substrate 10, for grounding or providing a fixed potential reference. A reverse-biased PN junction is formed between the third P-type well 308 and the second N-type well 304. This is used to block the lateral diffusion of charge carriers in the photonic avalanche diode.

[0081] In this embodiment, along the direction perpendicular to the thickness of the substrate 10 (horizontal direction), the third P-type well 308 is located on the side of the second N-type well 304 away from the second P-type well 303. That is, the second N-type well 304 is sandwiched between the third P-type well 308 and the second P-type well 303 (protective ring structure), and is distributed around the core region of the SPAD (first P-type well 301, first N-type well 302, shallow trench isolation, second P-type well 303), forming another layer of isolation barrier around the SPAD, adjacent to the second N-type well 304 and forming an electrical contact.

[0082] The third P-type well 308 is formed within the epitaxial layer 20 and is fabricated using a standard CMOS P-type well doping process. The doping concentration has been optimized and is compatible with the processes of the first P-type well 301 and the second P-type well 303. It has a ring-shaped layout, which can be consistent with the surrounding range of the second N-type well 304. It does not occupy too much chip area and does not affect the layout and operation of the first lead electrode 307, the second lead electrode 306, and the quenching element 402.

[0083] The third P-type well 308 and the second N-type well 304 form a reverse-biased PN junction to block the lateral diffusion of charge carriers inside the SPAD device, especially to block the diffusion of charge carriers from the core region of the SPAD to the peripheral CMOS circuit 401. At the same time, it assists the second N-type well 304 and the third N-type well 305 in achieving three-dimensional isolation, further improving the isolation effect. In addition, it provides a stable bearing base for the third lead electrode 309, ensuring that the third lead electrode 309 can achieve reliable electrical contact and potential output.

[0084] In this embodiment, the third lead electrode 309 is formed in the third P-type well 308, corresponding to the annular layout of the third P-type well 308, and achieves good electrical contact with the third P-type well 308, ensuring that the potential can be uniformly transmitted to the entire third P-type well 308, and ensuring the stable operation of the reverse bias PN junction formed by the third P-type well 308 and the second N-type well 304.

[0085] The third lead-out electrode 309 is flush with the surface of the third P-type well 308 on the side away from the substrate 10. It can be made of metal electrode materials (such as aluminum, copper, etc.) that are compatible with standard CMOS processes. Its structure is consistent with the first two lead-out electrodes, without protrusion or depression, avoiding electric field concentration at the electrode edge, and facilitating chip packaging and external circuit connection.

[0086] The third lead electrode 309 is used for grounding or providing a fixed potential reference. By applying a fixed potential (such as ground potential GND) to the third P-type well 308, it ensures that a reverse-biased PN junction can be stably formed between the third P-type well 308 and the second N-type well 304, providing a stable potential basis for blocking the lateral diffusion of charge carriers, and further stabilizing the overall potential distribution of the device, reducing interference caused by potential fluctuations.

[0087] It should be understood that the third P-type well 308 (P-type) and the second N-type well 304 (N-type) are closely adjacent to each other. A fixed potential is applied through the third lead electrode 309, so that the two form a reverse-biased PN junction. This PN junction is in the cut-off state, and the depletion region is widened. This can effectively block the lateral diffusion of charge carriers (electrons and holes) in the core region of the SPAD to the outside of the second N-type well 304, avoid the electrical crosstalk caused by charge carriers entering the peripheral CMOS circuit 401, further improve the isolation effect, and solve the technical problem of incomplete isolation in traditional SPADs.

[0088] Based on the above description of the single-photon avalanche diode of the integrated IC, the single-photon avalanche diode of this embodiment, through its N-on-P structure, DNW surrounding isolation, and the synergistic cooperation of each structure, has the following advantages: The embodiments of this application adopt an N-on-P structure, which significantly improves PDE with limited sacrifice of fill factor, resulting in high avalanche trigger probability and fast response speed. Combined with shallow trench isolation and guard ring structure, it suppresses edge breakdown, reduces dark count rate, and achieves high photon detection efficiency and detection accuracy, making it suitable for core scenario requirements such as ranging and low light detection.

[0089] This application embodiment surrounds the entire N-on-P SPAD photosensitive unit with a DNW (or other deep n-type well), blocking photogenerated carriers (electrons) in the P-EPI from entering the SPAD and interfering with the avalanche signal. This effectively improves SPAD timing jitter, providing a faster response to strong light pulse signals and further enhancing detection timeliness. Timing jitter refers to the random deviation between the trigger time of the avalanche signal generated after a single-photon avalanche diode (SPAD) detects a photon and the theoretical trigger time. Essentially, it is an unstable fluctuation in the trigger time of the avalanche signal (usually measured in ps or ns). Simply put, ideally, when the incident photons arrive at the SPAD at the same time, the trigger time of the avalanche signal should be completely synchronized. However, in reality, due to factors such as carrier movement, electric field fluctuations, and external interference, the trigger time will exhibit a small, random offset, which is the timing jitter.

[0090] This application embodiment constructs a three-dimensional isolation structure 3010, which blocks carrier diffusion in all directions, completely solves the electrical crosstalk and leakage problems when SPAD and CMOS circuit 401 are integrated, and ensures stable operation of the device.

[0091] All structures in the embodiments of this application can be fabricated using standard CMOS processes without the need for additional special processes or materials. The core adopts an N-on-P structure and a DNW-surrounded structure, which can be monolithically integrated with CMOS readout circuits, reducing integration difficulty and manufacturing costs, and facilitating mass production.

[0092] The embodiments of this application have a reasonable and compact structural layout, occupy a small chip area, and offer two types of quenching elements 402 to suit different application scenarios. They can meet the needs of various high-performance single-photon detection applications such as lidar, 3D imaging, weak light detection, and quantum communication.

[0093] The embodiments of this application are described in detail below using a complete example: This embodiment discloses an integrated IC single-photon avalanche diode (SPAD) that can be adapted to high-performance single-photon detection scenarios such as lidar, 3D imaging, and quantum communication. It can be monolithically integrated with CMOS circuits and has the advantages of high detection efficiency, high stability, and low dark count rate. Its specific structure is as follows.

[0094] The single-photon avalanche diode of this embodiment includes, from bottom to top (along the substrate thickness direction): a substrate, an epitaxial layer, and various well structures, isolation structures, lead-out electrodes, and quenching elements formed within the epitaxial layer; along the direction perpendicular to the substrate thickness (horizontal direction), the various well structures and isolation structures are arranged in a ring-shaped layout, and the specific structure, position, and connection relationship of each component are as follows: The substrate is a P-type silicon substrate, which serves as the basic support carrier for the entire SPAD device, providing a stable substrate for the formation of subsequent epitaxial layers and various well structures, and ensuring the stability of the device structure and the reliability of its electrical characteristics.

[0095] The epitaxial layer is a P-type epitaxial layer, formed on the upper surface of the substrate using a standard CMOS epitaxial growth process. The thickness and doping concentration of the epitaxial layer are precisely optimized to support various well structures and isolation structures, avoid interference from substrate impurities on SPAD performance, and provide a basis for photon absorption and carrier transport.

[0096] The core avalanche region is used to achieve photon absorption, carrier generation, and avalanche multiplication. Local isolation structures are used to isolate the internal structures of the core region and prevent mutual interference, as detailed below: The first P-type well is formed in the middle region of the epitaxial layer, located in the lower middle part of the epitaxial layer along the substrate thickness direction. It is the core region for photon absorption and carrier generation. It is prepared using a standard CMOS P-type well doping process with a moderate doping concentration to ensure that the incident photons can be fully absorbed and generate sufficient electron-hole pairs.

[0097] The first N-type well is formed within the epitaxial layer, located on the side of the first P-type well away from the substrate along the substrate thickness direction, and is in contact with the first P-type well. Together, they form an avalanche PN junction. The first P-type well is the P-type end of the PN junction, and the first N-type well is the N-type end of the PN junction, providing a strong electric field basis for avalanche multiplication.

[0098] The second P-type well is formed in the epitaxial layer, located at the same horizontal level as the first N-type well (along the substrate thickness direction), and is in contact with the first P-type well; along the direction perpendicular to the substrate thickness, the second P-type well is arranged in a ring around the periphery of the first N-type well as a protective ring structure to disperse the electric field at the edge of the avalanche PN junction and suppress edge breakdown.

[0099] The isolation structure employs shallow trench isolation (STI), formed between the second P-type well and the first N-type well, distributed horizontally to fill the gap between them. This shallow trench isolation is fabricated using a standard CMOS STI process, where shallow trenches are etched within the epitaxial layer and filled with silicon dioxide insulating material. After planarization, the trenches are flush with the surfaces of the epitaxial layer, the second P-type well, and the first N-type well. This serves to block the lateral diffusion of charge carriers between the second P-type well and the first N-type well, and to assist the guard ring structure in optimizing the electric field distribution.

[0100] The peripheral isolation structure is used to achieve electrical isolation between the SPAD and the CMOS circuitry in the integrated IC, blocking the longitudinal and lateral diffusion of charge carriers. Specifically, it includes: The third N-type well is a deep N-type well (DNW), which is formed in the epitaxial layer. It is located on the side of the first P-type well away from the first N-type well along the substrate thickness direction and is in contact with the first P-type well. It is prepared using a standard CMOS deep N-type well doping process, and the doping concentration is higher than that of ordinary N-type wells. It is responsible for achieving vertical isolation of the SPAD core region and blocking carrier diffusion to the substrate.

[0101] The second N-type well is formed within the epitaxial layer, located on the side of the third N-type well away from the substrate along the substrate thickness direction, and in contact with the third N-type well; in the horizontal direction, the second N-type well is formed in a ring around the second P-type well and the first P-type well, together with the shallow trench isolation and the second P-type well, to form the outer isolation barrier of the core region, responsible for achieving lateral isolation of the SPAD core region.

[0102] The third P-type well is formed within the epitaxial layer, located horizontally on the side of the second N-type well away from the second P-type well, closely adjacent to the second N-type well, and arranged in a ring-like layout. It is fabricated using a standard CMOS P-type well doping process. The third P-type well and the second N-type well form a reverse-biased PN junction, further blocking the lateral diffusion of charge carriers.

[0103] Three leads serve as the electrical interface between the SPAD and external circuits. All three are fabricated using standard CMOS metal electrode technology (aluminum material) and have a flush-mount structure, as detailed below: The first lead electrode is formed in the first N-type well and is flush with the surface of the first N-type well on the side away from the first P-type well. It is used to apply a reverse bias voltage to the first N-type well, so that the avalanche PN junction is in a reverse bias state and provides a strong electric field for avalanche multiplication.

[0104] The second lead electrode is formed in the second P-type well and is flush with the surface of the second P-type well on the side opposite to the first P-type well. It is used for grounding or providing a fixed potential reference, providing a stable potential for the protection ring structure, and also serving as a connection node for the quenching element.

[0105] The third lead electrode is formed in the third P-type well and is flush with the surface of the third P-type well facing away from the substrate. It is used for grounding or providing a fixed potential reference, applying a stable potential to the third P-type well, and ensuring the stable operation of the reverse bias PN junction between the third P-type well and the second N-type well.

[0106] Quenching elements are used to quench avalanche currents generated by SPADs, enabling rapid device reset. One of the following two types can be selected, both fabricated using standard CMOS processes and compatible with the overall structure fabrication: When the quenching element is a quenching MOSFET: a PMOS or NMOS transistor can be selected. The first terminal of the quenching MOSFET is connected to the second lead electrode, and the second terminal is connected to a preset voltage (VDD or GND depending on the type of MOSFET). The gate is used to receive external control signals. The MOSFET is turned off and turned on through the gate control signal, quickly cutting off the avalanche current and completing the quenching and reset.

[0107] When the quenching element is a high-resistance polysilicon resistor: one end of the high-resistance polysilicon resistor is connected to the second lead electrode, and the other end is connected to a preset voltage (consistent with the preset voltage connected to the quenching MOS transistor). No additional control terminal is required. It can limit the avalanche current and reduce the bias voltage across the SPAD by its own high resistance characteristics, thereby achieving avalanche current quenching.

[0108] In this embodiment, the SPAD operates in Geiger mode. The complete working process is as follows, combining the functions of each structure to achieve single-photon detection: Bias and potential setting: A reverse bias voltage is applied to the first N-type well through the first lead electrode, so that the avalanche PN junction formed by the first P-type well and the first N-type well is in a reverse bias state, generating a strong electric field; the second lead electrode and the third lead electrode are grounded to provide a stable ground potential for the second P-type well and the third P-type well, ensuring that the reverse bias PN junction formed by the second P-type well (guard ring), the third P-type well and the second N-type well works stably.

[0109] Photon absorption and carrier generation: After an incident single photon irradiates the device surface, it penetrates the epitaxial layer and is fully absorbed in the first P-type well. Its energy is transferred to the electrons in the well, generating electron-hole pairs, which provide initial carriers for avalanche multiplication.

[0110] Avalanche multiplication: Electrons, as minority carriers, are rapidly accelerated under the influence of the strong electric field in the depletion region of the avalanche PN junction. After gaining sufficient kinetic energy, they collide with atoms in the trap, generating more electron-hole pairs, triggering a chain reaction, and forming an avalanche current.

[0111] Avalanche current quenching: After the avalanche current is generated, the quenching element immediately takes effect. If it is a quenching MOSFET, the gate receives the control signal and quickly turns off, cutting off the avalanche current loop. If it is a high-resistance polysilicon resistor, it terminates the avalanche process and completes the avalanche current quenching by limiting the current and reducing the voltage through high resistance.

[0112] Device Reset and Continuous Detection: After the avalanche current is quenched, the bias voltage across the SPAD quickly recovers to the reverse bias working voltage, and the device is reset from the avalanche state to the standby state, continuing to absorb subsequent incident photons. The above process is repeated to achieve continuous single-photon detection.

[0113] Isolation and protection: During operation, shallow trench isolation blocks carrier crosstalk between the second P-type well and the first N-type well; the third N-type well blocks longitudinal carrier diffusion; the reverse bias PN junction formed by the second N-type well and the third P-type well blocks lateral carrier diffusion, ensuring that the core area of ​​the SPAD does not interfere with the peripheral CMOS circuit and ensuring stable operation of the device.

[0114] Secondly, embodiments of this application also provide a photon detection system, which includes a single-photon avalanche diode of the integrated IC described in the first aspect.

[0115] This photon detection system uses the SPAD as the detection device, along with peripheral circuits such as bias circuits, signal processing circuits, and power supply circuits, to achieve accurate detection, signal conversion, and data output of single-photon signals. Due to the use of the SPAD described in the first aspect, this photon detection system possesses advantages such as high detection efficiency, low dark count rate, and low timing jitter. It is adaptable to various scenarios requiring high-sensitivity single-photon detection, such as weak light detection, quantum communication, and fluorescence detection, and can accurately capture weak photon signals while ensuring the stability and timeliness of detection.

[0116] Thirdly, embodiments of this application provide a lidar system, the system including the single-photon avalanche diode of the integrated IC described in the first aspect.

[0117] The SPAD, as the core receiving device of the lidar system, is used to receive the single-photon signal after the laser pulse is reflected. In conjunction with the laser emission module, scanning module, and signal processing module, it enables distance measurement, target recognition, and 3D imaging. Benefiting from the advantages of the SPAD described in the first aspect, its high PDE (photometric efficiency) with limited sacrifice of fill factor can improve the lidar's detection range and sensitivity. The improved timing jitter enhances the lidar's rapid response to strong light pulse signals, improving ranging accuracy and scanning efficiency, making it suitable for high-performance applications such as automotive lidar and industrial lidar.

[0118] Fourthly, embodiments of this application also provide an imaging system that integrates a single-photon avalanche diode of the integrated IC described in the first aspect.

[0119] The SPAD, serving as the photosensitive core of the imaging system, can be integrated into a SPAD array. Combined with imaging drive circuitry, signal readout circuitry, and image processing module, it enables functions such as low-light imaging and 3D imaging. Due to the SPAD's advantages of high PDE, low dark count rate, and low timing jitter, this imaging system can capture clear photon signals in low-light environments, reducing noise interference and improving image quality. Simultaneously, its high compatibility with CMOS circuits allows for a smaller imaging module size, lower system integration costs, and adaptability to various imaging scenarios such as medical imaging, security monitoring, and 3D scanning.

[0120] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A single-photon avalanche diode integrated into an IC, characterized in that, The single-photon avalanche diode includes: Substrate; An epitaxial layer formed on the substrate; The epitaxial layer contains a first P-type well, a first N-type well, and a second P-type well; wherein, along the thickness direction of the substrate, the first N-type well and the second P-type well are located on the side of the first P-type well away from the substrate and are in contact with the first P-type well; along the thickness direction perpendicular to the substrate, the second P-type well surrounds the first N-type well and is spaced apart from the first N-type well to form a protective ring structure. The first P-type well and the first N-type well form an avalanche PN junction; after the incident photon is absorbed in the first P-type well, an electron-hole pair is generated, in which the electron, as a minority carrier, is accelerated in the depletion region of the avalanche PN junction, triggering avalanche multiplication.

2. The single-photon avalanche diode according to claim 1, characterized in that, The single-photon avalanche diode further includes: a second N-type well and a third N-type well formed in the epitaxial layer; Along the thickness direction of the substrate, the third N-type well is located on the side of the first P-type well that is away from the first N-type well; Along the thickness direction of the substrate, the second N-type well is located on the side of the third N-type well away from the substrate and is in contact with the third N-type well; Along a direction perpendicular to the thickness of the substrate, the second N-type well is disposed around the periphery of the second P-type well and the first P-type well.

3. The single-photon avalanche diode according to claim 2, characterized in that, The third N-type well is a deep N-type well, which is formed using standard CMOS technology.

4. The single-photon avalanche diode according to claim 2, characterized in that, The second N-type well is connected to the third N-type well and a preset voltage is applied, so that the third N-type well forms a reverse-biased PN junction with the first P-type well and the epitaxial layer respectively, so as to electrically isolate the single-photon avalanche diode from the CMOS circuit in the integrated IC.

5. The single-photon avalanche diode according to any one of claims 2-4, characterized in that, The single-photon avalanche diode includes a third P-type well and a third lead-out electrode; Along the direction perpendicular to the substrate thickness, the third P-type well is located on the side of the second N-type well that is away from the second P-type well; The third lead electrode is formed in the third P-type well, and the third lead electrode is flush with the side surface of the third P-type well that is away from the substrate, for grounding or providing a fixed potential reference. A reverse-biased PN junction is formed between the third P-type well and the second N-type well to block the lateral diffusion of charge carriers in the photonic avalanche diode.

6. The single-photon avalanche diode according to any one of claims 1-4, characterized in that, The single-photon avalanche diode further includes a quenching element, which is used to quench the avalanche current generated by the single-photon avalanche diode.

7. The single-photon avalanche diode according to claim 6, characterized in that, The single-photon avalanche diode further includes a first lead-out electrode and a second lead-out electrode; The first lead electrode is formed in the first N-type well, and the first lead electrode is flush with the surface of the first N-type well away from the first P-type well, for applying a reverse bias voltage; The second lead electrode is formed in the second P-type well, and the second lead electrode is flush with the side surface of the second P-type well opposite to the first P-type well, for grounding or providing a fixed potential.

8. The single-photon avalanche diode according to claim 7, characterized in that, The quenching element is a quenching MOS transistor or a high-resistance polysilicon resistor. When the quenching element is the quenching MOS transistor, the first terminal of the quenching MOS transistor is connected to the second lead electrode, the second terminal of the quenching MOS transistor is connected to a preset voltage, and the gate of the quenching MOS transistor is used to receive control signals. When the quenching element is the high-resistance polycrystalline silicon resistor, one end of the high-resistance polycrystalline silicon resistor is connected to the second lead electrode, and the other end is connected to a preset voltage.

9. The single-photon avalanche diode according to any one of claims 1-4, characterized in that, The single-photon avalanche diode further includes an isolation structure formed between the second P-type well and the first N-type well.

10. A photon detection system, characterized in that, Includes the single-photon avalanche diode as described in any one of claims 1-9.

11. A lidar system, characterized in that, Includes the single-photon avalanche diode as described in any one of claims 1-9.

12. An imaging system, characterized in that, Includes the single-photon avalanche diode as described in any one of claims 1-9.

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