Display device and method of manufacturing the same

Abstract

A display device according to an embodiment of the disclosure includes a substrate, a first planarization layer disposed on the substrate, a second planarization layer disposed on the first planarization layer and having an opening, a pixel electrode disposed on the first planarization layer within the opening and extending along an inner side surface of the second planarization layer, and a bank disposed on the pixel electrode and having a hole smaller than the opening. An edge of the opening includes a specific curved area, the opening is defined by the inner side surface of the second planarization layer, and a specific portion of the inner side surface of the second planarization layer corresponding to the specific area can include at least one step.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0181946, filed on December 9, 2024, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0002] Embodiments of this disclosure relate to a display device and a method of manufacturing the same. Background Technology

[0003] In display devices, there are self-emissive display devices where the display panel emits its own light. In a self-emissive display device, the display panel may include a light-emitting device in each sub-pixel.

[0004] Meanwhile, light generated by the light-emitting device of the display panel is emitted to the outside of the display panel through various components. However, some of the light generated by the light-emitting device may be trapped inside the display panel and not escape to the outside. As the amount of light that fails to escape and remains trapped inside the display panel increases, the brightness of the corresponding sub-pixels may decrease. Therefore, the quality of the image displayed on the display panel may eventually deteriorate. In addition, image quality may also be degraded when external light is reflected by the display panel. Summary of the Invention

[0005] This disclosure describes a display device structure that improves light extraction efficiency and image uniformity through an optical side mirror design. A stepped second planarization layer with sloping sidewalls allows pixel electrodes to reflect light outwards, thereby forming a primary emission region (e.g., a first emission region EA1) and a secondary emission region (e.g., an additional second emission region EA2) from the reflected light. Corner regions, which typically have low brightness, are addressed by employing a multi-step geometry at the planarization layer and the embankment sidewalls, achieving uniform brightness across edges and corners while reducing power consumption.

[0006] This manufacturing method employs controlled exposure techniques (such as halftone masks) to precisely form these multi-step geometries, ensuring repeatability in mass production. This stepped design also improves the coating uniformity of the organic encapsulation layer, preventing defects that could compromise moisture resistance or reduce device reliability.

[0007] This structure further integrates flexible and foldable display capabilities, employing a crack-resistant pattern for enhanced durability, and a built-in touch sensor layer arranged along the inclined surface to maintain optical clarity. Combined with the microcavity effect created by the reflective and transparent electrode layers, this design enhances brightness, color purity, and low-power performance, making it suitable for next-generation foldable, wearable, and mobile displays.

[0008] For example, various embodiments of this disclosure can provide a display device with a structure that improves light extraction efficiency.

[0009] Embodiments of this disclosure can provide display devices having structures that improve coating uniformity by providing diffusion paths for organic encapsulation layers.

[0010] The technical advantages of the embodiments of this disclosure are not limited to those described above, and other advantages not mentioned will be clearly understood by those skilled in the art based on the following description.

[0011] Embodiments of this disclosure may provide a display device comprising: a substrate; a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer and having an opening; a pixel electrode disposed within the opening on the first planarization layer and extending along an inner surface of the second planarization layer; and a dam disposed on the pixel electrode and having a hole smaller than the opening, wherein the edge of the opening includes a specific curved region, the opening is defined by the inner surface of the second planarization layer, and a specific portion of the inner surface of the second planarization layer corresponding to the specific region includes at least one step.

[0012] Embodiments of this disclosure may provide a method for manufacturing a display device, comprising: forming a first planarization layer on a substrate; forming a second planarization layer having an opening on the first planarization layer; forming a pixel electrode disposed on the first planarization layer and extending along a side surface of the second planarization layer outside the opening within the opening; and forming a dam on the pixel electrode, the dam having a hole smaller than the opening, wherein forming the second planarization layer includes forming at least one step at a corner portion of the inner surface of the second planarization layer by adjusting the exposure amount.

[0013] According to embodiments of this disclosure, by arranging a second planarization layer having steps and an inclined surface and by extending the pixel electrode along the inclined surface, light generated in the emitting layer of the light-emitting device can be reflected at the inclined surface of the pixel electrode and emitted to the outside. Therefore, light extraction efficiency can be improved.

[0014] According to embodiments of this disclosure, the light extraction efficiency can be further improved through the stepped structure of the second planarization layer.

[0015] According to embodiments of this disclosure, enhanced light extraction efficiency enables the achievement of desired brightness while reducing the driving time or driving voltage of the light-emitting device, thereby allowing for low-power designs that reduce power consumption and extend the lifespan of the light-emitting device.

[0016] According to embodiments of this disclosure, the steps formed in the embankment corresponding to the steps formed in the second planarization layer can prevent the organic encapsulation layer from being uncoated or improperly coated.

[0017] The effects of the embodiments of this disclosure are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art based on the description of the claims. Attached Figure Description

[0018] This disclosure will be more fully understood from the following detailed description and accompanying drawings. The detailed description and accompanying drawings are provided for illustrative purposes only and are not intended to limit the scope of this specification. Figure 1 This is a plan view of a display panel according to an embodiment of the present disclosure. Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A cross-sectional view of the structure of the display panel. Figure 3 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure. Figure 4 The light emission of a sub-pixel region is shown according to an embodiment of this disclosure. Figure 5 This is a plan view of the sub-pixel region according to an embodiment of the present disclosure. Figure 6 This is an embodiment based on the present disclosure. Figure 5 Cross-sectional view. Figure 7 The light emission of a sub-pixel region according to an embodiment of this disclosure is shown. Figure 8 This is a cross-sectional view of a sub-pixel region according to an embodiment of the present disclosure. Figure 9 This is a flowchart illustrating a method for manufacturing sub-pixel regions according to an embodiment of the present disclosure. Figures 10 to 11 A method for manufacturing sub-pixel regions according to an embodiment of the present disclosure is shown. Figures 12 to 16 This is a plan view of the sub-pixel region according to an embodiment of the present disclosure. Figure 17 The light emission of a sub-pixel region according to an embodiment of this disclosure is shown. Detailed Implementation

[0019] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that may be implemented by way of illustration. In the drawings, the same reference numerals and symbols may be used to designate the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such description may make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0020] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of this disclosure. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0021] When referring to a first element as "connected or coupled to a second element," "in contact with a second element," or "overlapping with a second element," it should be interpreted as not only that the first element is "directly connected or coupled to a second element" or "directly in contact with a second element or overlapping with a second element," but also that a third element may be "inserted" between the first and second elements, or that the first and second elements may be "connected or coupled to each other via a fourth element," "in contact with each other," or "overlapping with each other." Here, the second element may be included in at least one of two or more elements that are "connected or coupled to each other," "in contact with each other," or "overlapping with each other."

[0022] When time-relative terms such as “after,” “follow,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, treatment, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately.”

[0023] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of an element or feature (e.g., level, range, etc.) includes tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even when no such description is explicitly given. In addition, the term "can" fully encompasses all the meanings of the term "able to".

[0024] Various embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a diagram illustrating an example of the bending structure and wiring structure in a plan view of a display panel 110 according to an embodiment of the present disclosure.

[0026] refer to Figure 1 According to embodiments of the present disclosure, the substrate 111 of the display panel 110 may include a display area DA and a non-display area NDA. The display area DA and the non-display area NDA may be referred to as areas of the display panel 110.

[0027] All wiring and electrodes are formed on substrate 111. In the display device according to embodiments of the present disclosure, substrate 111 may be a flexible substrate capable of bending. In this disclosure, "bending" may have the same meaning as "folding" or "flexible".

[0028] The non-display area NDA is the area where no image is displayed, and may correspond to the area that does not include the display area DA. Subpixels SP are not set in the non-display area NDA. However, at least one dummy subpixel that does not directly participate in image display may be set in the non-display area NDA.

[0029] The non-display area NDA may include a first non-display area NDA1, a bent area BA, and a second non-display area NDA2.

[0030] The first non-display area NDA1 may be located around the display area DA, and may be the area closest to the display area DA among the first non-display area NDA1, the bent area BA, and the second non-display area NDA2.

[0031] The second non-display area NDA2 may include pad areas PA1 and PA2 with various pads arranged thereon, and may be the area farthest from the display area DA among the first non-display area NDA1, the bending area BA, and the second non-display area NDA2.

[0032] The bending region BA is the area where the substrate 111 is bent, and it can be located between the first non-display region NDA1 and the second non-display region NDA2.

[0033] The substrate 111 may include a display area DA for displaying an image and a non-display area NDA that is an outer region of the display area DA. Multiple sub-pixels SP may be disposed in the display area DA. The non-display area NDA may include a gate GIP region in the panel in which a gate drive circuit of the GIP type is formed, a bend area BA through which various wirings pass and to which the data drive circuit is electrically connected, and a second non-display area NDA2.

[0034] For example, the GIP area can be located in the left outer region and / or right outer region of the display area DA. The bend area BA can be located in the upper outer region or lower outer region of the display area DA. The second non-display area NDA2 can be further peripheral than the bend area BA and can include pad areas PA1 and PA2 that are electrically connected to circuit structures such as printed circuit boards.

[0035] As described above, the substrate 111 may include a folded bending region BA, and the folded bending region BA may be located below the non-folded portion. The bending region BA may be part of the non-display region NDA, and may be located between the drive circuit region electrically connected to the data drive circuit and the display region DA.

[0036] According to the structure of the sub-pixel SP, in order to drive the sub-pixel SP, multiple driving voltage lines DVL for providing driving voltage VDD to the sub-pixel SP and at least one base voltage line VSSL for applying base voltage VSS to the common electrode CE of the light-emitting device ED in each sub-pixel SP can be further disposed on the substrate 111.

[0037] refer to Figure 1 For example, multiple drive voltage lines (DVLs) can be arranged along the column direction, but are not limited to this. In order to effectively transmit the drive voltage VDD through the multiple drive voltage lines (DVLs), a drive voltage pattern integrated with or electrically connected to the multiple drive voltage lines (DVLs) can be set in the non-display area (NDA).

[0038] Multiple drive voltage lines (DVL) can be electrically connected via drive voltage patterns to data drive circuits or printed circuit boards that are connected to pad areas PA1 and PA2 via the bend area BA.

[0039] At least one base voltage line VSSL can be positioned in the non-display area NDA to surround the outer area of ​​the display area DA, thereby effectively delivering the base voltage VSS. Additionally, at least one base voltage line VSSL can be electrically connected via a bend area BA to a data drive circuit or printed circuit board connected to the drive circuit area.

[0040] The substrate 111 may include a crack prevention pattern PCD. The crack prevention pattern PCD may be formed outside the base voltage line VSSL in the non-display area NDA, but is not limited thereto.

[0041] For example, the crack prevention pattern PCD can be a pattern formed to prevent cracking in the wiring passing through the substrate 111, and can be formed as a serrated pattern, but is not limited thereto.

[0042] For example, when the bending area BA is bent, some signal lines passing through the bending area BA may break (electrically open circuit) or short-circuit with adjacent signal lines. In this case, accurate signals may not be transmitted through the broken or short-circuited signal lines, which may cause display driving problems, resulting in improper image display and a significant degrade in image quality. Therefore, a breakage prevention pattern PCD may be included to prevent such problems, but is not limited to this.

[0043] The aforementioned display panel 110 includes a flexible substrate 111, and a portion of the substrate 111 is folded backward by bending a bending region BA connected to the data driving circuit. The folded bending region BA becomes a portion that cannot display images and is not visible from the front. Therefore, by utilizing... Figure 1 The bending structure and wiring arrangement shown can significantly reduce the bezel size of the display device and provide a visually pleasing narrow bezel design.

[0044] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A cross-sectional view of an example structure of the display panel 110.

[0045] refer to Figure 2 The display panel 110 according to the embodiments of the present disclosure may include a substrate 111, a transistor portion, a light-emitting device portion, and an encapsulation portion, but the embodiments of the present disclosure are not limited thereto.

[0046] The substrate 111 can be a single-layer or multi-layer substrate. When the substrate 111 is a multi-layer structure, it may include a first substrate 301, an intermediate substrate layer 302, and a second substrate 303. The intermediate substrate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer; however, embodiments of this disclosure are not limited thereto. The intermediate substrate layer 302 may be an inorganic insulating layer, but is not limited thereto. The intermediate substrate layer 302 can prevent the charge charged in the first substrate 301, which is a polyimide layer, from affecting the transistors disposed on the second substrate 303, which is also a polyimide layer.

[0047] Furthermore, the intermediate substrate layer 302 can prevent moisture from penetrating upward through the first substrate 301. For example, the intermediate substrate layer 302 can be formed as a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), or it can be formed as a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0048] The transistor portion may include insulating layers 311, 312, 313, 321, 322 and 323 on substrate 111, thin-film transistors TFT1 and TFT2, and storage capacitor C.ST And various electrodes or signal lines.

[0049] The thin-film transistors TFT1 and TFT2 included in the transistor section may include a first thin-film transistor TFT1 and a second thin-film transistor TFT2.

[0050] The first thin-film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c.

[0051] The first electrode E1a is the gate electrode, and the second electrode E1b and the third electrode E1c can be either drain electrodes or source electrodes. In the following text, for ease of explanation, the first electrode E1a is referred to as the first gate electrode E1a, the second electrode E1b as the first source electrode E1b, and the third electrode E1c as the first drain electrode E1c. However, embodiments of this disclosure are not limited thereto.

[0052] The first active layer ACT1 may include a first semiconductor material. For example, the first semiconductor material may include, but is not limited to, oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS). The first thin-film transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, but is not limited to.

[0053] The second thin-film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c.

[0054] The fourth electrode E2a is the gate electrode, and the fifth electrode E2b and the sixth electrode E2c can be either drain electrodes or source electrodes. In the following text, for ease of explanation, the fourth electrode E2a is referred to as the second gate electrode E2a, the fifth electrode E2b as the second source electrode E2b, and the sixth electrode E2c as the second drain electrode E2c. However, embodiments of this disclosure are not limited thereto.

[0055] The second active layer ACT2 may include a second semiconductor material. For example, the second semiconductor material may include, but is not limited to, oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS). The second thin-film transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, but is not limited to.

[0056] The semiconductor materials of the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 can be as follows.

[0057] For example, the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 may include oxide semiconductor material or low-temperature polycrystalline silicon semiconductor material.

[0058] exist Figure 2 Depending on the configuration of the sub-pixel circuit SPC, the second thin-film transistor TFT2 connected to the pixel electrode PE of the light-emitting device ED can be a driving transistor DT or another transistor different from the driving transistor DT. For example, it can be a light-emitting control transistor connected between the driving transistor DT and the light-emitting device ED.

[0059] The second active layer ACT2 of the second thin-film transistor TFT2 can be located at a higher position from the substrate 111 than the first active layer ACT1 of the first thin-film transistor TFT1.

[0060] The first buffer layer 311 can be disposed below the first active layer ACT1 of the first thin-film transistor TFT1, and the second buffer layer 321 can be disposed below the second active layer ACT2 of the second thin-film transistor TFT2. For example, the first active layer ACT1 of the first thin-film transistor TFT1 can be located on the first buffer layer 311, and the second active layer ACT2 of the second thin-film transistor TFT2 can be located on the second buffer layer 321. The second buffer layer 321 can be positioned higher than the first buffer layer 311.

[0061] Storage capacitor C ST It can be disposed within various metal layers in the display panel 110. For example, storage capacitor C ST It may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0062] The light-emitting device portion may include a plurality of light-emitting devices ED disposed on the planarization layer 330. Each of the plurality of light-emitting devices ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0063] The encapsulation portion may include an encapsulation layer 200 on multiple light-emitting devices (EDs). The encapsulation layer 200 may be a single layer or multiple layers, but embodiments of this disclosure are not limited thereto. In addition to the encapsulation layer 200, the encapsulation portion may also include at least one dammed area (DAM) for preventing the spillage of material forming the encapsulation layer 200. In particular, when the second encapsulation layer 342 included in the encapsulation layer 200 is an organic encapsulation layer made of organic material, the dammed area (DAM) can prevent the spillage of organic material.

[0064] In the following text, reference will be made to Figure 2 The structure or vertical structure of the display panel 110 according to embodiments of the present disclosure will be described in more detail.

[0065] refer to Figure 2 The first buffer layer 311 may be disposed on the substrate 111. The first buffer layer 311 may be a single layer or multiple layers, but the embodiments of the present disclosure are not limited thereto. When the first buffer layer 311 is multiple layers, the first buffer layer 311 may include a lower buffer layer 311a and an upper buffer layer 311b.

[0066] The first active layer ACT1 of the first thin-film transistor TFT1 may be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0067] The first gate insulating layer 312 can be disposed on the first active layer ACT1 of the first thin-film transistor TFT1. The first gate electrode E1a of the first thin-film transistor TFT1 can be disposed on the first gate insulating layer 312. The first interlayer insulating layer 313 can be disposed on the first gate electrode E1a of the first thin-film transistor TFT1. Here, the metal layer on which the first gate electrode E1a of the first thin-film transistor TFT1 is disposed can be referred to as the first gate metal layer.

[0068] The second buffer layer 321 can be disposed on the first interlayer insulation layer 313.

[0069] The second active layer ACT2 of the second thin-film transistor TFT2 can be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0070] The second gate insulating layer 322 can be disposed on the second active layer ACT2 of the second thin-film transistor TFT2. The second gate electrode E2a of the second thin-film transistor TFT2 can be disposed on the second gate insulating layer 322. The second interlayer insulating layer 323 can be disposed on the second gate electrode E2a of the second thin-film transistor TFT2. Here, the metal layer on which the second gate electrode E2a of the second thin-film transistor TFT2 is disposed can be referred to as the second gate metal layer.

[0071] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 can be disposed on the second interlayer insulating layer 323.

[0072] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 can be connected to the source connection region and the drain connection region of the first active layer ACT1 respectively through holes in the second interlayer insulating layer 323, the second gate insulating layer 322, the second buffer layer 321, the first interlayer insulating layer 313 and the first gate insulating layer 312.

[0073] The second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 can be connected to the source connection region and the drain connection region of the second active layer ACT2, respectively, through holes in the second interlayer insulating layer 323 and the second gate insulating layer 322.

[0074] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, as well as the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2, may include a first source-drain metal and may be disposed in the first source-drain metal layer.

[0075] refer to Figure 2 For example, storage capacitor C ST It can be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor C ST It can be formed by three or more capacitor electrodes, and can be in the form of two or more capacitors connected in parallel.

[0076] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 can be disposed in various metal layers disposed in the display panel 110.

[0077] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 on the first gate insulating layer 312, and may be disposed in the first gate metal layer, but the embodiments of this disclosure are not limited thereto. For example, the second capacitor electrode CAPE2 may be disposed on the first interlayer insulating layer 313.

[0078] The second source electrode E2b of the second thin-film transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 through holes in the second interlayer insulating layer 323, the second gate insulating layer 322, and the second buffer layer 321.

[0079] refer to Figure 2The transistor portion may further include a first shielding pattern BSM1 disposed on the substrate 111. The first shielding pattern BSM1 may overlap with the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 may be disposed below the first active layer ACT1 of the first thin-film transistor TFT1. For example, the first shielding pattern BSM1 may be disposed between the substrate 111 and the first buffer layer 311 or between the lower buffer layer 311a and the upper buffer layer 311b.

[0080] The transistor portion may further include a second shielding pattern BSM2 disposed on the substrate 111. The second shielding pattern BSM2 may overlap with the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 may be disposed below the second active layer ACT2 of the second thin-film transistor TFT2. For example, the second shielding pattern BSM2 may be disposed in a metal layer between the first interlayer insulating layer 313 and the second buffer layer 321. The second shielding pattern BSM2 may be disposed in the same metal layer as the second capacitor CAPE2, but embodiments of this disclosure are not limited thereto. In another example, the second shielding pattern BSM2 may be disposed in the same first gate metal layer as the first gate electrode E1a of the first thin-film transistor TFT1.

[0081] The planarization layer 330 can be disposed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2, and can be disposed below the light-emitting device ED. The planarization layer 330 can be an organic insulating layer including an organic insulating material.

[0082] For example, planarization layer 330 can be configured as a single layer. In another example, planarization layer 330 may include two layers. Planarization layer 330 may include a first planarization layer 331 and a second planarization layer 332. In another example, planarization layer 330 may include three or more layers. Embodiments of this disclosure are not limited thereto.

[0083] refer to Figure 2 The connection electrode RE can be disposed on the first planarization layer 331. The connection electrode RE can be electrically connected to the second source electrode E2b and the pixel electrode PE of the second thin-film transistor TFT2.

[0084] The connection electrode RE can be electrically connected to the second source electrode E2b of the second thin-film transistor TFT2 through a hole in the first planarization layer 331. The second source electrode E2b of the second thin-film transistor TFT2 can be electrically connected to the storage capacitor C. ST The second capacitor electrode CAPE2.

[0085] The connecting electrode RE can be disposed in the second source-drain metal layer on the first planarization layer 331, and can include the second source-drain metal.

[0086] The second planarization layer 332 can be disposed on the connecting electrode RE.

[0087] refer to Figure 2 The light-emitting device portion can be disposed on the second planarization layer 332. The light-emitting device ED can be formed on the second planarization layer 332. The light-emitting device ED can include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region of the light-emitting device ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact.

[0088] The pixel electrode PE can be disposed on the second planarization layer 332. The pixel electrode PE can be electrically connected to the connection electrode RE through a hole in the second planarization layer 332.

[0089] The dam 340 can be disposed on the pixel electrode PE. The opening of the dam 340 can expose a portion of the pixel electrode PE to form a light-emitting area. The opening of the dam 340 can overlap with a portion of the pixel electrode PE.

[0090] For example, the dam portion 340 may be formed of a material including black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but the embodiments of this disclosure are not limited thereto. When the dam portion 340 is formed of a material including black pigment or black dye, it may be a black dam portion. When the dam portion 340 is formed of a material including black pigment or black dye, it may block external light or reflected external light, thereby improving the brightness of the display device.

[0091] The intermediate layer EL of the light-emitting device ED can be disposed on the portion of the pixel electrode PE and the embankment 340. The common electrode CE can be disposed on the intermediate layer EL.

[0092] refer to Figure 2 The encapsulation portion can be disposed on the light-emitting device portion and can be located on the common electrode CE. The encapsulation portion may include an encapsulation layer 200 formed on the common electrode CE.

[0093] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the light-emitting device ED. The encapsulation layer 200 can be formed as a single layer or multiple layers, but the embodiments of this disclosure are not limited thereto.

[0094] For example, the encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343, but the embodiments of this disclosure are not limited thereto. For example, the first encapsulation layer 341 and the third encapsulation layer 343 may include inorganic encapsulation layers, and the second encapsulation layer 342 may include an organic encapsulation layer, but the embodiments of this disclosure are not limited thereto.

[0095] The display panel 110 according to embodiments of the present disclosure may include a built-in touch sensor. In this case, the display panel 110 according to embodiments of the present disclosure may include a touch sensor layer 210 formed on the encapsulation layer 200.

[0096] refer to Figure 2 The touch sensor layer 210 may include a plurality of touch electrodes TE corresponding to the touch sensor, and may include at least one touch metal layer for forming the plurality of touch electrodes TE.

[0097] For example, the touch sensor layer 210 may include a first touch metal layer on which a plurality of first touch metals TM1 are disposed and a second touch metal layer on which a plurality of second touch metals TM2 are disposed to form a plurality of touch electrodes TE. In this case, the touch sensor layer 210 may also include a touch interlayer insulating layer 352 disposed between the first touch metal layer and the second touch metal layer.

[0098] For example, one of the first touch metal layer and the second touch metal layer can be a sensor metal layer, while the other can be a bridge metal layer.

[0099] For example, the first touch metal layer can be a bridging metal layer, and the second touch metal layer can be a sensor metal layer. In this case, the plurality of second touch metals TM2 disposed in the second touch metal layer can be sensor metals forming a touch sensor, and the plurality of first touch metals TM1 disposed in the first touch metal layer can be bridging metals electrically connecting the plurality of second touch metals TM2 as sensor metals. For example, two or more second touch metals TM2 and at least one first touch metal TM1 can constitute a first touch electrode TE1. In this case, two or more second touch electrodes TE2 can be electrically connected through at least one first touch metal TM1.

[0100] In another example, the first touch metal layer may be a sensor metal layer, and the second touch metal layer may be a bridging metal layer. In this case, the plurality of first touch metals TM1 disposed in the first touch metal layer may be sensor metals forming a touch sensor, and the plurality of second touch metals TM2 disposed in the second touch metal layer may be bridging metals electrically connecting the plurality of first touch metals TM1 that serve as sensor metals.

[0101] In another example, each of the first touch metal layer and the second touch metal layer can be a sensor metal layer and a bridging metal layer. For example, the first touch metal layer can be both a sensor metal layer and a bridging metal layer, and the second touch metal layer can be both a sensor metal layer and a bridging metal layer. In this case, the plurality of first touch metals TM1 disposed in the first touch metal layer can include sensor metal and bridging metal, and the plurality of second touch metals TM2 disposed in the second touch metal layer can include sensor metal and bridging metal.

[0102] refer to Figure 2 The touch sensor layer 210 may further include a touch buffer layer 351 disposed on the encapsulation layer 200. The touch buffer layer 351 may be disposed between the encapsulation layer 200 and the touch metal layer. For example, a first touch metal layer may be disposed on the touch buffer layer 351, and an interlayer insulation layer 352 may be disposed on the first touch metal layer.

[0103] refer to Figure 2 The touch sensor layer 210 may also include a touch protection layer 353 configured to cover the touch metal layer. For example, the touch protection layer 353 may be disposed on a second touch metal layer.

[0104] For example, the touch buffer layer 351 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material, the touch interlayer insulation layer 352 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material, and the touch protection layer 353 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material.

[0105] For example, at least one of the touch buffer layer 351 and the touch interlayer insulating layer 352 may extend from the display area DA to the non-display area NDA. The touch protection layer 353 may extend from the display area DA to the non-display area NDA.

[0106] The touch wiring TL can electrically connect the touch electrode TE and the touch pad TP. The touch wiring TL can be configured by at least one of the first touch metal TM1 and the second touch metal TM2.

[0107] For example, a touch wiring TL may include multiple wiring segments, and each of the multiple wiring segments may be a single wiring segment or a dual wiring segment. Here, a single wiring segment may be a segment with one signal path, and a dual wiring segment may be a segment with two signal paths connected in parallel.

[0108] The touch wiring TL can be set along the inclined surface of the encapsulation layer 200 and can extend to the touch pad TP through the top of the dams DAM1 and DAM2.

[0109] Touch buffer layer 351 may have an opening that exposes at least a portion of the touch pad TP. Touch wiring TL can be electrically connected to the touch pad TP through the opening in touch buffer layer 351. Touch interlayer insulation layer 352 may be disposed on the touch wiring TL and may extend to the area where the touch pad TP is disposed. Touch protection layer 353 may be disposed only in the display area DA, or may extend to the non-display area NDA and also be disposed on the touch wiring TL. In some cases, touch protection layer 353 may further extend to the top of the touch pad TP.

[0110] Each of the plurality of touch electrodes TE can be a mesh electrode with multiple openings. In this case, each of the plurality of touch electrodes TE can be configured by at least one of the second touch metals TM2. However, embodiments of this disclosure are not limited thereto.

[0111] For example, multiple touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. When the first touch metal layer is a bridging metal layer and the second touch metal layer is a sensor metal layer, two or more second touch metals TM2 forming a first touch electrode TE1 corresponding to the touch sensor can be electrically connected via at least one first touch metal TM1 serving as a bridging metal. For example, two second touch metals TM2 spaced apart from each other can be electrically connected via a first touch metal TM1 to form a first touch electrode TE1.

[0112] refer to Figure 2 The plurality of first touch metals TM1 and the plurality of second touch metals TM2 can be configured not to overlap with the light-emitting device ED. The plurality of first touch metals TM1 and the plurality of second touch metals TM2 can overlap with the embankment 340. Therefore, the luminous efficiency of the light-emitting device ED can be improved.

[0113] refer to Figure 2 The touch wiring TL can connect the touch pad TP in the pad area PA in the second non-display area NDA2 and the first touch electrode TE1 in the display area DA. Therefore, the touch wiring TL can span the second non-display area NDA2, the bending area BA, and the first non-display area NDA1.

[0114] The touch wiring TL may include a first wiring segment TLa, a second wiring segment TLb, and a third wiring segment TLc. For example, the touch wiring TL may include the first wiring segment TLa and the second wiring segment TLb disposed in the first non-display area NDA1 and the second non-display area NDA2, and the third wiring segment TLc disposed in the bending area BA. The third wiring segment TLc may connect the first wiring segment TLa and the second wiring segment TLb.

[0115] The first wiring segment TLa of the touch wiring TL can be a single wiring segment, and may also include a third touch metal layer, wherein the third touch metal TM3 is disposed in the third touch metal layer.

[0116] The first wiring segment TLa of the touch wiring TL can extend along the inclined surface of the encapsulation layer 200 and can be set on top of at least one of the dam sections DAM1 and DAM2.

[0117] For example, the first wiring segment TLa of the touch wiring TL can be connected to the third wiring segment TLc of the touch wiring TL through at least one of the first touch metal layer and the second touch metal layer.

[0118] The second wiring segment TLb of the touch wiring TL may include at least one of a first touch metal layer in which a first touch metal TM1 is disposed and a second touch metal TM2 is disposed.

[0119] For example, the second wiring segment TLb of the touch wiring TL can be electrically connected to the touch pad TP through a contact hole (opening) passing through the second planarization layer 332, the touch buffer layer 351 and the touch interlayer insulation layer 352.

[0120] For example, the third wiring segment TLc of the touch wiring TL can be connected to the second wiring segment TLb of the touch wiring TL.

[0121] The third wiring section TLc of the touch wiring TL may include metal layers different from the first to third touch metal layers in which the first touch metal TM1, the second touch metal TM2 and the third touch metal TM3 are disposed.

[0122] The touch pad TP can be electrically connected to the second wiring segment TLb of the touch wiring TL, and can include a metal layer different from the first to third touch metal layers.

[0123] refer to Figure 2 The display panel 110 of the display device according to an embodiment of the present disclosure may further include a common voltage line VSSL to which a common voltage VSS is applied, and a connection pattern for connecting the common electrode CE and the common voltage line VSSL.

[0124] For example, the connection pattern may include a first connection pattern CP1 and a second connection pattern CP2.

[0125] For example, the first connection pattern CP1 can connect the common electrode CE and the second connection pattern CP2, and the second connection pattern CP2 can connect the first connection pattern CP1 and the common voltage line VSSL, but is not limited thereto.

[0126] For example, the first connection pattern CP1 may include the same material as the pixel electrode PE. The second connection pattern CP2 may include the same material as the connection electrode RE.

[0127] Figure 3 This is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0128] refer to Figure 3 A first planarization layer 331 is formed on the substrate 111. The top surface of the first planarization layer 331 is parallel to the surface of the substrate 111. Other layers may be formed between the substrate 111 and the first planarization layer 331. The first planarization layer 331 can reduce height differences between the substrate 111 or the layers formed on the substrate 111. The first planarization layer 331 may be formed from, but is not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist.

[0129] A second planarization layer 332 with an opening PH can be disposed on the first planarization layer 331. The first planarization layer 331 and the second planarization layer 332 can be integrally formed. The first planarization layer 331 and the second planarization layer 332 can be collectively referred to as planarization layer 330. The first planarization layer 331 and the second planarization layer 332 can be formed from the same material and can be formed simultaneously by the same process (e.g., mask process), but are not limited thereto. The second planarization layer 332 includes a top surface and side surfaces. The top surface of the second planarization layer 332 is the surface located at the very top of the second planarization layer 332 and can be substantially parallel to the top surface of the first planarization layer 331 or the substrate 111. The side surfaces of the second planarization layer 332 can have an inclined shape extending from the top surface toward the first planarization layer 331.

[0130] exist Figure 3 In this context, the planarization layer 330 is described as including a first planarization layer 331 and a second planarization layer 332, but the detailed structure of the planarization layer 330 is not limited to the first planarization layer and the second planarization layer, and may be defined differently.

[0131] refer to Figure 3 The light-emitting device ED can be disposed on the first planarization layer 331. The light-emitting device ED may include a pixel electrode PE disposed on the first planarization layer 331 and the second planarization layer 332, an intermediate layer EL disposed on the pixel electrode PE, and a common electrode CE disposed on the intermediate layer EL.

[0132] The pixel electrode PE can be disposed on the first planarization layer 331 within the opening PH of the second planarization layer 332, and can extend along the inner surface of the second planarization layer 332. The pixel electrode PE can be disposed on the top surface of the first planarization layer 331, the inner surface of the second planarization layer 332, and the top surface of the second planarization layer 332. Therefore, the pixel electrode PE can have a flat top surface on the top surfaces of the first planarization layer 331 and the second planarization layer 332, and can have a sloping top surface on the side surface of the second planarization layer 332.

[0133] The pixel electrode PE can consist of a reflective layer and a transparent conductive layer disposed on the reflective layer. Since the display device according to the embodiments of this disclosure is a top-emitting type light-emitting display device, the reflective layer can reflect the light emitted from the light-emitting device ED towards the top.

[0134] The reflective layer can be made of metallic materials. For example, the reflective layer can be made of metallic materials such as aluminum (Al), silver (Ag), copper (Cu), or magnesium-silver alloy (Mg:Ag), but is not limited to these.

[0135] refer to Figure 3 A dam 340 with a dam aperture BH smaller than the opening PH can be disposed on the pixel electrode PE. The dam 340 includes a top surface and side surfaces. The top surface of the dam 340 is the surface located at the very top of the dam 340 and can be substantially parallel to the second planarization layer 332. The side surfaces of the dam 340 can have an inclined shape from the top surface toward the first planarization layer 331. The dam aperture BH region can correspond to the main light-emitting region.

[0136] The dam 340 can be made of organic or inorganic materials. For example, when the dam 340 is made of organic materials, it can be formed of polyimide, acrylic acid, or benzocyclobutene resin. When the dam layer is made of inorganic materials, the dam layer can be formed of amorphous silicon, silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0137] The intermediate layer EL can be disposed on the pixel electrode PE and the dam 340. For example, in the dam hole BH, the intermediate layer EL can be disposed on the pixel electrode PE, and in the region outside the dam hole BH, the intermediate layer EL can be disposed on the dam 340.

[0138] Since the intermediate layer EL is disposed on the dam 340 outside the dam hole BH, the intermediate layer EL can also be configured to conform to the shape of the dam 340. Therefore, the intermediate layer EL can have a flat top surface on the pixel electrode PE inside the dam hole BH and on the dam 340 outside the dam hole BH, and can have an inclined top surface on the side surface of the dam 340.

[0139] The intermediate EL layer can be a layer for emitting light of a specific color, and can include at least one of a red emitting layer, a green emitting layer, a blue emitting layer, and a white emitting layer. The intermediate EL layer can also include various layers, such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron blocking layer, and an electron transport layer. The intermediate EL layer can be an organic emitting layer made of organic materials, but is not limited to this. For example, the intermediate EL layer can be a quantum dot emitting layer or a micro-LED.

[0140] The common electrode (CE) can be disposed on the intermediate layer (EL). The common electrode (CE) can supply electrons to the intermediate layer (EL). The common electrode (CE) can be made of a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or tin oxide (TO), or a ytterbium (Yb) alloy. The common electrode (CE) can also be made of a metallic material such as silver (Ag), copper (Cu), or a magnesium-silver alloy (Mg:Ag), or a metallic material with a very thin thickness. Because the display device is top-emitting, the common electrode (CE) can be very thin, so that its refractive index does not affect light propagation.

[0141] Since the common electrode CE is disposed on the intermediate layer EL outside the dam hole BH, the common electrode CE can also be disposed in accordance with the shape of the dam 340. Therefore, the common electrode CE can have a flat top surface on the pixel electrode PE inside the dam hole BH and on the dam 340 outside the dam hole BH, and can have an inclined top surface on the side surface of the dam 340.

[0142] refer to Figure 3 The encapsulation portion 200 can be disposed on the light-emitting device ED. The encapsulation portion 200 can be configured to cover the common electrode CE. The encapsulation portion 200 can protect the intermediate layer EL from moisture or oxygen penetration from the outside of the display device.

[0143] The encapsulation portion 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343.

[0144] The first encapsulation layer 341 can be disposed on the common electrode CE and can inhibit the permeation of moisture or oxygen. The first encapsulation layer 341 can be made of inorganic materials, such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), or aluminum oxide (AlyOz), but is not limited thereto.

[0145] When the first encapsulation layer 341 is disposed on the common electrode CE, the first encapsulation layer 341 can also be configured to conform to the shape of the common electrode CE. Therefore, the first encapsulation layer 341 can have a flat top surface on the pixel electrode PE within the dam hole region BH and on the dam 340 outside the dam hole BH, and can have an inclined top surface on the side surface of the dam 340.

[0146] The second encapsulation layer 342 may be disposed on the first encapsulation layer 341 to planarize its surface. The second encapsulation layer 342 may also cover foreign matter or particles that may occur during the manufacturing process. The second encapsulation layer 342 may be made of organic materials, such as, but not limited to, silicon carbide (SiOxCz), acrylic acid, or epoxy resin.

[0147] Similar to the first encapsulation layer 341, the third encapsulation layer 343 can be disposed on the second encapsulation layer 342 and can inhibit the permeation of moisture or oxygen. The third encapsulation layer 343 can be made of inorganic materials, such as silicon nitride (SiNx), silicon oxynitride (SiNxOy), silicon oxide (SiOx), or aluminum oxide (AlyOz), but is not limited thereto. The third encapsulation layer 343 can be made of the same material as the first encapsulation layer 341 or a different material than the first encapsulation layer 341.

[0148] Since the display device according to the embodiments of this disclosure is a top-emitting display device, a microcavity can be realized. For example, in the display device according to the embodiments of this disclosure, by setting the distance between the reflective layer of the pixel electrode PE and the common electrode CE, constructive interference of light emitted from the intermediate layer EL can be achieved to improve light efficiency.

[0149] In the display panel 110 according to an embodiment of the present disclosure, a portion of the pixel electrode PE may extend along the inclined surface of the second planarization layer 332. In this disclosure, this structure is referred to as an optical side mirror (OSM) structure.

[0150] The display panel 110 according to embodiments of the present disclosure may include an optical mirror structure, so that the second emission region EA2 may be additionally formed by light reflected from a portion of the pixel electrode PE disposed on the side surface of the second planarization layer 332. That is, the emission region formed in each of the plurality of sub-pixels may include not only the first emission region EA1 but also the second emission region EA2.

[0151] Of the total amount of light emitted from the intermediate EL layer, some light can be trapped inside the display panel 110 and may not be emitted from the outside. The ratio of the amount of light emitted to the outside of the display panel 110 to the total amount of light emitted from the intermediate EL layer is usually called the light extraction efficiency.

[0152] The optical side mirror (OSM) structure of the display panel 110 according to the embodiments of the present disclosure can improve light extraction efficiency.

[0153] Figure 4 Light emission in a sub-pixel region SPA according to an embodiment of the present disclosure is shown.

[0154] like Figure 4 As shown, the sub-pixel region SPA can form a first emission region EA1 corresponding to the hole in the embankment and a second emission region EA2 surrounding the first emission region EA1. An intermediate region MA, optically distinguishable from the first emission region EA1 and the second emission region EA2, can exist between the first emission region EA1 and the second emission region EA2. Alternatively, the intermediate region MA may not exist between the first emission region EA1 and the second emission region EA2.

[0155] The first emission region EA1 can be referred to as the main emission region of the opening PH. The first emission region EA1 can correspond to the embankment hole BH.

[0156] The intermediate region MA can correspond to the region of the opening PH of the second planarization layer 332, excluding the embankment hole BH.

[0157] The second emission region EA2 can correspond to the region between the start and end points of the inclined surface of the second planarization layer 332.

[0158] The first emission region EA1 can have a first brightness. The second emission region EA2 can have a second brightness lower than the first brightness. The intermediate region MA can have a third brightness lower than the second brightness.

[0159] Figure 5 This is a plan view of a sub-pixel region SPA according to an embodiment of the present disclosure.

[0160] refer to Figure 5 The subpixel region SPA may include an opening PH and a second planarization layer 332. The edge of the opening PH may include a corner portion 550 and an edge portion 540. The opening PH refers to the opening of the second planarization layer, and in the following text, the opening PH is used to indicate the opening of the second planarization layer.

[0161] The curved area included in the edge of the opening PH may correspond to the corner portion 550. Even under the same process conditions, the corner portion 550 and the edge portion 540 may have different cross-sections. For example, the inclination angle of the second planarization layer 332 in the corner portion 550 may be greater than the inclination angle of the second planarization layer 332 in the edge portion 540. The distance between the end of the second planarization layer 332 in the corner portion 550 and the end of the embankment 340 may be longer than the distance between the end of the second planarization layer 332 in the edge portion 540 and the end of the embankment 340.

[0162] Figure 6 An embodiment according to this disclosure is shown. Figure 5 Cross-sectional view of the corner portion 550 and the edge portion 540.

[0163] refer to Figure 6 The structure of the second planarization layer 332 may differ between the corner portion 550 and the edge portion 540. The structure of the sub-pixel region SPA according to embodiments of this disclosure will be described in more detail below. Figure 6 Includes corner section diagram 520 and edge section diagram 510. Figure 6 Edge section diagram 510 and Figure 3 The same as described in the text, therefore it will be omitted.

[0164] refer to Figure 6 In the corner portion 550 corresponding to the curved edge region of the opening PH, the inclination of the second planarization layer 332 can be formed more steeply. The second angle θ2 (also referred to as "second inclination angle θ2") between the side surfaces of the first planarization layer 331 and the second planarization layer 332 formed in the corner portion 550 can be greater than the first angle θ1 (also referred to as "first inclination angle θ1") between the side surfaces of the first planarization layer 331 and the second planarization layer 332 formed in the edge portion 540 (see also 510).

[0165] Referring to the corner cross-sectional view 520, the second separation distance d2 between the end of the second flattening layer 332 in the corner portion 550 and the end of the embankment 340 can be greater than the first separation distance d1 between the end of the second flattening layer 332 in the edge portion 540 and the end of the embankment 340.

[0166] Due to the difference in angle and separation distance between the edge portion 540 and the corner portion 550, light may not be emitted from the corner portion 550.

[0167] Figure 7 Light emission in a sub-pixel region SPA according to an embodiment of the present disclosure is shown.

[0168] refer to Figure 7 There is a possibility that light may not be emitted from the corner portion 550 of the second emission region EA2. The amount of light emitted between the edge portion 540 and the corner portion 550 may differ. The corner portion 550 may emit less light than the edge portion 540. Therefore, a difference may occur between the edge portion 540 and the corner portion 550, leading to image quality degradation.

[0169] The following describes a structure for improving light emission in corner sections to address this problem.

[0170] Figure 8 This is a cross-sectional view of a sub-pixel region SPA according to an embodiment of the present disclosure.

[0171] refer to Figure 8 The method used to solve Figure 4 and Figure 7 The corner section 550 shown is an improved corner launch structure to address the launch problem.

[0172] Figure 8 The edge cross-sectional view 530 of the opening PH of the second planarization layer 332 shown is... Figure 6 The edge section shown is the same as in Figure 510, and therefore the description is omitted.

[0173] A corner cross-sectional view 530 will be described. Corner cross-sectional view 530 discloses other layers disposed on the second planarization layer 332. The display panel 110 may include a substrate 111, a first planarization layer 331 disposed on the substrate 111, a second planarization layer 332 having an opening PH and disposed on the first planarization layer 331, a pixel electrode PE disposed within the opening PH on the first planarization layer 331 and extending along the inner surface of the second planarization layer 332, and a dam 340 disposed on the pixel electrode PE and having a hole BH smaller than the opening PH. The edge of the opening PH may include a specific curved region, and a specific portion 700 of the inner surface of the second planarization layer 332 corresponding to the specific region may have at least one step.

[0174] In the following text, the term “opening PH” refers to the opening of the second planarization layer, and the term “hole” refers to the hole in the dike, and both terms are used accordingly.

[0175] The following is for reference. Figure 8A detailed description of the cross-sectional view of the corner portion is provided. A first planarization layer 331 may be disposed on the substrate 111. The top surface of the first planarization layer 331 may be parallel to the substrate 111. Other layers may be disposed between the substrate 111 and the first planarization layer 331. The first planarization layer 331 may mitigate the height difference between the layers disposed on the substrate 111 or the substrate 111 itself. The first planarization layer 331 may be formed from, but is not limited to, one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, benzocyclobutene, and photoresist.

[0176] A second planarization layer 332 with an opening PH can be disposed on the first planarization layer 331. The second planarization layer 332 includes a top surface and side surfaces. The top surface of the second planarization layer 332 is the topmost surface of the second planarization layer 332 and can be substantially parallel to the top surface of the first planarization layer 331 or the substrate 111. A certain portion of the inner side surface of the second planarization layer 332 may include a first inclined surface 810 extending from the bottom surface of the second planarization layer 332, a first connecting surface 820 extending from the first inclined surface 810 and having a gentler slope than the first inclined surface 810, and a second inclined surface 830 extending from the first connecting surface 820 and having a steeper slope than the first connecting surface 820.

[0177] In the vertical direction, the first height H1 from the start point to the end point of the first inclined surface 810 may be different from the second height H2 from the start point to the end point of the second inclined surface 830.

[0178] A specific portion of the inner surface of the second planarization layer 332 can be recessed inward at a specific height.

[0179] The first planarization layer 331 and the second planarization layer 332 can be integrally formed. The combination of the first planarization layer 331 and the second planarization layer 332 can be referred to as planarization layer 330. The first planarization layer 331 and the second planarization layer 332 can be formed from the same material. The second planarization layer 332 may include steps formed by adjusting the exposure using a halftone mask.

[0180] Although the planarization layer 330 is in Figure 8 The planarization layer 330 is described as including a first planarization layer 331 and a second planarization layer 332, but the detailed configuration of the planarization layer 330 is not limited to the first planarization layer 331 and the second planarization layer 332, and may be defined differently.

[0181] refer to Figure 8The light-emitting device ED can be disposed on the first planarization layer 331. The light-emitting device ED may include a pixel electrode PE disposed on the first planarization layer 331 and the second planarization layer 332, an intermediate layer EL disposed on the pixel electrode PE, and a common electrode CE disposed on the intermediate layer EL.

[0182] The pixel electrode PE can be disposed on the first planarization layer 331 within the opening PH, and can extend along the inner surface of the second planarization layer 332. The pixel electrode PE can be disposed on the top surface of the first planarization layer 331, the inner surface of the second planarization layer 332, and the top surface of the second planarization layer 332. Therefore, the pixel electrode PE can be disposed along the shape of the first inclined surface 810, the first connecting surface 820, and the second inclined surface 830 of the second planarization layer 332, and can have a stepped inclined side surface.

[0183] The pixel electrode may consist of a reflective layer and a transparent conductive layer disposed on the reflective layer. Since the display device according to the embodiments of this disclosure is a top-emitting type light-emitting display device, the reflective layer can reflect the light emitted from the light-emitting device ED towards the top.

[0184] The reflective layer can be made of metallic materials. For example, the reflective layer can be made of metallic materials such as aluminum (Al), silver (Ag), copper (Cu), or magnesium-silver alloy (Mg:Ag), but is not limited to these.

[0185] refer to Figure 8 A dam portion 340 having an opening smaller than the opening pH can be disposed on the pixel electrode PE. The dam portion 340 includes a top surface and side surfaces. The top surface of the dam portion 340 is the surface located at the topmost portion of the dam portion 340 and can be substantially parallel to the second planarization layer 332. The side surfaces of the dam portion 340 can have an inclined shape from the top surface toward the first planarization layer 331. The side surfaces of the dam portion 340 can be shaped along the first inclined surface 810, the first connecting surface 820, and the second inclined surface 830 of the second planarization layer 332. The dam portion 340 can also have steps on its side surfaces. A portion of the inner side surface of the dam portion 340 corresponding to one of the steps in the second planarization layer 332 can include at least one step.

[0186] The embankment can be made of organic or inorganic materials. For example, when the embankment 340 is made of organic materials, it can be formed of a resin based on polyimide, acrylic acid or benzocyclobutene, and when it is made of inorganic materials, it can be formed of amorphous silicon, silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto.

[0187] The light-emitting device may include an intermediate layer EL disposed on the pixel electrode PE and extending above the embankment, and a common electrode CE disposed on the intermediate layer EL. The intermediate layer EL and the common electrode CE may have steps in a region of the second planarization layer 332 having at least one step.

[0188] The intermediate layer EL can be disposed on a portion of the pixel electrode PE and a portion of the dam 340. For example, the intermediate layer EL can be disposed on the pixel electrode PE inside the dam hole BH and on the dam 340 outside the dam hole BH. Since the intermediate layer EL is disposed on the dam 340 outside the dam hole, it can also be disposed along the shape of the dam 340. Therefore, the intermediate layer EL can have a flat upper surface on the pixel electrode PE inside the dam hole BH and on the dam 340 outside the dam hole. The intermediate layer EL can be disposed along the shape of the first inclined surface 810, the first connecting surface 820 and the second inclined surface 830 of the second planarization layer 332, and can include steps on its side surface. The portion of the side surface of the intermediate layer EL corresponding to one of the steps of the second planarization layer 332 can include at least one step.

[0189] The intermediate EL layer can be a layer for emitting light of a specific color, and can include at least one of a red emitting layer, a green emitting layer, a blue emitting layer, and a white emitting layer. Furthermore, the intermediate EL layer can also include various layers, such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron blocking layer, and an electron transport layer. The intermediate EL layer can be an organic light-emitting layer made of organic materials, but is not limited to this. For example, the intermediate EL layer can be a quantum dot emitting layer or a micro-LED.

[0190] The common electrode CE can be disposed on the intermediate layer EL. Since the common electrode CE is disposed on the intermediate layer EL outside the dam hole BH, it can also be disposed along the shape of the dam 340. Therefore, the common electrode CE can have a flat upper surface on the intermediate layer EL inside the dam hole BH and on the dam 340 outside the dam hole BH, and can have an inclined side surface on the side surface of the dam 340. The common electrode CE can be disposed along the shape of the intermediate layer EL, and the portion of the side surface of the common electrode CE corresponding to one of the steps of the second planarization layer 332 can include at least one step.

[0191] The common electrode (CE) supplies electrons to the intermediate layer (EL). The common electrode (CE) can be formed from a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or tin oxide (TO), or a ytterbium (Yb) alloy. Alternatively, the common electrode (CE) can be formed from a metallic material such as silver (Ag), copper (Cu), or a magnesium-silver alloy (Mg:Ag), or a very thin metallic material. Because the display device is top-emitting, the common electrode (CE) can be very thin, so its refractive index may not affect light propagation.

[0192] refer to Figure 8 The encapsulation portion 200 can be disposed on the light-emitting device ED. The encapsulation portion 200 can be configured to cover the common electrode CE. The encapsulation portion 200 can protect the intermediate layer EL from moisture or oxygen penetration from the outside of the display device.

[0193] The encapsulation portion 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343.

[0194] The display panel 110 according to an embodiment of the present disclosure may have an optical mirror structure, and the additional second emitting region EA2 may be formed by light reflected from a portion of the pixel electrode PE disposed on the side surface of the second planarization layer 332. That is, the light-emitting region formed in each of the plurality of sub-pixels may include not only the first emitting region EA1, but also the second emitting region EA2.

[0195] Some of the total light emitted from the intermediate EL layer can be captured inside the display panel 110 and may not be emitted to the outside. The ratio of the amount of light emitted to the outside of the display panel 110 to the total amount of light emitted in the intermediate EL layer is usually called the light extraction efficiency.

[0196] The display panel 110 according to an embodiment of the present disclosure can increase the ratio of light normally emitted to the outside of the display panel 110 by adjusting the exposure and forming a step in the second planarization layer 332 at the corner portion 550 of the opening PH. Therefore, light extraction efficiency can be improved compared to existing optical side mirror structures.

[0197] The display panel 110 according to an embodiment of the present disclosure can provide a path for extensive application of an organic encapsulation layer by forming steps in the second planarization layer 332.

[0198] refer to Figure 8 The sub-pixel region SPA may include a planarization layer opening PH and a planarization layer 332. The planarization layer opening PH is an opening PH of the planarization layer 332. The planarization layer opening PH may include an edge portion 540 and a corner portion 550.

[0199] In one example, the edge of the planarization layer opening PH can be polygonal and can include specific segments corresponding to the vertices of the polygon. In another example, the edge of the planarization layer opening PH can have a circular or elliptical shape and can include specific segments 700 corresponding to the perimeter of the circle or ellipse.

[0200] The edge of the planarization layer opening PH may include a plurality of straight edge portions 540 and a plurality of curved corner portions 550. Each of the plurality of corner portions 550 may correspond to a specific segment, and the inner surface of the corner of the second planarization layer 332 corresponding to each of the plurality of corner portions 550 may have at least one step, while the inner surface of the edge of the second planarization layer 332 corresponding to each of the plurality of edge portions 540 may not have a step.

[0201] In each of the plurality of corner portions 550, the third separation distance d3 between the inner corner surface of the second planarization layer 332 and the inner surface of the embankment 340 can be equal to or greater than the first separation distance d1 between the inner edge surface of the second planarization layer 332 and the inner surface of the embankment 340 in each of the plurality of edge portions 540. Furthermore, Figure 8 The third separation distance d3 can be equal to or less than the second separation distance d2.

[0202] In each of the plurality of corner portions 550, the third tilt angle θ3 of the inner surface of the corner of the second planarization layer 334 may be equal to or greater than the first tilt angle θ1 of the inner surface of the edge of the second planarization layer 334 in each of the plurality of edge portions. The third tilt angle θ3 may be equal to or less than Figure 6 The second tilt angle θ2 in the middle.

[0203] The luminescent region may include a first luminescent region EA1 corresponding to the hole in the embankment and formed by light emitted from the intermediate layer EL, and a second luminescent region EA2 surrounding the first luminescent region EA1 and formed by light reflected from the inner surface of the second planarization layer 332. The second luminescent region EA2 may include a luminescent region formed by light reflected from a specific portion.

[0204] The display device according to embodiments of this disclosure may be a mobile display such as a TV, smartphone or tablet computer, a wearable display such as a watch, a vehicle display or a foldable display.

[0205] Figure 9 This is a flowchart illustrating the steps of a method for manufacturing a subpixel area SPA according to an embodiment of the present disclosure.

[0206] refer to Figure 9The manufacturing method of the display device may include the steps of forming a first planarization layer 331 on a substrate 111, forming a second planarization layer 332 by adjusting the exposure amount, forming a pixel electrode PE, and forming a dam 340.

[0207] In step S10, the first planarization layer 331 can be formed on the substrate 111.

[0208] In step S20, which forms the second planarization layer 332 by adjusting the exposure amount, the second planarization layer 332 can be formed on the first planarization layer 331, and openings PH and steps can be formed in the second planarization layer 332 by adjusting the exposure amount.

[0209] In step S30 of forming the pixel electrode PE, the pixel electrode PE may be formed to extend from the upper portion of the first planarization layer 331 to the side and upper portion of the second planarization layer 332. The pixel electrode PE may be formed to conform to the shape of the second planarization layer 332 and include steps.

[0210] In step S40, the dam 340 may be formed on the pixel electrode PE. The dam 340 may include a dam hole BH and be formed along the pixel electrode PE to have the same shape. The dam 340 may also have steps similar to the second planarization layer 332. In some examples, the dam may not include steps.

[0211] A method for manufacturing a display device may include: forming a first planarization layer 331 on a substrate 111; forming a second planarization layer 332 having an opening PH on the first planarization layer 331; forming a pixel electrode PE disposed on the first planarization layer 331 within the opening PH and extending along the side surface of the second planarization layer 332 outside the opening PH; and forming a dam 340 on the pixel electrode PE having an opening smaller than the opening PH. In the step of forming the second planarization layer 332, at least one step may be formed at a corner portion 550 on the inner surface of the second planarization layer 332 by adjusting the exposure amount.

[0212] The non-corner portion of the inner surface of the second planarization layer 332 may not have steps.

[0213] The corner portion 550 of the inner surface of the second planarization layer 332 may include a first inclined surface 810 extending from the bottom surface of the second planarization layer 332, a first connecting surface 820 extending from the first inclined surface 810 and having a gentler slope than the first inclined surface 810, and a second inclined surface 830 extending from the first connecting surface 820 and having a steeper slope than the first connecting surface 820.

[0214] In the step of forming the second planarization layer 332, at least one of the first height H1 from the starting point to the ending point of the first inclined surface 810 and the size of the first connecting surface 820 can be adjusted by controlling the amount of light.

[0215] When using positive PR for exposure, increasing the exposure can reduce the first height or increase the size of the first connecting surface.

[0216] Figure 10 and Figure 11 This is a schematic diagram of a method for manufacturing a sub-pixel region SPA according to an embodiment of the present disclosure.

[0217] Figure 10 An example of using positive PR in the exposure process of the second planarization layer is described. Negative PR can also be used in other examples. References Figure 10 The second planarization layer 332 can be exposed at 100% PH at the openings, and at 0% PH for areas of the second planarization layer 332 other than the corner portions 550, meaning they are not exposed. The corner portions 550 can be exposed in the range of 0-100%. In one embodiment, 50% exposure can be applied to the corner portions 550. However, this disclosure is not limited thereto. After the exposure process, an etching process can be performed to etch the second planarization layer 332 and form the openings.

[0218] refer to Figure 11 Some areas of the second planarization layer 332 can be exposed at 100% to form an opening PH. Corner portions 550 can be exposed at 50% to form a step in the second planarization layer 332. The edge 540 of the second emission region can be exposed at 0% and may not form a step.

[0219] refer to Figure 11 A dam 340 can be formed on a second planarization layer 332 having formed openings PH. Exposure and etching processes can be performed on some areas of the dam 340 to form dam holes BH. The area of ​​the dam holes BH can be smaller than the area of ​​the second planarization layer 332.

[0220] Figures 12 to 16 This is a plan view of a sub-pixel region SPA according to an embodiment of the present disclosure.

[0221] refer to Figure 12 The edge of the opening PH can be rectangular and can include specific segments corresponding to the vertices of the rectangle. For example, the opening PH can have four corner portions 550 corresponding to the four vertices, and the specific portions 700 corresponding to the four corner portions can have steps formed in the second planarization layer 332.

[0222] refer to Figure 12 The edge of the opening PH may include a curved section, and a specific portion 700 of a specific section corresponding to the inner surface of the second planarization layer 332 may include at least one step. Figure 12 It can include four curved specific sections 700.

[0223] refer to Figure 13 The edge of the opening PH can be a pentagon and can include specific segments corresponding to the vertices of the pentagon. For example, the opening PH can have five corner portions 550 corresponding to the five vertices, and specific portions corresponding to the five corner portions 550 can include steps in the second planarization layer 332.

[0224] refer to Figure 13 The edge of the opening PH may include a curved section, and a specific portion 700 of a specific section corresponding to the inner surface of the second planarization layer 332 may include at least one step. Figure 13 It can include five specific curved sections 700.

[0225] refer to Figure 14 The edge of the opening PH can be hexagonal and can include specific segments corresponding to the vertices of the hexagon. For example, the opening PH can have six corner portions 550 corresponding to the six vertices, and specific portions 700 corresponding to the six corner regions can include steps in the second planarization layer 332.

[0226] refer to Figure 14 The edge of the opening PH may include a curved section, and a specific portion 700 of a specific section corresponding to the inner surface of the second planarization layer 332 may include at least one step. Figure 14 It can include five specific curved sections 700.

[0227] refer to Figure 15 The edge of the opening PH can have a circular shape and can include a specific segment corresponding to the periphery of the circle. The specific segment corresponding to the periphery can have steps in the second planarization layer 332.

[0228] refer to Figure 16 The edge of the opening PH can be elliptical and can include specific segments corresponding to the periphery of the ellipse. The specific segments corresponding to the periphery can have steps in the second planarization layer 332.

[0229] Figure 17 The luminescent appearance of a subpixel region SPA according to an embodiment of the present disclosure is shown.

[0230] refer to Figure 17The corner portion of the left sub-pixel region SPA can remain non-emitting because no step is formed in the corner portion 550 of the second planarization layer 332. The corner portion of the right sub-pixel region SPA can emit light because a step is formed in the corner portion 550 of the second planarization layer 332. As a result, the sub-pixel region SPA with a step formed in the corner portion can have an increased area of ​​the second emission region EA2 and can improve light extraction efficiency.

[0231] The display device according to embodiments of the present disclosure can be described as follows.

[0232] A display device according to embodiments of the present disclosure may include: a substrate; a first planarization layer disposed on the substrate; a second planarization layer disposed on the first planarization layer and having an opening; a pixel electrode disposed within the opening, on the first planarization layer, and extending along an inner surface of the second planarization layer; and a dam disposed on the pixel electrode and having a hole smaller than the opening. The edge of the opening may include a curved section, and the opening may be defined by an inner surface of the second planarization layer. A specific portion corresponding to a specific section of the inner surface of the second planarization layer may have at least one step.

[0233] The edges of the opening can be polygonal and can include specific segments corresponding to the vertices of the polygon.

[0234] The edge of the opening can be circular or elliptical in shape, and can include specific sections corresponding to the perimeter of the circle or ellipse.

[0235] A portion of the inner surface of the embankment corresponding to at least one step of the second flattening layer may include at least one step.

[0236] A specific portion of the inner surface of the second planarization layer may include a first inclined surface extending from the bottom surface of the second planarization layer, a first connecting surface extending from the first inclined surface and having a gentler slope than the first inclined surface 810, and a second inclined surface 830 extending from the first connecting surface 820 and having a steeper slope than the first connecting surface 820.

[0237] In the vertical direction, the first height from the starting point to the ending point of the first inclined surface may be different from the second height from the starting point to the ending point of the second inclined surface.

[0238] A specific portion of the inner surface of the second planarization layer can be recessed inward at a specific height.

[0239] The edge of the opening may include multiple straight edge portions and multiple curved corner portions. Each of the multiple curved corner portions may correspond to a specific segment. The inner surface of the corner of the second planarization layer corresponding to the multiple curved corner portions may have at least one step. The inner surface of the edge of the second planarization layer corresponding to the multiple straight edge portions may not have a step.

[0240] In each of the multiple corner portions, the inclination angle of the inner surface of the corner portion of the second planarization layer can be greater than or equal to the inclination angle of the inner surface of the edge of the second planarization layer in each of the multiple straight edge portions.

[0241] In each of the multiple corner sections, the distance between the inner surface of the corner of the second flattening layer and the inner surface of the embankment can be greater than or equal to the distance between the inner surface of the edge of the second flattening layer and the inner surface of the embankment in each of the multiple straight edge sections.

[0242] The display device may include an intermediate layer disposed on a pixel electrode and extending above a dam, and a common electrode disposed on the intermediate layer. The intermediate layer and the common electrode may have steps in a region of the second planarization layer including at least one step.

[0243] The display device may include a first emitting region and a second emitting region. The first emitting region is formed by light emitted from the light-emitting layer corresponding to an aperture in the embankment. The second emitting region surrounds the first emitting region and is formed by light reflected from the inner surface of a second planarization layer. The second emitting region may include an emitting region formed by light reflected from a specific portion.

[0244] A method of manufacturing a display device may include: forming a first planarization layer on a substrate; forming a second planarization layer having an opening on the first planarization layer; forming a pixel electrode disposed on the first planarization layer within the opening and extending along a side surface of the second planarization layer outside the opening; and forming a dam having a hole smaller than the opening on the pixel electrode. In the step of forming the second planarization layer, at least one step can be formed at a corner portion of the inner surface of the second planarization layer by adjusting the exposure amount.

[0245] The non-corner portion of the inner surface of the second planarization layer may not include steps.

[0246] The corner portion of the inner surface of the second planarization layer may include a first inclined surface extending from the bottom surface of the second planarization layer, a first connecting surface extending from the first inclined surface and having a gentler slope than the first inclined surface, and a second inclined surface extending from the first connecting surface and having a steeper slope than the first connecting surface.

[0247] In the step of forming the second planarization layer, at least one of the first height from the start point to the end point of the first inclined surface and the size of the first connecting surface can be adjusted by controlling the exposure amount.

[0248] Further embodiments of this disclosure include the following:

[0249] In some embodiments, the display device includes a substrate and a first planarization layer 331, the first planarization layer 331 having a first surface 331FS facing the substrate 111 and a second surface 331SS opposite to the first surface 331FS. The display device also includes a second planarization layer 332 disposed on the second surface 331SS of the first planarization layer 331. The second planarization layer 332 has a first surface 332FS, a second surface 332SS opposite to the first surface 332FS, and an inner surface ISS extending between the first surface 332FS and the second surface 332SS. A pixel electrode PE is disposed on the second surface of the first planarization layer, along the inner surface of the second planarization layer, and located on the second surface of the second planarization layer. A dam 640 is disposed on the pixel electrode. In some embodiments, when viewed in a plan view, the lateral dimension LD1 of the dam is greater than or equal to the lateral dimension LD2 of the inner surface ISS of the second planarization layer 332, and overlaps with at least a portion of the second surface of the second planarization layer.

[0250] In some embodiments, the second planarization layer includes an opening defined by a plurality of edge portions and a plurality of corner portions. The edge portions extend along straight segments, while the corner portions interconnect with the edge portions and are positioned at curved or angled locations within the opening. The combination of the edge portions and corner portions defines the boundary shape of the opening in the plan view.

[0251] In some examples, the opening in the second planarization layer is polygonal in plan view. This polygonal shape includes multiple linear edge portions interconnected by corner portions located at angle transitions between adjacent edge portions. In some embodiments, the opening overlaps with the display area of ​​the substrate, such that light emitted from the emitting layer disposed within the opening is emitted outward through the display area.

[0252] In an alternative embodiment, the opening in the second planarization layer has a curved periphery in the plan view. The shape of the curved periphery can be circular, elliptical, or arc-shaped. The opening with the curved periphery can also overlap with the display area of ​​the substrate, such that the emission area conforms to a curved or circular geometry.

[0253] In some embodiments, a first tilt angle θ1 is defined at one of the edge portions between the second surface of the first planarization layer and the inner surface ISS of the second planarization layer, and a second tilt angle θ2 is defined at one of the corner portions between the second surface of the first planarization layer and the inner surface ISS of the second planarization layer. The second tilt angle θ2 at the corner portion may be greater than the first tilt angle θ1 at the edge portion, such that the sidewall of the corner portion is steeper than the sidewall of the edge portion.

[0254] In some embodiments, the second planarization layer includes a lower second planarization layer 332a and an upper second planarization layer 332b disposed on the lower second planarization layer 332a. The lower second planarization layer 332a includes a first inclined surface 810, and the upper second planarization layer 332b includes a second inclined surface 830. A first connecting surface 820 extends between the first inclined surface 810 of the lower second planarization layer 332a and the second inclined surface 830 of the upper second planarization layer 332b. In some embodiments, the inner surface ISS of the second planarization layer 332 may therefore sequentially include the first inclined surface 810, the second inclined surface 830, and the first connecting surface 820.

[0255] In some examples, the lower second planarization layer 332a has a first height H1 measured from the second surface of the first planarization layer to the first connecting surface, while the upper second planarization layer 332b has a second height H2 measured from the first connecting surface to the second surface of the second planarization layer. The first height H1 and the second height H2 may be different from each other to form a stepped sidewall structure.

[0256] In some embodiments, the first connecting surface 820, extending between the first inclined surface 810 and the second inclined surface 830, is substantially planar. The planar configuration of the first connecting surface provides a stable intermediate platform region between the two inclined surfaces.

[0257] In some examples, the inner surface ISS of the second planarization layer 332 includes a first inclined surface 810, a second inclined surface 830, and a first connecting surface 820, such that the inner surface ISS defines a stepped shape STP. The stepped inner surface ISS forms a continuous closed profile in a planar view and defines multiple emission regions when viewed in cross-section.

[0258] In some embodiments, the second planarization layer has openings defined by a plurality of edge portions and a plurality of corner portions. The stepped inner surface may be formed only at the plurality of corner portions, while the plurality of edge portions retain a stepless feature and include a single sloping surface.

[0259] In some examples, the continuous closed profile defined by the second planarization layer includes a primary emission region (e.g., a first emission region EA1) and a secondary emission region (e.g., an additional second emission region EA2) disposed adjacent to the primary emission region. The secondary emission region may be defined along a stepped sidewall region, while the primary emission region may be disposed within a main opening of the second planarization layer.

[0260] In some embodiments, the stepped profile of the second planarization layer defines at least two emission regions with different brightness levels. For example, a first emission region may be defined along a downwardly sloping surface adjacent to the first planarization layer, and a second emission region may be defined along an upwardly sloping surface adjacent to the second planarization layer. Differences in the slope, separation distance, or reflection geometry between the emission regions may result in brightness differences.

[0261] The above description has been presented to enable those skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The above description and drawings are provided as examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure.

Claims

1. A display device, comprising: substrate; A first planarization layer is disposed on the substrate; A second planarization layer is disposed on the first planarization layer and has an opening having an edge including a specific curved region; A pixel electrode is disposed within the opening, on the first planarization layer, and extends along the inner surface of the second planarization layer; as well as A dam portion, wherein the dam portion is disposed on the pixel electrode and has a hole smaller than the opening, The opening is defined by the inner surface of the second planarization layer, and The inner surface of the second planarization layer, corresponding to a specific portion of the specific curved region, includes at least one step.

2. The display device according to claim 1, in, The edge of the opening has a polygonal shape, and the specific curved area corresponds to the vertex of the polygon.

3. The display device according to claim 1, in, The edge of the opening has a circular or elliptical shape, and the specific curved area corresponds to the periphery of the circle or ellipse.

4. The display device according to claim 1, in, The portion of the inner surface of the embankment corresponding to at least one step of the second flattening layer includes at least one step.

5. The display device according to claim 1, in, The specific portion of the inner surface of the second planarization layer includes: A first inclined surface, the first inclined surface extending from the bottom surface of the second planarization layer; A first connecting surface, which extends from the first inclined surface and has a gentler slope than the first inclined surface; and A second inclined surface extends from the first connecting surface and has a steeper slope than the first connecting surface.

6. The display device according to claim 5, in, In the vertical direction, the first height from the starting point to the ending point of the first inclined surface is different from the second height from the starting point to the ending point of the second inclined surface.

7. The display device according to claim 1, in, The specific portion of the inner surface of the second planarization layer is recessed inward from a selected height.

8. The display device according to claim 1, in, The edge of the opening includes multiple straight edge portions and multiple curved corner portions. Each corner portion corresponds to the specific curved area. Wherein, the inner surface of the corner of the second planarization layer corresponding to each of the plurality of corner portions includes at least one step, and Wherein, the inner edge surface of the second planarization layer corresponding to each of the plurality of edge portions does not include steps.

9. The display device according to claim 1, in, In each of the plurality of corner portions, the inner surface of the corner of the second planarization layer has a first tilt angle; in each of the plurality of edge portions, the inner surface of the edge of the second planarization layer has a second tilt angle; and the first tilt angle is equal to or greater than the second tilt angle.

10. The display device according to claim 1, in, In each of the plurality of corner portions, there is a first separation distance between the inner surface of the corner of the second planarization layer and the inner surface of the embankment; in each of the plurality of edge portions, there is a second separation distance between the inner surface of the edge of the second planarization layer and the inner surface of the embankment; and the first separation distance is equal to or greater than the second separation distance.

11. The display device according to claim 1, further comprising: An intermediate layer is disposed on the pixel electrode and extends over the embankment; as well as A common electrode, wherein the common electrode is disposed on the intermediate layer, The intermediate layer and the common electrode both have steps in the region of the second planarization layer, which includes the at least one step.

12. The display device according to claim 11, further comprising: A first emission region, the first emission region corresponding to the hole in the embankment and formed by light emitted from the intermediate layer; as well as A second emission region surrounds the first emission region and is formed by light reflected from the inner surface of the second planarization layer. The second emission region includes an emission region formed by light reflected from the specific portion.

13. A display device, comprising: substrate; A first planarization layer has a first surface and a second surface opposite to the first surface, the first surface of the first planarization layer facing the substrate; A second planarization layer is disposed on the second surface of the first planarization layer, the second planarization layer having a first surface, a second surface, and an inner surface extending between the first surface and the second surface; A pixel electrode is disposed on the second surface of the first planarization layer, and is also disposed on the inner surface and the second surface of the second planarization layer; as well as A dam portion, wherein the dam portion is disposed on the pixel electrode, In the plan view, the lateral dimension of the embankment is greater than or equal to the lateral dimension of the inner surface of the second planarization layer, and the embankment overlaps with at least a portion of the second surface of the second planarization layer.

14. The display device according to claim 13, wherein, The second planarization layer has openings defined by multiple edge portions and multiple corner portions.

15. The display device according to claim 14, wherein, The openings in the second planarization layer have a polygonal shape in the plan view, and The opening in the second planarization layer overlaps with the display area of ​​the substrate.

16. The display device according to claim 14, wherein, The second planarization layer has an opening, and the opening of the second planarization layer has a curved periphery in a plan view. The opening in the second planarization layer overlaps with the display area of ​​the substrate.

17. The display device according to claim 14, wherein, At one of the plurality of edge portions, a first tilt angle is defined between the second surface of the first planarization layer and the inner surface of the second planarization layer; Wherein, at one of the multiple corner portions, a second tilt angle is defined between the second surface of the first planarization layer and the inner surface of the second planarization layer; Wherein, the second tilt angle at the corner portion is greater than the first tilt angle at the edge portion.

18. The display device according to claim 13, wherein, The second planarization layer includes a lower second planarization layer and an upper second planarization layer disposed on the lower second planarization layer. The lower second planarization layer includes a first inclined surface, and the upper second planarization layer includes a second inclined surface; a first connecting surface extends between the first inclined surface and the second inclined surface. The inner surface of the second planarization layer includes the first inclined surface of the lower second planarization layer, the second inclined surface of the upper second planarization layer, and the first connecting surface.

19. The display device according to claim 18, wherein, The lower second planarization layer has a first height measured from the second surface of the first planarization layer to the first connecting surface. The upper second planarization layer has a second height measured from the first connecting surface to the second surface of the second planarization layer, and The first height and the second height are different from each other.

20. The display device according to claim 18, wherein, The first connecting surface, which extends between the first inclined surface and the second inclined surface, is substantially planar.

21. The display device according to claim 18, wherein, The inner surface of the second planarization layer, which has a stepped shape formed by the first inclined surface, the second inclined surface, and the first connecting surface, forms a continuous closed profile in a plan view and defines multiple emission regions in a cross-sectional view.

22. The display device according to claim 21, wherein, The second planarization layer has openings defined by multiple edge portions and multiple corner portions, and The stepped inner surface is formed only at the multiple corner portions, and not at the multiple edge portions.

23. The display device according to claim 21, wherein, The continuous closed contour of the second planarization layer defines the main emission region surrounded by the secondary emission region.

24. The display device according to claim 21, wherein, The stepped profile of the second planarization layer defines at least two emission regions with different brightness levels.

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