Display panel including an interconnection structure and electronic device including the display panel

Abstract

A display panel including an interconnection structure and an electronic device including the display panel are disclosed. The display panel includes a substrate, a light emitting diode arranged above the substrate, and a circuit layer between the substrate and the light emitting diode. The circuit layer includes an interconnection structure including a first conductive material layer, a first insulating layer above the first conductive material layer, a first conductor including a side portion on an inner wall of the first insulating layer defining a first contact hole and a lower portion integrally formed with the side portion and directly contacting a portion of an upper surface of the first conductive material layer, an inorganic filler including an inorganic insulating material in a recess surrounded by the side portion, a second insulating layer above the first insulating layer, and a second conductor directly contacting an upper surface of the side portion of the first conductor through a second contact hole in the second insulating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0181955, filed on December 9, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] One or more embodiments relate to a method of manufacturing an interconnect structure, a display panel including the interconnect structure, and an electronic device including the display panel. Background Technology

[0003] Recently, display panels have been used in various electronic devices. With the widespread use of display panels, the demand for high-resolution display panels and display panels of various shapes has increased, and research on the space utilization of display panels has been ongoing to achieve high-resolution display panels. Summary of the Invention

[0004] Sufficient space may be desired for designing a high-resolution display panel, and for this purpose, it may be desirable to reduce the area occupied by the contact structure used for electrical connections between the two components. Accordingly, one or more embodiments include a method for forming a connection structure suitable for high resolution with minimal processes, a display panel including the connection structure, and an electronic device including the display panel.

[0005] According to one or more embodiments, a display panel includes a substrate, light-emitting diodes disposed above the substrate, and a circuit layer disposed between the substrate and the light-emitting diodes. The circuit layer includes an interconnect structure comprising: a first conductive material layer disposed above the substrate; a first insulating layer disposed above the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap a portion of the upper surface of the first conductive material layer; a first conductor including a side portion and a lower portion, wherein the side portion is on the inner wall of the first insulating layer defining the first contact hole, and the lower portion is integrally formed with the side portion as a single, indivisible part and directly contacts a portion of the upper surface of the first conductive material layer; an inorganic filler disposed in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler includes an inorganic insulating material; a second insulating layer disposed above the first insulating layer, wherein a second contact hole is defined in the second insulating layer to overlap the first contact hole; and a second conductor directly contacting the upper surface of the side portion of the first conductor through the second contact hole of the second insulating layer.

[0006] In one embodiment, the second insulating layer may include an inorganic insulating material, and the inorganic insulating material of the second insulating layer may be the same as the inorganic insulating material of the inorganic filler.

[0007] In one embodiment, the side of the first conductor may be in direct contact with the inner wall of the first insulating layer, and the first point where the side of the first conductor and the inner wall of the first insulating layer contact each other may be spaced apart by a first distance along a second point where the inner wall and the upper surface of the first insulating layer intersect each other.

[0008] In one embodiment, the upper surface of the side portion of the first conductor may be located on an imaginary plane parallel to the upper surface of the substrate.

[0009] In one embodiment, the upper surface of the side portion of the first conductor may be inclined relative to an imaginary plane parallel to the upper surface of the substrate.

[0010] In one embodiment, the second conductor may be in direct contact with the upper surface of the inorganic filler.

[0011] In one embodiment, the display panel may further include a third insulating layer above the second insulating layer, wherein the third contact hole may be defined in the third insulating layer to overlap with the second contact hole.

[0012] In one embodiment, the first conductor may include: a first first conductor including a first side portion and a first lower portion, wherein the first side portion directly contacts the inner wall of the first insulating layer defining the first contact hole, and the first lower portion is integrally formed with the first side portion as a single, indivisible part and directly contacts a portion of the upper surface of the first conductive material layer; and a second first conductor including a second side portion and a second lower portion, wherein the second side portion directly contacts the first side portion of the first first conductor, and the second lower portion directly contacts the first lower portion, wherein an inorganic filler may be surrounded by the second side portion of the second first conductor.

[0013] In one embodiment, the circuit layer may further include: a transistor disposed above a substrate, wherein the transistor may include a semiconductor layer and a gate electrode; and a capacitor including a first electrode and a second electrode overlapping each other, wherein a first conductive material layer may define one of the semiconductor layer, the gate electrode, the first electrode, and the second electrode.

[0014] In one embodiment, the contact area between the second conductor and the first conductor may have a closed-loop shape in a plan view.

[0015] In one embodiment, the width of the upper portion of the first contact hole, measured by the point where the upper surface and inner wall of the first insulating layer intersect each other, can be greater than the width of the upper surface of the inorganic filler, and can be less than the width of the lower portion of the second contact hole, measured by the point where the inner wall of the second insulating layer and the upper surface of the first insulating layer intersect each other.

[0016] According to one or more embodiments, a method of manufacturing a display panel is provided. The display panel includes a substrate, light-emitting diodes disposed above the substrate, and a circuit layer disposed between the substrate and the light-emitting diodes and including interconnect structures. In such embodiments, the method of manufacturing the display panel includes a method of manufacturing interconnect structures. In such embodiments, the method of manufacturing interconnect structures includes: forming a first conductive material layer above the substrate; forming a first insulating layer on the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap with a portion of an upper surface of the first conductive material layer; forming a first conductor in the first contact hole, wherein the first conductor includes a side portion and a lower portion, wherein the side portion is on an inner wall of the first insulating layer defining the first contact hole, and the lower portion is integrally formed with the side portion as a single, indivisible portion and directly contacts a portion of the upper surface of the first conductive material layer; forming an inorganic filler in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler includes an inorganic insulating material; and forming a second conductor directly contacting the upper surface of the side portion of the first conductor.

[0017] In one embodiment, forming the inorganic filler may include forming an insulating material layer above the upper surface of the first insulating layer and the upper surface of the side portion of the first conductor to at least partially fill the recess, and removing a portion of the insulating material layer that overlaps with the first contact hole while leaving a portion of the insulating material layer in the recess corresponding to the inorganic filler, wherein the insulating material layer is removed so that a second insulating layer can be formed above the upper surface of the first insulating layer, and the second contact hole that overlaps with the first contact hole can be defined in the second insulating layer.

[0018] In one embodiment, the second conductor can directly contact the upper surface of the side portion of the first conductor through the second contact hole of the second insulating layer.

[0019] In one embodiment, the contact area between the second conductor and the first conductor may have a closed-loop shape in a plan view.

[0020] In one embodiment, forming the first conductor may include the following process: forming a conductive layer over a portion of the upper surface of a first insulating layer, the inner wall of the first insulating layer, and the upper surface of a first conductive material layer; forming a planarization layer comprising an organic material to fill a recess surrounded by a portion of the conductive layer formed on the inner wall of the first insulating layer; etching back the planarization layer; removing a portion of the conductive layer from the upper surface of the first insulating layer, while leaving a portion of the conductive layer inside a first contact hole corresponding to the first conductor; and removing any residue of the planarization layer from the recess.

[0021] In one embodiment, the etch-back planarization layer and the removal of a portion of the conductive layer can be performed in the same etching process.

[0022] In one embodiment, the side of the first conductor may be in direct contact with the inner wall of the first insulating layer, and the first point where the side of the first conductor and the inner wall of the first insulating layer contact each other may be spaced apart by a first distance along a second point where the inner wall and the upper surface of the first insulating layer intersect each other.

[0023] In one embodiment, the upper surface of the side portion of the first conductor may be located on an imaginary plane parallel to the upper surface of the substrate.

[0024] In one embodiment, the upper surface of the side portion of the first conductor may be inclined relative to an imaginary plane parallel to the upper surface of the substrate.

[0025] According to one or more embodiments, an electronic device includes a display panel according to the above embodiments and a lower cover supporting the display panel.

[0026] According to one or more embodiments, an electronic device includes a display panel having a resolution of 1500 pixels per inch (ppi) or higher, wherein the display panel includes a substrate, light-emitting diodes disposed above the substrate, and a circuit layer disposed between the substrate and the light-emitting diodes. In such an embodiment, the circuit layer includes an interconnect structure comprising: a first conductive material layer disposed above the substrate; a first insulating layer disposed above the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap a portion of the upper surface of the first conductive material layer; a first conductor electrically connected to the first conductive material layer, disposed in the first contact hole, and having a closed-loop shape in a plan view; a second insulating layer disposed above the first insulating layer, wherein a second contact hole is defined in the second insulating layer; and a second conductor directly contacting at least a portion of the first conductor through the second contact hole in the second insulating layer, wherein the area of ​​the contact area between the second conductor and the first conductor is approximately 0.039 square micrometers (μm). 2 ~ Approximately 3.11 μm 2 Within the range.

[0027] In one embodiment, the first conductor may include a side portion and a lower portion, wherein the side portion is on the inner wall of the first insulating layer defining the first contact hole, and the lower portion is integrally formed with the side portion as a single, indivisible part and directly contacts a portion of the upper surface of the first conductive material layer, and the interconnect structure may further include an inorganic filler disposed in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler includes an inorganic insulating material.

[0028] In one embodiment, the side of the first conductor may be in direct contact with the inner wall of the first insulating layer, and the first point where the side of the first conductor and the inner wall of the first insulating layer contact each other may be spaced apart by a first distance along a second point where the inner wall and the upper surface of the first insulating layer intersect each other.

[0029] In one embodiment, the upper surface of the side portion of the first conductor may be located on an imaginary plane parallel to the upper surface of the substrate.

[0030] In one embodiment, the upper surface of the side portion of the first conductor may be inclined relative to an imaginary plane parallel to the upper surface of the substrate.

[0031] In one embodiment, the second insulating layer may include an inorganic insulating material, and the inorganic insulating material of the second insulating layer may be the same as the inorganic insulating material of the inorganic filler.

[0032] In one embodiment, the circuit layer may further include: a transistor disposed above a substrate, wherein the transistor includes a semiconductor layer and a gate electrode; and a capacitor including a first electrode and a second electrode overlapping each other, wherein a first conductive material layer may define one of the semiconductor layer, the gate electrode, the first electrode, and the second electrode. Attached Figure Description

[0033] The above and other features of specific embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 This is a perspective view of an electronic device according to an embodiment;

[0035] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment;

[0036] Figure 3 This is a block diagram illustrating an electronic device according to an embodiment;

[0037] Figure 4 This is a schematic diagram illustrating an equivalent circuit diagram of a light-emitting diode (LED) of a display panel according to an embodiment and the circuit connected to the LED;

[0038] Figure 5 This is a cross-sectional view of a portion of a display panel according to one embodiment;

[0039] Figures 6A to 6I This is a cross-sectional view illustrating a process for forming an interconnect structure included in a circuit layer of a display panel according to an embodiment;

[0040] Figure 7A When viewed in a direction perpendicular to the upper surface of the substrate Figure 6EA plan view of the first conductor;

[0041] Figure 7B yes Figure 6E Enlarged cross-sectional view of region VIIb;

[0042] Figure 8 It is based on the reference Figure 6F Cross-sectional view of an embodiment of the described process;

[0043] Figure 9A The illustration is based on a reference. Figure 6I A plan view of the contact structure between the second conductor and the first conductor in the described process;

[0044] Figure 9B This is a cross-sectional view of an interconnect structure based on a process according to one embodiment;

[0045] Figure 9C This is a plan view illustrating the contact structure between the second conductor and the first conductor according to a process according to an embodiment;

[0046] Figures 10A to 10G This is a cross-sectional view illustrating a process for forming an interconnect structure included in a circuit layer of a display panel according to an embodiment;

[0047] Figure 11A and Figure 11B This is a cross-sectional view illustrating a process of forming a first conductor in a process of forming an interconnect structure included in a circuit layer of a display panel, according to an embodiment.

[0048] Figure 12 The diagram illustrates a cross-sectional view of an interconnect structure according to one embodiment; and

[0049] Figure 13 This is a perspective view of an electronic device according to an embodiment. Detailed Implementation

[0050] The invention will be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0051] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings herein, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. Thus, references to an element “a,” followed by references to an element “the,” in the claims include one element and multiple elements. For example, unless the context clearly indicates otherwise, “a single element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expressions “at least one of a, b, and c” or “selected from at least one of a, b, and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0053] It will be further understood that, when used in this specification, the terms “comprising” or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0054] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediary element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0055] For ease of description, the dimensions of the components in the accompanying drawings may be enlarged. In other words, this disclosure is not limited thereto because the dimensions and shapes of the components in the accompanying drawings are arbitrarily shown for ease of description.

[0056] When an embodiment can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0057] It will be understood that when a layer, region, area, component, or element is referred to as being "connected to" another layer, region, area, component, or element, it may be "directly connected" to the other layer, region, area, component, or element, or it may be "indirectly connected" to the other layer, region, area, component, or element, with one or more intermediary layers, regions, areas, components, or elements therein. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, it may be "directly electrically connected" to the other layer, region, or component, or it may be "indirectly electrically connected" to the other layer, region, or component, with one or more intermediary layers, regions, or components therein.

[0058] Furthermore, this document may use relative terms such as “below” or “bottom” and “above” or “top” to describe the relationship between one element and another illustrated in the figures. It will be understood that, in addition to the orientation illustrated in the figures, relative terms are intended to include different orientations of the device. For example, if a device in a figure is flipped, an element described as being “below” to other elements will then be oriented “above” to other elements. Thus, depending on the specific orientation of the figure, the term “below” can encompass both “below” and “above” orientations. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” other elements will then be oriented “above” to other elements. Thus, the terms “below” or “under” can include both “above” and “below” orientations.

[0059] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include stated values ​​and mean within an acceptable range of deviation from that particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] Embodiments are described herein with reference to cross-sectional views, which are schematic representations of preferred embodiments. Therefore, variations in the shapes illustrated are expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to specific shapes of the regions illustrated herein, but rather to include, for example, deviations in shape due to manufacturing processes. For instance, regions illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the regions and are not intended to limit the scope of the claims.

[0062] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and similar reference numerals will indicate similar elements in the description, and redundant descriptions will be omitted for the sake of brevity.

[0063] Figure 1 This is a perspective view of an electronic device 1 according to an embodiment. Figure 2 The diagram shows an exploded perspective view of an electronic device 1 according to an embodiment, and Figure 3 This is a block diagram illustrating an electronic device 1 according to an embodiment.

[0064] refer to Figure 1 and Figure 2 According to one embodiment, the electronic device 1 can be a device for displaying moving images or still images. Figure 1 The illustrated electronic device 1 is an embodiment of a smartphone. In such an embodiment, electronic device 1 may include a cover window 70, a display panel 10, a data driver 20, a display circuit board 30, a component 40, a bracket 60, a main circuit board 50, a battery 80, and a lower cover 90.

[0065] In the plan view described herein, "left," "right," "up," and "down" can refer to the direction when viewing the display panel 10 in the vertical (or thickness) direction. For example, "left" can refer to the -x direction, "right" can refer to the +x direction, "up" can refer to the +y direction, and "down" can refer to the -y direction.

[0066] In a plan view or when viewed in the z-direction, the electronic device 1 may have a rectangular shape. In one embodiment, for example, as... Figure 1 As shown, electronic device 1 can have a rectangular planar shape, which has a shorter side in the x-direction and a longer side in the y-direction. The corners where the shorter side in the x-direction and the longer side in the y-direction intersect each other can be rounded with a certain curvature or formed at right angles. The planar shape of electronic device 1 is not limited to a rectangular shape, and can be any polygonal shape, elliptical shape, or atypical shape.

[0067] A cover window 70 can be arranged above the display panel 10 to cover the upper surface of the display panel 10. Accordingly, the cover window 70 can protect the upper surface of the display panel 10.

[0068] The cover window 70 may include a transparent cover unit DA70 corresponding to the display area DA of the display panel 10 and a light-shielding cover unit NDA70 surrounding the transparent cover unit DA70. The light-shielding cover unit NDA70 may include an opaque material (e.g., a colored opaque material) that blocks light. In a plan view or when viewed in the z-direction, the light-shielding cover unit NDA70 may overlap with the peripheral area PA of the display panel 10.

[0069] Display panel 10 may be disposed below cover window 70. Display panel 10 may include display area DA and peripheral area PA surrounding display area DA. Display area DA may be an area for displaying images. In one embodiment, display area DA may include an area (hereinafter referred to as component area) that transmits light emitted from component 40 disposed below display panel 10. Component 40 may include a sensor or camera that uses visible light, infrared light, or sound.

[0070] Display panel 10 may be a light-emitting display panel including light-emitting diodes (LEDs). The LEDs may include organic light-emitting diodes (OLEDs) containing an organic emitting layer. The LEDs may also be inorganic light-emitting diodes comprising inorganic materials. Inorganic light-emitting diodes may include PN junction diodes comprising inorganic semiconductor materials. When a forward voltage is applied to the PN junction diode, holes and electrons can be injected into it, and the energy generated by the recombination of holes and electrons can be converted into light energy to emit light of a specific color. The LEDs may also include quantum dots.

[0071] The display panel 10 can be a rigid display panel or a flexible display panel that is easy to bend. In one embodiment, the display panel 10 can be assembled between the cover window 70 and the lower cover 90 while a portion of the peripheral area PA is bent.

[0072] In one embodiment, the data driver 20 may be arranged on the display panel 10 in the form of an integrated circuit (IC). In another embodiment, the data driver 20 may be arranged on the display circuit board 30.

[0073] The display circuit board 30 can be attached to one side of the display panel 10. The display circuit board 30 can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (rigid PCB) that is rigid and therefore not easy to bend, or a composite PCB that includes a rigid PCB and an FPCB.

[0074] In one embodiment, the touch sensor driver may be disposed on the display circuit board 30. The touch sensor driver may be formed as an integrated circuit. The touch sensor driver may be attached to the display circuit board 30. The touch sensor driver may be electrically connected to the touch electrodes of the touch screen layer of the display panel 10 through the display circuit board 30.

[0075] The touchscreen layer of display panel 10 can detect user touch input using at least one of various touch methods, such as resistive and capacitive methods. For example, when the touchscreen layer of display panel 10 detects user touch input using a capacitive method, the touch sensor driver can apply a drive signal to the drive electrode in the touch electrodes and detect the voltage in the mutual electrostatic capacitance (hereinafter referred to as "mutual capacitance") charged between the drive electrode and the sensing electrode in the touch electrodes, thereby determining whether a user touch has occurred. User touch can include contact touch and proximity touch. Contact touch may mean that the user's finger or an object such as a pen directly contacts the cover window 70 arranged above the touchscreen layer. Proximity touch may mean that the user's finger or an object such as a pen is close to or separated from the cover window 70, for example, hovering. The touch sensor driver can transmit sensor data to the main processor 5100 according to the detected voltage, and the main processor 5100 can calculate the touch coordinates of the touch input by analyzing the sensor data.

[0076] A controller for supplying driving voltages for driving the data driver 20, the gate driver, and the pixels of the display panel 10 can be arranged on the display circuit board 30.

[0077] A bracket 60 for supporting the display panel 10 may be disposed below the display panel 10. The bracket 60 may include plastic, metal, or both plastic and metal. The bracket 60 may be provided with a first camera hole CMH1 into which a camera device 5310 is inserted, a battery hole BH into which a battery 80 is disposed, and a cable hole CAH through which a cable connected to the display circuit board 30 passes. The bracket 60 may be provided with a component hole CPH that overlaps with the display panel 10. The component hole CPH may overlap with a component 40 of the main circuit board 50 in the third direction (z-direction). In one embodiment, the display area DA of the display panel 10 may overlap with a component 40 of the main circuit board 50 in the third direction (z-direction). In another embodiment, the bracket 60 may not be provided with a component hole CPH.

[0078] In one embodiment, component 40 may include first to fourth components 41, 42, 43, and 44 overlapping the display panel 10. The first to fourth components 41, 42, 43, and 44 may be provided as a proximity sensor, an illumination sensor, an iris sensor, a face recognition sensor, or a camera (or image sensor). An infrared proximity sensor can detect objects positioned near the upper surface of the electronic device 1, and an illumination sensor can sense the brightness of light incident on the upper surface of the electronic device 1. Furthermore, an iris sensor can capture images of the iris of a person positioned above the upper surface of the electronic device 1, and a camera can capture images of objects positioned above the upper surface of the electronic device 1. Component 40 is not limited to proximity sensors, illumination sensors, iris sensors, face recognition sensors, and cameras, and may include other sensors described below.

[0079] The main circuit board 50 and the battery 80 can be arranged below the bracket 60. The main circuit board 50 can be a rigid PCB or an FPCB.

[0080] The main circuit board 50 may include a main processor 5100, a camera device 5310, a main connector 55, and a component 40. The main processor 5100 may be formed as an integrated circuit. The camera device 5310 may be disposed on both the upper and lower surfaces of the main circuit board 50, and each of the main processor 5100 and the main connector 55 may be disposed on one of the upper and lower surfaces of the main circuit board 50.

[0081] The main processor 5100 can control all functions of the electronic device 1. In one embodiment, for example, the main processor 5100 can output digital video data to the data driver 20 via the display circuit board 30, causing the display panel 10 to display an image. The main processor 5100 can receive sensing data from the touch sensor driver. The main processor 5100 can determine whether a user touch is present based on the sensing data and perform an operation corresponding to a direct touch or proximity touch by the user. The main processor 5100 can be an application processor, a central processing unit, or a system-on-a-chip (SoC) including integrated circuits.

[0082] Camera device 5310 can process image frames, such as still images or moving images, acquired by an image sensor in camera mode, and output the processed image frames to main processor 5100. Camera device 5310 may include at least one selected from camera sensors (e.g., charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS) sensors), light sensors (or image sensors), and laser sensors. Camera device 5310 may be connected to an image sensor in component 40 overlapping with display area DA to process images input from the image sensor.

[0083] The cable passing through the cable hole CAH of the bracket 60 can be connected to the main connector 55, and thus the main circuit board 50 can be electrically connected to the display circuit board 30.

[0084] like Figure 3 As shown, in addition to the main processor 5100, camera device 5310 and main connector 55, the main circuit board 50 may further include a wireless communication device 5200, an input unit 5300, a sensor unit 5400, an output unit 5500, an interface unit 5600, a memory 5700 and / or a power supply unit 5800.

[0085] The wireless communication device 5200 may include at least one selected from the broadcast receiving module 5210, the mobile communication module 5220, the wireless Internet module 5230, the short-range communication module 5240, and the location information module 5250.

[0086] The broadcast receiving module 5210 can receive broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include satellite channels and terrestrial channels.

[0087] Mobile communication module 5220 can transmit / receive radio signals to / from at least one of a base station, an external terminal, and a server in a mobile communication network established according to mobile communication technical standards or communication methods (e.g., Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA 2000), Enhanced Voice Data Optimized or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High-Speed ​​Downlink Packet Access (HSDPA), High-Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), and LTE-A Advanced (LTE-A)). The radio signals may include various forms of data transmitted / received based on voice call signals, video call signals, or text / multimedia messages.

[0088] Wireless Internet module 5230 can refer to a module used for wireless Internet access. Wireless Internet module 5230 can be configured to transmit / receive wireless signals in a communication network according to wireless Internet technologies. Wireless Internet technologies may include, for example, Wireless LAN (WLAN), Wireless Fidelity (WiFi), WiFi Direct, and / or Digital Living Network Alliance (DLNA).

[0089] The short-range communication module 5240 can be used for short-range communication and can support short-range communication by using at least one of the following technologies: Bluetooth®, Radio Frequency Identification (RFID), Infrared Data Association (IrDA), Ultra Wideband (UWB), ZigBee, Near Field Communication (NFC), Wireless Fidelity (WiFi), WiFi Direct, and Wireless Universal Serial Bus (Wireless USB). The short-range communication module 5240 can support wireless communication between electronic device 1 and a wireless communication system, between electronic device 1 and another electronic device, or between electronic device 1 and a network in which another electronic device (or an external server) is located, via a short-range wireless communication network (wireless local area network). The short-range wireless communication network can be a short-range wireless personal area network (wireless personal area network). The other electronic device can be a wearable device capable of exchanging data (or interoperating) with electronic device 1.

[0090] The location information module 5250 may be a module for obtaining the location (or current location) of the electronic device 1, and may include a global positioning system (GPS) module or a WiFi module.

[0091] The input unit 5300 may include an image input unit such as a camera device 5310 for inputting image signals, an audio input unit such as a microphone 5320 for inputting audio signals, and an input device 5330 for receiving information from a user.

[0092] The camera device 5310 can process image frames, such as still images or moving images, acquired by the image sensor in video call mode or shooting mode. The processed image frames can be displayed on the display panel 10 or stored in the memory 5700.

[0093] Microphone 5320 can process external audio signals into electronic voice data. Depending on the function (or application) performed in electronic device 1, the processed voice data can be used in various ways.

[0094] The main processor 5100 can control the operation of the electronic device 1 to correspond to information input via the input device 5330. The input device 5330 may include mechanical input units or touch input units such as buttons, dome switches, microwheels, or microswitches located on the rear or side surface of the electronic device 1. The touch input unit may include (or be defined by) the touch screen layer of the display panel 10.

[0095] Sensor unit 5400 may include one or more sensors that can sense at least one of information selected from electronic device 1, information about the surrounding environment of electronic device 1, and user information, and can generate a corresponding sensing signal. Main processor 5100 may control the driving or operation of electronic device 1 based on the sensing signal, or perform data processing, functions, or operations related to applications installed on electronic device 1. Sensor unit 5400 may include at least one selected from proximity sensors, lighting sensors, accelerometers, magnetic sensors, gravity sensors (G-sensors), gyroscopes, motion sensors, RGB sensors, infrared sensors (IR sensors), finger scanning sensors, ultrasonic sensors, optical sensors, battery gauges, environmental sensors (e.g., barometers, hygrometers, thermometers, radiation detection sensors, thermal detection sensors, or gas detection sensors), and chemical sensors (e.g., electronic noses, health sensors, or biometric sensors).

[0096] The output unit 5500 can be used to generate visual, auditory or tactile outputs, and may include at least one selected from the display panel 10, audio output unit 5510, tactile module 5520 and light output unit 5530.

[0097] Display panel 10 can display (output) information processed in electronic device 1. In one embodiment, for example, display panel 10 can display execution screen information of an application driven in electronic device 1, or display user interface (UI) or graphical user interface (GUI) information corresponding to the execution screen information. Display panel 10 may include a display layer for displaying images and a touch screen layer for detecting user touch input. Accordingly, display panel 10 can function as one of the input devices 5330 providing an input interface between electronic device 1 and user, and can simultaneously function as one of the output units 5500 providing an output interface between electronic device 1 and user.

[0098] In call signal receiving mode, call mode, recording mode, voice recognition mode, or broadcast receiving mode, the audio output unit 5510 can output audio data received from the wireless communication device 5200 or stored in the memory 5700. The audio output unit 5510 can also output audio signals related to the functions performed in the electronic device 1 (e.g., call signal receiving tone or message receiving tone). The audio output unit 5510 may include a receiver and a speaker. At least one selected from the receiver and speaker may be an audio generating device attached to the lower part of the display panel 10 and causing the display panel 10 to vibrate to output audio. The audio generating device may be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electrical signal, or it may be an exciter that vibrates the display panel 10 by generating magnetic force using a voice coil.

[0099] The haptic module 5520 can produce various tactile effects that users can perceive. The haptic module 5520 can provide vibrations as a tactile effect to the user. The haptic module 5520 can not only transmit tactile effects through direct contact, but can also be implemented so that users can experience tactile effects through the muscles of their fingers or arms.

[0100] The light output unit 5530 can output a signal to notify of an event by using light from a light source. Examples of events occurring in the electronic device 1 may include message reception, call signal reception, missed calls, alarms, calendar notifications, email reception, and information reception via an application. The signal output from the light output unit 5530 can be achieved by the electronic device 1 emitting light of a single color or multiple colors from its front or rear surface. When the electronic device 1 detects user confirmation of the event, it can terminate the signal output.

[0101] Interface unit 5600 can serve as a path for connecting various types of external devices to electronic device 1. Interface unit 5600 may include at least one of the following: a wired / wireless headphone port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device including an identification module, an audio input / output (I / O) port, a video I / O port, and a headphone port. When an external device is connected to interface unit 5600, electronic device 1 can perform appropriate controls associated with the connected external device.

[0102] Memory 5700 can store data used to support various functions of electronic device 1. Memory 5700 can store multiple applications (applications) driven in electronic device 1, data and instructions for the operation of electronic device 1. At least some of the multiple applications can be downloaded from an external server via wireless communication. Memory 5700 can store applications used for the operation of main processor 5100, and can temporarily store input / output data such as phone books, messages, still images and / or moving images. In addition, memory 5700 can store tactile data of various vibration modes provided to tactile module 5520 and audio data of various audio frequencies provided to audio output unit 5510. Memory 5700 can include at least one type of storage medium selected from flash memory, hard disk, solid-state drive (SSD), silicon disk drive (SDD), multimedia card micro, card memory (e.g., SD and XD memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, magnetic disk, and optical disk.

[0103] Under the control of the main processor 5100, the power supply unit 5800 can receive external and / or internal power and supply power to each of the components included in the electronic device 1. The power supply unit 5800 may include a battery 80. Furthermore, the power supply unit 5800 may include a connection port, which may be an example of an interface unit 5600 to which an external charger for charging the battery is electrically connected. Alternatively, the power supply unit 5800 may be configured to wirelessly charge the battery 80 without using the connection port. The battery 80 may be arranged so as not to overlap with the main circuit board 50 in the third direction (z-direction). The battery 80 may overlap with the battery hole BH of the bracket 60.

[0104] The lower cover 90 can be a housing that supports the display panel 10 and onto which the display panel 10 is mounted, and can form the appearance of the electronic device 1. The lower cover 90 can be disposed below the main circuit board 50 and the battery 80. The lower cover 90 can be fastened and fixed to the bracket 60. The lower cover 90 can include plastic, metal, or both plastic and metal.

[0105] The second camera aperture CMH2 may be defined or formed in the lower cover 90 to expose the lower surface of the camera device 5310. The position of the camera device 5310 and the positions of the corresponding first camera aperture CMH1 and second camera aperture CMH2 are not limited to... Figure 2 The position shown in the diagram can be modified in various ways.

[0106] Figure 4 This is a schematic illustration of an equivalent circuit diagram of a light-emitting diode (LED) of a display panel and a circuit connected to the LED according to an embodiment.

[0107] The above reference Figure 2 The described display panel 10 can provide an image via pixels PX arranged in two dimensions in the display area DA. Each pixel PX (see...) Figure 2 This can include light-emitting diodes (LEDs) (see...) Figure 4 ).exist Figure 2 In an embodiment where the display panel 10 includes pixels PX arranged two-dimensionally in a display area DA, the display area DA includes light-emitting diodes (LEDs) arranged two-dimensionally. Figure 4 Light-emitting diodes (LEDs) can be electrically connected to pixel circuitry (PC). Like LEDs, pixel circuitry (PC) can be arranged in the display area DA (see [link to display area]). Figure 2 )middle.

[0108] In one embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. The first transistor T1 may be a driving transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be switching transistors.

[0109] The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (PMOS) or n-channel MOSFETs (NMOS). In one embodiment, Figure 4 The illustration shows that each of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 is a PMOS. The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be transistors that include a low-temperature polycrystalline silicon (LTPS) semiconductor layer.

[0110] although Figure 4 The illustration shows an embodiment where each of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 is a PMOS, but this disclosure is not limited thereto. In another embodiment, each of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be an NMOS. In one embodiment, at least one selected from the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a PMOS or may be an NMOS. In one embodiment, for example, among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, the third transistor T3 and the fourth transistor T4 may be NMOS, and the other transistors may be PMOS. In one embodiment, for example, among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, the fifth transistor T5 may be a PMOS, and the other transistors may be NMOS.

[0111] although Figure 4The illustration shows an embodiment where the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are transistors including an LTPS semiconductor layer, but this disclosure is not limited thereto. In another embodiment, the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be transistors including an oxide semiconductor layer. In one embodiment, at least one selected from the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor including an LTPS semiconductor layer, and the remaining transistors may be transistors including an oxide semiconductor layer. In one embodiment, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor layer having low leakage current, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a semiconductor layer comprising polysilicon. In one embodiment, the fifth transistor T5 may include a semiconductor layer comprising polysilicon, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor layer.

[0112] The pixel circuit PC can be electrically connected to signal lines and voltage lines. Signal lines may include gate lines such as the scan signal line GWL, bypass control line GBL, initialization control line GIL, and transmit control line EML, as well as data lines DL. Voltage lines may include a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a first voltage line VDDL.

[0113] A first voltage line VDDL can be connected to transmit a first power supply voltage VDD to a first transistor T1. A first initialization voltage line VIL1 can be connected to transmit a first initialization voltage Vint, used to initialize the first transistor T1, to the pixel circuit PC. A second initialization voltage line VIL2 can be connected to transmit a second initialization voltage Vaint, used to initialize the first electrode of a light-emitting diode (LED), to the pixel circuit PC.

[0114] The first transistor T1 can be electrically connected to the first voltage line VDDL via the fifth transistor T5, and can be electrically connected to the light-emitting diode LED via the sixth transistor T6. The first transistor T1 can act as a driving transistor, and can receive the data signal Dm based on the switching operation of the second transistor T2, so as to supply driving current to the light-emitting diode LED.

[0115] The second transistor T2 can be a data write transistor and can be electrically connected to the scan signal line GWL and the data line DL. The second transistor T2 can be electrically connected to the first voltage line VDDL via the fifth transistor T5. By being turned on according to the scan signal GW received through the scan signal line GWL, the second transistor T2 can perform a switching operation to transmit the data signal Dm received through the data line DL to the first node N1.

[0116] The third transistor T3 can be electrically connected to the scan signal line GWL, and can be electrically connected to the light-emitting diode (LED) via the sixth transistor T6. Based on the scan signal GW received through the scan signal line GWL, the third transistor T3 can be turned on, connecting to the first transistor T1 as a diode, i.e., connecting the first transistor T1 in a diode configuration.

[0117] The fourth transistor T4 can be the first initialization transistor and can be electrically connected to the initialization control line GIL and the first initialization voltage line VIL1. In response to the initialization control signal GI received via the initialization control line GIL, the fourth transistor T4 can be turned on to transfer the first initialization voltage Vint from the first initialization voltage line VIL1 to the gate electrode of the first transistor T1, thereby initializing the voltage at the gate electrode of the first transistor T1. The initialization control signal GI can correspond to a scan signal from another pixel circuit arranged in the row preceding the pixel circuit PC.

[0118] The fifth transistor T5 can be an operation control transistor, and the sixth transistor T6 can be an emitter control transistor. The fifth transistor T5 and the sixth transistor T6 can be electrically connected to the emitter control line EML, and can be simultaneously turned on in response to the emitter control signal EM received via the emitter control line EL to form a current path, allowing drive current to flow from the first voltage line VDDL to the light-emitting diode LED. The first electrode of the light-emitting diode LED can be electrically connected to the first transistor T1 via the sixth transistor T6, and its second electrode can be electrically connected to the second voltage line VSSL, which is configured to supply the second power supply voltage VSS.

[0119] The seventh transistor T7 can be the second initialization transistor and can be electrically connected to the bypass control line GBL, the second initialization voltage line VIL2, and the sixth transistor T6. In response to the bypass control signal GB received via the bypass control line GBL, the seventh transistor T7 can be turned on to transfer the second initialization voltage Vaint from the second initialization voltage line VIL2 to the first electrode of the light-emitting diode LED, thereby initializing the first electrode of the light-emitting diode LED.

[0120] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 may be electrically connected to the gate electrode of the first transistor T1, and the second electrode CE2 may be electrically connected to the first voltage line VDDL. The storage capacitor Cst may be configured to store and maintain a voltage corresponding to the voltage difference between the first voltage line VDDL and the gate electrode of the first transistor T1, thereby maintaining the voltage applied to the gate electrode of the first transistor T1.

[0121] although Figure 4 The illustration shows an embodiment in which the first initialization voltage line VIL1 and the second initialization voltage line VIL2 are electrically connected to the fourth transistor T4 and the seventh transistor T7, respectively; however, this disclosure is not limited thereto. In another embodiment, the first initialization voltage line VIL1 and the second initialization voltage line VIL2 may be the same initialization voltage line, and a single initialization voltage line may be electrically connected to each of the fourth transistor T4 and the seventh transistor T7.

[0122] although Figure 4 The illustration shows an embodiment of a pixel circuit PC including seven transistors and a storage capacitor, but this disclosure is not limited thereto. In another embodiment, the pixel circuit PC may include three to six transistors, may include eight or more transistors, or may include two or more capacitors.

[0123] Figure 5 This is a cross-sectional view of a portion of a display panel 10 according to one embodiment.

[0124] refer to Figure 5 An embodiment of the display panel 10 may include a substrate 100, light-emitting diodes (LEDs) above the substrate 100, and a circuit layer 200 between the substrate 100 and the LEDs. The circuit layer 200 may include pixel circuitry electrically connected to the LEDs. The pixel circuitry may include, as referenced above... Figure 4 The transistors and capacitors described, and Figure 5 The diagram illustrates the components of circuit layer 200 as shown in the reference above. Figure 4 The description includes the storage capacitor Cst and the first to third transistors T1, T2 and T3.

[0125] The substrate 100 may comprise various materials such as glass or plastic materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide. In embodiments where the substrate 100 comprises a plastic material, flexibility can be improved compared to embodiments where the substrate 100 comprises a glass material. A buffer layer BL, comprising silicon oxynitride, silicon oxide, and / or silicon nitride, formed to prevent impurity penetration, may be provided over the substrate 100.

[0126] The first to third transistors T1, T2, and T3 may be disposed above the buffer layer BL. Each of the first to third transistors T1, T2, and T3 may include a semiconductor layer and a gate electrode. The first transistor T1 may include a first semiconductor layer 210a and a first gate electrode 225a, the second transistor T2 may include a second semiconductor layer 210b and a second gate electrode 225b, and the third transistor T3 may include a third semiconductor layer 210c and a third gate electrode 225c.

[0127] The first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c may comprise amorphous silicon, polycrystalline silicon, oxide semiconductor, or organic semiconductor materials. The first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c may comprise the same material as each other, or they may comprise different materials. In one embodiment, for example, the first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c may comprise the same material, such as amorphous silicon or polycrystalline silicon. In another embodiment, for example, the first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c may comprise the same material, such as oxide semiconductor. In one embodiment, the first semiconductor layer 210a and the second semiconductor layer 210b may comprise polycrystalline silicon, and the third semiconductor layer 210c may comprise an oxide semiconductor.

[0128] although Figure 5 The illustration shows an embodiment in which the first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c are arranged in the same layer (e.g., buffer layer BL) (or directly on the same layer), but this disclosure is not limited thereto. In another embodiment, the third semiconductor layer 210c may be arranged in a different layer than the first semiconductor layer 210a and the second semiconductor layer 210b (or directly on a different layer than the first semiconductor layer 210a and the second semiconductor layer 210b).

[0129] The gate insulating layer can be disposed between the gate electrode and the semiconductor layer of each of the first to third transistors T1, T2 and T3. Figure 5 The illustration shows an embodiment in which a first gate insulating layer GI1 is disposed above a first semiconductor layer 210a, a second semiconductor layer 210b, and a third semiconductor layer 210c. The first gate insulating layer GI1 may comprise an inorganic insulating material or an organic insulating material. In one embodiment, the first gate insulating layer GI1 may comprise an inorganic insulating material such as silicon oxynitride, silicon oxide, or silicon nitride, and may have a single-layer or multi-layer structure of the above materials.

[0130] The first gate electrode 225a, the second gate electrode 225b, and the third gate electrode 225c can be arranged above the first semiconductor layer 210a, the second semiconductor layer 210b, and the third semiconductor layer 210c, respectively, with the first gate insulating layer GI1 located between them.

[0131] In a plan view or when viewed in the z-direction, the first gate electrode 225a may overlap with the channel region 210a1 of the first semiconductor layer 210a, the second gate electrode 225b may overlap with the channel region 210b1 of the second semiconductor layer 210b, and the third gate electrode 225c may overlap with the channel region 210c1 of the third semiconductor layer 210c. The first semiconductor layer 210a may include regions 210a2 and 210a3 disposed on two opposite sides of the channel region 210a1, wherein one of regions 210a2 and 210a3 may be a source region, and the other may be a drain region. The second semiconductor layer 210b may include regions 210b2 and 210b3 disposed on both sides of the channel region 210b1, wherein one of regions 210b2 and 210b3 may be a source region, and the other may be a drain region. The third semiconductor layer 210c may include regions 210c2 and 210c3 disposed on both sides of the channel region 210c1, wherein one of regions 210c2 and 210c3 may be a source region and the other may be a drain region.

[0132] Each of the first gate electrode 225a, the second gate electrode 225b, and the third gate electrode 225c may include at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure comprising the above materials.

[0133] The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. In one embodiment, the storage capacitor Cst may overlap with the first transistor T1 in a plan view. In one embodiment, for example, the first electrode CE1 of the storage capacitor Cst may be integrated with the first gate electrode 225a, that is, integrally formed as a single, inseparable part with the first gate electrode 225a. In another embodiment, the first gate electrode 225a and the first electrode CE1 of the storage capacitor Cst may be separated into separate components.

[0134] Each of the first electrode CE1 and the second electrode CE2 may include at least one material selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure comprising the above materials.

[0135] The second gate insulating layer GI2 can be disposed between the first electrode CE1 and the second electrode CE2. The second gate insulating layer GI2 may include inorganic insulating materials or organic insulating materials. In one embodiment, the second gate insulating layer GI2 may include inorganic insulating materials such as silicon oxynitride, silicon oxide, or silicon nitride, and may have a single-layer or multi-layer structure of the above materials.

[0136] Each of the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 may be disposed above the second gate insulating layer GI2. The first interlayer insulating layer ILD1 and the third interlayer insulating layer ILD3 may comprise inorganic insulating materials such as silicon oxynitride, silicon oxide, or silicon nitride, or may comprise organic insulating materials. The second interlayer insulating layer ILD2 may comprise inorganic insulating materials such as silicon oxynitride, silicon oxide, or silicon nitride.

[0137] The semiconductor layer of the transistor, its gate electrode, and / or the electrodes of the storage capacitor Cst can be electrically connected to a voltage line or signal line for providing a preset voltage or signal, or can be electrically connected to another transistor. For the aforementioned electrical connections, the circuit layer 200 of the display panel 10 according to one embodiment may include an interconnect structure ICS.

[0138] In one embodiment, the interconnect structure ICS may be disposed above the second semiconductor layer 210b. The first conductor 1130 may reside in a contact hole defined in at least one insulating layer above the second semiconductor layer 210b and may not extend to the upper surface of the at least one insulating layer. In such an embodiment, as Figure 5 As shown, the first conductor 1130 may be in a contact hole defined or formed through the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1. The first conductor 1130 may extend along the inner wall (inner surface) and bottom surface (i.e., the inner lower surface of each layer defining the contact hole) of the contact hole, and may not be above the upper surface of the first interlayer insulating layer ILD1.

[0139] The first conductor 1130 may include a side portion disposed above (along or to cover) the inner wall defining the contact hole and a lower portion contacting the upper surface of the second semiconductor layer 210b. The contact hole is not filled by the first conductor 1130. In the contact hole, inorganic filler 1400 may be present in a recess defined by the side and lower portions of the first conductor 1130. The inorganic filler 1400 may at least partially fill the recess.

[0140] The second conductor 1160 can contact the upper surface of the side portion of the first conductor 1130 and the upper surface of the inorganic filler 1400, and therefore, the second conductor 1160 can be electrically connected to region 210b2 of the second semiconductor layer 210b through the first conductor 1130.

[0141] In one embodiment, the second conductor 1160 may be a data line DL (see...) Figure 4 Part of it. In another embodiment, the data line DL (see...) Figure 4 The second conductor 1160 can be a separate component and can be connected through a circuit not in the circuit. Figure 5 Another contact hole illustrated in the figure is electrically connected to the second conductor 1160. In some embodiments, the second conductor 1160 may contact the upper surface of the first conductor 1130, for example, the upper surface of a side portion of the first conductor 1130, through a contact hole defined or formed through the second interlayer insulation layer ILD2 and the third interlayer insulation layer ILD3.

[0142] The contact points between the second conductor 1160 and the first conductor 1130 (e.g., direct contact points between the second conductor 1160 and the first conductor 1130) and the contact points between the first conductor 1130 and the second semiconductor layer 210b (e.g., direct contact points between the first conductor 1130 and the second semiconductor layer 210b) can be arranged in a direction perpendicular to the upper surface of the substrate 100. The contact points between the second conductor 1160 and the first conductor 1130 and the contact points between the first conductor 1130 and the second semiconductor layer 210b can overlap each other in a direction perpendicular to the upper surface of the substrate 100 (i.e., the thickness direction or z-direction of the substrate 100).

[0143] As a comparative example, when the first conductor 1130 extends through the aforementioned contact hole to the upper surface of the first interlayer insulating layer ILD1, and the second conductor 1160 contacts a portion of the first conductor 1130 extending to the upper surface of the first interlayer insulating layer ILD1, the contact points of the second conductor 1160 and the first conductor 1130, as well as the contact points of the first conductor 1130 and the second semiconductor layer 210b, can be laterally offset (e.g., laterally moved) in the x-direction (or y-direction). Therefore, a large area may be desired for the contact between the second semiconductor layer 210b and the second conductor 1160 through the first conductor 1130 in the display area DA. According to the comparative example, when viewed in a direction perpendicular to the upper surface of the substrate 100 (e.g., the z-direction), the contact points of the second conductor 1160 and the first conductor 1130, as well as the contact points of the first conductor 1130 and the second semiconductor layer 210b, may not overlap with each other. In this case, the area occupied by the contact points in the display area DA used for electrically connecting the second conductor 1160, the first conductor 1130 and the second semiconductor layer 210b may become relatively large, and it may be difficult to achieve a high-resolution display panel 10 that includes many contact structures.

[0144] According to one embodiment, as described above, since the contact points of the second conductor 1160 and the first conductor 1130, as well as the contact points of the first conductor 1130 and the second semiconductor layer 210b, overlap each other in a direction perpendicular to the upper surface of the substrate 100, the area occupied by the contact points in the display area DA can be minimized, and thus the space utilization of the display area DA can be improved and a high-resolution (e.g., 1500 pixels per inch (ppi) or higher) display panel 10 can be effectively realized.

[0145] As a comparative example, when an organic filler comprising an organic insulating material is provided in the recess according to the shape of the first conductor 1130, a conductor, such as the second conductor 1160, disposed above the organic filler may be lifted by gases released from the organic filler during the heat treatment process performed in the manufacturing process of the display panel 10. In this case, the contact points between the second conductor 1160 and the first conductor 1130 may be damaged or may not be effectively maintained. Furthermore, in this case, it may be desirable to arrange an intermediate conductor between the first conductor 1130 and the second conductor 1160 to protect the organic filler, thus potentially increasing the number of processes. In embodiments of this disclosure, the above problems can be effectively prevented by including an inorganic filler 1400.

[0146] In one embodiment, an interconnect structure ICS for electrical connections of transistors can be provided. In one embodiment, for example, the electrical connection structure between the first gate electrode 225a of the first transistor T1 and the third semiconductor layer 210c of the third transistor T3 may include the interconnect structure ICS. In one embodiment, the first gate electrode 225a of the first transistor T1 may be integrally formed with the first electrode CE1 of the storage capacitor Cst as a single, inseparable part, and in such an embodiment, the electrical connection structure between the first gate electrode 225a of the first transistor T1 and the third semiconductor layer 210c of the third transistor T3 may be referred to as the electrical connection structure between the first electrode CE1 of the storage capacitor Cst and the third semiconductor layer 210c of the third transistor T3.

[0147] The first conductor 2130 and the inorganic filler 1400 may be located in contact holes of at least one insulating layer (e.g., the second gate insulating layer GI2 and the first interlayer insulating layer ILD1) above the first gate electrode 225a. The first conductor 2130 and the inorganic filler 1400 may be located only in their respective contact holes. The first conductor 2130' and the inorganic filler 1400 may be located in contact holes of at least one insulating layer (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, and the first interlayer insulating layer ILD1) above the third semiconductor layer 210c. The first conductor 2130' and the inorganic filler 1400 may be located only in their respective contact holes.

[0148] The second conductor 2160 can directly contact the upper surface of the side portion of each of the first conductors 2130 and 2130'. In one embodiment, the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 can be provided with contact holes that overlap with the first conductors 2130 and 2130', respectively. The second conductor 2160 can directly contact the upper surface of each of the first conductors 2130 and 2130', such as the upper surface of the side portion of each of the first conductors 2130 and 2130', through the contact holes of the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3.

[0149] In one embodiment, an interconnect structure ICS can be provided for the electrical connection of the voltage line and the storage capacitor Cst. In one embodiment, the first conductor 3130 and the inorganic filler 1400 may be in a contact hole of at least one insulating layer (e.g., a first interlayer insulation layer ILD) above the second electrode CE2 of the storage capacitor Cst. The first conductor 3130 and the inorganic filler 1400 may be only in the corresponding contact hole and may not extend to the upper surface of the insulating layer in which the corresponding contact hole is formed.

[0150] The second conductor 3160 can directly contact the upper surface of the first conductor 3130, for example, the upper surface of the side portion of the first conductor 3130. In one embodiment, the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 can be provided with contact holes that overlap with the first conductor 3130 and the inorganic filler 1400, and the second conductor 3160 can directly contact the upper surface of the side portion of the first conductor 3130 through the contact holes.

[0151] In one embodiment, the second conductor 3160 may be the first voltage line VDDL (see...) Figure 4 Part of ). In another embodiment, the first voltage line VDDL (see Figure 4 The first conductor 3160 and the second conductor 3160 can be separate components, and the first voltage line VDDL (see...) Figure 4 ) can be obtained by not being in Figure 5 The other contact hole shown in the diagram is electrically connected to the second conductor 3160.

[0152] Each of the first conductors 1130, 2130, 2130' and 3130 and the second conductors 1160, 2160 and 3160 may include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0153] The upper insulating layer UL can be disposed above the interconnect structure ICS. The upper insulating layer UL may include an organic insulating material. A light-emitting diode (LED) can be disposed above the upper insulating layer UL. The LED may include a pixel electrode 310, an intermediate layer 320, and a counter electrode 330. Although not explicitly stated... Figure 5 As shown in the diagram, however, pixel electrode 310 can be electrically connected to a transistor, as in the reference above. Figure 4 The sixth transistor T6 described (see...) Figure 4 ).

[0154] Pixel electrode 310 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or any compound thereof. In another embodiment, pixel electrode 310 may further include a conductive oxide layer above and / or below the reflective layer. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). In one embodiment, pixel electrode 310 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0155] The intermediate layer 320 may include an emitter layer 322 and a first functional layer 321 and a second functional layer 323 disposed below and above the emitter layer 322, respectively. The first functional layer 321 may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second functional layer 323 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). In one embodiment, the intermediate layer 320 may include a stacked structure comprising multiple stacked structures including the first functional layer 321, the emitter layer 322, and the second functional layer 323.

[0156] A dam layer BNL can be disposed above the pixel electrode 310. The dam layer BNL can be provided with an opening that overlaps with the pixel electrode 310 and can cover the edge of the pixel electrode 310. The dam layer BNL may include an organic insulating material.

[0157] The counter electrode 330 may include a conductive material having a low work function. In one embodiment, for example, the counter electrode 330 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Alternatively, the counter electrode 330 may further include a layer such as ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer comprising the above materials. The counter electrode 330 may be integrally formed as a single, inseparable portion within a plurality of light-emitting diodes (LEDs) to correspond to a plurality of pixel electrodes 310.

[0158] Figures 6A to 6I The illustration shows a configuration according to an embodiment including a display panel 10 (see figure). Figure 5 Circuit layer 200 (see) Figure 5 A cross-sectional view of the process (or method) of the interconnect structure ICS in ). Figure 7A When viewed in a direction perpendicular to the upper surface of the substrate 100 Figure 6E A plan view of the first conductor 130. Figure 7B yes Figure 6E An enlarged cross-sectional view of region VIIb. Figure 8 It is based on the reference Figure 6F Cross-sectional view of an embodiment of the described process. Figure 9A The illustration is based on a reference. Figure 6I A plan view of the contact structure between the second conductor 160 and the first conductor 130 in the described process. Figure 9B This is a cross-sectional view of an interconnect structure ICS according to a process based on one embodiment, and Figure 9C This is a plan view illustrating the contact structure of the second conductor 160 and the first conductor 130 according to a process according to an embodiment.

[0159] refer to Figures 6A to 6I Forming circuit layer 200 (see Figure 5 An embodiment of the process (or method) for the interconnect structure ICS of the first conductive material layer 110 may include: a process of forming a first conductive material layer 110 over a substrate 100; a process of forming a first insulating layer 120 including a first contact hole CNT1 overlapping a portion of the upper surface of the first conductive material layer 110; a process of forming a first conductor 130 including a side portion on the inner wall of the first insulating layer 120 defining the first contact hole CNT1 and a lower portion integrally connected to the side portion (or integrally formed with the side portion as a single, indivisible part) and directly contacting a portion of the upper surface of the first conductive material layer 110; a process of forming an inorganic filler 1400 disposed in a recess R surrounded by the side portion of the first conductor 130 in the first contact hole CNT1; and a process of forming a second conductor 160 directly contacting the upper surface of the side portion of the first conductor 130.

[0160] refer to Figure 6A A first conductive material layer 110 may be formed above the substrate 100. Although not in Figure 6A The diagram shows that, prior to the formation of the first conductive material layer 110, a buffer layer BL (see figure) is included. Figure 5 Various insulating layers can be formed on the substrate 100 first.

[0161] The first conductive material layer 110 may include semiconductor materials and / or metallic materials. The first conductive material layer 110 may include polycrystalline silicon, oxide semiconductor or organic semiconductor, or may include at least one selected from silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0162] A first insulating layer 120 may be formed over a first conductive material layer 110. The first insulating layer 120 may be provided with a first contact hole CNT1 that exposes a portion of the upper surface of the first conductive material layer 110; that is, the first contact hole CNT1 may be formed through the first insulating layer 120 to expose that portion of the upper surface of the first conductive material layer 110. The first insulating layer 120 may comprise an inorganic insulating material comprising silicon oxynitride, silicon oxide, and / or silicon nitride, or may comprise an organic insulating material. The first insulating layer 120 may have a single-layer or multi-layer structure comprising the above insulating materials.

[0163] Subsequently, the first conductor 130 (see...) Figure 6E This can be formed in the first contact hole CNT1 of the first insulating layer 120. (Refer to...) Figures 6A to 6E Description of the formation of the first conductor 130 (see) Figure 6E The process of ).

[0164] like Figure 6A As shown, the conductive layer 130M can be formed over the first insulating layer 120 including the first contact hole CNT1. The conductive layer 130M can include a metallic material. The conductive layer 130M can include at least one selected from silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and can have a single-layer or multi-layer structure including the above materials. In one embodiment, the conductive layer 130M can be formed by a sputtering process.

[0165] The conductive material (e.g., a metallic material) used to form the conductive layer 130M can also be deposited by advancing into the first contact hole CNT1 at a predetermined depth. The conductive layer 130M can be continuously formed above a portion of the upper surface of the first conductive material layer 110 by passing through the upper surface 120us of the first insulating layer 120 and the inner wall 120is of the first insulating layer 120 defining the first contact hole CNT1. The conductive material (e.g., a metallic material) forming the conductive layer 130M through the first contact hole CNT1 can form a hanging structure OH near the point where the inner wall 120is and the upper surface 120us of the first insulating layer 120 intersect each other. Furthermore, the portion 130Ms of the conductive layer 130M disposed above the inner wall 120is of the first insulating layer 120 can have a shape in which its thickness gradually decreases in the depth direction (e.g., the -z direction) of the first contact hole CNT1.

[0166] refer to Figure 6BA planarization layer PL can be formed above the conductive layer 130M. The planarization layer PL may include an organic insulating material or a photoresist. The planarization layer PL may cover the upper surface of the conductive layer 130M and may fill the recess R surrounded by a portion 130Ms of the conductive layer 130M.

[0167] refer to Figure 6C A portion of the planarization layer PL can be removed via an etching-back process. A portion of the planarization layer PL above the upper surface of the conductive layer 130M can be removed via an etching-back process. After the etching-back process, the remaining portion of the planarization layer PL can be retained in the recess R.

[0168] refer to Figure 6C and Figure 6D The first conductor 130 can be formed by removing a portion of the conductive layer 130M via an etch-back process. A portion of the conductive layer 130M disposed above the upper surface 120µs of the first insulating layer 120 can be removed, and in this case, the reference layer above can also be removed. Figure 6A The described overhanging structure OH (see Figure 6A The conductive layer 130M left by the etching process can form the first conductor 130. To form the first conductor 130, the planarization layer PL in the recess R can correspond to a type of protective layer or sacrificial layer to prevent etching of the portion of the conductive layer 130M corresponding to the first conductor 130. The first conductor 130 may include a side portion 130s on the inner wall 120is of the first insulating layer 120 and a lower portion 130b on a portion of the upper surface of the first conductive material layer 110.

[0169] refer to Figure 6D and Figure 6E The planarization layer PL in the recess R can be removed. Therefore, the first conductor 130 can be in the first contact hole CNT1, and the recess R can be formed inside the first conductor 130.

[0170] refer to Figure 6E and Figure 7A In the plan view, the recess R may be surrounded by the side portion 130s of the first conductor 130, and the bottom surface of the recess R (or the inner lower surface defining the recess R) may correspond to the lower portion 130b of the first conductor 130.

[0171] refer to Figure 6E and Figure 7BThe side portion 130s of the first conductor 130 can directly contact the inner wall 120is of the first insulating layer 120. The first point P1 where the side portion 130s of the first conductor 130 and the inner wall 120is of the first insulating layer 120 intersect or contact each other can be spaced apart by a first distance d1 along the inner wall 120is and the second point P2 where the inner wall 120is and the upper surface 120us of the first insulating layer 120 intersect each other. In this embodiment where the first point P1 is spaced apart along the inner wall 120is of the first insulating layer 120 and the second point P2, the conductive layer 130M (see...) can be effectively prevented from... Figure 6D Material residue remains on the upper surface 120µs of the first insulating layer 120.

[0172] The upper surface 130us of the side portion 130s of the first conductor 130 can be located parallel to the substrate 100 (see...). Figure 6E The imaginary plane IMS on the upper surface of the surface is essentially the same plane. Alternatively, due to Figure 6A The shape of the overhanging structure OH shown in the figure indicates that the upper surface 130us of the side portion 130s of the first conductor 130 can be tilted relative to the imaginary plane IMS at a first angle θ. The first angle θ can be greater than approximately 0 degrees and equal to or less than approximately 45 degrees (0 < θ ≤ 45°). In this embodiment where the upper surface 130us of the side portion 130s of the first conductor 130 is at a first angle θ relative to the imaginary plane IMS, compared to the case where the upper surface 130us of the side portion 130s of the first conductor 130 is substantially parallel to the imaginary plane IMS, and compared to the second conductor 160 described below (see... Figure 6I The contact area can be increased.

[0173] Subsequently, the inorganic packing 1400 arranged in the recess R can be formed (see... Figure 6I The process will be referenced. Figures 6F to 6I Description of the formation of inorganic filler 1140 (see) Figure 6I The process of ).

[0174] refer to Figure 6F An insulating material layer 140L may be formed over the first insulating layer 120, and a first conductor 130 may be formed in the first contact hole CNT1. The insulating material layer 140L may include inorganic insulating materials such as silicon oxynitride, silicon nitride, and / or silicon oxide.

[0175] An insulating material layer 140L can be formed on the upper surface 120us of the first insulating layer 120 and in the recess R. In one embodiment, for example, the insulating material layer 140L can be disposed above the upper surface 120us of the first insulating layer 120 and the upper surface 130us of the side portion 130s of the first conductor 130, and can at least partially fill the recess R. Although Figure 6FThe illustration shows an embodiment where the insulating material layer 140L completely fills the recess R, but this disclosure is not limited thereto. In another embodiment, such as Figure 8 As shown, the insulating material layer 140L can partially fill the recess R, and voids vd can exist (or be formed) therein. In the following description, for ease of explanation, Figure 6F The structure shown in the diagram will be described as an example.

[0176] refer to Figure 6G An additional insulating material layer 150L may be formed above the insulating material layer 140L. The additional insulating material layer 150L may completely cover the upper surface of the insulating material layer 140L. The additional insulating material layer 150L may include organic insulating materials or inorganic insulating materials.

[0177] refer to Figure 6H By performing an etching process on the entire surface of the additional insulating material layer 150L, ​​the thickness of the additional insulating material layer 150L can be adjusted, and the flatness of the upper surface of the additional insulating material layer 150L can also be adjusted.

[0178] refer to Figure 6I The portions of the insulating material layer 140L and the additional insulating material layer 150L corresponding to the first contact hole CNT1 can be removed using a process such as etching.

[0179] In the process of removing the portion of the insulating material layer 140L corresponding to the first contact hole CNT1, a portion of the insulating material layer 140L present in the recess R may be inorganic filler 1400, and another portion of the insulating material layer 140L disposed above the first insulating layer 120 may be a second insulating layer 140 including the second contact hole CNT2. The second insulating layer 140 may be separated from the inorganic filler 1400, and both the inorganic filler 1400 and the second insulating layer 140 may comprise the same inorganic insulating material.

[0180] As described above, in the process of removing a portion of the insulating material layer 140L, the first conductor 130 can be exposed to the outside through the second contact hole CNT2.

[0181] In the process of removing the portion of the additional insulating material layer 150L corresponding to the first contact hole CNT1, a third insulating layer 150 including a third contact hole CNT3 can be formed. The third insulating layer above the second insulating layer may have the third contact hole CNT3. The third contact hole CNT3 may overlap with the second contact hole CNT2. The third contact hole CNT3 and the second contact hole CNT2 can be formed by the same etching process and can be considered as a single contact hole.

[0182] Subsequently, a second conductor 160 can be formed. After forming the inorganic filler 1400, the second insulating layer 140, and the third insulating layer 150, a conductive layer (not shown) can be formed and then patterned to form the second conductor 160. The second conductor 160 may include at least one selected from silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure comprising the above materials.

[0183] The second conductor 160 can directly contact the upper surface of the first conductor 130, for example, the upper surface 130us of the side portion 130s of the first conductor 130. The second conductor 160 can also directly contact the upper surface of the inorganic filler 1400. The second conductor 160 can directly contact the first conductor 130 and the inorganic filler 1400 through the second contact hole CNT2 and the third contact hole CNT3.

[0184] In one embodiment, such as Figure 6I As shown, the second contact hole CNT2 can completely expose the upper surface of the inorganic filler 1400 and the upper surface 130us of the first conductor 130. In one embodiment, for example, the third width W3 of the lower portion of the second contact hole CNT2, measured by the point where the lower portion of the inner wall of the second insulating layer 140 defining the second contact hole CNT2 and the upper surface 120us of the first insulating layer 120 intersect each other, can be greater than the second width W2 of the upper portion of the first contact hole CNT1, measured by the point where the inner wall of the first insulating layer 120 and the upper surface 120us intersect each other, and the second width W2 of the first contact hole CNT1 can be greater than the first width W1 of the upper surface of the inorganic filler 1400. The upper surface 130us of the side portion 130s of the first conductor 130 can completely contact the second conductor 160. In a plan view (or when viewed in a direction perpendicular to the upper surface of the substrate 100), as Figure 9A As shown, the contact area CA of the second conductor 160 and the first conductor 130 can have a closed-loop shape (e.g., annular shape).

[0185] In another embodiment, such as Figure 9BAs shown, the third width W3 can be greater than the first width W1 and less than the second width W2. In such an embodiment, the lower portion of the inner wall of the second insulating layer 140 can extend to the upper surface 130us of the side portion 130s of the first conductor 130, and the third width W3 of the lower portion of the second contact hole CNT2, measured by the point where the inner wall of the second insulating layer 140 and the upper surface 130us of the side portion 130s of the first conductor 130 intersect each other, can be greater than the first width W1 and less than the second width W2. In such an embodiment, as... Figure 9B As shown, a portion of the upper surface 130us of the side portion 130s of the first conductor 130 can contact the second conductor 160, and in a plan view (or when viewed in a direction perpendicular to the upper surface of the substrate 100), the contact area CA of the second conductor 160 and the first conductor 130 can have a closed-loop shape (e.g., annular shape).

[0186] In another embodiment, such as Figure 9C As shown, the center of the second contact hole CNT2 is spaced apart from the center of the first contact hole CNT1 (for example, when the center of the second contact hole CNT2 is offset from the center of the first contact hole CNT1), and the contact area CA' of the second conductor 160 and the first conductor 130 can have a generally arc-shaped shape.

[0187] The contact area between the second conductor 160 and the first conductor 130 ( Figure 9A CA or Figure 9C The area of ​​CA' can be approximately 0.039 square micrometers (μm). 2 ~ Approximately 3.11 μm 2 Within the range.

[0188] refer to Figures 6A to 6I The interconnection structure ICS of the first conductive material layer 110, the first conductor 130, and the second conductor 160 described above can be provided in the reference above. Figure 5 The described circuit layer 200 (see Figure 5 In the first conductive material layer 110, the reference above can be used. Figure 5 The semiconductor layer or electrode described. In one embodiment, the first conductive material layer 110 may be a second semiconductor layer 210b (see...). Figure 5 ) or third semiconductor layer 210c (see Figure 5 In one embodiment, the first conductive material layer 110 may be the first gate electrode 225a (see...). Figure 5 ), the first electrode CE1 of the storage capacitor Cst (see Figure 5 ) or the second electrode CE2 of the storage capacitor Cst (see Figure 5 ).

[0189] In one embodiment, reference Figures 6A to 6I , Figure 7A , Figure 7B , Figure 8 and Figures 9A to 9C The first conductive material layer 110, the first conductor 130, and the second conductor 160 described herein can be respectively connected to Figure 5 The second semiconductor layer 210b, the first conductor 1130, and the second conductor 1160 of the second transistor T2 correspond to each other.

[0190] In one embodiment, reference Figures 6A to 6I , Figure 7A , Figure 7B , Figure 8 and Figures 9A to 9C The first conductive material layer 110, the first conductor 130, and the second conductor 160 described herein can be respectively connected to Figure 5 The first gate electrode 225a, the first conductor 2130, and the second conductor 2160 of the first transistor T1 correspond to each other. Furthermore, refer to... Figures 6A to 6I The first conductive material layer 110, the first conductor 130, and the second conductor 160 described herein can be respectively connected to Figure 5 The third semiconductor layer 210c, the first conductor 2130', and the second conductor 2160 of the third transistor T3 correspond to each other.

[0191] In one embodiment, reference Figures 6A to 6I , Figure 7A , Figure 7B , Figure 8 and Figures 9A to 9C The first conductive material layer 110, the first conductor 130, and the second conductor 160 described herein can be respectively connected to Figure 5 The second electrode CE2 of the storage capacitor Cst corresponds to the first conductor 3130 and the second conductor 3160.

[0192] According to the reference Figures 6A to 6I The described embodiments can be referenced as follows Figure 6G The description refers to the formation of an additional insulating material layer 150L, ​​and thus as... Figure 6I The third insulating layer 150 is formed as shown; however, this disclosure is not limited thereto. In another embodiment, the additional insulating material layer 150L may not be formed, and therefore, the etch-back process for removing a portion of the additional insulating material layer 150L may also be omitted. Figure 6H In another embodiment, an additional insulating material layer 150L can be formed, but the etch-back process for removing a portion of the additional insulating material layer 150L can be omitted. Figure 6H In other words, refer to Figure 6G and / or Figure 6H The described process may be optional.

[0193] Figures 10A to 10GThe illustration shows a configuration according to an embodiment including a display panel 10 (see figure). Figure 5 Circuit layer 200 (see) Figure 5 A cross-sectional view of the interconnect structure ICS in the process.

[0194] refer to Figure 10A As shown in the reference above Figure 6A As described, a first conductive material layer 110 can be formed over the substrate 100, and a first insulating layer 120 including the first contact hole CNT1 can be formed therein. Then, a conductive layer 130M can be formed over the first insulating layer 120 including the first contact hole CNT1. The materials and specific processes used for the conductive layer 130M are the same as described above. Figure 6A The materials and specific processes described are the same.

[0195] refer to Figure 10B A planarization layer PL may be formed above the conductive layer 130M. The planarization layer PL may include an organic insulating material or a photoresist. The planarization layer PL may cover the upper surface of the conductive layer 130M and may fill the recess R surrounded by a portion 130Ms of the conductive layer 130M disposed on the inner wall 120is of the first insulating layer 120 defining the first contact hole CNT1.

[0196] refer to Figure 10C A portion of the planarization layer PL and a portion of the conductive layer 130M can be removed by an etching-back process. The process of removing a portion of the planarization layer PL and a portion of the conductive layer 130M can be performed in the same etching process. The etching process can be performed using an etching gas with an etching selectivity of approximately 1 for the conductive layer 130M relative to the planarization layer PL.

[0197] Since a portion of the conductive layer 130M has been removed, the first conductor 130 can be formed in the first contact hole CNT1, and a portion of the planarization layer PL can be retained in the recess R.

[0198] The first conductor 130 may include a side portion 130s disposed on the inner wall 120is of the first insulating layer 120 and a lower portion 130b integrally connected to the side portion 130s (or integrally formed as a single, indivisible part with the side portion 130s) and contacting a portion of the upper surface of the first conductive material layer 110. The side portion 130s of the first conductor 130 may directly contact the inner wall 120is of the first insulating layer 120. The side portion 130s of the first conductor 130 may have a shape in which its thickness gradually decreases in the direction toward the lower portion 130b (e.g., the -z direction). (Refer to the above...) Figure 7BThe point where the side portion 130s of the first conductor 130 and the inner wall 120is of the first insulating layer 120 intersect each other can be located below the point where the upper surface 120us of the first insulating layer 120 and the inner wall 120is intersect each other. The upper surface 130us of the side portion 130s of the first conductor 130 can be substantially parallel to the upper surface of the substrate 100.

[0199] After that, the planarization layer PL remaining in the recess R can be removed.

[0200] Reference Figures 10D to 10G The described process can be referenced above. Figures 6F to 6I The processes described are the same.

[0201] refer to Figure 10D An insulating material layer 140L may be formed above a first insulating layer 120 on which the first conductor 130 has been formed. The insulating material layer 140L may include inorganic insulating materials such as silicon oxynitride, silicon nitride, and / or silicon oxide.

[0202] An insulating material layer 140L can be formed on the upper surface 120us of the first insulating layer 120 and in the recess R. In one embodiment, for example, the insulating material layer 140L can be disposed above the upper surface 120us of the first insulating layer 120 and the upper surface 130us of the side portion 130s of the first conductor 130, and can at least partially fill the recess R. Although Figure 10D The illustration shows an embodiment where the insulating material layer 140L completely fills the recess R, but this disclosure is not limited thereto. In another embodiment, as referenced above... Figure 8 The insulating material layer 140L can partially fill the recess R, and the gap vd (see...) Figure 8 It can exist or form within it.

[0203] refer to Figure 10E An additional insulating material layer 150L may be formed above the insulating material layer 140L. The additional insulating material layer 150L may completely cover the upper surface of the insulating material layer 140L. The additional insulating material layer 150L may include organic insulating materials or inorganic insulating materials.

[0204] refer to Figure 10F By performing an etching process on the entire surface of the additional insulating material layer 150L, ​​the thickness of the additional insulating material layer 150L can be adjusted, and the flatness of the upper surface of the additional insulating material layer 150L can also be adjusted.

[0205] refer to Figure 10G The portions of the insulating material layer 140L and the additional insulating material layer 150L corresponding to the first contact hole CNT1 can be removed using a process such as etching.

[0206] In the process of removing the portion of the insulating material layer 140L corresponding to the first contact hole CNT1, a portion of the insulating material layer 140L present in the recess R may be inorganic filler 1400, and another portion of the insulating material layer 140L disposed above the first insulating layer 120 may be a second insulating layer 140 including the second contact hole CNT2. The second insulating layer 140 may be separated from the inorganic filler 1400, and both the inorganic filler 1400 and the second insulating layer 140 may comprise the same inorganic insulating material. As described above, in the process of removing a portion of the insulating material layer 140L, the first conductor 130 may be exposed to the outside through the second contact hole CNT2.

[0207] In the process of removing the portion of the additional insulating material layer 150L corresponding to the first contact hole CNT1, a third insulating layer 150 including a third contact hole CNT3 can be formed. The third contact hole CNT3 and the second contact hole CNT2 can be formed by the same etching process and can be considered as a single contact hole.

[0208] Subsequently, a second conductor 160 can be formed. After forming the inorganic filler 1400, the second insulating layer 140, and the third insulating layer 150, a conductive layer (not shown) can be formed and then patterned to form the second conductor 160. The second conductor 160 can directly contact the upper surface of the first conductor 130, for example, the upper surface 130us of the side portion 130s of the first conductor 130. The second conductor 160 can also directly contact the upper surface of the inorganic filler 1400. The second conductor 160 can directly contact the first conductor 130 and the inorganic filler 1400 through the second contact hole CNT2 and the third contact hole CNT3.

[0209] According to the reference Figures 10A to 10G The described embodiments can be referenced as follows Figure 10E The description refers to the formation of an additional insulating material layer 150L, ​​and thus as... Figure 10G The third insulating layer 150 is formed as shown; however, this disclosure is not limited thereto. In another embodiment, the additional insulating material layer 150L may not be formed, and therefore, the etch-back process for removing a portion of the additional insulating material layer 150L may also be omitted. Figure 10F In another embodiment, an additional insulating material layer 150L can be formed, but the etch-back process for removing a portion of the additional insulating material layer 150L can be omitted. Figure 10F In other words, refer to Figure 10E and / or Figure 10F The described process may be optional.

[0210] refer to Figures 10A to 10GThe interconnection structure ICS of the first conductive material layer 110, the first conductor 130, and the second conductor 160 described above can be provided in the reference above. Figure 5 The described circuit layer 200 (see Figure 5 )middle.

[0211] Figure 11A and Figure 11B This is a cross-sectional view illustrating a process of forming a first conductor in a process of forming an interconnect structure including a circuit layer in a display panel according to an embodiment.

[0212] Figure 11A The illustration shows a first conductor (hereinafter referred to as "first-1 conductor") 1301 formed in a first contact hole CNT1 of the first insulating layer 120 after the first insulating layer 120 is formed over the substrate 100. The process for forming the first-1 conductor 1301 can be referenced above. Figures 6A to 6E The formation of the first conductor 130 is described (see Figure 6E The process is the same.

[0213] The first-1 conductor 1301 may include a first side portion 1301s disposed on (or in contact with) the inner wall 120is of the first insulating layer 120, and a first lower portion 1301b integrally formed with the first side portion 1301s as a single, indivisible part and in direct contact with a portion of the upper surface of the first conductive material layer 110. The recess R may be surrounded by the first side portion 1301s of the first-1 conductor 1301.

[0214] In such Figure 11A In the state shown where the first conductor 1301 is formed, the process according to... Figures 6A to 6E The process, as Figure 11B The diagram shows the formation of a second first conductor (hereinafter referred to as "the first-second conductor") 1302. The first-second conductor 1302 may include a second side 1302s disposed on (or in contact with) a first side 1301s of the first-first conductor 1301 and a second lower portion 1302b disposed on (or in contact with) a first lower portion 1301b of the first-first conductor 1301. In one embodiment, inorganic filler 1400 may be surrounded by the second side 1302s of the first-second conductor 1302.

[0215] By repeatedly executing the reference Figures 6A to 6E The described process allows the first conductor 130 to have a dual structure, consisting of a first-1 conductor 1301 and a first-2 conductor 1302. By forming the first conductor 130 with this dual structure, the connection with the second conductor 160 (see...) can be increased. Figure 6I ) contact area.

[0216] although Figure 11A and Figure 11B The diagram illustrates the reference for repeated execution. Figures 6A to 6I Some of the processes described (e.g., references) Figures 6A to 6E The embodiments described herein are examples of processes, but this disclosure is not limited thereto. In another embodiment, reference is made to... Figures 10A to 10G References in the described process Figures 10A to 10C The described process can be repeated to form, for example, Figure 11B The first conductor 130 is shown in the diagram.

[0217] Figure 12 This is a cross-sectional view of an interconnect structure ICS according to one embodiment.

[0218] refer to Figure 12 In one embodiment, the first insulating layer 120 may be disposed above the first conductive material layer 110, and the first conductor 130 and the inorganic filler 1400 may be disposed in the first contact hole CNT1 of the first insulating layer 120. The process, materials and other structural features of the first conductive material layer 110, the first insulating layer 120, the first conductor 130 and the inorganic filler 1400 may be the same as those described above.

[0219] Figure 12 The second conductor 160 illustrated in the figure can be formed using the same process as that used to form the first conductor 130. In one embodiment, for example, the second conductor 160 can be formed according to reference... Figures 6A to 6E Described process or reference Figures 10A to 10C The process described is used to form it. Therefore, as... Figure 12 As shown, similar to the first conductor 130, the second conductor 160 may not extend to the upper surfaces of the second insulating layer 140 and the third insulating layer 150, but may instead reside only in the second contact hole CNT2 of the second insulating layer 140 and the third contact hole CNT3 of the third insulating layer 150. In embodiments where the process of forming the third insulating layer 150 is omitted as described above, the second conductor 160 may not extend to the upper surface of the second insulating layer 140, but may instead reside only in the second contact hole CNT2 of the second insulating layer 140.

[0220] The second conductor 160 may include a side portion 160s that contacts the inner wall of contact holes (e.g., second contact hole CNT2 and third contact hole CNT3) of the second insulating layer 140 and the third insulating layer 150, and a lower portion 160b that contacts the first conductor 130. The lower portion 160b of the second conductor 160 may contact the upper surface of each of the first conductor 130 and the inorganic filler 1400.

[0221] The second conductor 160 may not extend to the upper surface of the insulating layer corresponding to the contact hole in which the second conductor 160 is located. In one embodiment, for example, as Figure 12 As shown, the second conductor 160 is located in the second contact hole CNT2 of the second insulating layer 140 and the third contact hole CNT3 of the third insulating layer 150. The second conductor 160 may not extend to the upper surface of the third insulating layer 150. In another embodiment, the third insulating layer 150 may be omitted, and in such an embodiment, the second conductor 160 may be arranged together with inorganic filler (hereinafter, as opposed to inorganic filler 1400, referred to as upper inorganic filler 1700) in the second contact hole CNT2, which serves as a contact hole of the second insulating layer 140.

[0222] The inorganic packing 1700 can be used with Figures 6F to 6I or Figure 6F and Figure 6I The same process is used to form it. The upper inorganic filler 1700 may include the same material as the fourth insulating layer 170. The upper inorganic filler 1700 and the fourth insulating layer 170 may include inorganic insulating materials such as silicon oxynitride, silicon nitride, and / or silicon oxide.

[0223] The third conductor 180 may contact the upper surface of each of the second conductor 160 and the upper inorganic filler 1700. The third conductor 180 may be formed after the contact hole (e.g., fourth contact hole CNT4) of the fourth insulating layer 170 is formed, and the third conductor 180 may include at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure including the above materials.

[0224] Figure 13 This is a perspective view illustrating an electronic device including a display panel according to one embodiment.

[0225] refer to Figure 13 Embodiments of electronic devices including display panels according to the above embodiments may include not only electronic devices for displaying images, such as smartphones (or mobile phones) 1a, tablet PCs 1b, laptop computers 1c, televisions (TVs) 1d, or desktop monitors 1e, but also wearable electronic devices including display modules, such as smart glasses 1f, head-mounted displays 1g, or smartwatches 1h, and vehicle electronic devices 1i including display modules, such as central information displays (CIDs) arranged in a navigation system, dashboard, central instrument panel, or dashboard of a car, or rearview mirror displays.

[0226] According to one embodiment of the present disclosure, a method for manufacturing a high-resolution display panel, a display panel, and an electronic device may be provided that can minimize the area used for contact while simplifying the manufacturing process.

[0227] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and that they will fully convey the inventive concept to those skilled in the art.

[0228] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display panel, comprising: substrate; Light-emitting diodes are arranged above the substrate; as well as A circuit layer is disposed between the substrate and the light-emitting diode. The circuit layer includes an interconnect structure. The interconnection structure includes: A first conductive material layer is disposed above the substrate; A first insulating layer is disposed above the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap with a portion of the upper surface of the first conductive material layer; The first conductor includes a side portion and a lower portion, wherein the side portion is on the inner wall of the first insulating layer defining the first contact hole, and the lower portion is integrally formed with the side portion as a single, inseparable part and directly contacts a portion of the upper surface of the first conductive material layer; An inorganic filler is disposed in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler comprises an inorganic insulating material; A second insulating layer is disposed above the first insulating layer, wherein a second contact hole is defined in the second insulating layer to overlap with the first contact hole; and The second conductor directly contacts the upper surface of the side portion of the first conductor through the second contact hole of the second insulating layer.

2. The display panel according to claim 1, wherein, The second insulating layer comprises an inorganic insulating material, and The inorganic insulating material of the second insulating layer is the same as the inorganic insulating material of the inorganic filler.

3. The display panel according to claim 1, wherein, The side portion of the first conductor is in direct contact with the inner wall of the first insulating layer, and The first point where the side portion of the first conductor and the inner wall of the first insulating layer contact each other is spaced apart by a first distance along the inner wall and the second point where the inner wall of the first insulating layer and the upper surface of the first insulating layer intersect each other.

4. The display panel according to claim 1, wherein, The upper surface of the side portion of the first conductor lies on an imaginary plane parallel to the upper surface of the substrate.

5. The display panel according to claim 1, wherein, The upper surface of the side portion of the first conductor is inclined relative to an imaginary plane parallel to the upper surface of the substrate.

6. The display panel according to claim 1, wherein, The second conductor is in direct contact with the upper surface of the inorganic filler.

7. The display panel according to claim 1, further comprising: The third insulating layer is located above the second insulating layer. The third contact hole is defined in the third insulating layer to overlap with the second contact hole.

8. The display panel according to claim 1, wherein, The first conductor includes: A first conductor includes a first side portion and a first lower portion, wherein the first side portion directly contacts the inner wall of the first insulating layer defining the first contact hole, and the first lower portion is integrally formed with the first side portion as a single, inseparable part and directly contacts a portion of the upper surface of the first conductive material layer; and The second first conductor includes a second side portion and a second lower portion, the second side portion directly contacting the first side portion of the first first conductor, and the second lower portion directly contacting the first lower portion. The inorganic filler is surrounded by the second side portion of the second first conductor.

9. The display panel according to claim 1, wherein, The circuit layer further includes: A transistor, disposed above the substrate, wherein the transistor includes a semiconductor layer and a gate electrode; and A capacitor includes a first electrode and a second electrode that overlap each other. The first conductive material layer defines one of the semiconductor layer, the gate electrode, the first electrode, and the second electrode.

10. The display panel according to claim 1, wherein, The contact area between the second conductor and the first conductor has a closed-loop shape in the plan view.

11. The display panel according to claim 1, wherein, The width of the upper portion of the first contact hole, measured by the point where the upper surface of the first insulating layer and the inner wall intersect each other, is greater than the width of the upper surface of the inorganic filler, and less than the width of the lower portion of the second contact hole, measured by the point where the inner wall of the second insulating layer and the upper surface of the first insulating layer intersect each other.

12. An electronic device, comprising: The display panel includes a substrate, light-emitting diodes disposed above the substrate, and a circuit layer disposed between the substrate and the light-emitting diodes; as well as The lower cover supports the display panel. The circuit layer includes: A first conductive material layer is disposed above the substrate; A first insulating layer is disposed above the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap with a portion of the upper surface of the first conductive material layer; The first conductor includes a side portion and a lower portion, wherein the side portion is on the inner wall of the first insulating layer defining the first contact hole, and the lower portion is integrally formed with the side portion as a single, inseparable part and directly contacts a portion of the upper surface of the first conductive material layer; An inorganic filler is disposed in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler comprises an inorganic insulating material; A second insulating layer is disposed above the first insulating layer, wherein a second contact hole is defined in the second insulating layer to overlap with the first contact hole; and The second conductor directly contacts the upper surface of the side portion of the first conductor through the second contact hole of the second insulating layer.

13. The electronic device according to claim 12, wherein, The second insulating layer comprises an inorganic insulating material, and The inorganic insulating material of the second insulating layer is the same as the inorganic insulating material of the inorganic filler.

14. The electronic device according to claim 12, wherein, The side portion of the first conductor is in direct contact with the inner wall of the first insulating layer, and The first point where the side portion of the first conductor and the inner wall of the first insulating layer contact each other is spaced apart by a first distance along the inner wall and the second point where the inner wall of the first insulating layer and the upper surface of the first insulating layer intersect each other.

15. The electronic device according to claim 12, wherein, The upper surface of the side portion of the first conductor lies on an imaginary plane parallel to the upper surface of the substrate.

16. The electronic device according to claim 12, wherein, The upper surface of the side portion of the first conductor is inclined relative to an imaginary plane parallel to the upper surface of the substrate.

17. The electronic device according to claim 12, wherein, The circuit layer further includes: A transistor, disposed above the substrate, wherein the transistor includes a semiconductor layer and a gate electrode; and A capacitor includes a first electrode and a second electrode that overlap each other. The first conductive material layer defines one of the semiconductor layer, the gate electrode, the first electrode, and the second electrode.

18. An electronic device comprising a display panel having a resolution of 1500 ppi or higher. in, The display panel includes a substrate, light-emitting diodes disposed above the substrate, and a circuit layer disposed between the substrate and the light-emitting diodes. The circuit layer includes an interconnect structure. The interconnection structure includes: A first conductive material layer is disposed above the substrate; A first insulating layer is disposed above the first conductive material layer, wherein a first contact hole is defined in the first insulating layer to overlap with a portion of the upper surface of the first conductive material layer; A first conductor, electrically connected to the first conductive material layer, is disposed in the first contact hole and has a closed-loop shape in a plan view; A second insulating layer is disposed above the first insulating layer, wherein the second contact hole is defined in the second insulating layer; and The second conductor directly contacts at least a portion of the first conductor through the second contact hole in the second insulating layer. The contact area between the second conductor and the first conductor is 0.039 μm. 2 ~3.11μm 2 Within the range.

19. The electronic device according to claim 18, wherein, The first conductor includes: Side portion, on the inner wall of the first insulating layer defining the first contact hole; and The lower part, integrally formed with the side portion as a single, inseparable unit, and directly contacts a portion of the upper surface of the first conductive material layer, and The interconnection structure further includes an inorganic filler disposed in a recess surrounded by the side portion of the first conductor in the first contact hole, wherein the inorganic filler comprises an inorganic insulating material.

20. The electronic device according to claim 19, wherein, The side portion of the first conductor is in direct contact with the inner wall of the first insulating layer, and The first point where the side portion of the first conductor and the inner wall of the first insulating layer contact each other is spaced apart by a first distance along the inner wall and the second point where the inner wall of the first insulating layer and the upper surface of the first insulating layer intersect each other.

21. The electronic device according to claim 19, wherein, The upper surface of the side portion of the first conductor lies on an imaginary plane parallel to the upper surface of the substrate.

22. The electronic device according to claim 19, wherein, The upper surface of the side portion of the first conductor is inclined relative to an imaginary plane parallel to the upper surface of the substrate.

23. The electronic device according to claim 19, wherein, The second insulating layer comprises an inorganic insulating material, and The inorganic insulating material of the second insulating layer is the same as the inorganic insulating material of the inorganic filler.

24. The electronic device according to claim 18, wherein, The circuit layer further includes: A transistor, disposed above the substrate, wherein the transistor includes a semiconductor layer and a gate electrode; and A capacitor includes a first electrode and a second electrode that overlap each other. The first conductive material layer defines one of the semiconductor layer, the gate electrode, the first electrode, and the second electrode.

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