Electronic device and method of manufacturing the same

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, a bonding element, a first electronic unit, a conductive element, a circuit structure, and a connection element. The substrate includes a first surface and a second surface opposite to each other in a first direction, wherein the substrate includes a recess and a through-hole passing through the first surface and the second surface. The bonding element is disposed in the recess. The first electronic unit is disposed in the recess and bonded to the substrate by the bonding element. The conductive element is disposed in the through-hole and electrically connected to the first electronic unit. The circuit structure is disposed on the first surface of the substrate and electrically connected to the first electronic unit and the conductive element. The connection element is disposed on the conductive element, wherein a reflow temperature of the bonding element is higher than a reflow temperature of the connection element.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method for manufacturing the same, and more particularly to an electronic device with good reliability and a method for manufacturing the same. Background Technology

[0002] In current semiconductor packaging technology, mounting electronic units with different functions on the same substrate is one way to improve the performance of electronic devices. However, as electronic devices continue to be developed towards lighter, thinner, shorter, and smaller sizes, and as users' performance requirements for electronic devices continue to increase, the density of electronic units mounted on the aforementioned substrates is also increasing. This makes the alignment margin of electronic units more stringent, and the aspect ratio of the vias penetrating the substrate is also constantly increasing. As a result, the reliability of conductive components formed within the vias may be difficult to meet current or future requirements.

[0003] Accordingly, those skilled in the art continue to improve the reliability of electronic devices. Summary of the Invention

[0004] This disclosure provides an electronic device and a method for manufacturing the same, which helps to improve the reliability of the electronic device.

[0005] According to embodiments of this disclosure, an electronic device includes a substrate, a bonding element, a first electronic unit, a conductive element, a circuit structure, and a connecting element. The substrate includes a first surface and a second surface opposite to each other in a first direction, wherein the substrate includes a groove extending from the first surface into the substrate and a through-hole penetrating the first and second surfaces. The bonding element is disposed in the groove. The first electronic unit is disposed in the groove and bonded to the substrate by the bonding element. The conductive element is disposed in the through-hole and electrically connected to the first electronic unit. The circuit structure is disposed on the first surface of the substrate and electrically connects the first electronic unit and the conductive element. The connecting element is disposed on the conductive element, wherein the reflow soldering temperature of the bonding element is higher than the reflow soldering temperature of the connecting element.

[0006] According to embodiments of the present disclosure, a method for manufacturing an electronic device includes: providing a substrate, wherein the substrate includes a first surface and a second surface opposite to each other in a first direction, and includes a groove extending from the first surface into the substrate and a through hole penetrating the first surface and the second surface; providing a bonding element in the groove; providing a first electronic unit on the bonding element such that the first electronic unit is bonded to the substrate via the bonding element; providing a conductive element in the through hole; and providing a connection element on the conductive element, wherein the reflow temperature of the bonding element is higher than the reflow temperature of the connection element.

[0007] Based on the above, in the electronic device and manufacturing method of the present disclosure, the reflow soldering temperature of the bonding element is designed to be higher than that of the connecting element. In this way, when the connecting element is subsequently reflow soldered, the bonding element is less likely to be affected by the reflow soldering process, thereby improving the reliability of the bonding element bonding the first electronic unit to the substrate.

[0008] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are included to further illustrate this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0010] Figure 1 This is a cross-sectional schematic diagram of an electronic device according to a first embodiment of the present disclosure;

[0011] Figure 2 This is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present disclosure;

[0012] Figure 3 This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0013] Figure 4 This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to another embodiment of the present disclosure;

[0014] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to a third embodiment of the present disclosure;

[0015] Figure 6 and Figure 7 This is a cross-sectional schematic diagram of a method for manufacturing a first electronic unit according to different embodiments of the present disclosure;

[0016] Figure 8A and Figure 8B This is a top view schematic diagram of a first electronic unit according to different embodiments of the present disclosure;

[0017] Figure 9A and Figure 9B These are cross-sectional schematic diagrams of the first electronic unit according to different embodiments of the present disclosure; and

[0018] Figure 10 This is a cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. Detailed Implementation

[0019] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure show only a portion of the packaging structure, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. For example, for clarity, the relative dimensions, thicknesses, and positions of various film layers, regions, and / or structures may be reduced or enlarged.

[0020] Certain terms are used throughout this specification and the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "having" and "comprising" are open-ended terms and should therefore be interpreted as meaning "including but not limited to...".

[0021] In this document, the phrase "one element is disposed on another element" is used to conveniently describe the relative position between the element and the other element, and is not intended to define the process steps or sequence of the element and the other element.

[0022] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting this disclosure. It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, the element or membrane may be directly on or directly connected to the other element or membrane, or there may be an inserted element or membrane between them (in a non-direct case). Conversely, when an element or membrane is referred to as being "directly" on or "directly connected" to another element or membrane, there is no inserted element or membrane between them. Furthermore, when an element or membrane is referred to as overlapping another element, the element or membrane at least partially overlaps with the other element or membrane.

[0023] The terms “about,” “approximately,” “substantially,” or “roughly” used in this document generally mean falling within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Furthermore, the phrases “given range is from a first value to a second value” or “given range falls within the range of a first value to a second value” indicate that the given range includes the first value, the second value, and other values ​​in between.

[0024] In some embodiments of this disclosure, terms such as “connection” and “interconnection”, unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, wherein another structure is disposed between the two structures. Terms such as “connection” and “interconnection” may also include situations where both structures are movable or both structures are fixed. Furthermore, the terms “electrical connection” and “coupling” encompass any direct and indirect electrical connection means.

[0025] In the following embodiments, the same or similar elements will be referred to by the same or similar reference numerals, and their descriptions will be omitted. Furthermore, features in different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it, and simple equivalent changes and modifications made in accordance with this specification or claims are still within the scope of this disclosure. That is, the embodiments described below can be completed by replacing, recombining, or mixing technical features in several different embodiments without departing from the spirit of this disclosure. In addition, the terms "first," "second," etc., mentioned in this specification or claims are only used to name different elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor are they used to limit the manufacturing order or installation order of the elements.

[0026] In some embodiments of this disclosure, the thickness, length, and width may be measured using an optical microscope (OM), or the thickness or width may be measured from a cross-sectional image in an electron microscope, but this is not a limitation.

[0027] In some embodiments of this disclosure, surface roughness can be observed using electron microscopes such as scanning electron microscopes (SEM) and transmission electron microscopes (TEM) at appropriate magnification, and the undulations can be compared at unit lengths (e.g., 10 μm). In some embodiments, the peaks and valleys of the surface undulations have a distance difference of 0.15 μm to 1 μm. Appropriate magnification means that at least one surface can show at least 10 peaks of undulation roughness or average roughness in the field of view at this magnification. Each film layer shown in the accompanying drawings of this disclosure can be a rough surface. It is worth noting that the rough surface of each film layer can refer to the high and low undulations of the surface of each film layer as observed by electron microscopy in a cross-sectional view.

[0028] The manufacturing process of the electronic device disclosed herein can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, and can be chip-first or chip-last RDL first. The electronic device described herein can be applied to high-speed computing modules, power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, silicon photonics co-package devices, sensing devices, or splicing devices, but is not limited thereto.

[0029] The following examples illustrate exemplary embodiments of this disclosure, and the same element symbols are used in the drawings and description to denote the same or similar parts.

[0030] Figure 1 This is a cross-sectional schematic diagram of an electronic device according to a first embodiment of the present disclosure.

[0031] Please refer to Figure 1 The electronic device 10 includes a substrate 100, a first electronic unit EU1, a bonding element BE1, a conductive element 110, and a connecting element CE1.

[0032] The substrate 100 may comprise polyimide, glass, silicon, or other suitable substrate materials. In some embodiments, the substrate 100 may be a glass substrate comprising glass. In some embodiments, the thickness of the substrate 100 in a first direction (e.g., the Z direction) may range from 50 μm to 1000 μm. The coefficient of thermal expansion (CTE) of the substrate 100 may range from 2 ppm / °C to 10 ppm / °C. This design mitigates the risk of warpage that may occur when subsequent components are formed on the substrate 100.

[0033] In this embodiment, the substrate 100 includes a first surface 100s1 and a second surface 100s2 opposite to each other in a first direction. The substrate 100 includes a groove 100c extending from the first surface 100s1 into the substrate 100 and through holes 100tv penetrating the first surface 100s1 and the second surface 100s2. In this embodiment, the groove 100c may be disposed between the through holes 100tv. In some embodiments, the substrate 100 may include a mark 100m for alignment or tracking. For example, the mark 100m may be an alignment mark or a tracking mark.

[0034] In some embodiments, the through-hole 100tv of the substrate 100 can be formed by drilling, etching, or a combination thereof on the substrate 100. For example, a laser drilling process can be performed on a first surface 100s1 and a second surface 100s2 of the substrate 100 that are opposite each other in a first direction (e.g., the Z direction) to form a through-hole 100tv through the substrate 100, or a laser drilling process can be performed from at least one surface of the substrate 100 to form a through-hole 100tv through the substrate 100, but this is not a limitation. In other embodiments, a modification process (e.g., laser modification process) and an etching process can be performed on at least one surface of the substrate 100 to form the through-hole 100tv in the substrate 100. In some embodiments, the etching process can include acid etching, alkaline etching, or a combination thereof. In some embodiments, the extension line of the sidewall of the through-hole 100tv has an angle θ with the substrate 100 in its first direction (e.g., the Z direction), and the angle θ can be greater than or equal to 0 degrees and less than or equal to 20 degrees. In some embodiments, the sidewall of the perforation 100tv may have a first roughness, and the first surface 100s1 and the second surface 100s2 of the substrate 100 may have a second roughness and a third roughness, respectively, wherein the first roughness may be less than the second roughness and the third roughness. Through the above design, the skin effect of the electronic device 10 can be reduced, but is not limited thereto.

[0035] The first electronic unit EU1 is disposed in the recess 100c. In this embodiment, the first electronic unit EU1 may include a base layer 130 and a bonding pad 130p. The electronic unit may be, for example, a known good die (KGD), a diode, an antenna unit, a sensor, a structure formed by semiconductor-related processes, or a component of a structure formed by semiconductor-related processes disposed on a base layer (e.g., a base layer containing a substrate material such as polyimide, glass, or silicon substrate), but is not limited thereto. The bonding pad 130p may include any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), tungsten (W), nickel (Ni), tantalum (Ta), nitrides, carbides, other suitable metals, or alloys thereof, or combinations thereof. In some embodiments, the bonding pad 130p may include a multilayer structure. For example, the bonding pad 130p may include a seed layer and a conductive layer formed on the seed layer. The seed layer can be formed, for example, by chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), other suitable deposition methods, or combinations thereof. The conductive layer can be formed, for example, by growing the seed layer through an electroplating process.

[0036] In this embodiment, the base layer 130 may include a first side (e.g., a front side) on which a connection pad for transmitting signals is disposed, and a second side (e.g., a back side) opposite to the first side in a first direction (e.g., the Z direction), wherein the bonding pad 130p is disposed on the second side of the base layer 130. In some embodiments, the connection pad for transmitting signals may be, for example, an input / output pad (I / O pad). In some embodiments, the bonding pad 130p may be electrically insulated from the input / output pad. In this embodiment, the bonding pad 130p may be embedded in the base layer 130 and include a surface exposed on the second side of the base layer 130. In some embodiments, in a second direction perpendicular to the first direction (e.g., the X direction), the width W1 of the base layer 130 on the first side (e.g., the front side) may be greater than the width W2 of the base layer 130 on the second side (e.g., the back side), which may help improve the reliability of the electronic device 10.

[0037] A bonding element BE1 is disposed in a recess 100c and bonds the first electronic unit EU1 to the substrate 100. The bonding element BE1 may include solder with a surface tension capable of supporting the first electronic unit EU1. For example, the bonding element BE1 may include tin (Sn), copper (Cu), silver (Ag), other metal alloys, or combinations thereof. In this embodiment, the bonding element BE1 may be a solder ball, such as a solder ball or other suitable bonding element, but is not limited thereto. The coefficient of thermal expansion of the bonding element BE1 may be greater than or equal to 10 ppm / °C and less than or equal to 25 ppm / °C. The modulus of elasticity of the bonding element BE1 may be greater than or equal to 30 GPa and less than or equal to 130 GPa, or greater than or equal to 50 GPa and less than or equal to 110 GPa, or greater than or equal to 70 GPa and less than or equal to 90 GPa. According to some embodiments, the ratio of the coefficient of thermal expansion of the bonding element BE1 to the coefficient of thermal expansion of the first electronic unit EU1 may be greater than or equal to 1.5 and less than or equal to 5. This design can improve the bonding quality of the first electronic unit EU1, but is not limited thereto.

[0038] According to some embodiments, a bonding element BE1' may be disposed in the groove 100d and bond the first electronic unit EU1 to the substrate 100. The bonding element BE1' and the bonding element BE1 may be made of the same or different materials. Furthermore, the bonding element BE1' and the bonding element BE1 may have the same or different dimensions. For example, in the Z direction, the depth of the groove 100c (i.e., Figure 1 The first distance D1 shown is related to the depth of the groove 100d (i.e., Figure 1The second distance D2 shown may be the same or different, and the height of the first electronic unit EU1 in groove 100c may be the same or different from the height of the first electronic unit EU1 in groove 100d. For example, when the depth of groove 100c (i.e., the first distance D1) is different from the depth of groove 100d (i.e., the second distance D2), different sizes of bonding elements can be selected. That is, appropriate bonding elements should be selected according to the design to keep the design flexible.

[0039] A conductive element 110 is disposed in a through-hole 100tv. In this embodiment, the conductive element 110 may include a seed layer 110a and a conductive layer 110b disposed on the seed layer 110a. The seed layer 110a may be disposed on the sidewall of the through-hole 100tv, or the seed layer 110a may be disposed on at least a portion of the first surface 100s1 and at least a portion of the second surface 100s2 of the substrate 100 and extend into the through-hole 100tv. In some embodiments, the seed layer 110a may be formed, for example, by chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), other suitable deposition methods, or combinations thereof. The seed layer 110a may include any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), tungsten (W), nickel (Ni), tantalum (Ta), nitrides, carbides, other suitable metals, or alloys thereof, or combinations thereof. In some embodiments, the seed layer 110a may be in direct contact with the substrate 100. In some embodiments, the conductive layer 110b may be formed, for example, by electroplating, chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), resistance heating evaporation, electron beam evaporation, other suitable deposition methods, or combinations thereof, but is not limited thereto. The conductive layer 110b may include a conductive material such as copper (Cu). In some embodiments, the conductive layer 110b may be formed by growing a seed layer 110a through an electroplating process.

[0040] The connecting element CE1 is disposed on the conductive element 110. In this embodiment, the reflow temperature of the bonding element BE1 is higher than that of the connecting element CE1. This reduces the impact of the reflow process on the bonding element CE1 during subsequent reflow soldering processes, and may decrease the formation of brittle materials, thereby improving the reliability of the bonding element BE1 in bonding the first electronic unit EU1 to the substrate 100. However, this is not a limitation. In some embodiments, the connecting element CE1 may include solder balls. In some embodiments, the connecting element CE1 may include a conductive material with a reflow temperature lower than that of the bonding element BE1, such as tin, nickel, copper, other metal alloys, other suitable materials, or combinations thereof. In some embodiments, the coefficient of thermal expansion of the connecting element CE1 may be greater than or equal to 20 ppm / ℃ and less than or equal to 30 ppm / ℃, and the elastic modulus of the connecting element CE1 may be greater than or equal to 20 GPa and less than or equal to 40 GPa. According to some embodiments, the coefficient of thermal expansion of the bonding element BE1 may be less than that of the connecting element CE1, wherein the ratio of the coefficient of thermal expansion of the connecting element CE1 to that of the bonding element BE1 may be greater than or equal to 1.2 and less than or equal to 3. This design improves the reliability of the electronic device 10.

[0041] In some embodiments, the electronic device 10 may further include a bonding pad 120. In this embodiment, the bonding pad 120 may be disposed on the bottom surface of the recess 100c, wherein a bonding element BE1 may be disposed between the first electronic unit EU1 and the bonding pad 120, and in a first direction (e.g., the Z direction), the bonding element BE1 overlaps with the bonding pad 130p of the first electronic unit EU1. In this embodiment, based on factors of surface energy and wetting ability, the bonding element BE1 tends to adhere to surfaces with good wetting ability and / or high surface energy during reflow soldering. For example, metal surfaces such as copper, nickel, and gold have good wetting ability and high surface energy compared to insulating surfaces of polymer materials. Therefore, when the first electronic unit EU1 is placed on the bonding element BE1 and a reflow soldering process is performed, the first electronic unit EU1 can, based on the above factors, align the bonding pad 130p of the first electronic unit EU1 with the bonding pad 120 disposed on the bottom surface of the recess 100c via the bonding element BE1. In other words, the first electronic unit EU1 can achieve self-alignment through the arrangement of the bonding element BE1 and the bonding pad 120, which helps to improve the reliability of the electronic device 10.

[0042] In some embodiments, the electronic device 10 may further include a circuit structure CS1. In this embodiment, the circuit structure CS1 may be disposed on a first surface 100s1 of the substrate 100. The circuit structure CS1 may include an insulating layer IL1 formed on the substrate 100 and a wiring structure WS1 formed in the insulating layer IL1, wherein the wiring structure WS1 may be electrically connected to the first electronic unit EU1 and the conductive element 110. The circuit structure CS1 may include at least one insulating layer and at least one conductive layer to allow for wiring redistribution and / or further increase the fan-out area of ​​the lines, or different electronic units may be electrically connected to each other through the circuit structure CS1. Alternatively, the circuit structure CS1 may be a substrate used as an electrical interface wiring between one line and another line. The purpose of the circuit structure CS1 is to extend the interconnect to a wider spacing or to redistribute the interconnect to another interconnect with a different spacing. In other words, the circuit structure CS1 herein may also be a redistribution layer / structure. The circuit structure herein or hereinafter may be electrically connected to each chip or electronic unit by connecting elements or other bonding elements. The steps for forming the circuit structure CS1 may include thermal processing, deposition processing, oxidation processing, annealing processing, surface treatment, or other processes.

[0043] The insulating layer IL1 may include a plurality of insulating layers alternately stacked along a first direction (e.g., the Z direction). In this embodiment, the insulating layer IL1 may include a filled insulating layer that fills the recess 100c and surrounds the first electronic unit EU1. In this embodiment, "one element surrounding another element" may mean that the element can at least contact the side surface of the other element in a cross-sectional view. For example, such as Figure 1 As shown, the filling insulating layer can contact the side surface of the first electronic unit EU1. In some embodiments, the material of the filling insulating layer surrounding the first electronic unit EU1 in the insulating layer IL1 may be different from the material of the insulating layer surrounding the wiring structure WS1 in the insulating layer IL1, but this disclosure is not limited thereto. The wiring structure WS1 may include a plurality of conductive patterns formed in the insulating layer IL1 and alternately stacked along the Z direction, and conductive vias connecting the conductive patterns.

[0044] The insulating layer IL1 may comprise organic or inorganic materials. Organic materials include, but are not limited to, polyimide (PI), poly-p-xylylene (also known as Parylene), benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials. The wiring structure WS1 may comprise any suitable conductive material, such as copper, titanium, nickel, combinations or alloys of the above materials.

[0045] In some embodiments, the electronic device 10 may further include a second electronic unit EU2. In this embodiment, the second electronic unit EU2 may be provided on a circuit structure CS1 and electrically connected to the first electronic unit EU1 and the conductive element 110 via a wiring structure WS1 of the circuit structure CS1. In this embodiment, the second electronic unit EU2 may include a second electronic element 140 and a connection pad 140p. In some embodiments, the second electronic element 140 may include a die, chip, diode, antenna unit, memory unit, photonic integrated circuit (PIC) unit, sensor, or a structure related to semiconductor processes. In some embodiments, the connection pad 140p may be located on one side of the second electronic element 140. In embodiments where the electronic element is a chip, the side with the connection pad 140p is the front side of the chip (also referred to as the active side in some embodiments), and the other side opposite the front side of the chip is the back side (also referred to as the passive side in some embodiments). In this embodiment, the second electronic unit EU2 may be different from the first electronic unit EU1. The connecting pad 140p may include any suitable conductive material, such as copper (Cu), aluminum (Al), nickel (Ni), molybdenum (Mo), titanium (Ti), alloys or combinations of the above materials, or other suitable materials, but not limited thereto.

[0046] In some embodiments, the electronic device 10 may further include an encapsulation layer ML1. The encapsulation layer ML1 can prevent the first electronic unit EU1 and / or the second electronic unit EU2 from being affected by external moisture, thereby improving the reliability of the electronic device 10. The encapsulation layer ML1 may include any suitable encapsulation material, such as epoxy molding compound (EMC), but is not limited thereto.

[0047] Figure 2 This is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present disclosure. Figure 2 The electronic device 12 shown is Figure 1The electronic device 12 is similar to the electronic device 10, but the main difference is that the substrate 100' of the electronic device 12 is different from the substrate 100 of the electronic device 10. Other identical or similar components are represented by the same or similar component symbols, which will not be repeated here.

[0048] Please refer to Figure 2 The substrate 100' of the electronic device 12 may include a first substrate 100a, a second substrate 100b, and a dielectric layer DL1 between the first substrate 100a and the second substrate 100b. The substrate 100' may include a first surface 100's1 and a second surface 100's2 opposite to each other in the Z direction, wherein the top surface of the first substrate 100a may correspond to the first surface 100's1 of the substrate 100', and the bottom surface of the second substrate 100b may correspond to the second surface 100's2 of the substrate 100'. In this embodiment, the first substrate 100a and the second substrate 100b may include the same or different materials. In this embodiment, the coefficients of thermal expansion of the first substrate 100a and the second substrate 100b may be the same or different. For example, the coefficient of thermal expansion of the first substrate 100a may be less than that of the second substrate 100b. In this embodiment, the rigidity of the first substrate 100a and the second substrate 100b may be the same or different. For example, the rigidity of the first substrate 100a may be less than that of the second substrate 100b. In this embodiment, the warping trends of the first substrate 100a and the second substrate 100b may be the same or different. For example, the warping trend of the first substrate 100a may be opposite to that of the second substrate 100b, wherein the outer side of the substrate warps upward along a first direction or downward along a first direction. The dielectric layer DL1 may include any suitable organic or inorganic material as described above. For example, the dielectric layer DL1 may include silicon, silicon oxide, silicon-based materials, or silicon-based mixtures. In this embodiment, the dielectric layer DL1 may be disposed on the bottom surface of the first substrate 100a and bonded to the second substrate 100b by a hybrid bonding method. For example, at the bonding interface IF1, the first portion of the conductive layer 110b disposed in the first substrate 100a and the second portion of the conductive layer 110b disposed in the second substrate 100b are metal-to-metal bonded, while the portion of the dielectric layer DL1 in contact with the second substrate 100b is oxide-to-oxide bonded. In this embodiment, the thickness of the first substrate 100a in the Z direction may be greater than the thickness of the second substrate 100b in the Z direction.

[0049] Figure 3 This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 4This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to another embodiment of the present disclosure. Figure 3 and Figure 4 Some steps of a method for manufacturing an electronic device are shown in different embodiments of this disclosure.

[0050] Please refer to Figure 1 and Figure 3 The conductive element 110 can be provided in the via 100tv, for example, through the steps shown below. First, a carrier plate Csub1 is provided. The material of the carrier plate Csub1 may include glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, other suitable substrate materials, or combinations thereof, but is not limited thereto. Next, an anti-warping layer WAL1, a release layer RL1, and a seed layer SL1 are sequentially provided on the carrier plate Csub1.

[0051] The anti-warping layer WAL1 can be a single-layer or multi-layer structure comprising organic and / or inorganic materials, wherein the inorganic materials may include silicon dioxide (SiO2), silicon nitride (SixNy), silicon oxynitride (SiOxNy), or other suitable inorganic materials, but this disclosure is not limited thereto. The release layer RL1 can be a temporary bonding layer, which may include a thermally-type or optically-type release material with adhesive properties to temporarily adhere subsequently formed working units, elements, or films to the release layer RL1. In other words, the release layer RL1 can assist in the removal of subsequently formed working units, elements, or films from the carrier substrate Csub1. When a thermally-type release material is used to form the release layer RL1, the thermally-type release material loses its adhesiveness upon heating, allowing the elements or films formed thereon to be peeled off from the release layer RL1. For example, the release layer RL1 can be a thermal release tape (HRT) or a light-to-heat-conversion (LTHC) peel-off coating. When an optical release material is used to form the release layer RL1, the optical release material loses its adhesiveness when exposed to radiation, such as ultraviolet light (UV light), allowing the elements or films formed thereon to be peeled off from the release layer RL1. The seed layer SL1 can comprise any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), tungsten (W), nickel (Ni), tantalum (Ta), nitrides, carbides, other suitable metals, or alloys thereof, or combinations thereof.

[0052] Then, please refer to Figure 3Conductive pillars CP1 are formed above the carrier plate Csub1, with positions corresponding to the through holes 100tv on the substrate 100. Then, the substrate 100 is bonded to the carrier plate Csub1 with the through holes 100tv aligned with the conductive pillars CP1. Afterwards, an electroplating process is performed on the seed layer 110a formed on the surface of the through holes 100tv to form a crystal layer in the through holes 100tv as described above. Figure 1 The conductive element 110 is shown. Since the conductive pillar CP1 is formed on the carrier plate Csub1 before the first electronic unit EU1 is bonded to the substrate 100, the impact of the process of forming the conductive pillar CP1 on the first electronic unit EU1 can be reduced, thereby improving the reliability of the electronic device 10. In this embodiment, before providing the bonding element BE1 in the groove 100c, the bonding pad 120 is provided on the bottom surface of the groove 100c.

[0053] In this embodiment, when the first electronic unit EU1 is provided at the position corresponding to the groove 100c of the substrate 100 on the carrier plate Csub1, the first surface 100s1 of the substrate 100 is bonded to the carrier plate Csub1 by aligning the through hole 100tv with the conductive post CP1 and the groove 100c with the first electronic unit EU1. In some alternative embodiments, such as Figure 4 As shown, when the first electronic unit EU1 has been provided into the groove 100c of the substrate 100, the second surface 100s2 of the substrate 100 is bonded to the carrier plate Csub1.

[0054] In some other embodiments, such as Figure 2 and Figure 3 As shown, after bonding the first surface 100s1 of the substrate 100 to the carrier plate Csub1, another substrate with a thickness less than that of the substrate 100 can be provided on the second surface 100s2 of the substrate 100 as needed to form a substrate similar to... Figure 2 The substrate 100' shown includes a first substrate 100a and a second substrate 100b. In this embodiment, a conductive pillar CP1 (corresponding to...) may be formed in the other substrate. Figure 2 The conductive layer 110b shown is disposed in the first portion of the first substrate 100a. Another conductive pillar (corresponding to...) Figure 2 The conductive layer 110b shown is disposed in the second portion of the second substrate 100b. In some embodiments, another substrate may be bonded to the second surface 100s2 of the substrate 100 in a hybrid bonding manner.

[0055] Figure 5 This is a cross-sectional schematic diagram of an electronic device according to a third embodiment of the present disclosure. Figure 5 The electronic device 14 shown is Figure 1The electronic device 10 shown is similar, but the main difference is that the recess 100c' of the electronic device 14 is different from the recess 100c of the electronic device 10. Other identical or similar components are represented by the same or similar component symbols, which will not be repeated here.

[0056] Please refer to Figure 5 The corner where the bottom surface of the groove 100c' connects to the sidewall may have a chamfering design, and the extension direction of the sidewall may be parallel to the Z direction. In this embodiment, the opposite sidewalls of the groove 100c' in the X direction are respectively separated from the adjacent through-hole 100tv by a first distance D1 and a second distance D2, wherein the ratio of the second distance D2 to the first distance D1 (i.e., D2 / D1) is in the range of 0.6 to 1.5, which helps to reduce the risk of cracks in the substrate 100” during the process of forming the through-hole 100tv.

[0057] Figure 6 and Figure 7 This is a cross-sectional schematic diagram of a method for manufacturing a first electronic unit according to different embodiments of the present disclosure. Figure 8A and Figure 8B This is a top view schematic diagram of a first electronic unit according to different embodiments of the present disclosure.

[0058] Please refer to Figure 6 , Figure 1 The first electronic unit EU1 shown can be formed through the following steps. First, a carrier substrate Csub2 is provided. Next, a release layer RL2 is provided on the carrier substrate Csub2. The carrier substrate Csub2 may include materials listed above as those listed above for the carrier substrate Csub1. The release layer RL2 may include materials listed above as those listed above for the release layer RL1. Then, a wafer comprising a plurality of base layers 130 (in some embodiments, the plurality of base layers 130 may comprise dies) is provided on the release layer RL2, wherein the plurality of base layers 130 may undergo a singulation process along the dicing line SCL1 after subsequent formation of bonding pads 130p to form a plurality of independent first electronic units EU1 (in some embodiments, the first electronic unit EU1 after the singulation process may be referred to as a chip). In this embodiment, the wafer is provided on the release layer RL2 with its front side W1f facing the release layer RL2.

[0059] Subsequently, a plurality of grooves r1 are formed on the back side W1b of the wafer. In some embodiments, the grooves r1 can be formed by performing processes such as laser cutting, sawing, or etching on the back side W1b of the wafer. Then, conductive material is filled into the plurality of grooves r1 to form bonding pads 130p. In this embodiment, the top surface of the bonding pad 130p may be coplanar with the back side W1b of the wafer. In this embodiment, the bonding pad 130p can be formed by the following steps. First, a seed layer in which the plurality of grooves r1 are filled is formed on the back side W1b of the wafer. Next, a conductive layer can be formed by growing the seed layer, for example, by electroplating. Then, a planarization process such as chemical mechanical polishing (CMP) or etchback is performed on the conductive layer and the seed layer to remove the conductive layer and the seed layer on the back side W1b of the wafer, thereby forming the bonding pad 130p in each groove r1.

[0060] In some embodiments, a monomerization process can be performed along the dicing line SCL1 to form a plurality of independent first electronic units EU1. In some embodiments, the monomerization process described above can be used to form... Figure 1 The shape of the base layer 130 shown, for example in the X direction, means that the width W1 of the base layer 130 on the first side (e.g., the front side) may be greater than the width W2 of the base layer 130 on the second side (e.g., the back side). In other embodiments, such as Figure 9A As shown, the base layer 130 can be shaped into a sidewall with a trapezoidal profile through the monomerization process described above. For example, in the X direction, the width W1' of the base layer 130 on the first side (e.g., the front side) can be smaller than the width W2' of the base layer 130 on the second side (e.g., the back side). In this way, the contact area between the sidewall of the base layer 130 and other film layers can be increased, thereby helping to improve the reliability of the electronic device 10.

[0061] In some alternative embodiments, such as Figure 7 As shown, the carrier substrate Csub2' may have space to accommodate a wafer containing multiple base layers 130, which helps to improve the stability of performing the above-described process. In other embodiments, such as Figure 7 As shown, bonding pad 130p' can be formed on the back side W1b of the wafer. In some embodiments, bonding pad 130p' can be formed on the back side W1b of the wafer by the following steps: First, a seed layer is provided on the back side W1b of the wafer. Next, the seed layer is grown to form a conductive layer by an electroplating process. Then, the conductive layer and the seed layer are patterned to form a shape as shown. Figure 7 The bonding pad shown is 130p'.

[0062] In this embodiment, multiple bonding pads 130p can be configured in each base layer 130, and the multiple bonding pads 130p are formed to be mirror-symmetrical in the horizontal direction. Figure 8A and Figure 8B As shown, the multiple bonding pads 130p can be mirror-symmetrical in the X or Y direction (i.e., in the horizontal direction perpendicular to the Z direction), which can help improve the reliability of the electronic device 10.

[0063] Please continue to refer to this. Figure 8A According to some embodiments, the geometric center of the plurality of bonding pads 130p should be close to the geometric center of the first electronic unit EU1. Specifically, the geometric center of the plurality of bonding pads 130p can be the center of a geometric pattern (e.g., a dashed line) formed by connecting the centers of adjacent bonding pads 130p in the X or Y direction. For example, when the geometric pattern (e.g., the dashed line) is rectangular, the geometric center of the plurality of bonding pads 130p is the intersection of the diagonals of that rectangle. That is, the distance between the geometric center of the plurality of bonding pads 130p and the geometric center of the first electronic unit EU1 (e.g., center 130c) should be less than or equal to 10 micrometers, thereby improving the bonding quality.

[0064] Please continue to refer to this. Figure 8B According to some embodiments, the geometric centers of the plurality of bonding pads 130p should be close to the geometric center of the first electronic unit EU1, and the geometric centers of the plurality of bonding pads 130p should be close to the geometric center of another bonding pad 130p' surrounded by the plurality of bonding pads 130p. That is, the distance between the geometric centers of the plurality of bonding pads 130p and the geometric center of the first electronic unit EU1 should be less than or equal to 10 micrometers, and the distance between the geometric centers of the plurality of bonding pads 130p and the geometric center of another bonding pad 130p' should be less than or equal to 10 micrometers, thereby improving the bonding quality.

[0065] Figure 9A and Figure 9B This is a cross-sectional schematic diagram of a first electronic unit according to different embodiments of the present disclosure. Figure 9A The first electronic unit EU1a shown is EU1a and Figure 9B The first electronic unit EU1b shown can correspond to Figure 1 The first electronic unit EU1 is shown.

[0066] Please refer to Figure 9AThe first electronic unit EU1a may include a base layer 132, bonding pads 130p, an insulating layer 134, connecting pads 136, and a wall 138. The base layer 132 may be, for example, a film layer comprising a substrate material such as polyimide, glass, or silicon. In some embodiments, the base layer 132 may include a first side on which an active layer is disposed, and a second side opposite to the first side on which bonding pads 130p are disposed. In this embodiment, bonding pads 130p may be embedded in a recess 132r of the base layer 132, and the active layer may include an insulating layer 134 disposed on the base layer 132, and connecting pads 136 and wall 138 formed in the insulating layer 134. In some alternative embodiments, bonding pads 130p may be disposed on the second side of the base layer 132 (e.g., corresponding to...). Figure 7 (The example shown).

[0067] Insulating layer 134 may comprise any suitable insulating material. Connecting pad 136 may be electrically connected to, for example, Figure 1 The wiring structure WS1 of the circuit structure CS1 shown is illustrated. The connecting pad 136 may comprise any suitable conductive material, such as titanium (Ti), titanium nitride (TiN), tungsten (W), nickel (Ni), tantalum (Ta), nitrides, carbides, other suitable metals, or alloys thereof, or combinations thereof. In some embodiments, the wall 138 may be located at the edge adjacent to the base layer 132 (and...). Figure 6 or Figure 7 The cutting line SCL1 shown is located near the edge of the active layer, which helps to reduce the risk of delamination of the active layer during the monomerization process. The wall 138 may include any suitable material. In some embodiments, the base layer 132 has a chamfer 132c on one edge adjacent to the active layer.

[0068] In some embodiments, such as Figure 9B As shown, the base layer 132' of the first electronic unit EU1b may include a first portion 132a and a second portion 132b on the first portion 132a, wherein the second portion 132b has a chamfer 132c on one edge adjacent to the active layer. In this embodiment, the surface roughness of the sidewall of the first portion 132a may be less than the surface roughness of the sidewall of the second portion 132b. In this embodiment, the ratio of the height H2 of the second portion 132b to the height H1 of the first portion 132a (i.e., H2 / H1) is in the range of 0.8 to 3, which helps to improve the adhesion between the base layer 132' and other film layers.

[0069] Figure 10 This is a cross-sectional schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. Figure 10 The electronic device 20 shown is Figure 1Similar to the illustrated electronic device 10, the main difference lies in that the bonding pad 220 of the electronic device 20 is embedded in the substrate 100 below the bottom surface of the recess 100c and includes a buffer layer BL1 and a circuit structure CS2. In other words, the upper surface of the bonding pad 220 adjacent to the bottom surface of the first electronic unit EU1 is substantially coplanar with the bottom surface of the recess 100c, which helps to further improve the reliability of the electronic device 20. Other identical or similar components are indicated by identical or similar component symbols and will not be repeated here.

[0070] In this embodiment, the circuit structure CS2 may be disposed on the second surface 100s2 of the substrate 100. The circuit structure CS2 may include an insulating layer IL2 formed on the substrate 100 and a wiring structure WS2 formed in the insulating layer IL2, wherein the wiring structure WS2 may be electrically connected to the conductive element 110. The circuit structure CS2 may include at least one insulating layer and at least one conductive layer to allow for circuit redistribution and / or further increase the fan-out area of ​​the circuit, or different electronic units may be electrically connected to each other through the circuit structure CS2. Alternatively, the circuit structure CS2 may be a substrate used as an electrical interface wiring between one line and another line. The purpose of the circuit structure CS2 is to extend the interconnect to a wider spacing or to redistribute the interconnect to another interconnect with a different spacing. In other words, the circuit structure CS2 in this document may also be a redistribution layer / structure. The circuit structure described herein or below may be electrically connected to each chip or electronic unit by connecting elements or other bonding elements. The steps for forming the circuit structure CS2 may include thermal processing, deposition processing, oxidation processing, annealing processing, surface treatment, or other processes. The insulating layer IL2 may include a plurality of insulating layers alternately stacked along a first direction (e.g., the Z direction). The wiring structure WS2 may include a plurality of conductive patterns formed in the insulating layer IL2 and alternately stacked along the Z direction, and conductive vias connecting the conductive patterns.

[0071] Insulating layer IL2 may, for example, contain insulating materials as listed in insulating layer IL1 above, but is not limited thereto. Wiring structure WS2 may, for example, contain conductive materials as listed in wiring structure WS1 above, but is not limited thereto.

[0072] In this embodiment, the buffer layer BL1 may be disposed on the first surface 100s1 and the second surface 100s2 of the substrate 100 and extend to the sidewalls of the perforation 100tv, which can help mitigate stress-induced cracking of the substrate 100, but is not limited thereto. For example, the buffer layer BL1 can repair defects (e.g., microcracks) generated when the perforation 100tv is formed in the substrate 100 by the aforementioned modification process (e.g., laser modification process) and etching process. In other embodiments, such as when the substrate 100 is a glass substrate, the buffer layer BL1 can mitigate the difference in coefficient of thermal expansion (CTE) between the substrate 100 and the conductive element 110 subsequently formed in the perforation 100tv, thereby improving the adhesion of the conductive element 110 formed in the perforation 100tv or mitigating the stress applied to the substrate 100. In this embodiment, the buffer layer BL1 is at least disposed on the sidewalls of the perforation 100tv and extends to the first surface 100s1 and the second surface 100s2 of the substrate 100.

[0073] The buffer layer BL1 may include materials such as polyimide (PI), parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), oxides, other suitable materials, or combinations thereof. That is, the buffer layer BL1 may comprise a single layer or multiple layers stacked together. When the buffer layer BL1 is a multiple layer stack, it may be a stack of organic materials, a stack of inorganic materials, or a mixed stack of organic and inorganic materials.

[0074] The following will be through Figure 1 To illustrate the manufacturing method of the electronic device 10 disclosed herein, but... Figure 1 The electronic device 10 shown is not limited to this.

[0075] Please refer to Figure 1First, a substrate 100 is provided. The substrate 100 includes a first surface 100s1 and a second surface 100s2 opposite to each other in a first direction (e.g., the Z direction), and includes a groove 100c extending from the first surface 100s1 into the substrate 100 and a through-hole 100tv penetrating the first surface 100s1 and the second surface 100s2. Next, a bonding element BE1 is provided in the groove 100c. Then, a first electronic unit EU1 is provided on the bonding element BE1, such that the first electronic unit EU1 is bonded to the substrate 100 through the bonding element BE1. Subsequently, a conductive element 110 is provided in the through-hole 100tv. Afterward, a connection element CE1 is provided on the conductive element 110, wherein the reflow soldering temperature of the bonding element BE1 is higher than the reflow soldering temperature of the connection element CE1.

[0076] In summary, in the electronic device and manufacturing method of the present disclosure, the reflow soldering temperature of the bonding element is designed to be higher than that of the connecting element. In this way, when the connecting element is subsequently reflow soldered, the bonding element is less likely to be affected by the reflow soldering process, thereby improving the reliability of the bonding element bonding the first electronic unit to the substrate.

[0077] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure. Features between embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0078] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of this disclosure, and features between the various embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Those skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. An electronic device, characterized in that, include: A substrate includes a first surface and a second surface opposite to each other in a first direction, wherein the substrate includes a groove and a through hole through the first surface and the second surface; A connecting element is disposed in the groove; A first electronic unit is disposed in the groove and bonded to the substrate by the bonding element; A conductive element is disposed in the perforation and electrically connected to the first electronic unit; A circuit structure is disposed on the first surface of the substrate and electrically connected to the first electronic unit and the conductive element; as well as A connecting element is disposed on the conductive element, wherein the reflow soldering temperature of the bonding element is higher than the reflow soldering temperature of the connecting element.

2. The electronic device according to claim 1, characterized in that, Also includes: A first bonding pad is disposed on the bottom surface of the groove or embedded in the substrate below the bottom surface of the groove, wherein the bonding element is disposed between the first electronic unit and the first bonding pad, and in the first direction, the bonding element overlaps with a second bonding pad of the first electronic unit.

3. The electronic device according to claim 2, characterized in that, The first electronic unit includes a base layer and a connecting pad, wherein the connecting pad is disposed on a first side of the base layer, and in the first direction, the second connecting pad is disposed on a second side opposite to the first side of the base layer.

4. The electronic device according to claim 3, characterized in that, The second bonding pad is embedded in the recess of the base layer.

5. The electronic device according to claim 3, characterized in that, In a second direction perpendicular to the first direction, the width of the base layer on the first side is greater than the width of the base layer on the second side.

6. The electronic device according to claim 2, characterized in that, The second bonding pad is configured in a plurality of ways, and the plurality of the second bonding pads are configured to be mirror-symmetrical in a second direction perpendicular to the first direction.

7. The electronic device according to claim 6, characterized in that, The distance between the geometric center of the plurality of second bonding pads and the geometric center of the first electronic unit is less than 10 micrometers.

8. A method for manufacturing an electronic device, characterized in that, include: A substrate is provided, wherein the substrate includes a first surface and a second surface opposite to each other in a first direction, and includes a groove extending from the first surface into the substrate and a through hole penetrating the first surface and the second surface; A coupling element is provided in the groove; A first electronic unit is provided on the bonding element such that the first electronic unit is bonded to the substrate via the bonding element; A conductive element electrically connected to the first electronic unit is provided in the perforation; as well as A connecting element is provided on the conductive element, wherein the reflow soldering temperature of the connecting element is higher than that of the connecting element.

9. The method according to claim 8, characterized in that, The step of providing the conductive element in the through hole includes: Provide carrier board; Conductive pillars are formed on the carrier plate at positions corresponding to the through holes in the substrate; The substrate is bonded to the carrier plate by aligning the perforations with the conductive posts; and An electroplating process is performed on the seed layer formed on the surface of the perforation to form the conductive element in the perforation.

10. The method according to claim 9, characterized in that, When the first electronic unit is provided at a position on the carrier plate corresponding to the groove of the substrate, the first surface of the substrate is bonded to the carrier plate.

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