Method and circuit for voltage droop response

Abstract

The present technology relates to methods and circuits for implementing a voltage droop response, and discloses a method of responding to a voltage droop in an electronic circuit; the method comprising: in response to a voltage droop event, switching activity from a nominal clock source to a fallback clock source after a predetermined time delay according to a programmable delay value.

Description

[0001] This technology relates to methods and circuits for implementing voltage droop response. Specifically, this technology relates to responding to voltage droop events and voltage recovery events in an information processing system.

[0002] Some computer circuits (such as the central processing unit (CPU) or graphics processing unit (GPU)) may experience performance issues. For example, a CPU may experience voltage droop due to the large variations in the current required by the power delivery network (PDN).

[0003] There is a need for mitigation measures to address these performance issues.

[0004] This technology relates to solving or mitigating such performance problems or improving known mitigation techniques.

[0005] According to a first method of the present technology, a method is provided in response to voltage droop in an electronic circuit; the method includes: in response to a voltage droop event, switching activity from a nominal clock source to a backoff clock source after a predetermined time delay based on a programmable delay value.

[0006] This method may include detecting voltage droop events.

[0007] Switching an activity from a nominal clock source to a fallback clock source may include switching a state machine from a nominal state to a fallback state.

[0008] A predetermined time delay based on the programmable delay value can correspond to the duration between starting the delay counter and the delay counter reaching the programmable delay value. For example, the delay counter can start from zero and count upwards until it reaches the programmable delay value. Alternatively, a predetermined time delay based on the programmable delay value can correspond to the duration between starting the delay counter at the programmable delay value and the delay counter reaching zero. Therefore, a predetermined threshold is determined based on the programmable delay value.

[0009] The switching may include: switching the activity from a nominal clock source to a zero source in response to a voltage droop event; starting a delay counter in response to switching the activity to a zero source; and switching the activity from a zero source to a backoff clock source in response to the delay counter reaching a predetermined threshold based on a programmable delay value.

[0010] This method may include: switching the activity to zero source in response to a sign-off violation event.

[0011] Switching to a zero source may include pausing the activity so that it does not operate according to any clock. Switching to a zero source may include stopping the activity so that once the activity is switched to that source, no further clock edge propagation occurs. The activity may switch to a zero source in response to events other than a sign-off violation. For example, in response to a voltage droop event, the activity may switch from a nominal clock source to a zero source before switching from a zero source to a fallback clock source.

[0012] Sign-off violations can be severe voltage droop events, i.e., events where the switchback clock frequency is insufficient to ensure proper circuit functioning. Sign-off violations can also result from rare, deep droop events such as power outages. Alternatively, any droop can trigger a sign-off violation when the circuit is operating at the lower limit of acceptable voltage margins, as any drop in voltage risks causing hold-time failures that cannot be resolved by frequency reduction. In response to a sign-off violation event, activity can be stopped, paused, or held. Circuit functioning may rely on static data retention within the circuit until the sign-off violation event has passed.

[0013] In some implementations, switching the activity to zero source is triggered by receiving an asynchronous signal; and is configured to pause the activity for one cycle of the nominal clock source.

[0014] The method may include: in response to a voltage recovery event, switching activity from a backoff clock source to a nominal clock source after a predetermined time delay based on a programmable delay value and a predetermined duration based on a programmable minimum backoff value.

[0015] This method may include detecting voltage recovery events.

[0016] The predetermined duration based on the programmable minimum backoff value can correspond to the duration between starting the minimum backoff duration counter and the minimum backoff duration counter reaching the programmable minimum backoff value. For example, the minimum backoff duration counter can start from zero and count upwards until it reaches the programmable minimum backoff value. Alternatively, the predetermined duration based on the programmable minimum backoff value can correspond to the duration between starting the minimum backoff duration counter at a programmable delay value and the minimum backoff duration counter reaching zero.

[0017] Switching activities in response to a voltage recovery event may include: activating a minimum backoff duration counter in response to a voltage recovery event; switching the activity from a backoff clock source to a zero source in response to the minimum backoff duration counter reaching a predetermined threshold based on a programmable minimum backoff value; activating a delay counter in response to switching the activity to a zero source; and switching the activity from a zero source to a nominal clock source in response to the delay counter reaching a predetermined threshold based on a programmable delay value.

[0018] The method may include: resetting the minimum backoff duration counter in response to a voltage droop event that occurs after the minimum backoff duration counter has been started and before the minimum backoff duration counter reaches a predetermined threshold based on a programmable minimum backoff value. For example, the method may include: resetting the minimum backoff duration counter in response to a voltage droop event that occurs after the minimum backoff duration counter has been started and before the minimum backoff duration counter reaches a programmable minimum backoff value. Alternatively, the method may include: resetting the minimum backoff duration counter in response to a voltage droop event that occurs after the minimum backoff duration counter has been started and before the minimum backoff duration counter reaches zero.

[0019] A predetermined duration defined by a programmable minimum backoff value can have a duration that is substantially the same as a predetermined delay defined by a programmable delay value.

[0020] A predetermined duration defined by a programmable minimum backoff value can have a duration that is substantially different from a predetermined delay defined by a programmable delay value.

[0021] A predetermined delay, defined by a programmable delay value, can be zero. In other words, a predetermined delay can have a duration of zero seconds; or it can have no duration, i.e., no delay at all.

[0022] In another method, an electronic circuit is provided configured to respond to a voltage droop in another electronic circuit; the electronic circuit provides: a nominal clock source; a backoff clock source; and a programmable delay value; wherein, in response to a voltage droop event, the electronic circuit switches from the nominal clock source to the backoff clock source after a predetermined time delay according to the programmable delay value. In some embodiments, the electronic circuit configured to respond to a voltage droop is a clock multiplexer circuit. In some embodiments, the electronic circuit experiencing a voltage droop is a voltage droop detector circuit. In some embodiments, the electronic circuit includes body circuitry to mitigate the effects of voltage droop.

[0023] In another approach, an electronic circuit is provided that includes a programmable state machine according to the present technology, wherein the programmable state machine is configured to switch from a nominal state to a fallback state in response to a voltage droop event.

[0024] In response to a voltage droop event, the state machine can switch from the nominal state to the zero state; in response to switching the state machine to the zero state, a delay counter can be started; and in response to the delay counter reaching a predetermined threshold based on a programmable delay value, the state machine can switch from the zero state to the rollback state.

[0025] In response to a signing violation, the state machine can switch to state zero.

[0026] In some implementations, the state machine switches to the zero state upon receiving an asynchronous signal and within one cycle of the nominal clock source.

[0027] In response to a voltage recovery event, the state machine can switch from the backoff state to the nominal state after a predetermined time delay based on a programmable delay value and a predetermined duration based on a programmable minimum backoff value.

[0028] In response to a voltage recovery event, a minimum backoff duration counter can be started; in response to the minimum backoff duration counter reaching a predetermined threshold based on a programmable minimum backoff value, the state machine can switch from a backoff state to a zero state; in response to switching the state machine to a zero state, a delay counter can be started; and in response to the delay counter reaching a predetermined threshold based on a programmable delay value, the state machine can switch from a zero state to a nominal state.

[0029] The minimum backoff duration counter can be reset in response to a voltage droop event that occurs after the minimum backoff duration counter is started and before the minimum backoff duration counter reaches a predetermined threshold based on the programmable minimum backoff value.

[0030] A predetermined duration defined by a programmable minimum backoff value can have a duration that is substantially the same as a predetermined delay defined by a programmable delay value.

[0031] A predetermined duration defined by a programmable minimum backoff value can have a duration that is substantially different from a predetermined delay defined by a programmable delay value.

[0032] A predetermined delay defined by a programmable delay counter can be zero. In other words, a predetermined delay can have a duration of zero seconds; or it can have no duration, i.e., no delay at all.

[0033] In another method, a method for responding to voltage droop in an integrated circuit is provided, the method comprising: storing a set of clock parameters in a clock selection state machine, the clock parameters including a nominal clock operating at a nominal frequency, a backoff clock operating at a backoff frequency different from the nominal frequency, and a configurable output clock; wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency, and when the state machine is in a backoff state, the output clock is configured to output the backoff frequency; switching the state machine to the backoff state in response to a voltage droop event; and switching the state machine to the nominal state in response to a voltage recovery event; wherein, when the state machine switches to the backoff state, the output clock switches to the output zero for a predetermined delay according to a programmable delay value before switching to the backoff frequency; and wherein, when the state machine switches to the nominal state, after a predetermined duration according to a programmable minimum backoff value, the output clock switches to the output zero for a predetermined delay according to a programmable delay value before switching to the nominal frequency.

[0034] In another method, a programmable state machine is provided, comprising: a circuit configured to respond to a voltage droop in an integrated circuit; the programmable state machine circuit comprising: a nominal clock operating at a nominal frequency; a backoff clock operating at a backoff frequency different from the nominal frequency; and an output clock; wherein, when the state machine is in a nominal state, the output clock is configured to output the nominal frequency, and when the state machine is in a backoff state, the output clock is configured to output the backoff frequency; wherein, in response to a voltage droop event, the state machine switches from the nominal state to the backoff state, and in response to a voltage recovery event, the state machine switches from the backoff state to the nominal state; wherein, when the state machine switches to the backoff state, the output clock switches to the output zero for a predetermined delay according to a programmable delay value before switching to the backoff frequency; and wherein, when the state machine switches to the nominal state, after a predetermined duration according to a programmable minimum backoff value, the output clock switches to the output zero for a predetermined delay according to a programmable delay value before switching to the nominal frequency.

[0035] In another method, a method for programming a programmable state machine according to the present technology is provided, the method comprising: performing at least one of testing, measuring, simulating, providing or bootstrapping a response of an integrated circuit to a voltage droop event; setting a programmable delay value; performing at least one of testing, measuring, simulating, providing or bootstrapping a response of an integrated circuit to a voltage recovery event; and setting a programmable minimum backoff value.

[0036] Testing the integrated circuit's response to a voltage droop event may include exposing a programmable state machine to the voltage droop event to determine an appropriate value for a predetermined delay of a programmable delay counter. Testing the integrated circuit's response to a voltage recovery event may include exposing a programmable state machine to the voltage recovery event to determine an appropriate value for a predetermined duration of a programmable minimum backoff duration counter.

[0037] Measuring the integrated circuit's response to a voltage droop event may include exposing a programmable state machine to the voltage droop event and measuring parameters of the programmable state machine to determine an appropriate value for a predetermined delay of a programmable delay counter. Measuring the integrated circuit's response to a voltage recovery event may include exposing a programmable state machine to the voltage recovery event and measuring parameters of the programmable state machine to determine an appropriate value for a predetermined duration of a programmable minimum backoff duration counter.

[0038] The response of an analog integrated circuit to a voltage droop event may include simulating a programmable state machine to determine an appropriate value for a predetermined delay of a programmable delay counter. The response of an analog integrated circuit to a voltage recovery event may include simulating a programmable state machine to determine an appropriate value for a predetermined duration of a programmable minimum backoff duration counter.

[0039] Providing an integrated circuit's response to a voltage droop event may include setting a predetermined delay value for a programmable delay counter determined based on empirical data, without testing the programmable state machine. Providing an integrated circuit's response to a voltage recovery event may include setting a predetermined delay value for a programmable minimum backoff duration counter determined based on empirical data, without testing the programmable state machine.

[0040] The bootstrap integrated circuit's response to a voltage droop event may include setting a predetermined delay value for a programmable delay counter based on data received from a remote server by the programmable state machine during startup or reset. Similarly, the integrated circuit's response to a voltage recovery event may include setting a predetermined delay value for a programmable minimum backoff duration counter based on data received from a remote server by the programmable state machine during startup or reset.

[0041] In another approach, an electronic circuit is provided that includes electronic logic components operable to perform the steps of the method according to the present disclosure.

[0042] In another approach, a non-transitory computer-readable medium is provided for storing computer-readable code for manufacturing a programmable state machine according to the method of this disclosure.

[0043] In another approach, a system is provided comprising: an electronic circuit of the method of the present disclosure, the electronic circuit being implemented in at least one packaged chip; at least one system component; and a board; wherein the at least one packaged chip and at least one system component are assembled on the board.

[0044] In another approach, a chip-containing product is provided, which includes a system of the methods of this disclosure, the system being assembled on an additional board together with at least one other product component.

[0045] In another approach, a non-transitory computer-readable medium is provided for storing computer-readable code for manufacturing circuitry for detecting voltage droop events in any of the foregoing methods of this disclosure.

[0046] Specific implementations of the disclosed technology will now be described by way of example only, with reference to the accompanying drawings, in which:

[0047] Figure 1 A simplified example of a multiplexing device that is operable to implement at least a portion of the process of this technology in hardware is shown;

[0048] Figure 2 The waveform is shown at the backoff frequency of the output clock during the droop event, switching to a pause transition.

[0049] Figure 3 The waveform is shown at the backoff frequency during a droop event, switching to the output clock with minimal transition.

[0050] Figure 4 The waveform is shown where the output clock stops and does not switch to the backoff frequency during a droop event;

[0051] Figure 5 The waveform of the subsequent drooping event detected during the transition period is shown;

[0052] Figure 6 The waveform of the approval violation during the drooping event is shown;

[0053] Figure 7 A flowchart is shown showing the backoff frequency during a droop event, switching to the output clock via a pause transition;

[0054] Figure 8 A flowchart is shown showing the backoff frequency for switching to the output clock with minimal transition during a droop event;

[0055] Figure 9 A flowchart is shown showing the backoff frequency during a droop event that stops and does not switch to the output clock.

[0056] Figure 10 The system and chip-containing products were shown; and

[0057] Figure 11 A schematic diagram of a clock multiplexer circuit according to the method of this technology is shown.

[0058] The activity of synchronous digital circuitry on a switching chip (such as circuitry implementing the processor) can vary significantly within a few clock cycles (typically <10). This can correspond to a cycle shorter than the response time of the power supply and distribution network (PDN) to the chip, which can lead to transient changes in the supply voltage. Voltage droop is of particular concern because a drop in voltage can cause the digital circuitry to malfunction (e.g., power-down). Operating under overvoltage conditions to mitigate such power-down events during rare voltage droops is undesirable, as this increases the power consumption of the digital circuitry.

[0059] The methods described herein relate to responsive droop mitigation schemes with low intervention latency. These techniques rely on dedicated circuitry to protect the operation of digital circuitry (the main circuit). This includes detecting one or more types of voltage droop conditions and applying a mitigation response to a synchronous clock driving the activities of the main circuit. This technique discusses implementing mitigation actions in response to voltage droop in electronic circuitry (e.g., a droop detector circuit) to, for example, prevent circuit failure.

[0060] Clock management of the central processing unit (CPU) and graphics processing unit (GPU) shader cores has a direct impact on system performance, especially in the thermally constrained environment of battery-operated devices.

[0061] Modern CPUs and GPUs experience voltage droop due to the significant variations in the current required by power delivery networks (PDNs). This necessitates mitigation techniques to minimize voltage margins to reduce power consumption and heat generation, while minimizing the impact on performance. Reducing the clock frequency during a droop event is one such mitigation strategy.

[0062] Maintaining performance requires robust mechanisms to compensate for the heat generated in this mode. Reducing voltage and clock frequency is one such technique used to manage thermal budgets and extend battery life.

[0063] Power delivery network characteristics vary across on-chip silicon systems. Therefore, a standard droop response is not suitable for every specific power delivery network implementation. This technique provides a way to control or program the droop mitigation response to droop events based on system characteristics. In one example, a user tests a power delivery system and programs an appropriate droop response based on the power delivery network characteristics.

[0064] refer to Figure 1 The hardware illustrates a multiplexer structure that is operable to implement at least a portion of the process of this technique. Figure 1 A multiplexer 100 is shown as a module, such as part of a clock-controlled state machine (CCSM) arrangement operable in electronic circuitry.

[0065] According to this technique, several clock domains exist within the state machine. The output clock enters two stages of a clock multiplexer. The first stage has a pair of clock multiplexers controlled by clksel_nom and clksel_fb. ​​The output of the first multiplexer is called clk_nominal. This clock has a higher frequency and is typically a high-frequency, fast clock entering any CPU / GPU subsystem. The output of the second multiplexer is called clk_fallback. This clock has a lower frequency and acts as a fallback frequency in the event of a droop event. This is the fallback clock entering the CPU / GPU subsystem in the event of a droop event. The second stage of the clock multiplexer lies between clk_nominal and clk_fallback. This is controlled by clksel. This control switches when a droop event occurs. The output of the multiplexer is called clk_droop_mitigated. The clock domain clk_droop_mitigated is clk_nominal under normal circumstances and switches to clk_fallback in the event of a droop event.

[0066] Clock multiplexer 106 is operable to receive input NOM clock 102 and FB clock 104, the NOM clock representing the nominal source under current normal voltage and frequency tuning, and the FB clock representing the currently available backoff source under droop-relief voltage and frequency. Clock multiplexer 106 is controlled by clksel 108 to select the source used to provide output clkout 111.

[0067] The droop mitigation state machine 110 outputs clksel 108 in response to a droop detector 112 detecting a droop event. The droop detector has an input func_clk 114 connected to the NOM clock 102. The droop mitigation state machine 110 has an output TRIG_DROOP 116 connected to an input 118 of the droop mitigation state machine 110.

[0068] therefore, Figure 1 A specific implementation of a glitch-free multiplexer is shown, which, when outputting TRIG_DROOP 116, can have the following droop mitigation strategy for clkout 111:

[0069] • If clksel[1:0] = 0'b01, then the NOM clock is selected. Droop events are ignored, and clksel is driven by clk_nominal.

[0070] • If clksel[1:0] = 0'b10, then the FB clock is selected. A drooping event causes clksel to switch to the backoff frequency.

[0071] • If clksel[1:0] = 0'b00, then no clock is selected. In other words, clock propagation is stopped.

[0072] Figure 2 The waveform is shown during the droop event, switching to the backoff frequency of the output clock via a pause transition.

[0073] refer to Figure 2 Multiple signals and the nominal clock ( Figure 1 The NOM clock (102) clk_nominal and output clock ( Figure 1 The output clock is synchronized using clk_droop_mitigated or clkout 111. Initially, the output clock is at the nominal frequency. While high, when a droop event is detected, the output clock pauses and then switches to a (lower) backoff frequency for a period of time. Then, after the droop event, the output clock pauses again and switches back to the nominal frequency. The clksel signal controls multiplexer 100, which controls which of the nominal clock or the backoff clock is selected as the output clock.

[0074] This technology provides a first delay / counter A that extends the first pause between the output clock switching from the nominal clock and the backoff clock by a defined amount of time. This technology also provides a second delay / counter B that defines the minimum time the output clock will run at the backoff frequency while TRIG_DROOP remains stable at 1'b0 before switching back to the nominal clock.

[0075] The output clock initially operates at the nominal frequency (clksel=NOMINAL). At time 1), a droop event is detected (TRIG_DROOP is high). Shortly after, the output clock stops (stopclk_nominal is high and clksel=NOCLK). At time 2), the stop signal goes low, triggering the first delay / counter A. After delay A, the output clock runs at the fallback frequency while TRIG_DROOP remains high (clksel=FALLBACK). At time 3), once the droop event ends (TRIG_DROOP is low), counter B is triggered. Even without a droop event, the output clock continues to run at the fallback frequency until counter B completes its run. At time 4), the output clock pauses again after delay A, after which it resumes running at the nominal frequency to end the droop relief (time 5) (clksel=NOMINAL).

[0076] This means that the counter values ​​or delays A and B can be programmed appropriately based on the PDN characteristics.

[0077] For some PDNs, the pause between switching the output clock from the nominal frequency to the backoff frequency should be minimized. In this case, such as... Figure 3 As shown, delay A can be set to a minimum (zero) to minimize pauses and provide the fastest possible direct transition from the nominal clock to the fallback clock (and back to the nominal clock). In this case, clksel transitions directly from NOMINAL to FALLBACK.

[0078] Similarly, Figure 3 As shown, once TRIG_DROOP goes low (the droop event completes, voltage recovers), counter B will only begin counting down. Therefore, in the case where TRIG_DROOP goes low once the backoff clock starts running, the backoff clock will still continue for the minimum time set by counter B. Switching back from the backoff frequency to the nominal frequency can cause voltage droop, which could lead to the detection of another droop event. Counter B is programmed in this way to ensure that the voltage increases sufficiently after a droop event to avoid any triggering of another droop event.

[0079] In some scenarios, the output clock should pause (remain off) for the duration of the droop event before returning to the nominal clock; that is, the backoff clock should not be used. This can be useful when the circuit is in minimum dynamic voltage and frequency scaling (DVFS) mode, which means that the backoff clock cannot be safely used when a droop event occurs (see submission "Droop mitigation scheme with sign off").

[0080] like Figure 4 As shown, at time 1), when stopclk_nominal goes low, the output clock clk_droop_mitigated remains off (clksel=NOCLK). At time 2), when TRIG_DROOP is low, counter B starts counting down as usual. Meanwhile, the output clock remains off (clksel=NOCLK). At time 3), after counter B completes, the output clock starts running at the nominal frequency again (clksel=NOMINAL). Note that in this case, delay A is meaningless because cksel is set to NOCLK.

[0081] Figure 5This illustrates the scenario where TRIG_DROOP is triggered while counter B is already running. As shown in the figure, at time 1), counter B will reset after TRIG_DROOP goes high again. Then at time 2), once TRIG_DROOP goes low, counter B will start counting down again.

[0082] Figure 6 This illustrates a sign-off violation (i.e., the voltage droops too low) that occurs during droop mitigation. At time 1), a sign-off event occurs (TRIG_SOFF is high) when the output clock is running at a backoff frequency to provide droop mitigation. In response, the output clock is paused (clksel = NOCLK). Then, at time 2), when both TRIG_DROOP and TRIG_SOFF are low, counter B will resume counting down as usual.

[0083] Figure 7 A flowchart is shown showing the backoff frequency during a droop event, switching to the output clock via a pause transition.

[0084] This process depends on the value of TRANSITION_PAUSE. If the value of TRANSITION_PAUSE is not zero, it means that clk_droop_mitigated is paused for the period of time specified by TRANSITION_PAUSE during each clock domain transition. That is, transitioning from clk_nominal to clk_fallback, and then transitioning back from clk_fallback to clk_nominal again. This is called "pausing the transition".

[0085] Figure 8 This flowchart illustrates the fallback frequency for switching to the output clock with minimal transition during a droop event. If the value of TRANSITION_PAUSE is set to 0'x0, this means a transition to clk_fallback with minimal latency to the clock multiplexer is configured. This is referred to as an "immediate transition." Note that solid boxes will be bypassed. They are shown for ease of comparison across different mitigation processes.

[0086] Figure 9 A flowchart is shown showing the backoff frequency during a droop event that stops and does not switch to the output clock.

[0087] Figure 9This describes the clock mitigation process when the CCSM pauses clk_droop_mitigated throughout the droop event. Note that solid boxes are bypassed. They are shown for ease of comparison across different mitigation processes. Once a trigger exists on TRIG_DROOP, clk_droop_mitigated must be stopped. This is achieved through an internally generated signal called stopclk_nominal. Since TRIG_DROOP is synchronized with clk_nominal, and the second phase of the clock multiplexer is driving clk_nominal, TRIG_DROOP does not require any resynchronization. "stopclk_nominal" is an internal signal that changes from 0'b0 to 0'b1 once a 0'b0-0'b1 transition exists on TRIG_DROOP. This is used to stop clk_droop_mitigated as quickly as possible. Both "stopclk_nominal" and TRIG_DROOP are synchronized with clk_nominal. The stopclk_nominal signal is reset to 0'b0 when the CCSM has registered the event. Use the state "cur_clksel<1:0>" to confirm this.

[0088] Therefore, the method and circuit according to the present technology can be used to alleviate drooping in systems with dynamic voltage and frequency scaling, and the method can be implemented in the form of a non-transitory computer-readable medium including a structure of data and commands operable to enable a device to construct an assembly of electronic logic components, which, when embedded in and activated thereon, causes the electronic device to perform the steps of the method of the present technology as described above.

[0089] As will be apparent to those skilled in the art, a hybrid approach may also be adopted, wherein hardware logic, firmware, and / or software may be used in any combination to implement this technology.

[0090] like Figure 10As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, and the circuitry described above is implemented on a single chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package comprising a semiconductor device housing the semiconductor device implementing the circuitry described above, and a protective housing (e.g., made of metal, plastic, glass, or ceramic) for connectors (such as pads, solder balls, or pins) for connecting the semiconductor device to an external environment. Where more than one chip 400 is provided, these chips may be provided as separate integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interpolators, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0091] In some examples, a collection of chiplets (i.e., small modular chips with specific functionalities) may be referred to as a chip in itself. Chipslets may be individually packaged in semiconductor packages and / or packaged together with other chiplets in multi-chiplet semiconductor packages (e.g., using interpolators, or by using three-dimensional integration to provide multi-layer chiplet products comprising two or more vertically stacked integrated circuit layers).

[0092] One or more packaged chips 400 are assembled on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any one or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0093] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on an additional board 414.

[0094] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be disposed of by a user and / or intended for operational use by personnel or company.

[0095] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0096] Figure 11 A schematic diagram of a clock multiplexer circuit 1100 according to the method of this technique is shown. The clock multiplexer circuit 1100 has five inputs and one output. The inputs to the clock multiplexer circuit 1100 include a nominal clock source 1102 (clk_nominal), a fallback clock source 1104 (clk_fallback), a clock selector input 1106 (clksel[1:0]), a reset input 1108 (reset), and a stop clock input 1110 (stpclk_nominal). The output of the clock multiplexer circuit 1100 is the selected clock or a reduced clock 1112 (selected_clk).

[0097] Within the clock multiplexer circuit 1100, a combinational and synchronization logic block 1114 is disposed between the inputs and outputs of the circuit 1100. The clock multiplexer circuit 1100 is configured to select one of a nominal clock source 1102, a backoff clock source 1104, or no clock source to propagate to the output through the multiplexer. In normal operation, when no voltage droop event is present, the clock selector input 1106 selects the nominal clock input 1102, causing the nominal clock to be output at the selected clock output 1112. Alternatively, during a voltage droop event, the clock selector input 1106 can select the backoff clock input 1104, causing the backoff clock to be output at the selected clock output 1112.

[0098] For a signal from either the nominal clock source 1102 or the backoff clock source 1104 to reach the output, logic block 1114 must be traversed. Therefore, some latency or delay occurs as the signal propagates through multiplexer circuit 1100. In this way, when switching from the first source to the second source, after selecting the second source using clock selector input 1106, the clock edge of the first source can continue to propagate through the multiplexer. For example, when switching activity from the nominal clock source 1102 to the backoff clock source 1104, there may be a delay between the clock selector input changed to 2'b01 and the selected clock 1112 whose frequency has been changed to the backoff clock source 1104. This is undesirable; for example, when a voltage droop event is triggered, because the nominal clock edge can continue to propagate through the multiplexer to the selected clock output 1112, this could cause the main circuitry receiving the selected clock output 1112 to malfunction during the voltage droop event.

[0099] Therefore, after the clock selector input 1106 changes, it may be necessary to prevent the legacy clock edge from propagating through the multiplexer circuit 1100. This can be achieved by temporarily stopping any signals delivered to the selected clock output. This can be referred to as stopping, pausing, or gated output clocks. Figure 11 In this implementation, this is achieved using a stop clock input 1110. For example... Figure 11 As shown, the signal received at the stop clock input 1110 bypasses logic block 1114 to directly reach AND gate 1116, which feeds into clock gate 1118, and finally OR gate 1120. In this way, the stop clock input 1110 does not pass through combinational or synchronization logic 1114, and therefore does not delay such logic.

[0100] The signal received at stop clock input 1110 can be used to very quickly (e.g., within one clock cycle) stop any clock edge propagating to the selected clock output 1112, such that no further rising edge reaches output 1112 and the selected clock is stopped. The signal received at stop clock input 1110 can be asynchronous. By bypassing logic block 1114, the signal from stop clock input 1110 can essentially instantaneously (i.e., within one nominal clock cycle) switch the activity at the selected clock output 1112 to a zero source.

[0101] In this way, when a signal is received at the stop clock input 1110, the activity switches to the zero source (i.e., pauses). This signal can be an asynchronous signal. Switching the activity to the zero source (i.e., pausing the selected clock output 1112) can be triggered by receiving a signal at the stop clock input 1110. Receiving such a signal can be configured to pause the activity (switch the activity to the zero source) for one cycle of the nominal clock source.

[0102] After receiving a signal at stop clock input 1110 and subsequently gating or pausing output clock 1112, the edge of the selected clock source (e.g., a backoff clock source) can propagate through logic block 1114 toward the selected clock output 1112. After a predetermined delay has elapsed, the signal at stop clock input 1110 can be changed to allow output clock 1112 to restart. When output clock 1112 restarts, it can output a backoff clock as selected by clock selector input 1106. The same process can be followed when switching from backoff clock source 1104 to nominal clock source 1102. In this way, no conventional clock edge is delivered to the main circuitry, and circuit faults are mitigated. The predetermined delay can be configured based on a delay value. The delay value can be zero. In this case, the output clock can be restarted immediately after being gated by an asynchronous signal at stop clock input 1110.

[0103] As those skilled in the art will understand, this technology can be embodied in methods, circuits, or computer-readable media that include data and commands for constructing circuits. Therefore, this technology can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software, firmware, and hardware. When the term "component" is used, those skilled in the art will understand that it refers to any part of any of the above-described embodiments.

[0104] Furthermore, this technology may take the form of a computer program product tangibly embodied in a non-transitory computer-readable medium having computer-readable program code embodied thereon. The computer-readable medium may be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing.

[0105] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits including devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0106] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0107] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the present technology. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing the integrated circuit, or the FPGA may be deployed directly in a product.

[0108] Computer-readable code may include a mixture of code representations used in the manufacture of apparatus, such as including RTL representation, netlist representation, or a mixture of one or more of another computer-readable definition used in the semiconductor design and manufacturing process to manufacture apparatus embodying the present technology. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process to manufacture apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0109] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transient computer-readable medium such as semiconductors, disks, or optical discs. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept independently or collectively.

[0110] Program code can be executed entirely on the user's computer, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer via any type of network. Code components can be represented as procedures, methods, etc., and can include subcomponents, which can take the form of instructions or sequences of instructions at any level of abstraction (from direct machine instructions of the native instruction set to high-level compiled or interpreted language constructs).

[0111] Those skilled in the art will also appreciate that all or part of the logical methods according to embodiments of the present invention may be suitably embodied in a logic device comprising logic elements for performing the steps of the method, and such logic elements may include components such as logic gates in, for example, programmable logic arrays or application-specific integrated circuits. Such logical arrangements may also be embodied as enabling elements for temporarily or permanently establishing logical structures in such arrays or circuits using, for example, a virtual hardware descriptor language, which may be stored using a fixed carrier medium.

[0112] In an alternative, the implementation of this technology can be carried out in the form of a computer-implemented method for deploying services, which includes the step of deploying computer program code operable to cause the computer system or network to perform all the steps of the method when deployed to and executed on a computer infrastructure or network.

[0113] In another alternative, the implementation of this technology can be carried out in the form of a data carrier having functional data, including functional computer data structures, so that when loaded into and operated on a computer system or network, the computer system is able to perform all the steps of the method.

[0114] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0115] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features may be provided independently or in combination. For example, “at least one of [A], [B], and [C]” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0116] Although illustrative embodiments of the present technology have been described in detail with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments, and many improvements and modifications can be made to the above exemplary embodiments without departing from the scope of this disclosure.

Claims

1. A method in response to voltage droop in an electronic circuit; the method comprising: In response to a voltage droop event, the activity is switched from the nominal clock source to the backoff clock source after a predetermined time delay based on a programmable delay value.

2. The method of claim 1, wherein switching the activity from the nominal clock source to the fallback clock source includes switching the state machine from the nominal state to the fallback state.

3. The method of claim 1 or claim 2, wherein switching the activity from the nominal clock source to the fallback clock source comprises: In response to a voltage droop event, the activity is switched from the nominal clock source to the zero source; In response to switching the activity to the zero source, a delay counter is started; as well as In response to the delay counter reaching a predetermined threshold based on the programmable delay value, the activity is switched from the zero source to the backoff clock source.

4. The method according to any of the preceding claims, further comprising: In response to the signing violation incident, the activity will be switched to the zero source.

5. The method of claim 3 or claim 4, wherein switching the activity to a zero source is triggered by receiving an asynchronous signal; and is configured to pause the activity within one cycle of the nominal clock source.

6. The method according to any preceding claim, further comprising: In response to a voltage recovery event, the activity is switched from the backoff clock source to the nominal clock source after a predetermined time delay based on the programmable delay value and a predetermined duration based on the programmable minimum backoff value.

7. The method of claim 6, wherein switching activities in response to a voltage recovery event comprises: In response to a voltage recovery event, start the minimum backoff duration counter; In response to the minimum backoff duration counter reaching a predetermined threshold based on the programmable minimum backoff value, the activity is switched from the backoff clock source to the zero source; In response to switching the activity to the zero source, the delay counter is started; as well as In response to the delay counter reaching a predetermined threshold based on the programmable delay value, the activity is switched from the zero source to the nominal clock source.

8. The method according to claim 7, further comprising: In response to a voltage droop event that occurs after the minimum backoff duration counter is started and before the minimum backoff duration counter reaches the predetermined threshold according to the programmable minimum backoff value, the minimum backoff duration counter is reset.

9. The method according to any of the preceding claims, wherein the predetermined delay defined by the programmable delay value is zero.

10. An electronic circuit configured to respond to a voltage droop; the electronic circuit provides: A nominal clock source; a backoff clock source; and a memory for storing programmable delay values; in, In response to a voltage droop event, the electronic circuit switches from the nominal clock source to the backoff clock source after a predetermined time delay based on the programmable delay value stored in the memory.

11. The electronic circuit of claim 10, further comprising a state machine, wherein the state machine is configured to switch from a nominal state to a fallback state in response to a voltage droop event.

12. The state machine according to claim 11, wherein: In response to a voltage droop event, the state machine switches from the nominal state to the zero state; In response to switching the state machine to the zero state, a delay counter is started; and In response to the delay counter reaching a predetermined threshold based on the programmable delay value, the state machine switches from the zero state to the backoff state.

13. The state machine according to claim 11 or 12, wherein, In response to a signing violation event, the state machine switches to the zero state.

14. The state machine according to any one of claims 11 to 13, wherein the state machine switches to the zero state upon receiving an asynchronous signal and within one cycle of the nominal clock source.

15. The state machine according to any one of claims 11 to 14, wherein, In response to a voltage recovery event, the state machine switches from the backoff state to the nominal state after a predetermined time delay based on the programmable delay value and a predetermined duration based on the programmable minimum backoff value.

16. The state machine according to claim 15, wherein: In response to a voltage recovery event, start the minimum backoff duration counter; In response to the minimum backoff duration counter reaching a predetermined threshold based on the programmable minimum backoff value, the state machine switches from the backoff state to the zero state; In response to switching the state machine to the zero state, the delay counter is started; and In response to the delay counter reaching a predetermined threshold based on the programmable delay value, the state machine switches from the zero state to the nominal state.

17. The state machine according to claim 16, wherein, In response to a voltage droop event that occurs after the minimum backoff duration counter is started and before the minimum backoff duration counter reaches the predetermined threshold according to the programmable minimum backoff value, the minimum backoff duration counter is reset.

18. A method in response to voltage droop in an integrated circuit, the method comprising: The clock parameter set is stored in the clock selection state machine. The clock parameters include a nominal clock that operates at the nominal frequency, a backoff clock that operates at a backoff frequency different from the nominal frequency, and a configurable output clock. Specifically, when the state machine is in the nominal state, the output clock is configured to output the nominal frequency, and when the state machine is in the backoff state, the output clock is configured to output the backoff frequency. In response to a voltage droop event, the state machine is switched to the fallback state; and In response to a voltage recovery event, the state machine is switched to the nominal state; When the state machine switches to the backoff state, the output clock switches to output zero for a predetermined delay based on a programmable delay value before switching to the backoff frequency; and When the state machine switches to the nominal state, after a predetermined duration based on the programmable minimum backoff value, the output clock switches to output zero for a predetermined delay based on the programmable delay value before switching to the nominal frequency.

19. A state machine comprising circuitry configured to respond to a voltage droop in an integrated circuit; Programmable state machine circuits include: A nominal clock that operates at a nominal frequency; A backoff clock, which operates at a backoff frequency different from the nominal frequency; and Output clock; wherein, when the state machine is in the nominal state, the output clock is configured to output the nominal frequency, and when the state machine is in the backoff state, the output clock is configured to output the backoff frequency; In response to a voltage droop event, the state machine switches from the nominal state to the rollback state, and in response to a voltage recovery event, the state machine switches from the rollback state to the nominal state. When the state machine switches to the backoff state, the output clock switches to output zero for a predetermined delay based on a programmable delay value before switching to the backoff frequency; and When the state machine switches to the nominal state, after a predetermined duration based on the programmable minimum backoff value, the output clock switches to output zero for a predetermined delay based on the programmable delay value before switching to the nominal frequency.

20. A method for calibrating a state machine according to claim 19, the method comprising: Perform at least one of testing, measuring, simulating, providing, or bootstrapping the integrated circuit's response to a voltage droop event; Set the programmable delay value; Perform at least one of testing, measuring, simulating, providing, or bootstrapping the integrated circuit's response to a voltage recovery event; as well as Set the programmable minimum rollback value.

21. An electronic circuit comprising electronic logic components operable to perform the steps of the method according to any one of claims 1 to 9, 18 or 20.

22. A non-transitory computer-readable medium for storing computer-readable code for manufacturing an electronic circuit according to any one of claims 9 to 17, 19 or 21.

23. A system comprising: The electronic circuit according to any one of claims 9 to 17, 19 or 21 is implemented in at least one packaged chip; At least one system component; and plate; The at least one packaged chip and the at least one system component are assembled on the board.

24. A chip-containing product, the chip-containing product comprising the system of claim 23, the system being assembled on an additional board together with at least one other product component.

25. A non-transitory computer-readable medium for storing computer-readable code for manufacturing a circuit for detecting voltage droop events according to any of the preceding claims.

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