System-level cache circuit and read-write method thereof

Abstract

The application relates to the technical field of storage, in particular to a system-level cache circuit and a read-write method thereof; the bus interaction processing can be completed in the internal part of the cache circuit through an interaction control module, a read-write control module and a storage module; the interaction control module directly communicates with the bus, does not need a front-stage structure to provide read-write timing control logic, does not need to configure the cache circuit, can directly mount the cache circuit as an IP peripheral on the bus, and is easier to realize in actual application. On the other hand, the storage module is built by combining multiple levels of memories; the storage capacity of the cache circuit is improved while the read-write speed is ensured; the application has the advantages of low design difficulty and small occupied area.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a system-level cache circuit and its read / write method. Background Technology

[0002] A System-on-Chip (SOC) is a large-scale integrated circuit composed of a processor and various low-speed and high-speed Internet Protocols (IPs). With the advancement of electronic information technology and the increasing demands for circuit integration, the complexity of SOC design is growing. A single SOC chip must not only possess basic low-speed peripherals such as Serial Peripheral Interface (SPI), General-purpose Input / Output (GPIO), and Inter-Integrated Circuit (IIC), but also integrate high-speed peripherals such as Peripheral Component Interconnect Express (PCIE), Universal Chipplet Interconnect Express (UCIE), and Universal Serial Bus (USB). Furthermore, in the realm of complex IP design, the functionality and performance of IP circuits need to be verified and tested within the SOC.

[0003] As one of the key circuits in a System-on-a-Chip (SoC), the system-level cache circuit not only needs to ensure the safe startup and operation of the SoC system, but also needs to provide data caching space for the verification of high-speed IPs in the SoC system. For example, when performing functional verification and performance testing on IPs such as UCIE and Direct Memory Access (DMA) integrated in the SoC, the system-level cache circuit needs to be used to store high-bandwidth data streams. At the same time, the performance of the system-level cache circuit will affect the IP performance test results and the working efficiency of the SoC.

[0004] Currently, the commonly used methods for implementing cache circuits in the industry are:

[0005] 1. Double Data Rate (DDR) based cache circuit: This type of cache circuit has a significant advantage in storage capacity and high storage performance, and is widely used in various SOC systems. However, DDR-based system-level cache circuits require the design of complex DDR control circuits, which are difficult to design and result in a large footprint for the entire storage control circuit. Therefore, they are not suitable for use in some SOC chips with low storage capacity requirements.

[0006] 2. High-speed cache circuit based on Static Random-Access Memory (SRAM): This cache circuit is very fast and is often used to improve the memory access speed of the Central Processing Unit (CPU). However, its cache circuit capacity is small, its application scenarios are specific, and it is not suitable for system-level caching.

[0007] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0008] The technical problem to be solved by this invention is how to provide a system-level cache circuit with high storage performance and small footprint.

[0009] The present invention adopts the following technical solution:

[0010] In a first aspect, a system-level cache circuit is provided, comprising: an interactive control module, a read / write control module, and a storage module; the interactive control module is connected to the read / write control module, and the read / write control module is connected to the storage module; the storage module includes a multi-level memory.

[0011] The interactive control module is used to receive data signals transmitted from the bus and parse the data signals to obtain read / write control signals;

[0012] The read / write control module is used to generate a chip select control signal according to the read / write control signal, read the read data from the storage module through the chip select control signal, and send the read data to the interaction control module, which then transmits the read data to the bus.

[0013] The read / write control module is also used to select different levels of memory in the storage module to cache data from the bus according to the chip select control signal.

[0014] Preferably, the read / write control module includes a read / write response generation logic unit;

[0015] The read / write response generation logic unit is used to generate valid signals and response signals, and send the valid signals and response signals to the interactive control module;

[0016] When a single write operation is completed or data is read from the storage module, the read / write response generation logic unit sets the valid signal to a preset level.

[0017] When the response signal is a first preset value, it indicates that the current valid signal is a valid signal for reading data; when the response signal is a second preset value, it indicates that the current valid signal is a write completion flag signal.

[0018] The interactive control module is used to perform corresponding operations based on the valid signal of read data and the write completion flag signal.

[0019] Preferably, the read / write control module further includes a write address control unit, which is connected to the interactive control module;

[0020] The write address control unit includes a write address logic unit and multiple asynchronous FIFOs;

[0021] The write address logic unit is used to generate first control logic according to the read / write control signal;

[0022] The multiple asynchronous FIFOs in the write address control unit are used to obtain a write address signal according to the first control logic and the read / write control signal, and send the write address signal to the storage module;

[0023] The storage module is used to obtain the write address of the data based on the write address signal.

[0024] Preferably, the read / write control module further includes a write data control unit, which is connected to the interactive control module;

[0025] The write data control unit includes a write data logic unit and multiple asynchronous FIFOs;

[0026] The write data logic unit is used to generate second control logic according to the read / write control signal;

[0027] The multiple asynchronous FIFOs in the write data control unit are used to obtain write data according to the second control logic and the read / write control signal, and send the write data to the storage module;

[0028] The storage module is used to cache the written data to the corresponding address in the storage module according to the write address signal.

[0029] Preferably, the read / write control module further includes a read address control unit, which is connected to the interaction control module;

[0030] The read address control unit includes a read address logic unit and multiple asynchronous FIFOs;

[0031] The read address logic unit is used to generate third control logic according to the read / write control signal;

[0032] The multiple asynchronous FIFOs in the read address control unit are used to obtain the read address signal according to the third control logic and the read / write control signal, and send the read address signal to the storage module;

[0033] The storage module is used to obtain the address of the read data based on the read address signal.

[0034] Preferably, the read / write control module further includes a read control FIFO, a data readout control unit, a read data control unit, and a data output control unit connected in sequence; the read control FIFO is also connected to the interactive control module, and the data output control unit is also connected to the interactive control module;

[0035] The read control FIFO is used to cache each read address according to the read / write control signal, and the data readout control unit is used to read each read address when the read control FIFO is in a non-empty state.

[0036] The read data control unit includes a read data logic unit and multiple asynchronous FIFOs. The read data logic unit is used to generate a fourth control logic based on the read address read by the data read control unit. The multiple asynchronous FIFOs in the read data control unit are used to read the corresponding data from the storage module based on the fourth control logic and the read data address.

[0037] The data output control unit is used to select data read from multiple asynchronous FIFOs and transmit the selected data to the interactive control module.

[0038] Preferably, the storage module includes a first-level storage unit, a second-level storage unit, and a third-level storage unit;

[0039] The first-level storage unit includes multiple memories, and the second-level storage unit includes N first-level storage units;

[0040] The storage module includes N third-level storage units, and each third-level storage unit contains N second-level storage units, where N is greater than 1;

[0041] The write data is selected to be written to the first-level storage unit, the second-level storage unit, or the third-level storage unit based on the value of the write address bit in the write address signal.

[0042] Secondly, a read / write method is provided, which is implemented in the system-level cache circuit as described in the first aspect, and the read / write method includes:

[0043] The interactive control module receives data signals transmitted from the bus and parses the data signals to obtain read / write control signals;

[0044] The read / write control module generates a chip select control signal based on the read / write control signal, and selects different levels of memory in the storage module based on the chip select control signal, and caches the data from the bus into the selected memory.

[0045] The read / write control module reads data from the storage module via the chip select control signal and sends the read data to the interactive control module;

[0046] The interactive control module transmits the read data to the bus.

[0047] Preferably, the read / write control module includes a write address control unit and a write data control unit. The write address control unit includes a write address logic unit and multiple asynchronous FIFOs, and the write data control unit includes a write data logic unit and multiple asynchronous FIFOs.

[0048] The read / write control module generates a chip select control signal based on the read / write control signal. The read / write control module then selects different levels of memory in the storage module based on the chip select control signal, and caches data from the bus into the selected memory, including:

[0049] The write address logic unit generates first control logic based on the read / write control signal;

[0050] The multiple asynchronous FIFOs in the write address control unit obtain write address signals according to the first control logic and the read / write control signals, and send the write address signals to the storage module;

[0051] The storage module obtains the write address of the data according to the write address signal;

[0052] The write data logic unit generates second control logic based on the read / write control signal;

[0053] The multiple asynchronous FIFOs in the write data control unit obtain write data according to the second control logic and the read / write control signal, and send the write data to the storage module;

[0054] The storage module caches the written data to the corresponding address in the storage module according to the write address signal.

[0055] Preferably, the read / write control module further includes a read address control unit and a read data control unit. The read address control unit includes a read address logic unit and multiple asynchronous FIFOs. The read / write control module also includes a read control FIFO, a data readout control unit, a read data control unit, and a data output control unit connected in sequence. The read data control unit includes a read data logic unit and multiple asynchronous FIFOs.

[0056] The read / write control module reads data from the storage module via the chip select control signal and sends the read data to the interactive control module, including:

[0057] The read address logic unit generates third control logic based on the read / write control signal;

[0058] The multiple asynchronous FIFOs in the read address control unit obtain read address signals according to the third control logic and the read / write control signals, and send the read address signals to the storage module;

[0059] The storage module is used to obtain the address of the read data according to the read address signal;

[0060] The read control FIFO buffers each read address according to the read / write control signal, and the data readout control unit reads each read address when the read control FIFO is not empty.

[0061] The read data logic unit generates a fourth control logic based on the read address read by the data read control unit, and the multiple asynchronous FIFOs in the read data control unit read the corresponding data from the storage module according to the fourth control logic and the read data address;

[0062] The data output control unit selects data read from multiple asynchronous FIFOs and transmits the selected data to the interactive control module.

[0063] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0064] On the one hand, the present invention can complete bus interaction processing within the cache circuit through the interactive control module, read / write control module and storage module. The interactive control module communicates directly with the bus, without requiring the front-end structure to provide read / write timing control logic, nor does it require configuration operations on the cache circuit. The cache circuit can be directly mounted on the bus as an IP peripheral, which is easier to implement in practical applications.

[0065] On the other hand, by constructing a storage module comprising multi-level memory assembly, this invention improves the storage capacity of the cache circuit while ensuring read and write speeds, and has the advantages of low design difficulty and small footprint. At the same time, by adopting a multi-level storage structure and using read and write address-specific positioning for memory chip selection, each level of memory has independent read and write control logic, making it easy to modify the assembly width and depth of the memory. That is, when using different processes, only the underlying memory needs to be replaced in terms of process to achieve the process replacement of the entire cache module, so that the cache circuit proposed in this invention can be easily applied to different tape-out processes. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 This is a schematic diagram of a system-level cache circuit provided in an embodiment of the present invention;

[0068] Figure 2 This is a schematic diagram of the actual application structure of a system-level cache circuit provided in an embodiment of the present invention;

[0069] Figure 3 This is a schematic diagram of the read / write control module of a system-level cache circuit provided in an embodiment of the present invention;

[0070] Figure 4 This is a schematic diagram of the specific structure of a read / write control module for a system-level cache circuit provided in an embodiment of the present invention;

[0071] Figure 5 This is a schematic diagram of the structure of a storage module of a system-level cache circuit provided in an embodiment of the present invention;

[0072] Figure 6 This is a schematic diagram of the specific structure of a storage module of a system-level cache circuit provided in an embodiment of the present invention;

[0073] Figure 7This is a flowchart illustrating a read / write method provided in an embodiment of the present invention. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0075] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0076] In this invention, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0077] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0078] This embodiment provides a system-level cache circuit, such as Figure 1 As shown, it includes: an interactive control module, a read / write control module, and a storage module; the interactive control module is connected to the read / write control module, and the read / write control module is connected to the storage module; the storage module includes multi-level memory; the interactive control module is used to receive data signals transmitted from the bus, and parse the data signals to obtain read / write control signals; the read / write control module is used to generate a chip select control signal according to the read / write control signal, and read the read data from the storage module through the chip select control signal, and send the read data to the interactive control module, which then transmits the read data to the bus; the read / write control module is also used to select different levels of memory in the storage module to cache the data from the bus according to the chip select control signal.

[0079] like Figure 2As shown, the system-level cache circuit is an IP externally connected to the SOC data transmission bus. Its bus interface is the Advanced eXtensible Interface (AXI) interface, and its operating frequency can reach 1GHz. At the same time, the system-level cache circuit can be accessed by the CPU and high-speed peripherals, providing data cache space for the functional and performance testing of high-speed IPs in the SOC system.

[0080] The interactive control module is responsible for communicating with the external bus (i.e., Figure 2 The system communicates with the SOC data transmission bus, receives externally transmitted data signals, and parses them into read / write control signals. Furthermore, the interactive control module is also used to transmit data read from the storage module back to the bus. In one embodiment, the interactive control module is responsible for interacting with AXI. On one hand, it parses signals such as the bus read / write address and burst length, converting data with different burst lengths into read / write control signals with a burst length of 1 and a data bit width of 256 bits, and then sends these signals to the read / write control module for read / write control. On the other hand, the interactive control module is also used to transmit data read from the storage module by the read / write control module to the bus and generate a ready signal and a read / write response signal corresponding to the AXI bus.

[0081] The read / write control module receives read / write control signals from the interactive control module and generates a chip select control signal based on these signals. The chip select control signal controls data read and write operations, i.e., reading data from or writing data to the storage module. The storage module contains multi-level memory, including but not limited to SRAM, DRAM, or other types of cache memory. The storage module selects the appropriate storage level to cache data based on the chip select control signal issued by the read / write control module.

[0082] On the one hand, this embodiment can complete bus interaction processing within the cache circuit through the interactive control module, read / write control module and storage module. The interactive control module communicates directly with the bus, without requiring the front-end structure to provide read / write timing control logic, nor does it require configuration operations on the cache circuit. The cache circuit can be directly mounted on the bus as an IP peripheral, which is easier to implement in practical applications.

[0083] On the other hand, this embodiment improves the storage capacity of the cache circuit while ensuring read and write speed by constructing a storage module that includes multi-level memory assembly. It has the advantages of low design difficulty and small footprint. At the same time, by adopting a multi-level storage structure and using read and write address-specific positioning for memory chip selection, each level of memory has independent read and write control logic, making it easy to modify the assembly width and assembly depth of the memory. That is, when using different processes, only the underlying memory needs to be replaced by process replacement to realize the process replacement of the entire cache module. This allows the cache circuit proposed in this invention to be easily applied to different tape-out processes.

[0084] The structure of the system-level cache circuit will be described in more detail below.

[0085] In some implementations, such as Figure 3 As shown, the read / write control module includes a read / write response generation logic unit; the read / write response generation logic unit is used to generate a valid signal and a response signal, and send the valid signal and response signal to the interactive control module; when a single write operation is completed or data is read from the storage module, the read / write response generation logic unit sets the valid signal to a preset level; when the response signal is a first preset value, it indicates that the current valid signal is a valid signal for reading data; when the response signal is a second preset value, it indicates that the current valid signal is a write completion flag signal; the interactive control module is used to perform corresponding operations based on the valid signal for reading data and the write completion flag signal.

[0086] The read / write response generation logic unit is used to generate a valid signal (i.e., the svalid signal) and a response signal (i.e., the sresp signal). These two signals will be sent to the interactive control module for processing, and finally generate the rvalid signal, bvalid signal, and bresp signal of the AXI bus.

[0087] When a single write operation is completed in the storage module or data is read from the storage module, the read / write response generation logic unit sets the valid signal to a preset level (usually high). This valid signal is used to notify the interactive control module that data is ready or the operation is complete. The response signal works in conjunction with the valid signal to specify the specific meaning of the valid signal. Different preset values ​​can be used to represent different states or events. When the response signal is set to the first preset value, it indicates that the current valid signal represents valid data read from the storage module. This means that the interactive control module can receive and further process this read data. When the response signal is set to the second preset value, it indicates that the current valid signal represents a write operation that has been completed. This usually means that the written data has been successfully stored in the storage module.

[0088] The interactive control module performs corresponding operations based on valid signals and response signals from the read / write response generation logic unit. Specifically, for a valid signal indicating read data, it transmits the data to the bus. For a write completion flag signal, it performs post-write processing, such as updating the cache consistency state, initiating the next operation, or notifying other system components that the write operation has been completed.

[0089] This design allows system-level cache circuitry to perform data read and write operations in a clear and controlled manner, while ensuring operational integrity and data consistency. By using read / write response generation logic units, the system can accurately track the state of read and write operations, thereby improving overall performance and reliability.

[0090] In one embodiment, the preset level is set to high level, the first preset value is 0, and the second preset value is 1. When a single write operation is completed or data is read from the storage module, the read / write response generation logic unit will pull the valid signal high and use the response signal to identify the meaning represented by the high valid signal. That is, when the response signal is 0, it indicates that the valid signal is a valid signal for reading data, and when the response signal is 1, it indicates that the valid signal is a write completion flag signal.

[0091] It should be noted that the read / write control signal includes a variety of different signals, including maddr signal, mstrb signal, mlen signal and mdata signal, etc. For ease of explanation, this embodiment will use the read / write control signal for explanation, and will indicate which specific signal is used in the specific application scenario.

[0092] The `mstrb` signal is used to specify which bytes are valid in a single write transfer. In the AXI protocol, data is typically transmitted in 32-bit or 64-bit units, and the `mstrb` signal indicates which bytes in the data should be accepted by the receiving device. For example, if a write transfer contains 64 bits of data, then the `mstrb` signal will contain 8 bits, each corresponding to a single byte, with a high level indicating that the corresponding byte is valid.

[0093] The `mlen` signal is used to indicate the number of data operations in a single burst. In the AXI protocol, the `mlen` signal is typically used to represent the number of transmissions included in a burst. For example, if the `mlen` signal is set to 3, it means that a burst contains 4 transmissions (because the value of the `mlen` signal is usually 1 less than the actual number of transmissions).

[0094] The maddr signal is used by the master device to specify the address of data in the target slave device. In an AXI transfer, the maddr signal carries the memory address of the data to be read or written. The AXI protocol supports burst transfers, where the maddr signal specifies the starting address of the burst transfer, and subsequent addresses are automatically calculated by the AXI protocol based on the burst type and size. The mdata signal represents the data to be written to the storage module.

[0095] In some implementations, such as Figure 3 and Figure 4 As shown, the read / write control module further includes a write address control unit, which is connected to the interactive control module. The write address control unit includes a write address logic unit and multiple asynchronous FIFOs. The write address logic unit is used to generate first control logic based on the read / write control signal. The multiple asynchronous FIFOs in the write address control unit are used to obtain a write address signal (i.e., the wr_addr signal) based on the first control logic and the read / write control signal, and send the write address signal to the storage module. The storage module is used to obtain the write address of the data based on the write address signal.

[0096] The write address logic unit generates first control logic based on the maddr signal in the read / write control signal. This first control logic may include address generation, sorting, conflict detection, and resolution. The first control logic controls the operation of the asynchronous FIFO in the write address control unit, such as writing, reading, and data movement.

[0097] The multiple asynchronous FIFOs in the write address control unit are used to obtain write address signals according to the first control logic and the read / write control signals. Here, the read / write control signals are the concatenated signals of maddr, mstrb, and mlen. The multiple asynchronous FIFOs are high-speed cache memories used to temporarily store write address information. Asynchronous FIFOs allow write address signals to be processed and transmitted in different clock domains or without the need for synchronization signals. In one embodiment, the write address control unit includes 16 asynchronous FIFOs.

[0098] Based on the received write address signal, the storage module determines the write address of the data, and the corresponding location in the storage module will be used to store the upcoming data.

[0099] The write address control unit effectively manages the address information for write operations, maintaining data consistency and integrity even under high load or clock domain asynchrony. Because a FIFO acts as a buffer, it smooths the data flow when data rates change or processing speeds are inconsistent, thus reducing the risk of data loss. Furthermore, the write address control unit is designed for asynchronous operation, as different modules may operate at different clock frequencies. The use of an asynchronous FIFO ensures that the write address control unit can adapt to these different clock domains, thereby improving the overall system performance and reliability.

[0100] In some implementations, such as Figure 3 and Figure 4 As shown, the read / write control module further includes a write data control unit, which is connected to the interactive control module. The write data control unit includes a write data logic unit and multiple asynchronous FIFOs. The write data logic unit is used to generate second control logic based on the read / write control signal. The multiple asynchronous FIFOs in the write data control unit are used to obtain write data (i.e., the wr_data signal) based on the second control logic and the read / write control signal, and send the write data to the storage module. The storage module is used to cache the write data at the corresponding address in the storage module based on the write address signal.

[0101] The write data logic unit generates a second control logic based on the maddr signal in the read / write control signal. This second control logic may include data organization, conflict detection and resolution, and synchronization with the write address signal, used to control the operation of the asynchronous FIFO, such as writing, reading, and data movement.

[0102] The multiple asynchronous FIFOs in the write data control unit are also high-speed cache memories used to temporarily store write data information. Asynchronous FIFOs allow write data signals to be processed and transmitted in different clock domains or without the need for synchronization signals. Write data is generated according to the second control logic and the mdata signal in the read / write control signals, and this write data is then sent to the storage module. The read / write enable of the write data logic unit is consistent with the read / write enable of the write address logic unit, ensuring a one-to-one correspondence between address and data; that is, a piece of data is sent to the storage module at the same time as an address is sent. Based on the received write address signal, the storage module determines the write location of the data and caches the write data at the corresponding address.

[0103] This design allows the system to efficiently manage write operation data, maintaining data consistency and integrity even under high load or clock domain asynchrony. Using an asynchronous FIFO reduces the risk of data loss because, as a buffer, it smooths the data flow when data rates change or processing speeds are inconsistent. Furthermore, the write data control unit is designed with asynchronous operation in mind, which is crucial in complex SoC designs where different modules may operate at different clock frequencies. The use of an asynchronous FIFO ensures the write data control unit can adapt to these different clock domains, thereby improving the overall system performance and reliability.

[0104] In some implementations, such as Figure 3 and Figure 4 As shown, the read / write control module further includes a read address control unit, which is connected to the interactive control module. The read address control unit includes a read address logic unit and multiple asynchronous FIFOs. The read address logic unit is used to generate third control logic based on the read / write control signal. The multiple asynchronous FIFOs in the read address control unit are used to obtain a read address signal (i.e., the rd_addr signal) based on the third control logic and the read / write control signal, and send the read address signal to the storage module. The storage module is used to obtain the address of the read data based on the read address signal.

[0105] The read address control unit is used for cross-clock processing of the read address and sends the read address into the corresponding storage module. Its control logic is consistent with that of the write address control unit. The difference lies in the write enable of the asynchronous FIFO. The write enable of the asynchronous FIFO of the write address control unit is controlled by the mwrite signal, while the control logic of the asynchronous FIFO of the read address control unit is controlled by the mread signal.

[0106] The read address logic unit generates third control logic based on the maddr signal in the read / write control signals. This third control logic may include address generation, sorting, conflict detection, and resolution, and is used to control the operation of the asynchronous FIFO, such as writing, reading, and data movement.

[0107] The multiple asynchronous FIFOs in the read address control unit generate a read address signal by combining the maddr signal, mstrb signal and mlen signal in the third control logic and read / write control signals, and then send the read address signal to the storage module.

[0108] The storage module reads the address of the data according to the received read address signal, and extracts the data from the address to respond to the read request.

[0109] In some implementations, in order to cooperate with the read address control unit, such as Figure 3 and Figure 4 As shown, the read / write control module further includes a read control FIFO, a data readout control unit, a read data control unit, and a data output control unit connected in sequence; the read control FIFO is also connected to the interactive control module, and the data output control unit is also connected to the interactive control module; the read control FIFO is used to buffer each read address according to the read / write control signal, and the data readout control unit is used to read each read address when the read control FIFO is in a non-empty state; when data is written to the read control FIFO, the empty state signal is pulled low, indicating a non-empty state; when the read data address catches up with the write address, that is, when the read and write addresses are equal, the read control FIFO is in an empty state.

[0110] The read data control unit includes a read data logic unit and multiple asynchronous FIFOs. The read data logic unit is used to generate a fourth control logic based on the read address read by the read control unit. The multiple asynchronous FIFOs in the read data control unit are used to read the corresponding data (i.e., the rd_data signal) from the storage module according to the fourth control logic and the read data address. The data output control unit is used to select the data read from the multiple asynchronous FIFOs and transmit the selected data (sdata) to the interactive control module.

[0111] The read control FIFO is used to buffer each read address according to the maddr signal in the read / write control signal. When the read control FIFO is not empty, that is, when there are read addresses to be processed, the data readout control unit is responsible for reading these read addresses.

[0112] The read data logic unit in the read data control unit generates the fourth control logic based on the read address read by the data read control unit.

[0113] The asynchronous FIFO in the read data control unit reads the corresponding data from the storage module according to the fourth control logic and the address of the read data.

[0114] The overall process is as follows:

[0115] 1: The interactive control module receives the read request and sends the read address to the read control FIFO.

[0116] 2: Read control FIFO caches these read addresses.

[0117] 3: The data readout control unit detects that the read control FIFO is not empty and begins to read each read address.

[0118] 4: The read data logic unit of the read data control unit generates the fourth control logic, which guides the asynchronous FIFO in the read data control unit to read data from the storage module.

[0119] 5: The asynchronous FIFO in the read data control unit reads data from the storage module according to the fourth control logic and the read address, and temporarily stores it.

[0120] 6: The data output control unit selects data from the asynchronous FIFO in the read data control unit and sends it to the interactive control module.

[0121] 7: The interactive control module receives data and performs the next operation according to system requirements, sending the read data to the interactive control module, which then sends the read data to the bus.

[0122] Compared to existing storage circuits, the read / write control logic inside the read / write control module completes the conversion of bus control instructions to storage module timing and performs cross-clock domain processing for read / write operations. It is applicable to situations where the read / write operations of the front-end module to the storage module are not in the same clock domain, and no additional cross-clock domain processing logic is required.

[0123] In some implementations, such as Figure 5 As shown, the storage module includes a first-level storage unit, a second-level storage unit, and a third-level storage unit; the first-level storage unit includes multiple memory units, and the second-level storage unit contains N first-level storage units; the storage module includes N third-level storage units, and the third-level storage unit contains N second-level storage units, where N is greater than 1; the write data is selected to be written to the first-level storage unit, the second-level storage unit, or the third-level storage unit based on the value of the bit in the write address signal.

[0124] For example, in a 22-bit address space, addr[4:0] is used to align 256-bit transmissions, addr[6:5] is used for second-level memory cell selection, and addr[21:20] is used for third-level memory cell selection.

[0125] Taking a 4MB storage module as an example, refer to... Figure 6The first-level storage unit (L1) has a capacity of 64KB and contains eight 1024x64 SRAMs. The second-level storage unit (L2) has a capacity of 256KB and contains four L1 storages. The third-level storage unit (L3) has a capacity of 1MB and contains four L2 storages. The entire storage array has four L3 storages. When using different processes, the entire storage module can be replaced simply by replacing the underlying SRAM with a different process. This makes it easy to apply the storage module to different fabrication processes. When storing data, the three levels of storage space are selected based on the storage address. For example, there are multiple L3s, each L3 level includes multiple L2s, and each L2 level includes multiple L1s. When writing, 256 bits of data are written at a time. First, addr[21:20] selects which L3 level to write the data to, and then addr[6:5] selects which L2 level within the L3 level to write the data to. The L2 level write width is 256 bits, which matches the write data width. A 4MB SRAM requires a 22-bit address space, i.e., addr[21:0]. Array-based storage has the following characteristics:

[0126] (1) The interaction width between the storage module and the read / write control module is 256 bits. Therefore, when storing data, L2 storage is used as the basic storage interaction unit, that is, one storage address corresponds to 256 bits of data. This 256 bits of data is output by combining four L1 storage units with a width of 64 bits inside the L2 storage.

[0127] (2) When performing read and write operations on the storage module, the address sent by the read and write control module must satisfy the relationship addr = 32*n. When reading and writing with a width of less than 256 bits is required, the data reading and writing is controlled by the mask signal. The L2 storage will also select the L1 storage chip according to the mask signal.

[0128] (3) In the 22-bit address space, addr[4:0] is used to align the 256-bit transmission, addr[6:5] is used for L2 memory chip selection, and addr[21:20] is used for L3 memory chip selection. Compared with the commonly used high-order address chip selection logic, this memory module uses low-order address for chip selection, so that read and write operations of consecutive addresses will be performed back and forth in different SRAMs, improving the balance of usage frequency of different SRAMs.

[0129] Compared with commonly used storage modules, this module adopts a three-level storage structure, which has high flexibility in terms of depth and width splicing. Each L1 level storage block corresponds to a read / write control logic, and the control logic between each storage block is independent of each other. When changing the bit width or depth, it is only necessary to delete or add the corresponding control logic module. Therefore, this storage module has better portability and modifiability, and is more suitable for reuse in different projects.

[0130] The foregoing embodiments proposed a system-level cache circuit. This embodiment proposes a read / write method, which is implemented within the system-level cache circuit described in the foregoing embodiments. Figure 7 As shown, the read / write method includes:

[0131] Step 101: The interactive control module receives data signals transmitted from the bus and parses the data signals to obtain read / write control signals.

[0132] The interactive control module is responsible for communicating with the external bus, receiving externally transmitted data signals, and parsing them into read / write control signals. Furthermore, the interactive control module is also used to transmit data read from the storage module back to the bus. In one embodiment, the interactive control module interacts with AXI, parsing signals such as the bus read / write address and burst length, converting data with different burst lengths into read / write control signals with a burst length of 1 and a data bit width of 256 bits, and then sending these signals to the read / write control module for read / write control.

[0133] Step 102: The read / write control module generates a chip select control signal according to the read / write control signal, and selects different levels of memory in the storage module according to the chip select control signal, and caches the data from the bus into the selected memory.

[0134] Specifically, the write address logic unit generates first control logic based on the read / write control signal; the multiple asynchronous FIFOs in the write address control unit obtain write address signals based on the first control logic and the read / write control signal, and send the write address signals to the storage module; the storage module obtains the write address of the data based on the write address signals.

[0135] The maddr signal is the read / write address parsed by the interactive control module, and the output signals mwrite and mread of the interactive control module are used to characterize whether the maddr signal is a read address or a write address. The first control logic includes: the write address logic unit uses the mwrite signal as the write enable of the asynchronous FIFO, writes the data containing the maddr signal into the asynchronous FIFO for cross-clock domain processing, and then reads the data from the asynchronous FIFO to obtain the write address signal.

[0136] The write data logic unit generates a second control logic based on the read / write control signal; the multiple asynchronous FIFOs in the write data control unit obtain write data according to the second control logic and the read / write control signal, and send the write data to the storage module; the storage module caches the write data to the corresponding address in the storage module according to the write address signal.

[0137] To ensure consistency between the write address and the data, the write data control unit also uses the mwrite signal. The second control logic includes: the write data logic unit uses the mwrite signal as the write enable for the asynchronous FIFO, writes the mdata signal from the interactive control module into the asynchronous FIFO for cross-clock domain processing, and then reads the data from the asynchronous FIFO to obtain the written data. Step 103: The read / write control module reads the data from the storage module using the chip select control signal and sends the read data to the interactive control module.

[0138] The read address logic unit generates a third control logic based on the read / write control signal; the multiple asynchronous FIFOs in the read address control unit obtain a read address signal based on the third control logic and the read / write control signal, and send the read address signal to the storage module.

[0139] The third control logic includes: the read address logic unit uses the mread signal as the write enable of the asynchronous FIFO, writes the data containing the mread signal into the asynchronous FIFO for cross-clock domain processing, and then reads the data from the asynchronous FIFO to obtain the read address signal.

[0140] The storage module is used to obtain the address of the read data according to the read address signal; the read control FIFO buffers each read address according to the read write control signal, and the data read control unit reads each read address when the read control FIFO is not empty; the read data logic unit generates a fourth control logic according to the read address read by the data read control unit, and multiple asynchronous FIFOs in the read data control unit read corresponding data from the storage module according to the fourth control logic and the address of the read data; the data output control unit selects the data read from the multiple asynchronous FIFOs and transmits the selected data to the interactive control module.

[0141] The fourth control logic includes: reading data from the asynchronous FIFO in the read data control unit when it is not empty; the write condition for the asynchronous FIFO in the read data control unit is a valid signal indicating that the storage module has read data; when the asynchronous FIFO is full, the data output control unit controls the transmission of the read data to the interaction control unit. Step 104: The interaction control module transmits the read data to the bus.

[0142] The interactive control module receives data from the read / write control module. This data originates from the storage module and passes through the data output control unit and the read data control unit before finally reaching the interactive control module. Throughout the read operation, the interactive control module acts as a bridge between the storage circuitry and the system bus, ensuring that data can be efficiently and accurately read and sent to system components. The interactive control module significantly improves the overall system performance and response speed. For the specific structure of the system-level cache circuit, please refer to the aforementioned embodiment; it will not be repeated in this embodiment.

[0143] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A system-level cache circuit, characterized in that, include: The system includes an interactive control module, a read / write control module, and a storage module; the interactive control module is connected to the read / write control module, and the read / write control module is connected to the storage module; the storage module includes a multi-level memory. The interactive control module is used to receive data signals transmitted from the bus and parse the data signals to obtain read / write control signals; The read / write control module is used to generate a chip select control signal according to the read / write control signal, read data from the storage module through the chip select control signal, and send the read data to the interaction control module, which then transmits the read data to the bus. The read / write control module is also used to select different levels of memory in the storage module to cache data from the bus according to the chip select control signal.

2. The system-level cache circuit according to claim 1, characterized in that, The read / write control module includes a read / write response generation logic unit; The read / write response generation logic unit is used to generate a valid signal and a response signal, and send the valid signal and the response signal to the interactive control module; When a single write operation is completed or data is read from the storage module, the read / write response generation logic unit sets the valid signal to a preset level. When the response signal is a first preset value, it indicates that the current valid signal is a valid signal for reading data; when the response signal is a second preset value, it indicates that the current valid signal is a write completion flag signal. The interactive control module is used to perform corresponding operations based on the valid signal of read data and the write completion flag signal.

3. The system-level cache circuit according to claim 1, characterized in that, The read / write control module includes a write address control unit, which is connected to the interactive control module. The write address control unit includes a write address logic unit and multiple asynchronous FIFOs; The write address logic unit is used to generate first control logic according to the read / write control signal; The multiple asynchronous FIFOs in the write address control unit are used to obtain a write address signal according to the first control logic and the read / write control signal, and send the write address signal to the storage module; The storage module is used to obtain the write address of the data based on the write address signal.

4. The system-level cache circuit according to claim 3, characterized in that, The read / write control module further includes a write data control unit, which is connected to the interactive control module. The write data control unit includes a write data logic unit and multiple asynchronous FIFOs; The write data logic unit is used to generate second control logic according to the read / write control signal; The multiple asynchronous FIFOs in the write data control unit are used to obtain write data according to the second control logic and the read / write control signal, and send the write data to the storage module; The storage module is used to cache the written data to the corresponding address in the storage module according to the write address signal.

5. The system-level cache circuit according to claim 4, characterized in that, The read / write control module further includes a read address control unit, which is connected to the interaction control module. The read address control unit includes a read address logic unit and multiple asynchronous FIFOs; The read address logic unit is used to generate third control logic according to the read / write control signal; The multiple asynchronous FIFOs in the read address control unit are used to obtain the read address signal according to the third control logic and the read / write control signal, and send the read address signal to the storage module; The storage module is used to obtain the address of the read data based on the read address signal.

6. The system-level cache circuit according to claim 5, characterized in that, The read / write control module further includes a read control FIFO, a data readout control unit, a read data control unit, and a data output control unit connected in sequence; the read control FIFO is also connected to the interactive control module, and the data output control unit is also connected to the interactive control module. The read control FIFO is used to cache each read address according to the read / write control signal, and the data readout control unit is used to read each read address when the read control FIFO is in a non-empty state. The read data control unit includes a read data logic unit and multiple asynchronous FIFOs. The read data logic unit is used to generate a fourth control logic based on the read address read by the data read control unit. The multiple asynchronous FIFOs in the read data control unit are used to read the corresponding data from the storage module based on the fourth control logic and the read data address. The data output control unit is used to select data read from multiple asynchronous FIFOs and transmit the selected data to the interactive control module.

7. The system-level cache circuit according to claim 4, characterized in that, The storage module includes a first-level storage unit, a second-level storage unit, and a third-level storage unit; The first-level storage unit includes multiple memories, and the second-level storage unit includes N first-level storage units; The storage module includes N third-level storage units, and each third-level storage unit contains N second-level storage units, where N is greater than 1; The write data is selected to be written to the first-level storage unit, the second-level storage unit, or the third-level storage unit based on the value of the write address bit in the write address signal.

8. A reading and writing method, characterized in that, The read / write method is implemented in the system-level cache circuit as described in any one of claims 1 to 7, and the read / write method includes: The interactive control module receives data signals transmitted from the bus and parses the data signals to obtain read / write control signals; The read / write control module generates a chip select control signal based on the read / write control signal, and selects different levels of memory in the storage module based on the chip select control signal, and caches the data from the bus into the selected memory. The read / write control module reads data from the storage module via the chip select control signal and sends the read data to the interactive control module; The interactive control module transmits the read data to the bus.

9. The read / write method according to claim 8, characterized in that, The read / write control module includes a write address control unit and a write data control unit. The write address control unit includes a write address logic unit and multiple asynchronous FIFOs, and the write data control unit includes a write data logic unit and multiple asynchronous FIFOs. The read / write control module generates a chip select control signal based on the read / write control signal. The read / write control module then selects different levels of memory in the storage module based on the chip select control signal, and caches data from the bus into the selected memory, including: The write address logic unit generates first control logic based on the read / write control signal; The multiple asynchronous FIFOs in the write address control unit obtain write address signals according to the first control logic and the read / write control signals, and send the write address signals to the storage module; The storage module obtains the write address of the data according to the write address signal; The write data logic unit generates second control logic based on the read / write control signal; The multiple asynchronous FIFOs in the write data control unit obtain write data according to the second control logic and the read / write control signal, and send the write data to the storage module; The storage module caches the written data to the corresponding address in the storage module according to the write address signal.

10. The read / write method according to claim 8, characterized in that, The read / write control module further includes a read address control unit and a read data control unit. The read address control unit includes a read address logic unit and multiple asynchronous FIFOs. The read / write control module also includes a read control FIFO, a data readout control unit, a read data control unit, and a data output control unit connected in sequence. The read data control unit includes a read data logic unit and multiple asynchronous FIFOs. The read / write control module reads data from the storage module via the chip select control signal and sends the read data to the interactive control module, including: The read address logic unit generates third control logic based on the read / write control signal; The multiple asynchronous FIFOs in the read address control unit obtain read address signals according to the third control logic and the read / write control signals, and send the read address signals to the storage module; The storage module is used to obtain the address of the read data according to the read address signal; The read control FIFO buffers each read address according to the read / write control signal, and the data readout control unit reads each read address when the read control FIFO is not empty. The read data logic unit generates a fourth control logic based on the read address read by the data read control unit, and the multiple asynchronous FIFOs in the read data control unit read the corresponding data from the storage module according to the fourth control logic and the read data address; The data output control unit selects data read from multiple asynchronous FIFOs and transmits the selected data to the interactive control module.

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