Storage device, storage system including the same, and operating method thereof

Abstract

The present disclosure relates to a storage system. The storage system includes a host device including a command queue configured to queue commands; a non-volatile memory device configured to store a mapping information dataset for converting logical addresses to physical addresses; a storage controller configured to store a mapping table set in a volatile memory based on the mapping information dataset, wherein the host device can be configured to send a first logical address range associated with a first command to be queued in the command queue of the host device, and the storage controller can be configured to receive the first logical address range and store a first mapping table associated with a first mapping information data corresponding to the first logical address range among the mapping information dataset in the volatile memory.

Description

Technical Field

[0001] This disclosure relates to a storage device, a storage system including the storage device, and a method of operating the same. Background Technology

[0002] Semiconductor memories can be divided into volatile memory devices (such as static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM)) and non-volatile memory devices (such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM)). Volatile memory devices lose stored data when power is off, while non-volatile memory devices retain stored data when power is off. Summary of the Invention

[0003] This disclosure relates to a storage controller for reducing latency that may occur due to mapping loading that translates logical addresses into physical addresses, a storage device including the controller, and a storage system.

[0004] The problems to be solved by this disclosure are not limited to those described above, and other problems not mentioned can be clearly understood by those skilled in the art based on the following description of this disclosure.

[0005] According to some aspects, a storage system may include: a host device including a command queue configured to queue commands; a non-volatile storage device configured to store a mapping information dataset for translating logical addresses into physical addresses; and a storage controller configured to store a set of mapping tables in volatile memory based on the mapping information dataset, wherein the host device may be configured to send to the storage controller a first logical address range associated with a first command to be queued in the host device's command queue, and the storage controller may be configured to receive the first logical address range and store a first mapping table associated with first mapping information data corresponding to the first logical address range in the mapping information dataset in the volatile memory.

[0006] According to some aspects, a storage device may include: a non-volatile storage device configured to store a mapping information dataset for translating logical addresses into physical addresses; and a storage controller configured to store a set of mapping tables in volatile memory based on the mapping information dataset, wherein the storage controller may be configured to receive a first logical address range associated with a first command to be queued in a command queue of a host device, and to store a first mapping table associated with first mapping information data in the mapping information dataset corresponding to the first logical address range in the volatile memory.

[0007] According to some aspects, a method of operating a storage system includes a host device, a non-volatile storage device, and a storage controller. The host device includes a command queue configured to queue commands, the non-volatile storage device is configured to store a mapping information dataset for translating logical addresses into physical addresses, and the storage controller is configured to store a set of mapping tables in volatile memory based on the mapping information dataset. The method may include: the host device sending a first logical address range associated with a first command to be queued in the command queue to the storage controller; the storage controller receiving the first logical address range from the host device; and the storage controller storing a first mapping table associated with first mapping information data corresponding to the first logical address range in the mapping information dataset in the volatile memory.

[0008] According to various embodiments of this disclosure, by preloading the mapping table corresponding to the logical address associated with the command into volatile memory before obtaining the command, the latency that may occur due to mapping loading can be minimized.

[0009] According to various embodiments of this disclosure, if a mapping table corresponding to one or more logical addresses in the logical address list is already stored in volatile memory, unnecessary overwriting can be prevented by excluding the mapping table from the sacrificial data.

[0010] According to various embodiments of this disclosure, the problem of mapping tables corresponding to high-priority logical addresses being overwritten can be prevented.

[0011] According to various embodiments of this disclosure, by determining the sacrifice data based on information associated with at least one mapping table to which the refresh operation is to be performed, unnecessary resource consumption required to perform the refresh operation before overwriting the sacrifice data can be minimized.

[0012] The effects that can be obtained through this disclosure are not limited to those described above. Anyone skilled in the art will clearly understand any unmentioned technical effects based on the description of this disclosure set forth below. Attached Figure Description

[0013] The above and other embodiments and features of this disclosure will become clearer by referring to the accompanying drawings, which describe exemplary embodiments of the present disclosure in detail.

[0014] Figure 1 This is a diagram illustrating a storage system according to an embodiment of the present disclosure;

[0015] Figure 2 This is a diagram illustrating a non-volatile memory according to an embodiment of the present disclosure;

[0016] Figure 3 This is a perspective view showing a memory block according to an embodiment of the present disclosure;

[0017] Figure 4 This is a circuit diagram showing a memory block according to an embodiment of the present disclosure;

[0018] Figure 5A This is a diagram illustrating a detailed configuration of a storage system according to an embodiment of the present disclosure;

[0019] Figure 5B This is a diagram illustrating a detailed configuration of a storage system according to another embodiment of the present disclosure;

[0020] Figure 6 This is a flowchart illustrating an operation method of a storage system according to an embodiment of the present disclosure;

[0021] Figure 7A This illustrates one embodiment according to the present disclosure. Figure 6 A diagram showing an example of the mapping prompt command for step S610;

[0022] Figure 7B This illustrates another embodiment according to the present disclosure. Figure 6 A diagram showing an example of the mapping prompt command for step S610;

[0023] Figure 8A This is for illustrating an embodiment according to the present disclosure. Figure 6 The diagrams for steps S620 and S630;

[0024] Figure 8B This is for illustrating another embodiment according to the present disclosure. Figure 6 The diagrams for steps S620 and S630;

[0025] Figure 9 This is for illustrating an embodiment according to the present disclosure. Figure 6 The diagrams for steps S640 and S650;

[0026] Figure 10 This describes in detail one embodiment according to the present disclosure. Figure 6Flowchart of step S650;

[0027] Figure 11A and Figure 11B This is a diagram used to illustrate the process of identifying and covering sacrificed data;

[0028] Figure 12 This is for illustrating one embodiment according to the present disclosure. Figure 6 The diagrams for steps S660 and S670;

[0029] Figure 13 This illustrates one embodiment according to the present disclosure. Figure 6 The diagram for step S680; and

[0030] Figure 14 This is for illustrating one embodiment according to the present disclosure. Figure 6 The diagram for step S690. Detailed Implementation

[0031] In the following text, reference will be made to Figures 1 to 14 Various embodiments of this disclosure are described. Throughout the specification, the same reference numerals may refer to the same components.

[0032] Figure 1 This is a diagram illustrating a storage system 10 according to an embodiment of the present disclosure. (Refer to...) Figure 1 The storage system 10 may include a host device 20 and a storage device 100. The host device 20 and the storage device 100 may send and receive data and / or signals to each other.

[0033] The host device 20 may include a host controller 21 and a host memory 22. The host memory 22 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 100. The host memory 22 may include a command queue, which will be discussed later. Figure 5A and Figure 5B The host memory 22 can store a list of address ranges, which will be described later. Figure 7A Describe it.

[0034] According to one embodiment, the host controller 21 and the host memory 22 can be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 21 and the host memory 22 can be integrated into the same semiconductor chip. For example, the host controller 21 can be one of multiple modules disposed in an application processor, and the application processor can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 22 can be embedded memory disposed within the application processor, or it can be volatile memory or a memory module disposed outside the application processor.

[0035] In one embodiment, the host controller 21 may manage the following operations: storing data from the host memory 22 into non-volatile storage devices 300_1, 300_2, and 300_3 via the storage controller 200, or storing data from the storage devices 300_1, 300_2, and 300_3 into the host memory 22 via the storage controller 200.

[0036] The host controller 21 can generate commands to be executed in the storage device 100 (e.g., dataset management commands, read commands, write commands, TRIM commands, etc.) and store (e.g., queue them) in the host memory 22 (e.g., command queues in the host memory 22).

[0037] Storage device 100 may include storage controller 200 and multiple non-volatile storage devices (NVMs) 300_1, 300_2, and 300_3. Each of the storage controller 200 and the multiple NVMs 300_1, 300_2, and 300_3 can send and receive data or signals from each other. Although Figure 1 Three non-volatile memory devices 300_1, 300_2, and 300_3 are shown, but this disclosure is not limited thereto, and the storage device 100 may include any number of memory devices. For example, the storage device 100 may include multiple memory devices connected and arranged in an array.

[0038] Storage device 100 may include a storage medium for storing data in response to a request from host device 20. As an example, storage device 100 may include at least one of a solid-state drive (SSD), embedded memory, and removable external memory. If storage device 100 is an SSD, it may be a device conforming to the Non-Volatile Memory Faster (NVMe) standard. If storage device 100 is embedded memory or external memory, it may be a device conforming to the Universal Flash Memory (UFS) or Embedded Multimedia Card (eMMC) standard. Host device 20 and storage device 100 may each generate and transmit data packets according to their respective standard protocols.

[0039] When the non-volatile memory devices 300_1, 300_2, and 300_3 include flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical or bonded vertical) NAND (VNAND) memory array. As another example, the storage device 100 may include various other types of non-volatile and / or volatile memory. For example, the storage device 100 may include at least one of volatile or non-volatile memory, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), and resistive RAM. At least some of the plurality of non-volatile memory devices 300_1, 300_2, and 300_3 may alternatively be volatile memory devices.

[0040] The storage controller 200 may include a host interface 211, a controller interface circuit 212, and a central processing unit (CPU) 213. Furthermore, the storage controller 200 may also include an index read unit (IRU) 214, a flash translation layer (FTL) 215, a buffer memory 216, an error correction code (ECC) engine 217, and internal volatile memory 218. The storage controller 200 may also include working memory, into which the flash translation layer 215 is loaded, and data write and read operations on the non-volatile memory can be controlled by the CPU 213 executing the flash translation layer 215.

[0041] Host interface 211 can send data packets to and receive data packets from host device 20. Data packets sent from host device 20 to host interface 211 may include commands and / or data to be written to or sent to non-volatile storage devices 300_1, 300_2, and 300_3, and data packets sent from host interface 211 to host device 20 may include responses to commands, data read from non-volatile storage devices 300_1, 300_2, and 300_3, etc. Host interface 211 is shown as being included in storage controller 200, but this embodiment is not limited to this example. For example, host interface 211 may be located outside storage controller 200.

[0042] The controller interface circuit 212 can send data to be written to the non-volatile memory devices 300_1, 300_2, and 300_3, or receive data read from the non-volatile memory devices 300_1, 300_2, and 300_3. The controller interface circuit 212 can be implemented to conform to standard protocols such as toggle or ONFI.

[0043] The flash translation layer 215 can perform various functions, such as address mapping, wear leveling, and garbage collection. For example, the flash translation layer 215 can obtain the physical address corresponding to the logical address from the logical address. Furthermore, the buffer memory 216 can temporarily store data to be written to storage devices 300_1, 300_2, and 300_3, or data to be read from non-volatile storage devices 300_1, 300_2, and 300_3. The buffer memory 216 can be configured to be located within the storage controller 200, but it can also be placed outside the storage controller 200.

[0044] ECC engine 217 can perform error detection and correction functions on data read from non-volatile storage devices 300_1, 300_2, and 300_3. More specifically, ECC engine 217 can generate parity bits for write data to be written to non-volatile storage devices 300_1, 300_2, and 300_3, and the parity bits generated in this way can be stored together with the write data in non-volatile storage devices 300_1, 300_2, and 300_3. When reading data from non-volatile storage devices 300_1, 300_2, and 300_3, ECC engine 217 can use the parity bits read together with the read data to correct errors in the read data, and output the error-corrected read data.

[0045] Figure 2 This is a diagram illustrating a non-volatile memory according to an embodiment of the present disclosure. Although Figure 2 Each component is shown and described as including Figure 1 In a non-volatile storage device 300_1, but it should be understood that, referring to Figure 2 The described embodiments can be applied to... Figure 1 The storage controller 200 is connected to any non-volatile storage device.

[0046] Reference Figure 2The non-volatile memory device 300_1 may include a memory cell array 321, a voltage generator 322, a control logic circuit 323, a row decoder 340, and a page buffer circuit 350. In another embodiment, the non-volatile memory device 300_1 may also include data input / output circuitry or an input / output interface.

[0047] The memory cell array 321 includes multiple memory cells and can be connected to word lines (WL), serial select lines (SSL), ground select lines (GSL), and multiple bit lines (BL). Specifically, the memory cell array 321 can be connected to the row decoder 340 via word lines WL, serial select lines SSL and ground select lines GSL, and can be connected to the page buffer circuit 350 via multiple bit lines BL.

[0048] The memory cell array 321 may include multiple memory blocks BLK1 to BLKz. Each memory block BLK1 to BLKz may include multiple pages to which memory cells are connected. Each word line WL may be associated with one or more pages.

[0049] Each of the multiple memory blocks BLK1 to BLKz can have a three-dimensional structure or a vertical structure. Specifically, each memory block includes a structure extending along a first direction to a third direction. For example, each memory block includes multiple NAND strings extending along a third direction. In this case, the multiple NAND strings can be configured to be spaced apart at a specific distance along the first direction and a second direction.

[0050] Multiple memory blocks BLK1 to BLKz can be selected by the row decoder 340. For example, the row decoder 340 can select the memory block corresponding to the block address from the multiple memory blocks BLK1 to BLKz.

[0051] Each of the multiple memory blocks BLK1 to BLKz can correspond to a memory controller (e.g., Figure 1 (200 in the text) accesses a specific logical block. For example, a logical block may correspond to at least one physical memory block among multiple memory blocks BLK1 to BLKz. The flash translation layer of the storage controller (e.g., Figure 1 (215) can manage the mapping relationship between logical blocks and multiple memory blocks BLK1 to BLKz, and can use logical blocks to access multiple memory blocks BLK1 to BLKz.

[0052] Each memory cell included in the memory cell array 321 can store at least one bit of data. In one embodiment, the memory cell can be a single-level cell (SLC) that stores one bit of data. In one embodiment, the memory cell can be a multi-level cell (MLC) that stores more than two bits of data, such as an MLC (or two-level cell) that stores two bits of data, a three-level cell (TLC) that stores three bits of data, or a four-level cell (QLC) that stores four bits of data. However, this disclosure is not limited thereto.

[0053] When an erase voltage is applied to the memory cell array 321, multiple memory cells are in an erase state, and when a programming voltage is applied to the memory cell array 321, multiple memory cells can be in a programming state. At this time, each memory cell can have an erase state or at least one programming state distinguished by a threshold voltage. That is, the state of a memory cell can include an erase state and at least one programming state, and the specific state of each memory cell can be either an erase state or at least one programming state.

[0054] The control logic circuit 323 can comprehensively control various operations within the non-volatile memory device 300_1. For example, the control logic circuit 323 can output various control signals based on the command CMD, address ADDR, and control signal CTRL to write data to or read data from the memory cell array 321. The control logic circuit 323 can control multiple programming operations to be performed on multiple pages.

[0055] Various control signals output from the control logic circuit 323 can be provided to the voltage generator 322, the line decoder 340, and the page buffer circuit 350. For example, the control logic circuit 323 can provide the voltage control signal CTRL_vol to the voltage generator 322.

[0056] Voltage generator 322 can be connected to memory cell array 321 via multiple word lines WL. Voltage generator 322 can generate various types of voltages for performing programming, reading, and / or erasing operations on memory cell array 321 based on the voltage control signal CTRL_vol. Voltage generator 322 can generate word line voltages VWL, such as programming voltage, verification voltage, read voltage, erase voltage, etc.

[0057] The programming voltage, verification voltage, read voltage, erase voltage, etc., generated by the voltage generator 322 can be provided to selected word lines among multiple word lines WL. The selected word line can be at least one word line selected by the row address X-ADDR. Each word line in the multiple word lines WL includes multiple pages, and the programming, verification, read operations, etc., performed by the voltage generated by the voltage generator 322 can be performed on a page-by-page basis. For example, the programming voltage (or pulse) and verification voltage (or pulse) can be applied to selected pages within the selected word line, thereby performing programming and verification operations on the selected pages.

[0058] During an erase operation, voltage generator 322 may apply an erase voltage to the wells and / or common source lines of the memory block. Additionally, voltage generator 322 may apply an erase enable voltage (e.g., ground voltage) to all word lines WL of the memory block or to word lines corresponding to some sub-blocks based on the erase address. During an erase verification operation, voltage generator 322 may apply an erase verification voltage to all word lines WL of a memory block, or apply an erase verification voltage to each word line.

[0059] During programming operations, voltage generator 322 can apply a programming voltage to selected word lines among multiple word lines WL, and apply a programming pass voltage to unselected word lines among multiple word lines WL. Furthermore, during programming verification operations, voltage generator 322 can apply a programming verification voltage to selected word lines, and apply a verification pass voltage to unselected word lines.

[0060] During normal read operation, voltage generator 322 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line.

[0061] During a data recovery read operation, voltage generator 322 may apply a read pass voltage to the selected word line and a read voltage to at least one word line adjacent to the selected word line. Alternatively, voltage generator 322 may apply a read voltage to the selected word line and a read pass voltage to at least one word line adjacent to the selected word line.

[0062] The row decoder 340 can select a specific word line among the word lines WL in response to the row address X-ADDR received from the control logic circuit 323. Specifically, during programming operations, the row decoder 340 can provide a programming voltage to the selected word line. Furthermore, the row decoder 340 can select some serial select lines SSL or some ground select lines GSL in response to the row address X-ADDR received from the control logic circuit 323.

[0063] Page buffer circuit 350 can be connected to memory cell array 321 via multiple bit lines BL. Page buffer circuit 350 can select some bit lines among the multiple bit lines BL in response to a column address Y-ADDR received from control logic circuit 323. During verification operations (e.g., erase verification or program verification) or read operations, page buffer circuit 350 can act as a sense amplifier to sense data stored in selected memory cells via the selected bit lines. Simultaneously, when programming is in progress, page buffer circuit 350 can act as a write driver to input data to be stored in memory cell array 321. Page buffer circuit 350 may include multiple page buffers. In this case, each page buffer can be connected to at least one bit line.

[0064] Page buffer circuit 350 can store data read from memory cell array 321 or data to be stored in memory cell array 321.

[0065] Page buffer circuit 350 may include multiple page buffers, each page buffer connected to multiple bit lines BL. The multiple page buffers may be arranged corresponding to each bit line, and each page buffer may include multiple latches. Hereinafter, page buffer circuit 350 will be defined as including page buffers connected to each bit line. However, embodiments of this disclosure may define this term differently, and as an example, a configuration unit where one page buffer is set to correspond to multiple bit lines and arranged corresponding to each bit line may be defined as a page buffer unit. Page buffer circuit 350 may temporarily store data to be programmed into a selected page during a programming operation and temporarily store data read from the selected page during a read operation.

[0066] The control logic circuit 323, voltage generator 322, line decoder 340, and page buffer circuit 350 may be included in the peripheral circuit.

[0067] Figure 3 This is a perspective view showing a memory block according to an embodiment of the present disclosure, and Figure 4 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0068] Reference Figure 3The memory block BLK may include a stacked ST extending vertically along the direction VD on the upper part of the substrate SUB. For example, the memory block BLK may include a single stacked ST located between the substrate SUB and bit lines BL1, BL2, and BL3. A common source line CSL may be disposed on the substrate SUB, and an insulating film IL extending along the second horizontal direction HD2 may be sequentially disposed along the vertical direction VD in the region of the substrate SUB located between two adjacent common source lines CSL, and the insulating film IL may be spaced apart at a specific distance along the vertical direction VD. A pillar P penetrating the insulating film IL along the vertical direction VD may be disposed in the region of the substrate SUB located between two adjacent common source lines CSL. The pillar may be referred to as a channel via. The pillar P may be formed as a cup shape (or a bottom-closed cylinder) extending in the vertical direction VD. The surface layer S of each pillar P may include a silicon material of the first type and may be used as a channel region. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0069] In the region between two adjacent common source lines CSL, a charge storage layer CS is disposed along the exposed surfaces of the insulating film IL, pillars P, and substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Furthermore, gate electrodes GE (such as select lines GSL and SSL, and word lines WL1 to WL8) may be disposed on the exposed surface of the charge storage layer CS in the region between the two adjacent common source lines CSL. A drain DR may be disposed on each of a plurality of pillars P. Bit lines BL1, BL2, and BL3, extending in a first horizontal direction HD1 and spaced apart at specific distances along a second horizontal direction HD2, are disposed on the drain DR.

[0070] Reference Figure 4 The memory block BLK includes NAND strings NS11 to NS33, and each NAND string (e.g., NS11) may include a series-connected string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST. The transistors SST and GST included in each NAND string, as well as the memory cells MC, may be formed in a structure stacked vertically on a substrate.

[0071] Bit lines BL1, BL2, and BL3 can extend along a first direction, and word lines WL1 to WL8 can extend along a second direction. NAND strings NS11, NS21, and NS31 can be located between the first bit line BL1 and the common source line CSL, NAND strings NS12, NS22, and NS32 can be located between the second bit line BL2 and the common source line CSL, and NAND strings NS13, NS23, and NS33 can be located between the third bit line BL3 and the common source line CSL.

[0072] The string select transistor SST can be connected to the corresponding string select lines SSL1, SSL2, and SSL3. The memory cells MC can be connected to the corresponding word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST can be connected to the corresponding bit lines, and the ground select transistor GST can be connected to the common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines can vary depending on the embodiment.

[0073] Figure 5A This is a diagram illustrating a detailed configuration of a storage system 10 according to an embodiment of the present disclosure, and Figure 5B This is a diagram illustrating a detailed configuration of a storage system 10' according to another embodiment of the present disclosure. Figure 5A and Figure 5B The arrows shown are exemplary, and each component within the storage controller 200 can send and receive data or signals to each other.

[0074] The host memory 22 may include a command queue 23. The host memory 22 may store and manage various types of commands in the form of the command queue 23. At least some of the commands stored in the command queue 23 may be (but are not limited to) read commands, write commands, or TRIM commands.

[0075] Commands stored in command queue 23 may include mapping hint commands. Mapping hint commands may provide information associated with another command (e.g., a read command, a write command, and / or a TRIM command) to be executed in storage controller 200 and / or non-volatile storage device 300_1. For example, a mapping hint command may include information associated with a logical address to be accessed by another command (e.g., the starting block logical address and the number of logical blocks). In one example, a mapping hint command may be a Dataset Management (DSM) command. See below for further details. Figures 7A to 8B This will be described in detail.

[0076] The command queue 23 included in the host memory 22 can be implemented in various forms (such as a single queue, a multi-queue including multiple queues, a priority queue, a circular queue, etc.), and the embodiments are not limited to these examples. The command queue 23 of the host memory 22 can be located in a shared memory region accessible by the storage device (e.g., the storage controller 200 of the storage device).

[0077] The host controller 21 can queue commands to be executed / processed in the storage device into the command queue 23 of the host memory 22. The host controller 21 can notify the storage controller 200 that a new command has been added to the command queue 23. For example, the host controller 21 can notify the storage controller 200 that a new command has been added to the command queue 23 by sending an interrupt signal or the like.

[0078] The host controller 21 can reorder the commands stored in the command queue 23. For example, the order in which commands are executed or processed in the command queue 23 may not match the order in which they are stored in the command queue 23.

[0079] Non-volatile storage device 300_1 may store a dataset 310 of mapping information used to translate logical addresses to physical addresses. Similarly, volatile memory 230 may store a set 232 of mapping tables (MTs) used to translate logical addresses to physical addresses. The set 232 of mapping tables stored in volatile memory 230 may be loaded / stored by storage controller 200.

[0080] The storage controller 200 can store a mapping table set 232 in volatile memory 230 based on the mapping information dataset 310. The storage controller 200 can store / load mapping tables corresponding to at least a portion of the mapping information dataset 310 into volatile memory 230. The storage controller 200 can store / load mapping tables associated with at least a portion of the mapping information dataset 310 into volatile memory 230 based on logical addresses associated with commands received from the host device 20 and / or commands queued in the command queue of the host device 20.

[0081] In one example, the storage controller 200 may receive at least a portion of the mapping information dataset 310 from the non-volatile storage device 300_1, generate a mapping table based on the received portion of the mapping information dataset 310, and load / store the mapping table into the volatile memory 230. In another example, the storage controller 200 may request the non-volatile storage device 300_1 to load / store at least a portion of the mapping information dataset 310 into the volatile memory 230, and the non-volatile storage device 300_1 may, in response to the request from the storage controller 200, load / store the mapping table corresponding to at least a portion of the mapping information dataset 310 into the volatile memory 230.

[0082] Mapping table set 232 may include multiple mapping tables. Each of the multiple mapping tables may include a mapping relationship between a logical address used by the memory controller 200 to access the non-volatile storage device 300_1 and the corresponding physical address of the non-volatile storage device 300_1. For example, each of the multiple mapping tables may include multiple logical addresses and multiple physical addresses corresponding to those multiple logical addresses. The size of the mapping table or the number of logical addresses contained in the mapping table can be arbitrarily set.

[0083] The mapping table set 232 can be generated / stored based on the mapping information dataset 310 stored in the non-volatile storage device 300_1. For example, the mapping information dataset 310 includes mapping information data for converting logical addresses to physical addresses, and multiple mapping tables can be generated based on a portion of the mapping information dataset 310 and stored in the volatile memory 230.

[0084] In various embodiments of this disclosure, the mapping information dataset 310 may include a plurality of logical addresses corresponding to the total number of logical blocks, and a plurality of physical addresses corresponding to the plurality of logical addresses. A logical block may be a logical block used as a basic unit for data input / output, such as the smallest addressable unit used by an operating system or file system to manage storage space and read or write data. That is, the mapping information dataset 310 may include all logical addresses used by the storage controller 200 to access the non-volatile storage device 300_1, and the physical addresses corresponding to all logical addresses.

[0085] In various embodiments of this disclosure, the size of the mapping table set 232 may be smaller than the size of the mapping information dataset 310. That is, depending on the circumstances, a specific mapping table corresponding to the logical address used by the storage controller 200 to access the non-volatile storage device 300_1 may not be loaded / stored in the volatile memory 230. Therefore, to address this issue, various embodiments of preloading / stored mapping tables corresponding to the logical addresses referenced by the commands to be retrieved into the volatile memory 230 will be described in detail below.

[0086] The storage controller 200 may include a command processor 221, a processor 222, a prompt provider 223, a mapping accessor 224, a mapping loader 225, and a cache manager 226.

[0087] Reference Figure 5A The storage controller 200 of the storage system 10 may further include volatile memory 230. The volatile memory 230 may correspond to... Figure 1 Internal volatile memory 218.

[0088] Reference Figure 5B The volatile memory 230 of the storage system 10' can be externally connected to the storage controller 200 and the non-volatile storage device 300_1.

[0089] In one example Figure 5A and Figure 5B The volatile memory 230 can be DRAM, but is not limited to it.

[0090] In one example, command processor 221 and prompt provider 223 may be included in the host interface circuitry of storage controller 200 (e.g., Figure 1 In 211), the mapping accessor 224, mapping loader 225, and cache manager 226 may be included in the flash translation layer (e.g., Figure 1 In 215). In one example, processor 222 may correspond to Figure 1 CPU 213. Processor 222 may include one or more processors.

[0091] Command processor 221, processor 222, prompt provider 223, map accessor 224, map loader 225, and cache manager 226 may include or be implemented as processing circuitry. Processing circuitry may include a combination of hardware and software, such as hardware including logic circuitry, a processor executing software, or a combination thereof. For example, processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic device (PLD), a microprocessor, and an application-specific integrated circuit (ASIC).

[0092] Command processor 221 can check whether a new command is stored in command queue 23 by receiving a signal from host controller 21 or by periodically accessing command queue 23.

[0093] Command processor 221 can retrieve commands queued in command queue 23. Command processor 221 can retrieve commands sequentially according to the order in which they are queued in command queue 23. Additionally or alternatively, command processor can retrieve commands based on the priority of commands queued in command queue 23.

[0094] Command processor 221 can obtain information required by the storage controller 200 and / or non-volatile storage device 300_1 to perform a specific operation associated with the command by acquiring the command, such as command code (opcode), command identifier CID, logical block address LBA (e.g., a logical address in host memory and / or a logical address in non-volatile storage device 300_1), starting logical block address SLBA and number of logical blocks NLB, data length, flags and options, priority information (e.g., priority), and error check codes, etc.

[0095] Command processor 221 can send the acquired command to processor 222. For example, command processor 221 can pass at least some information to processor 222 required to perform a specific operation associated with the command.

[0096] Processor 222 can process commands received from command processor 221. For example, processor 222 can perform read operations, write operations, or page copy operations. Processor 222 can be implemented in hardware and / or software.

[0097] Processor 222 can obtain the logical address associated with a command for non-volatile memory device 300_1. Processor 222 can send the obtained logical address to mapping accessor 224. Processor 222 can request the physical address corresponding to the obtained logical address from mapping accessor 224.

[0098] Please refer to later Figure 12 The operation of command processor 221, processor 222 and mapping accessor 224 is described in detail.

[0099] Command processor 221 can retrieve mapped hint commands queued in command queue 23 and pass them to hint provider 223. For example, when command processor 221 is retrieving a previous command or when processor 222 is processing a previous command, hint provider 223 can retrieve mapped hint commands queued in command queue 23. Hint provider 223 can, based on the retrieved mapped hint commands, obtain a logical address or logical address range associated with one or more other commands (e.g., subsequent commands) to be queued (or already queued) in command queue 23. For example, hint provider 223 can obtain a logical address of non-volatile storage device 300_1 to be accessed during processing of a subsequent command, or a logical address range including such a logical address. Hint provider 223 can obtain the aforementioned logical address range by obtaining the starting logical block address and the number of logical blocks associated with one or more other commands queued in command queue 23.

[0100] Furthermore, the prompt provider 223 can also obtain priority information (e.g., priority) of the logical address range obtained based on the mapped prompt command. See later. Figure 8A and Figure 8B The operation of the prompt provider 223 associated with the mapping prompt command will be described in detail.

[0101] The prompt provider 223 can send the obtained information to the map loader 225 and / or the cache manager 226. The prompt provider 223 can send a request to the map loader 225 to load / store the map table corresponding to the obtained information into the volatile memory 230. The prompt provider 223 can send a request to the cache manager 226 to select / determine which data to sacrifice to overwrite the map table. See below for further details. Figures 9 to 11B This will be described in detail.

[0102] Mapping accessor 224 can access volatile memory 230 to obtain mapping tables. For example, mapping accessor 224 can obtain a portion of the mapping table set 232 loaded / stored in volatile memory 230. Mapping accessor 224 can obtain mapping tables based on requests from one or more processors 222.

[0103] Mapping accessor 224 can request a mapping table from volatile memory 230 corresponding to a logical address (or logical address range) received from processor 222. If the mapping table corresponding to the received logical address (or logical address range) is loaded / stored in volatile memory 230, mapping accessor 224 can obtain the corresponding mapping table and determine the physical address corresponding to the specific logical address of non-volatile storage device 300_1 from the obtained mapping table. Mapping accessor 224 can send the determined physical address to processor 222, and processor 222 can use the received physical address to process commands.

[0104] If the mapping table corresponding to the received logical address (or logical address range) is not loaded / stored in the volatile memory 230 (a mapping miss occurs), the mapping accessor 224 may request the mapping loader 225 to load / store the mapping table corresponding to the received logical address (or logical address range) in the volatile memory 230.

[0105] Map loader 225 may send a load request to non-volatile storage device 300_1 in response to a request from map accessor 224. In response to the map loader 225 sending a load request to non-volatile storage device 300_1, at least one mapping table corresponding to at least a portion of the mapping information dataset 310 stored in non-volatile storage device 300_1 can be loaded / stored in volatile memory 230. In this case, there may be risks, such as command execution being suspended during the time required to load / store the mapping table in volatile memory 230, and delays due to the loading / store of the mapping table.

[0106] Map loader 225 can send a load request to non-volatile memory device 300_1 in response to a request from prompt provider 223. This reduces the latency in loading the mapping table into volatile memory 230 when the mapping table corresponding to the logical address received at the time of the processor 222's request (e.g., the logical address to be accessed by a subsequent command) has not yet been loaded into volatile memory 230. (See below for further details.) Figures 6 to 9 This will be described in detail.

[0107] Cache manager 226 can determine the location of the loading / storing mapping table within volatile memory 230. For example, cache manager 226 can determine the sacrificed data in mapping table set 232 within volatile memory 230. Cache manager 226 can send the determined location within volatile memory 230 to mapping loader 225. In response to receiving the location in volatile memory 230 from cache manager 226, mapping loader 225 can store (e.g., overwrite) the mapping table corresponding to the mapping information data received from non-volatile storage device 300_1 at the received location, or control non-volatile storage device 300_1 to store the mapping table at the received location. See below for further details. Figure 11A and Figure 11B This will be described in detail.

[0108] In one embodiment, Figure 5A The non-volatile storage device 300_1 can respond to a request from the storage controller 200 by sending mapping information data corresponding to a specific logical address range in the mapping information dataset 310 to the storage controller 200, and the storage controller 200 can load / store the mapping table corresponding to the mapping information data received from the non-volatile storage device 300_1 into the volatile memory 230.

[0109] In one embodiment, Figure 5BThe non-volatile storage device 300_1 can, in response to a request from the storage controller 200, load / store a mapping table into the volatile memory 230 using mapping information data corresponding to a specific logical address range in the mapping information dataset 310.

[0110] Figure 6 This is a flowchart illustrating an operation method 600 of a storage system according to an embodiment of the present disclosure. The method of operating the storage system 600 can be... Figure 5A Storage system 10 or Figure 5B The storage system 10' is executed.

[0111] The following reference Figure 5A , Figure 5B and Figure 6 Host device 20 (e.g., host controller 21) can queue mapping hint commands and commands to be executed on storage controller 200 into command queue 23 (S610). Host device 20 can generate mapping hint commands based on information associated with one or more commands to be executed on storage controller 200. For example, host device 20 can generate mapping hint commands that include information associated with the logical address (e.g., starting block logical address and number of logical blocks) to be accessed by one or more commands to be executed on storage controller 200. (See below for further details.) Figure 7A and Figure 7B Here is a detailed example of a mapping prompt command generated by host device 20.

[0112] Storage controller 200 can retrieve mapping hint commands queued in command queue 23 from the host device (S620). In one embodiment, the mapping hint command can be retrieved from the host device before generating a subsequent command associated with the mapping hint command, or before the subsequent command is queued in command queue 23.

[0113] The storage controller 200 can obtain the logical address or logical address range (e.g., the starting block logical address and the number of logical blocks) associated with the commands queued in the host device's command queue (S630). See below for further details. Figure 8A and Figure 8B This will be described in detail.

[0114] Unlike the embodiments of steps S620 and S630 described above, the storage controller can obtain the logical address range associated with commands queued in the host device's command queue in various ways. For example, the host device can send a mapping hint command containing information associated with the logical address range to the storage controller, send the logical address range to the storage controller using an out-of-band (OOB) channel, or send the logical address range to the storage controller by setting a Peripheral Component Interconnect (PCI) register. This enables the storage controller to obtain the logical address range associated with commands queued in the host device's command queue.

[0115] The memory controller 200 may request a mapping table from the non-volatile memory device 300_1 corresponding to the logical address or logical address range obtained in step S630 (S640). (See later...) Figure 9 This will be described in detail. Alternatively, the storage controller 200 may request mapping information data corresponding to the logical address or logical address range obtained in step S630 from the non-volatile storage device 300_1, and receive the mapping information data to generate a mapping table.

[0116] In response to the request in step S640, the non-volatile storage device 300_1 and / or the storage controller 200 may load / store the mapping table associated with the mapping information data corresponding to the logical address or logical address range obtained in step S630 into the volatile memory 230 (S650). See below for further details. Figure 10 , Figure 11A and Figure 11B This will be described in detail.

[0117] Storage controller 200 can obtain commands queued in command queue 23 of host device 20 (S660). Storage controller 200 can obtain a logical address from the command obtained in step S660 (S670). See below for further details. Figure 12 This will be described in detail.

[0118] The storage controller 200 can determine the physical address corresponding to the obtained logical address of the non-volatile storage device 300_1 based on the mapping table loaded / stored in step S650 (S680). (See below for further details.) Figure 13 This will be described in detail.

[0119] The storage controller 200 can execute operations based on the physical address determined in step S680, according to a command (S690). See below for further details. Figure 14 This will be described in detail.

[0120] Figure 7A This illustrates one embodiment according to the present disclosure. Figure 6 The example diagram of the mapping prompt command 700 for step S610, and... Figure 7B This illustrates another embodiment according to the present disclosure. Figure 6 The following is an example diagram of the mapping prompt command 700' for step S610.

[0121] Reference Figure 7A The mapping prompt command 700 may include a data pointer 701, address range quantity information 702, and attribute information 703. The mapping prompt command 700 may be a dataset management command.

[0122] Data pointer 701 may point to a logical block address LBAa in host memory 22 where address range list data 710 is stored. Data pointer 701 may indicate the logical block address of one or more address ranges of address range list data 710. For example, data pointer 701 may point to one or more logical block addresses of one or more address ranges associated with one or more commands (e.g., read command, write command, trim command, etc.).

[0123] Address range quantity information 702 can indicate the number of address ranges indicated by data pointer 701. For example, address range quantity information 702 may include the number of logical block addresses LBAa indicated by data pointer 701.

[0124] Attribute information 703 may indicate attributes of the mapping hint command 700. For example, attribute information 703 may include mapping hint bit 704, which indicates whether a mapping table associated with the logical address (e.g., starting logical block address 723 and logical block number 722) stored in the logical block address LBAa indicated by data pointer 701 is stored in volatile memory (e.g., ...). Figure 5A and Figure 5B In (230). Mapping hint bit 704 can contain one or more bits.

[0125] The address range list data 710 stored in host memory 22 may include information about multiple address ranges RANGE 0 to RANGE k (where k is a natural number greater than or equal to 1). For example, information about each of the multiple address ranges RANGE 0 to RANGE k may include context attributes 720 and logical addresses (e.g., the number of logical blocks 722 and the starting logical block address 723).

[0126] Context attribute 720 may include priority information 721 for logical addresses (e.g., the number of logical blocks 722 and the starting logical block address 723). For example, priority information 721 may include the priority of the logical address range specified by the number of logical blocks 722 and the starting logical block address 723 from a predetermined number of priorities.

[0127] Priority information 721 can be represented by any number of bits.

[0128] In one embodiment, priority information 721 may reside in an existing data field within the context attribute 720 of the mapping prompt command 700, which serves as a dataset management command. For example, priority information 721 may reside in the data field containing access delay AL information, replacing the access delay AL information. For instance, the data field contains 2 bits, and the values ​​"01", "10", and "11" within the data field represent the lowest, medium, and highest priority, respectively. The value "00" may indicate that no priority is specified.

[0129] In one embodiment, priority information 721 may be located in an existing data field and / or a reserved field within context attribute 720. For example, priority information 721 may be located in the data field where access delay information is located, and may also be located in a reserved field. For example, priority information 721 may be represented by 4 bits, allowing for the representation of 15 priorities (e.g., bits “0001” to “1111”) and a state where no priority is specified (e.g., bits “0000”).

[0130] The address range list data 710 stored in the host memory 22 can be controlled by a host controller (e.g., connected to the host memory 22). Figure 1 (21) Update. For example, the host controller can update the priority information 721 in the logical address range.

[0131] Reference Figure 7B ,and Figure 7A Unlike the previous one, the mapping hint command '700' can include a list of address ranges 710.

[0132] Figure 8A This is for explaining one embodiment according to the present disclosure. Figure 6 The diagrams for steps S620 and S630, and Figure 8B This is for explaining another embodiment according to the present disclosure. Figure 6 The diagrams for steps S620 and S630. Figure 8A This can be used for explanation and usage. Figure 7A The diagram shows the operation steps S620 and S630 of the mapping prompt command 700, and... Figure 8B This can be used for explanation and usage. Figure 7BThe diagram shows the operation of steps S620 and S630 of the mapping prompt command 700'.

[0133] Reference Figure 8A Command processor 221 can retrieve the mapped prompt command 700 queued in the command queue 23 of host memory 22 of host device 20. Command processor 221 can then pass the retrieved mapped prompt command 700 to prompt provider 223.

[0134] Mapping hint command 700 can be used to direct to the storage controller (e.g., Figure 5A and Figure 5B The 200) provides commands that are associated with one or more logical address ranges. In one example, the mapping prompt command 700 may point to one or more logical block addresses within host memory 22, where logical addresses (or logical address ranges) associated with the first command CMD1 and the second command CMD2 are stored. The first command CMD1 and the second command CMD2 may be commands to be executed / processed by the storage controller in the subsequent order of the mapping prompt command 700. For example, after the storage controller processes the mapping prompt command 700, the second command CMD2 may be processed in the next order after the first command CMD1, and the mapping prompt command and / or the third command CMD3 may be processed in the next order after the second command CMD2. Each of the first command CMD1 and the second command CMD2 may be (but is not limited to) a read command, a write command, or a trim command. The first command CMD1 and the second command CMD2 are shown to be queued together with the mapping prompt command 700, but are not limited thereto, and the first command CMD1 and the second command CMD2 may be queued in the command queue 23 after the mapping prompt command 700 is dequeued and processed in the storage controller.

[0135] The prompt provider 223 can obtain one or more logical addresses 820 (or one or more logical address ranges including one or more logical addresses 820) associated with one or more commands queued in the command queue 23 based on the mapping prompt command 700. For example, the one or more logical addresses 820 obtained by the prompt provider 223 may include, but are not limited to, a first logical address (or logical address range) associated with the first command CMD1 and a second logical address (or logical address range) associated with the second command CMD2, and may include any number of logical addresses or logical address ranges.

[0136] In one embodiment, prompt provider 223 sends a read request 810 to host device 20 (or host controller 21). The read request 810 includes a logical block address LBAa in host memory 22 indicated by mapping prompt command 700, thereby obtaining one or more logical addresses 820 (or one or more logical address ranges including one or more logical addresses 820) from the region of host memory 22 corresponding to the logical block address LBAa. For example, mapping prompt command 700 may include a first logical block address in host memory 22 (where a first logical address associated with a first command CMD1 is stored) and a second logical block address in host memory 22 (where a second logical address associated with a second command CMD2 is stored). Host device 20 (or host controller 21) may, in response to read request 810 from prompt provider 223, send logical addresses 820 (or logical address ranges) associated with the first command CMD1 and the second command CMD2 to prompt provider 223. Figure 8A Logical address 820 can correspond to Figure 7A The number of logical blocks is 722 and the starting logical block address is 723.

[0137] Furthermore, in response to a read request 810 from the prompt provider 223, the host device 20 (or host controller 21) may send priority information 830 of logical address 820 to the prompt provider 223. The priority information 830 of logical address 820 may include the priority of each logical address (or logical address range) among a predetermined number of priorities.

[0138] Reference Figure 8B Command processor 221 can retrieve the mapped prompt command 700' queued in command queue 23 of host memory 22 of host device 20, and send the retrieved mapped prompt command 700' to prompt provider 223. Thus, prompt provider 223 can obtain one or more logical addresses or logical address ranges included in the mapped prompt command 700' (e.g., a first logical address range associated with the first command CMD1 and a second logical address range associated with the second command CMD2). Furthermore, prompt provider 223 can obtain priority information for one or more logical addresses (or logical address ranges).

[0139] Compared with the above reference Figure 8A and Figure 8BDepending on the described embodiment, host device 20 can send the logical address 820 associated with a command to be queued in command queue 23 of host device 20 to the storage controller in various ways. For example, host device 20 can send a mapping hint command to the storage controller, including information associated with logical address 820, send logical address 820 to the storage controller using an out-of-band OOB channel, or send logical address 820 to the storage controller by setting a PCI register.

[0140] Figure 9 This is for explaining one embodiment according to the present disclosure. Figure 6 The diagrams for steps S640 and S650.

[0141] Storage controller (e.g., Figure 5A and Figure 5B (200) can request a connection to the non-volatile storage device 300_1. Figure 6 The logical address obtained at step S630 (e.g., Figure 8A The mapping table corresponding to the 820 (or logical address range).

[0142] Prompt provider 223 can send to map loader 225 Figure 6 The logical address obtained at step S630.

[0143] In one embodiment, prompt provider 223 (or Figure 1 The host interface circuit 211 can generate including Figure 6 The logical address list 910, which is one or more logical addresses or one or more logical address ranges obtained at step S630, is sent to the mapping loader 225 (or Figure 1 The generated logical address list 910 is sent to the flash translation layer 215. For example, the logical address list 910 may include... Figure 7A and Figure 7B The first logical address LOG1 associated with the first command CMD1 and the second logical address LOG2 associated with the second command CMD2.

[0144] Map loader 225 (or Figure 1 The flash translation layer 215 can send a mapping load request 920 to the non-volatile storage device 300_1 in response to receiving a logical address list 910, to request loading / storing at least one mapping table 930 associated with mapping information data corresponding to one or more logical addresses included in the received logical address list 910.

[0145] In one embodiment, the mapping load request 920 may include a logical address associated with a specific instruction (e.g., a starting block logical address and a number of logical blocks). The mapping loader 225 may store at least one mapping table in the volatile memory 230 by requesting at least one mapping table associated with mapping information data corresponding to the logical address and number of logical blocks associated with a specific instruction from the non-volatile memory device 300_1.

[0146] In one embodiment, the non-volatile storage device 300_1 may respond to a response from a map loader 225 or a memory controller (e.g., Figure 5B The mapping load request 920 of (200) sends at least one mapping table 930 to the volatile memory 230. For example, at least one mapping table 930 may include a first mapping table MT1 and a second mapping table MT2, wherein the first mapping table MT1 includes a first physical address PHY1 corresponding to a first logical address LOG1, and the second mapping table MT2 includes a second physical address PHY2 corresponding to a second logical address LOG2.

[0147] In another embodiment, the non-volatile storage device 300_1 may respond to a mapping loader 225 or a memory controller (e.g., Figure 5A The mapping load request 920 of the 200) sends at least one mapping table 930 to the storage controller (or the volatile memory 230 of the storage controller).

[0148] In another embodiment, the non-volatile storage device 300_1 may respond to a response from the map loader 225 or the memory controller (e.g., Figure 5A The mapping load request 920 of (200) sends a portion of the mapping information dataset to the storage controller, and the storage controller can generate a mapping table 930 associated with the received portion of the mapping information dataset and store the mapping table 930 in the volatile memory 230.

[0149] Figure 10 A detailed illustration of an embodiment according to this disclosure is provided. Figure 6 The flowchart of step S650, and Figure 11A and Figure 11B This is a diagram used to explain the process of identifying and covering the sacrifice data 232_1 and 232_2.

[0150] Reference Figure 10 and Figure 11A The cache manager 226 can determine the sacrificed data 232_1 and 232_2 based on the priority of each of the multiple mapping tables (S652). Figure 11AIn this embodiment, sacrificial data 232_1 and 232_2 are shown as including two mapping tables, but the embodiments are not limited to this example. For example, the number of mapping tables included in sacrificial data 232_1 and 232_2 may be determined based on the number of one or more mapping tables 930 to be transferred from non-volatile storage device 300_1 to volatile memory 230.

[0151] In one embodiment, cache manager 226 may store priority information 1120 (e.g., priority) of each mapping table included in mapping table set 232 in association with each mapping table, and determine sacrificed data 232_1 and 232_2 based on the stored priority information 1120. For example, cache manager 226 may determine the mapping table with the lowest priority in mapping table set 232 (e.g., the mapping table with priority 0) as sacrificed data 232_1 and 232_2. Cache manager 226 may select multiple mapping tables as sacrificed data 232_1 and 232_2 in ascending order of priority.

[0152] The prompt provider 223 can be based on mapped prompt commands (e.g., Figure 8A The cache manager 226 generates priority information 1110 and sends the generated priority information 1110 to the cache manager 220. The hint provider 223 can determine the priority of each of the one or more mapping tables corresponding to the logical address based on the priority information 830 of the logical address or logical address range included in the mapping hint command (e.g., the priority of the logical address), generate a priority information list 1110 including the priority of each of the one or more mapping tables, and send the priority information list 1110 to the cache manager 226. The cache manager 226 can obtain the priority information list 1110 and update the priority information 1120 based on the obtained priority information list 1110.

[0153] In one embodiment, the priority of each logical address or logical address range and the priority of the mapping table set 232 correspond to any one of a predetermined number (e.g., three) priorities, and the prompt provider 223 can use the priority of a specific logical address (or logical address range) as the priority of the mapping table corresponding to that logical address (or logical address range).

[0154] In another embodiment, the hint provider 223 can determine the priority of a particular mapping table based on multiple priorities of multiple logical addresses (or logical address ranges) associated with that particular mapping table. For example, the hint provider 223 can use the highest priority among the multiple priorities of the multiple logical addresses (or logical address ranges) as the priority of the corresponding mapping table. This prevents the mapping table corresponding to a high-priority logical address from being overwritten. In another example, the hint provider 223 can use the lowest priority among the multiple priorities as the priority of the mapping table, or it can use the average or median of the multiple priorities as the priority.

[0155] Additionally or alternatively, cache manager 226 may obtain multiple logical addresses (or logical address ranges) associated with multiple commands queued in the command queue, and determine the sacrificed data 232_1 and 232_2 based on the logical addresses. For example, cache manager 226 may determine a portion of the data other than the mapping table corresponding to the multiple logical addresses (or logical address ranges) obtained from mapping table set 232 as sacrificed data 232_1 and 232_2. That is, if the mapping table corresponding to one or more logical addresses in logical address list 910 is already stored in volatile memory 230, unnecessary overwriting can be prevented by excluding that mapping table from the sacrificed data 232_1 and 232_2.

[0156] Alternatively, cache manager 226 may exclude the mapping tables to be refreshed from the sacrificed data 232_1 and 232_2. This minimizes unnecessary resource consumption caused by performing refresh operations before overwriting the sacrificed data 232_1 and 232_2.

[0157] The cache manager 226 can send information 1130 associated with the determined sacrifice data 232_1 and 232_2 to the map loader 225.

[0158] Map loader 225 can send a mapping load request 920 to non-volatile storage device 300_1. The mapping load request 920 sent by mapping loader 225 may include information 1130 associated with the sacrificed data 232_1 and 232_2. For example, the mapping load request 920 may include the addresses of the sacrificed data 232_1 and 232_2.

[0159] Reference Figure 10 and Figure 11BThe non-volatile storage device 300_1 can load / store one or more mapping tables 930 into the volatile memory 230 in response to receiving a mapping load request 920. For example, the non-volatile storage device 300_1 can load / store one or more mapping tables 930 into the volatile memory 230 by overwriting the determined sacrificial data 232_1 and 232_2 with one or more mapping tables 930 (S654). In another example, the non-volatile storage device 300_1 can send one or more mapping tables 930 to the storage controller, and the storage controller can load / store one or more mapping tables 930 into the volatile memory 230.

[0160] In one embodiment, the storage controller may load / store one or more mapping tables 930 corresponding to the mapping prompt command into the volatile memory 230 in response to an indication in the attribute information of the mapping prompt command that the bit indicating whether to store the mapping table in the volatile memory is equal to a predetermined value (e.g., 1).

[0161] In one embodiment, one or more mapping tables 930 can be loaded / stored in volatile memory 230 substantially simultaneously. In another embodiment, one or more mapping tables 930 can be loaded / stored in volatile memory 230 according to the order of command execution. For example, after loading / saving the first mapping table MT1, the second mapping table MT2 can be loaded / saved in the subsequent order of the first mapping table MT1.

[0162] In one embodiment, one or more mapping tables 930 may be loaded / stored while the storage controller is acquiring or processing commands that were previously processed in the order of one or more commands corresponding to one or more mapping tables 930.

[0163] Reference Figure 11B After overwriting one or more mapping tables 930, in some cases, a portion of one or more mapping tables 930 (e.g., MT2) may correspond to the lowest priority (e.g., 0) in the mapping table set 232 stored in volatile memory 230. In response to one or more mapping tables 930 having a portion in the mapping table set 232 corresponding to the lowest priority, the storage controller can load the mapping table corresponding to the logical address (or logical address range) associated with the next mapping hint command queued in the command queue from the non-volatile storage device, and store the loaded mapping table by overwriting the mapping table based on the next mapping hint command.

[0164] As a summary of the above embodiments, by preloading the mapping table corresponding to the logical address (or logical address range) associated with the command into the volatile memory 230 before obtaining the command, the capacity of the mapping table set 232 can be maintained to be smaller than the mapping information dataset of the non-volatile storage device 300_1 (e.g., Figure 5A and Figure 5B (310), and the mapping table corresponding to the acquired command is preloaded into the volatile memory 230, and thus the latency that may occur if the mapping table is loaded only after the command is acquired can be minimized.

[0165] Figure 12 This is for explaining one embodiment according to the present disclosure. Figure 6 The diagrams for steps S660 and S670, and Figure 13 This is for illustrating in detail one embodiment according to the present disclosure. Figure 6 The diagram for step S680.

[0166] Reference Figure 12 Command processor 221 can retrieve a specific command from command queue 23 (or host device 20). For example, command processor 221 can retrieve the first command CMD1 from command queue 23.

[0167] Command processor 221 can obtain a first logical address LOG1 associated with the first command CMD1 from the acquired first command CMD1. Command processor 221 can send the acquired first logical address LOG1 to processor 222.

[0168] Processor 222 can use the first logical address LOG1 to process the first command CMD1. For example, processor 222 can send the first logical address LOG1 to mapping accessor 224 and request the first physical address PHY1 corresponding to the first logical address LOG1 from mapping accessor 224.

[0169] Reference Figure 12 and Figure 13 In response to receiving the first logical address LOG1, the mapping accessor 224 can obtain the first mapping table MT1 corresponding to the first logical address LOG1 from the mapping table set 232 of the volatile memory 230. The first mapping table MT1 can be loaded into the volatile memory 230 before obtaining the first command CMD1. The first mapping table MT1 may include the first logical address LOG1 and the first physical address PHY1 corresponding to the first logical address LOG1.

[0170] Mapping accessor 224 can obtain the first mapping table MT1 loaded into volatile memory 230, and determine the first physical address PHY1 of non-volatile memory device 300_1 corresponding to the first logical address LOG1 based on the obtained first mapping table MT1.

[0171] Mapping accessor 224 can send the determined first physical address PHY1 to processor 222.

[0172] Figure 14 This is for illustrating an embodiment according to the present disclosure. Figure 6 The diagram for step S690.

[0173] Reference Figure 13 and Figure 14 The storage controller 200 can send data DATA to and receive data DATA from the non-volatile storage device 300_1, and send to the non-volatile storage device 300_1 the address ADDR including the first physical address PHY1, and other data. Figure 12 The first command CMD1 is associated with the storage device command 1400. Storage device command 1400 may instruct non-volatile storage device 300_1 to execute commands from a host device (e.g., ...). Figure 1 20) The command associated with the operation obtained by the command.

[0174] The non-volatile storage device 300_1 can perform operations requested by the storage controller 200 based on the first physical address PHY1 received from the storage controller 200 and the storage device command 1400. For example, Figure 12 The first command CMD1 is a read command, write command, or TRIM command, and the control logic circuit of the non-volatile memory device 300_1 (e.g., Figure 2 (323) can be based on the received storage device command 1400 (e.g., Figure 2 The CMD performs a read operation, write operation, or TRIM operation on a specific location of the memory cell array 321.

[0175] This disclosure is not limited to the above embodiments and drawings, and those skilled in the art can make various substitutions, modifications, and changes without departing from the technical spirit of this disclosure, and these will also fall within the scope of this disclosure. For example, one or more steps in the process described with reference to the flowcharts shown in some of the drawings may be omitted, the order of each step may be changed, one or more steps may be performed in overlapping time, or one or more steps may be performed repeatedly.

Claims

1. A storage system, comprising: Host devices, including command queues configured to queue commands; A non-volatile storage device is configured to store a dataset of mapping information used to translate logical addresses into physical addresses; as well as The storage controller is configured to store the mapping table set into volatile memory based on the mapping information dataset. The host device is configured to send a first logical address range associated with a first command to be queued in the command queue of the host device to the storage controller, and The storage controller is further configured as follows: Receive the first logical address range; and The first mapping table is stored in the volatile memory, and the first mapping table is associated with the first mapping information data in the mapping information dataset that corresponds to the first logical address range.

2. The storage system according to claim 1, wherein, After storing the first mapping table into the volatile memory, the storage controller is further configured to: Obtain the first command from the host device; Obtain the first logical address to be accessed by the first command from the first command obtained; Based on the first mapping table stored in the volatile memory, the physical address of the non-volatile storage device corresponding to the first logical address is determined; as well as Send a memory device command to the non-volatile memory device, instructing the non-volatile memory device to perform an operation associated with the first command, and the determined physical address of the non-volatile memory device. The first logical address is included in the first logical address range.

3. The storage system according to claim 1, wherein, The host device is also configured to send to the storage controller a second logical address range associated with a second command to be queued in the command queue and processed in the order following the first command. The storage controller is further configured as follows: Receive the second logical address range; and The second mapping table is stored in the volatile memory, and the second mapping table is associated with the second mapping information data in the mapping information dataset that corresponds to the second logical address range.

4. The storage system according to claim 3, wherein, The storage controller is further configured to: store the first mapping table in the volatile memory, and then store the second mapping table in the volatile memory.

5. The storage system according to claim 1, wherein, The host device is further configured to send the first logical address range to the storage controller by sending the starting logical block address and the number of logical blocks associated with the first command.

6. The storage system according to claim 1, wherein, The size of the mapping table set is smaller than the size of the mapping information dataset.

7. The storage system according to claim 1, wherein, The mapping information dataset includes multiple logical addresses corresponding to the total number of logical blocks, and multiple physical addresses corresponding to the multiple logical addresses.

8. The storage system according to claim 1, wherein, The first command is a read command, a write command, or a trim command.

9. The storage system according to claim 1, wherein, The host device is also configured to: Send a dataset management command to the storage controller, the dataset management command including the logical block address of the first logical address range stored in the host memory of the host device; as well as In response to a request from the storage controller for a region of the host memory corresponding to the logical block address, the first logical address range is sent to the storage controller.

10. The storage system according to claim 9, wherein, The dataset management commands also include attribute information for the dataset management commands. The attribute information includes bits indicating whether the mapping table should be stored in the volatile memory, and The storage controller is further configured to store the first mapping table in the volatile memory in response to the bit in the attribute information corresponding to a predetermined value.

11. The storage system according to claim 1, wherein, The host device is further configured to: send the first logical address range to the storage controller by sending a mapping prompt command including the first logical address range to the storage controller, and The storage controller is further configured to obtain the first logical address range from the mapping prompt command.

12. The storage system according to claim 1, wherein, The host device is also configured to: send the first logical address range to the storage controller using an out-of-band OOB channel, or send the first logical address range to the storage controller by setting a peripheral component interconnect PCI register.

13. The storage system according to claim 1, wherein, The storage controller is also configured to store the priority of each mapping table included in the mapping table set. The mapping table with the lowest priority in the set of mapping tables is determined as the sacrifice data, and The first mapping table is stored in the volatile memory by overwriting the determined sacrifice data with the first mapping table.

14. The storage system according to claim 13, wherein, The storage controller is also configured to: Obtain the priority of the first logical address range from the host device; The priority of the first mapping table is determined based on the priority of the first logical address range; as well as The determined priority of the first mapping table is stored in association with the first mapping table.

15. The storage system according to claim 14, wherein, The priority of the first logical address range corresponds to one of a predetermined number of priorities. Wherein, the priority of each mapping table in the mapping table set corresponds to one of the predetermined number of priorities, and The storage controller is configured to set the priority of the first logical address range to the priority of the first mapping table.

16. The storage system according to claim 14, wherein, The storage controller is also configured to: Obtain the priority of each of the one or more logical address ranges associated with the first mapping table; as well as The priority of the first mapping table is determined based on the priority of the first logical address range and the priority of each of the one or more logical address ranges.

17. The storage system according to claim 16, wherein, The priority of the first logical address range and the priority of each of the one or more logical address ranges correspond to any one of a predetermined number of priorities, and The storage controller is further configured to set the priority of the first mapping table to the highest priority among the priority of the first logical address range and the priority of each of the one or more logical address ranges.

18. The storage system according to claim 14, wherein, The priority of the first mapping table corresponds to the lowest priority among the mapping table sets stored in the volatile memory. The host device is further configured to: send a second logical address range associated with a second command to be queued in the command queue of the host device to the storage controller, and The storage controller is further configured as follows: Obtain the second logical address range; and In response to the first mapping table having a priority corresponding to the lowest priority among the mapping table sets stored in the volatile memory, the second mapping table is stored in the volatile memory by overwriting the first mapping table with a second mapping table associated with second mapping information data in the mapping information dataset that corresponds to the obtained second logical address range.

19. A storage device, comprising: A non-volatile storage device is configured to store a dataset of mapping information used to translate logical addresses into physical addresses; as well as The storage controller is configured as follows: The mapping table set is stored in volatile memory based on the mapping information dataset; Receive the first logical address range associated with the first command to be queued in the command queue of the host device; as well as The first mapping table is stored in the volatile memory, and the first mapping table is associated with the first mapping information data in the mapping information dataset that corresponds to the first logical address range.

20. A method of operating a storage system, the storage system comprising a host device, a non-volatile storage device, and a storage controller, the host device including a command queue configured to queue commands, the non-volatile storage device configured to store a mapping information dataset for translating logical addresses to physical addresses, and the storage controller configured to store a mapping table set into volatile memory based on the mapping information dataset, the method comprising: The host device sends a first logical address range associated with a first command to be queued in the command queue to the storage controller; The storage controller receives the first logical address range from the host device; as well as The storage controller stores the first mapping table into the volatile memory, and the first mapping table is associated with the first mapping information data in the mapping information dataset that corresponds to the first logical address range.

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