An IC pin I-V characteristic evaluation method under ESD stress based on a multi-layer perceptron
By constructing an IC pin IV characteristic behavior model based on a multilayer perceptron method, the problem of failing to effectively consider the influence of decoupling capacitors and active power supply clamping paths in existing technologies is solved. This enables more efficient and accurate evaluation of IC pin IV characteristics under ESD stress, and improves the simulation analysis accuracy of system-level ESD protection circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-12
Smart Images
Figure CN122197550A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of simulation technology of system-level ESD protection circuits, specifically involving a method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron. Background Technology
[0002] Traditional methods extract key parameters from transmission line pulse (TLP) test data and obtain the IV characteristics of IC pins in the form of piecewise linear (PWL) functions. This modeling method does not consider the impact of the opening and closing of decoupling capacitors and active power supply clamping paths on the results, which will produce large errors when dealing with the same ESD protection circuits installed on different PCBs.
[0003] Existing technical solutions treat decoupling capacitors and active power supply clamping paths as nonlinear capacitors and dynamic resistors, respectively. The additional charge parameters and dynamic switching parameters are extracted from TLP test data and added to the traditional model to construct a new transient model. The IV characteristics of IC pins are obtained using the new transient model.
[0004] Existing technical solutions mainly use nonlinear capacitance and dynamic resistance models to describe decoupling capacitors and active power supply clamping paths. This method requires the analysis of complex ESD discharge phenomena and the derivation of a large number of mathematical formulas during parameter extraction, which consumes a lot of time. Furthermore, this method only considers the decoupling capacitors on the PCB and does not take into account the influence of the PCB power distribution network on the impedance of the current loop under ESD stress conditions. Summary of the Invention
[0005] To overcome the shortcomings of the existing technology, the present invention aims to provide a method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron. This method has the advantages of high model building efficiency and more comprehensive consideration of the factors affecting the IC pins under ESD stress.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron includes the following steps; Step 1: Build the model, defining the network structure of the multilayer perceptron and its input and output layers; Step 2: Use Cadence Spectre to generate a dataset of multilayer perceptron models, and generate a large number of "input-output" samples through transistor-level circuit simulation (using Cadence Spectre); where the input is current and the output is voltage. Step 3: Based on the "input-output" samples, optimize the parameters of the multilayer perceptron using the backpropagation algorithm to obtain the weights; Step 4: Based on the weights, describe the multilayer perceptron network trained in Step 3 using Verilog-A language to obtain the Verilog-A model; Step 5: Import the Verilog-A model generated in Step 4 into the Cadence simulation environment, build a test circuit, and compare the model output with the original sample (or measured data) in Step 2 for evaluation.
[0007] Evaluation metrics include accuracy (error) and convergence.
[0008] Step one specifically involves: In the design of system-level ESD protection circuits, the external pins of integrated circuits are typically simulated and analyzed using behavioral models. Current or voltage is considered the model's input (independent variable), while the other is considered its output. Here, "model" refers to a behavioral model, a general concept; the model used in "model building" falls under the category of behavioral models.
[0009] A behavioral model with current as the independent variable is used for simulation analysis of system-level ESD protection circuits; the impedance of the power distribution network is parameterized, and the parameters are used as inputs to the IV characteristic behavioral model of IC pins; The power distribution network of the PCB is represented as a six-element RLC model; By using the resistance, capacitance, and inductance values in the six-element RLC model as inputs to the behavioral model, the influence of the power distribution network on the IV characteristics of IC pins is obtained. For the IV characteristic behavior model of the entire IC pin, the model input is I. io R1, L1, C1, and C2, with output V. io Input-output training data can be obtained from TLP simulations.
[0010] R1 and L1 are a series RL branch used to simulate the parasitic resistance and inductance of the power supply path; Rs is the internal resistance of the power supply; C3 is the first-stage decoupling capacitor; C1 is the second-stage decoupling capacitor; C2 is the load capacitor; R2 is used to simulate the equivalent resistance between the power supply and ground.
[0011] Step two specifically involves: Simulation data was obtained using the Cadence Spectre simulator in a circuit netlist simulation under a 180 nm complementary metal-oxide-semiconductor (CMOS) process. An ESD protection circuit was built in the Cadence Spectre simulator, with dual diodes used to protect the external IC pins (PADs). An RC-NMOS power clamp circuit and a simplified RLC power distribution network circuit were included between VDD and GND.
[0012] A simplified RLC power distribution network is used to maintain power supply stability. The dual diode protection circuit for the PAD is used to protect against ESD current that may be encountered at the IO port and provide a current discharge path. The RC-NMOS power clamping circuit is used to prevent ESD current from flowing through VDD and discharging into VSS through the internal circuit, causing damage to the internal circuit. The three structures are connected in parallel between the power supply and ground to form a system-level ESD protection circuit.
[0013] The RC-NMOS power clamping circuit is used to detect ESD events and provide a path for discharging charge. The inverter chain is used to enhance the control signal, and the clamping transistor M... clamp It is used to discharge static charge; when an ESD event occurs, V DD Voltage rises rapidly, RC network responds, output signal V RC The voltage level is low, and after being processed by the inverter, V... gate When the voltage level goes high, the clamping transistor turns on to discharge a large amount of ESD charge; when the chip is in operation, the RC network does not respond, and V... RC High level, V gate The value is 0, clamping transistor M clamp It is in the off state; the RC network is used for ESD event detection, and the RC time constant needs to be set reasonably, usually from several hundred ns to about 1 μs, clamping transistor M. clamp For discharging static charge, a MOSFET with a large aspect ratio is required, typically 2000-4000 micrometers.
[0014] In the RC-NMOS power clamping circuit of this invention, all MOS devices have the same gate length, and the inverter chain gate width is [W]. N1 W P1 W N2 W P2 W N3 W P3 [100, 200, 24, 48, 2, 12]μm, clamping transistor M clamp The gate width is 4000μm.
[0015] The circuit netlist used for circuit simulation includes on-chip ESD protection circuitry, decoupling capacitors, a 50Ω TLP tester, an RLC power distribution network, and an RC-NMOS power clamping circuit. The complete netlist includes the aforementioned RC-NMOS power clamping circuit and represents the overall circuit simulation structure. The on-chip ESD protection circuit protects against potential ESD current at the I / O ports, providing a discharge path for the current. Decoupling capacitors filter out high-frequency noise. A 50Ω TLP tester generates the TLP current. An RLC power distribution network maintains power supply stability. An RC-NMOS power clamping circuit prevents ESD current from flowing through VDD and discharging into VSS via internal circuitry, thus preventing damage to the internal circuitry. The 50Ω TLP tester generates the required TLP waveform for testing. The on-chip ESD protection circuit, RLC power distribution network, and RC-NMOS power clamping circuit together constitute the system-level ESD protection circuit.
[0016] In the complete netlist, one end of the TLP tester is connected to the IC pin, and the tester ground is connected to GND. Simulation is performed using a TLP pulse with a rise time of 10ns and a pulse width of 100ns. The training data for the multilayer perceptron was obtained through transient simulation, scanning the values of R1, L1, C1, and C2. The average values of current and voltage at 70%-90% of the time of the time-current and time-voltage waveforms in the TLP transient simulation were selected as the quasi-static current and voltage at the IC pins. Based on the range and step size of the RLC parameter scan, the IV characteristic curves were obtained as the dataset for the multilayer perceptron model.
[0017] Step three specifically involves: The first step is to randomly divide the data into a training dataset, a cross-validation dataset, and a test dataset; The second step is to input the training dataset into the multilayer perceptron model for iteration, randomly selecting samples for each iteration, and obtaining the training error based on the loss function. The third step is to use the calculated training error to update the model parameters through the backpropagation algorithm. Finally, after each iteration, the training error of the validation dataset is calculated using the loss function. If no significant reduction in the training error is observed for 50 consecutive epochs, the training process is stopped, and the finally converged multilayer perceptron model is obtained.
[0018] In step four: A single unit of a multilayer perceptron model is defined as a mathematical function that can have one or more inputs, and its output is expressed as equation (1-1): (1-1) inw i For the corresponding input x i The weight, b For bias, y For output, f The activation function is a nonlinear activation function; the existence of the activation function introduces nonlinearity into the neural network. Equation (1-2) is chosen as the activation function for the multilayer perceptron model. (1-2) The multilayer perceptron model used consists of four layers, including an input layer, an output layer, and two hidden layers. Each cell in a layer is connected to every cell in the next layer. Cells in the input layer are connected to cells in the hidden layers, and finally reach the output layer. Each node calculates according to (Equation (1-1)) and then outputs it to the node in the next layer, and finally passes it to the output layer; The fourth step is as follows: Equations (1-1) and (1-2) are implemented in Verilog-A, and a behavioral model capable of performing system-level ESD simulation using the Cadence Spectre simulator is constructed by establishing corresponding analog function functions. The model is evaluated using a test dataset derived from the total dataset obtained in step two. The input stimuli in the test dataset have never been used during the training of the multilayer perceptron model, and can effectively evaluate the performance of the multilayer perceptron model in predicting the output response when faced with unknown input stimuli. Simulation results of two randomly selected samples from the test dataset using a trained multilayer perceptron Verilog-A model and an actual circuit netlist in the Cadence Spectre simulator under input stimuli.
[0019] The beneficial effects of this invention are: The present invention employs a modeling method for an IV simulation model of IC pins under ESD stress conditions based on a multilayer perceptron. This method incorporates the influence of the PCB power distribution network on the impedance of the current loop under ESD stress conditions as input into the overall simulation model. Furthermore, it eliminates the need to analyze specific electrical phenomena, thereby improving the efficiency of model building. The model obtained by this method can provide more comprehensive and accurate results for the simulation analysis of system-level ESD protection circuits.
[0020] This invention considers the impact of power clamping paths and PCB power distribution networks on the impedance of current loops under ESD stress conditions. Improving construction efficiency means that existing technologies require fitting and extracting parameters from various curves in a dataset and analyzing actual physical phenomena; in this paper, the model's parameters are automatically trained by a neural network, eliminating the need for analysis of actual physical phenomena. Attached Figure Description
[0021] Figure 1 This is the multilayer perceptron unit model of the present invention.
[0022] Figure 2 This is a structural diagram of the multilayer perceptron model of the present invention.
[0023] Figure 3 This invention relates to a six-element RLC power distribution network.
[0024] Figure 4 This is a schematic diagram of the ESD protection circuit of the present invention.
[0025] Figure 5 This is a flowchart of the training process for the multilayer perceptron model of this invention.
[0026] Figure 6 The simulation results of the Verilog-A model of the multilayer perceptron and the actual circuit netlist of this invention are shown in the figure (the values in the two random sample RLC models are shown in the figure). Detailed Implementation
[0027] The present invention will now be described in further detail with reference to the accompanying drawings.
[0028] A method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron includes the following steps; Structure and principle of multilayer perceptron: A multilayer perceptron consists of several layers, each containing several units. These units are interconnected by weights, and multiple units in the current layer are scaled to a unit in the next layer after being multiplied by the weights, summed, biased, and activated. A multilayer perceptron is a neural network model that propagates input variables from input layer units to output layer units and uses weights and biases as intermediate parameters for computation. Figure 1 The image shows a single multilayer perceptron unit model.
[0029] A single unit of a multilayer perceptron can be defined as a mathematical function that can have one or more inputs and whose output can be expressed as equation (1-1): (1-1) in w i For the corresponding input xi The weight, b For bias, y For output, f The activation function is a nonlinear activation function. The existence of the activation function introduces nonlinearity into the neural network. In this invention, equation (1-2) is chosen as the activation function for the multilayer perceptron.
[0030] (1-2) The multilayer perceptron model used in this invention consists of four layers: an input layer, an output layer, and two hidden layers. Each unit in one layer connects to each unit in the next layer; units in the input layer connect to units in the hidden layers, and finally reach the output layer. Each node performs calculations according to (Equation (1-1)) and outputs the result to the node in the next layer, which is then passed to the output layer. The number of layers and units in each layer of the multilayer perceptron are as follows: Figure 2 As shown, the settings of these hyperparameters are determined by the dimension and sample size of the input data, empirical formulas, and trial-and-error experiments.
[0031] Step 1: Model Building In the design of system-level ESD protection circuits, the external pins of integrated circuits are typically analyzed using behavioral models. In these models, current or voltage is considered the input (independent variable), while the other is considered the output. Voltage is usually used as the independent variable to improve the efficiency of node analysis. However, under ESD stress conditions, some IC pins exhibit negative resistance (IV) characteristics, meaning the current is a multivalued function of the voltage. Therefore, this invention employs a behavioral model with current as the independent variable for the simulation analysis of system-level ESD protection circuits.
[0032] In common ESD testing scenarios, discharge current enters the integrated circuit (IC) through IC pins, exits through multiple power and ground pins, and returns to ground via the PCB power distribution network. The PCB power distribution network includes power planes, decoupling capacitors, and related parasitic components. PCBs with different power distribution network designs will have different impedances in the ESD current loop, potentially altering the current ratio flowing through each power or ground pin. The impedance of the current loop is strongly dependent on the decoupling capacitors. To capture the influence of the PCB power distribution network in a single-port IC pin model, this invention parameterizes the impedance of the power distribution network and uses these parameters as input to the IV characteristic behavior model of the IC pins.
[0033] This invention represents the power distribution network of a PCB as a six-element RLC model. For example... Figure 3 As shown, by using these RLC values as input to the behavioral model, the impact of the power distribution network on the IV characteristics of the IC pins can be obtained. Figure 3The power distribution network model parameters R1, L1, C1, and C2 have a significant impact on the IV characteristics of IC pins and are considered as inputs to the model.
[0034] For the entire model, the model input is I. io R1, L1, C1, and C2, with output V. io Input-output training data can be obtained from TLP simulations.
[0035] Step 2: Generate a dataset for the multilayer perceptron model using Cadence Spectre: All simulation data in this invention were obtained using the Cadence Spectre simulator in circuit netlist simulation under 180 nm complementary metal-oxide-semiconductor (CMOS) technology. Figure 4 The diagram shows a simulation of the ESD protection circuit, with external IC pins (PADs) protected by dual diodes. An RC-NMOS power clamp circuit and a simplified RLC power distribution network are included between VDD and GND.
[0036] The RC-NMOS power clamping circuit is used to detect ESD events and provide a path for discharging charge. The inverter chain is used to enhance the control signal, and the clamping transistor M... clamp It is used to discharge static charge. When an ESD event occurs, V DD Voltage rises rapidly, RC network responds, output signal V RC The voltage level is low, and after being processed by the inverter, V... gate When the voltage level goes high, the clamping transistor turns on to discharge a large amount of ESD charge; when the chip is in operation, the RC network does not respond, and V... RC High level, V gate The value is 0, clamping transistor M clamp It is in the off state. The RC network is used for ESD event detection, and the RC time constant needs to be set appropriately, typically from several hundred ns to around 1 μs, clamping transistor M. clamp For discharging static charge, MOS transistors with a large aspect ratio are required. In the RC-NMOS power clamping circuit of this invention, all MOS devices have the same gate length, and the inverter chain gate width is [W]. N1 W P1 W N2 W P2 W N3 W P3 [100, 200, 24, 48, 2, 12]μm, clamping transistor M clamp The gate width is 4000μm.
[0037] The complete netlist used for circuit simulation includes on-chip ESD protection circuitry, decoupling capacitors, a 50Ω TLP tester, an RLC power distribution network, and an RC-NMOS power clamping circuit. In the netlist, one end of the TLP tester is connected to an IC pin, and the tester ground is connected to GND. Simulation is performed using a TLP pulse with a rise time of 10ns and a pulse width of 100ns. Training data for the multilayer perceptron was obtained through transient simulation, scanning the values of R1, L1, C1, and C2. The scan range and step size for each parameter are given in Table 1.
[0038] Input parameters scope Step length R1 [2, 14]nH 2 nH L1 [20, 100]mΩ 20 mΩ C1 [2, 8]pF 2 pF C2 [0.1, 1]μF 0.1μF Table 1 Range and step size of RLC parameters for power distribution networks The average values of current and voltage at 70%-90% of the time of the time-current and time-voltage waveforms in the TLP transient simulation were selected as the quasi-static current and voltage at the IC pins. Based on the range and step size of the RLC parameter scan, a total of 1400 sets of IV characteristic curves were obtained as the dataset for the multilayer perceptron model.
[0039] Step 3: Training process of multilayer perceptron: The training process of the GRU model is as follows: Figure 5 As shown in the diagram. First, the 1400 datasets are randomly divided into training, cross-validation, and test datasets in an 8:1:1 ratio. Second, the training dataset is input into the multilayer perceptron model for iteration, with 16 samples randomly selected for each iteration, and the training error is calculated based on the loss function. Third, the calculated training error is used to update the model parameters via backpropagation. Finally, after each iteration, the training error of the validation dataset is calculated using the loss function. If no significant reduction in the training error is observed for 50 consecutive epochs, the training process is stopped, and the finally converged multilayer perceptron model is obtained.
[0040] Step 4: Verilog-A implementation of the multilayer perceptron model: Equations (1-1) and (1-2) can be implemented in Verilog-A. By establishing corresponding analog functions, a behavioral model capable of system-level ESD simulation using the Cadence Spectre simulator can be constructed. The pseudocode description of the multilayer perceptron model is shown in Table 2.
[0041] Table 2. Pseudocode for the Multilayer Perceptron Model Step 5: Evaluation and verification of the multilayer perceptron model implemented using Verilog-A: This invention selects a test dataset partitioned from the total dataset to evaluate the model. The input stimuli in the test dataset have never been used during the training of the multilayer perceptron model, which can effectively evaluate the performance of the multilayer perceptron model in predicting the output response when faced with unknown input stimuli.
[0042] Figure 6 The simulation results for two randomly selected samples from the test dataset, using a trained multilayer perceptron Verilog-A model and an actual circuit netlist under input stimuli, are presented in the Cadence Spectre simulator. The entire test dataset contains 140 samples, and the average goodness-of-fit (R0) is... 2 The mean square error (RMSE) was 0.995, and the average root mean square error (RMSE) was 0.00782. The largest RMSE in the entire test dataset did not exceed 1%, indicating that the trained multilayer perceptron Verilog-A model can accurately predict the IV characteristics of system-level IC pins under ESD stress conditions.
[0043] This invention incorporates the impact of the PCB power distribution network on the impedance of the current loop under ESD stress conditions as input into the overall simulation model. The invention implements a multilayer perceptron model using Verilog-A, resulting in a behavioral model capable of system-level ESD simulation using the Cadence Spectre simulator. The proposed and implemented multilayer perceptron behavioral model exhibits high fitting accuracy, with a maximum root mean square error of no more than 1% across the entire test dataset.
[0044] The modeling method of the IV simulation model of integrated circuit (IC) pins based on multilayer perceptron under electrostatic discharge (ESD) stress conditions adopted in this invention avoids the analysis and parameter extraction of complex electrical phenomena of external components and active power clamping paths on printed circuit boards (PCBs) under ESD stress conditions. It has high fitting accuracy and improves the efficiency of model building. It is a modeling method that can provide accurate results for the simulation analysis of system-level ESD protection circuits.
[0045] This invention aims to explore a modeling method for IV simulation models of IC pins based on multilayer perceptrons under ESD stress conditions. This method incorporates the influence of the PCB power distribution network on the impedance of the current loop under ESD stress conditions as input into the overall simulation model, without the need to analyze specific electrical phenomena, thus improving the efficiency of model building. Furthermore, the model obtained by this method can provide more comprehensive and accurate results for the simulation analysis of system-level ESD protection circuits.
Claims
1. A method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron, characterized in that, Includes the following steps; Step 1: Build the model, defining the network structure of the multilayer perceptron and its input and output layers; Step 2: Use Cadence Spectre to generate a dataset of multilayer perceptron models, and generate "input-output" samples through transistor-level circuit simulation; where the input is current and the output is voltage. Step 3: Based on the "input-output" samples, optimize the parameters of the multilayer perceptron using the backpropagation algorithm to obtain the weights; Step 4: Based on the weights, describe the multilayer perceptron network trained in Step 3 using Verilog-A language to obtain the Verilog-A model; Step 5: Import the Verilog-A model into the Cadence simulation environment, build a test circuit, compare the model output with the original sample in Step 2, and evaluate it.
2. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 1, characterized in that, Step one specifically involves: In the process of designing system-level ESD protection circuits, the external pins of integrated circuits are usually simulated and analyzed by behavioral models, where current or voltage is regarded as the input of the model, i.e., the independent variable, while the other is regarded as the output of the model.
3. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 2, characterized in that, A behavioral model with current as the independent variable is used for simulation analysis of system-level ESD protection circuits; the impedance of the power distribution network is parameterized, and the parameters are used as inputs to the IV characteristic behavioral model of IC pins; The power distribution network of the PCB is represented as a six-element RLC model; By using the resistance, capacitance, and inductance values in the six-element RLC model as inputs to the behavioral model, the influence of the power distribution network on the IV characteristics of IC pins is obtained. For the IV characteristic behavior model of IC pins, the model input is I. io R1, L1, C1, and C2, with output V. io The input-output training data is obtained from the TLP simulation.
4. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 3, characterized in that, R1 and L1 are a series RL branch used to simulate the parasitic resistance and inductance of the power supply path; Rs is the internal resistance of the power supply; C3 is the first-stage decoupling capacitor; C1 is the second-stage decoupling capacitor; C2 is the load capacitor; R2 is used to simulate the equivalent resistance between the power supply and ground.
5. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 1, characterized in that, Step two specifically involves: Simulation data was obtained by using the Cadence Spectre simulator to simulate the circuit netlist under the complementary metal-oxide-semiconductor process. An ESD protection circuit was built in the Cadence Spectre simulator. The external IC pin PAD was protected by dual diodes. An RC-NMOS power clamping circuit and a simplified RLC power distribution network circuit were included between VDD and GND.
6. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 5, characterized in that, A simplified RLC power distribution network is used to maintain power supply stability. The dual diode protection circuit for PAD is used to protect against ESD current that may be encountered at the IO port and provide a current discharge path. The RC-NMOS power clamping circuit is used to prevent ESD current from flowing through VDD and discharging into VSS through the internal circuit, causing damage to the internal circuit. The three structures are connected in parallel between the power supply and ground to form a system-level ESD protection circuit. The RC-NMOS power clamping circuit is used to detect ESD events and provide a path for discharging charge. The inverter chain is used to enhance the control signal, and the clamping transistor M... clamp It is used to discharge static charge; When an ESD event occurs, V DD Voltage rises rapidly, RC network responds, output signal V RC The voltage level is low, and after being processed by the inverter, V... gate When the voltage level goes high, the clamping transistor turns on to discharge a large amount of ESD charge; when the chip is in operation, the RC network does not respond, and V... RC High level, V gate The value is 0, clamping transistor M clamp It is in the off state; the RC network is used for ESD event detection, with an RC time constant of several hundred ns to 1 μs, and clamping transistor M. clamp For discharging static charge, MOSFETs with a diameter of 2000-4000 micrometers are selected.
7. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 6, characterized in that, The circuit netlist used for circuit simulation includes on-chip ESD protection circuitry, decoupling capacitors, a 50Ω TLP tester, an RLC power distribution network, and an RC-NMOS power clamping circuit. The complete netlist includes the aforementioned RC-NMOS power clamping circuit and represents the overall circuit simulation structure. The on-chip ESD protection circuit protects against potential ESD current at the I / O ports, providing a discharge path for the current. Decoupling capacitors filter out high-frequency noise. A 50Ω TLP tester generates the TLP current. An RLC power distribution network maintains power supply stability. An RC-NMOS power clamping circuit prevents ESD current from flowing through VDD and discharging into VSS via internal circuitry, thus preventing damage to the internal circuitry. The 50Ω TLP tester generates the required TLP waveform for testing. The on-chip ESD protection circuit, RLC power distribution network, and RC-NMOS power clamping circuit together constitute the system-level ESD protection circuit.
8. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 7, characterized in that, In the complete netlist, one end of the TLP tester is connected to the IC pin, and the tester ground is connected to GND. Simulation is performed using the TLP pulse. The training data for the multilayer perceptron was obtained through transient simulation, scanning the values of R1, L1, C1, and C2. The average values of current and voltage at 70%-90% of the time of the time-current and time-voltage waveforms in the TLP transient simulation were selected as the quasi-static current and voltage at the IC pins. Based on the range and step size of the RLC parameter scan, the IV characteristic curves were obtained as the dataset for the multilayer perceptron model.
9. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 8, characterized in that, Step three specifically involves: The first step is to randomly divide the data into a training dataset, a cross-validation dataset, and a test dataset; The second step is to input the training dataset into the multilayer perceptron model for iteration, randomly selecting samples for each iteration, and obtaining the training error based on the loss function. The third step is to use the calculated training error to update the model parameters through the backpropagation algorithm. Finally, after each iteration, the training error of the validation dataset is calculated using the loss function. If no significant reduction in the training error is observed for 50 consecutive epochs, the training process is stopped, and the finally converged multilayer perceptron model is obtained.
10. The method for evaluating the IV characteristics of IC pins under ESD stress based on a multilayer perceptron according to claim 9, characterized in that, In step four: A single unit of a multilayer perceptron model is defined as a mathematical function that can have one or more inputs, and its output is expressed as equation (1-1): （1-1） in w i For the corresponding input x i The weight, b For bias, y For output, f The activation function is a nonlinear activation function; the existence of the activation function introduces nonlinearity into the neural network. Equation (1-2) is chosen as the activation function for the multilayer perceptron model. （1-2） The multilayer perceptron model used consists of four layers, including an input layer, an output layer, and two hidden layers. Each cell in a layer is connected to every cell in the next layer. Cells in the input layer are connected to cells in the hidden layers, and finally reach the output layer. Each node is calculated according to equation (1-1) and then output to the node in the next layer, and finally passed to the output layer; In step four: Equations (1-1) and (1-2) are implemented in Verilog-A. By establishing corresponding analog functions, a behavioral model capable of performing system-level ESD simulation using the Cadence Spectre simulator is constructed. The model is evaluated using a test dataset derived from the total dataset obtained in step two. The input stimuli in the test dataset have never been used during the training of the multilayer perceptron model, and can effectively evaluate the performance of the multilayer perceptron model in predicting the output response when faced with unknown input stimuli. Simulation results in the Cadence Spectre simulator using a trained multilayer perceptron Verilog-A model and an actual circuit netlist, based on two randomly selected samples from the test dataset and input stimuli.