A PCB design rule generation method based on system-level EMC data assets

Abstract

The application discloses a PCB design rule generation method based on system-level EMC data assets, and belongs to the EMC design field.The method comprises the following steps: obtaining structured data assets in system-level EMC data assets, including decoupling instruction sets, etc.; generating a design constraint unit (DCU) through a rule analysis engine, each DCU containing a constraint object, a constraint type, a target value / range and source metadata; calling an EMC-physical mapping library to quantitatively convert EMC performance indexes in the DCU into PCB physical parameters, and generating an enhanced DCU; detecting and arbitrating the enhanced DCU, and generating a fusion constraint set; and converting the fusion constraint set into a PCB design rule data output through a format adapter.The application converts IC-level EMC analysis results into executable PCB design rules, the rules are traceable and evolvable, multi-source instruction fusion and multi-software adaptation are supported, and the design efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic compatibility (EMC) design technology, specifically involving a PCB design rule generation method based on system-level EMC data assets. It is particularly suitable for integration into EMC intelligent design instruments or as a computer software product (including standalone applications, software plug-ins, etc.), transforming structured data assets into PCB design rules that can be executed by PCB design software, thus realizing a closed loop from IC-level EMC analysis to PCB-level refined design. Background Technology

[0002] In the development of electronic products, the formulation of PCB design rules has a significant impact on the product's electromagnetic compatibility (EMC) performance. With the increasing complexity of electronic systems and the continuous improvement of signal speeds, PCBs often house dozens or even hundreds of integrated circuits (ICs), highlighting the growing importance of electromagnetic coupling between ICs and matching between ICs and peripheral circuits. Traditional PCB design rules primarily stem from engineer experience, company design specifications, or general design guidelines. These rules are typically in the form of qualitative descriptions (e.g., "decoupling capacitors should be placed as close as possible to IC power pins," "clock lines should be grounded," "input capacitors should be placed close to IC pins"), and engineers configure them into specific designs based on these rules. Such empirical rules have the following limitations:

[0003] The rules are based on personal experience and lack quantitative evidence, making it difficult to assess their accuracy and applicability.

[0004] The rules are in text form and cannot be directly parsed and executed by design tools; they require manual configuration by engineers.

[0005] The rules are highly generalized and difficult to personalize for specific IC combinations and application scenarios;

[0006] The rules are disconnected from the original analytical data, making it impossible to trace their source and confidence level, and design decisions lack a basis;

[0007] The rules are outdated and cannot reflect the progress of IC technology and the iteration of design experience in a timely manner.

[0008] Existing patent literature contains several technologies related to design rule generation. For example, patent application CN121389793A discloses a method and apparatus for ground plane segmentation of hybrid PCBs. It generates a ground plane segmentation strategy through a ground plane decision model and automatically generates segmentation lines using PCB design software. This method focuses on the specific rule of ground plane segmentation, and its input is the characteristic parameters of the hybrid PCB (number of layers, voltage level, grounding, etc.), rather than the processing results based on system-level EMC data assets. Patent application CN103389418A discloses an electromagnetic compatibility (EMC) testing method and apparatus. It checks whether the PCB layout conforms to the rules by reading an EMC rule script. However, the rule script is manually preset, belonging to rule checking rather than rule generation, and the rules are static and cannot dynamically adapt to IC changes. Patent application CN114117991A discloses a method, apparatus, and system for determining the location of chip decoupling capacitors. It determines the optimal location of a single decoupling capacitor by establishing a 3D PCB model and performing simulation iterations. This method focuses on local optimization of a single component, does not involve the generation of multi-IC system-level rules based on data assets, and relies on simulation iteration rather than data asset-driven approaches, making it difficult to adapt to the collaborative design needs of complex systems.

[0009] Patent application CN120874746A discloses an automatic PCB design rule checking and correction method, which uses a multimodal large model to parse PCB design documents and automatically generate checking rules. While this method achieves automatic rule generation, its rules originate from natural language understanding of the design documents, rather than structured analysis results based on system-level EMC data assets. The generated rules are primarily used for design checking, rather than layout and routing rules that can be directly executed by PCB design software. Furthermore, this method does not involve traceable metadata or closed-loop optimization mechanisms for the rules. Patent applications CN1667617A and CN101655881A disclose PCB design methods for automatically importing design rules, saving the design rules as database files for terminal access. These methods involve rule storage and import, not rule generation; the rules are manually preset and lack dynamic adaptability and data-driven characteristics. Patent application CN104732018A discloses a PCB routing processing method that reads preset design rules for signal isolation detection, falling under the category of rule checking. The patent applications with publication numbers CN119227631A and CN120633567A involve design rule checking and analysis, and both belong to rule application rather than rule generation.

[0010] In PCB design engineering practice, a wealth of layout and routing experience for specific ICs has been summarized into design guidelines. For example, analog input traces of high-speed ADCs should be of equal length and symmetrical, power supply pins should have multiple levels of decoupling capacitors, clock circuits should be kept away from noise sources, and the hot loop area of ​​switching power supplies should be minimized. While these rules of thumb are effective, they have always existed in the form of scattered documents and cannot be systematically utilized, let alone automatically adapted in specific designs.

[0011] In summary, existing technologies lack a method to transform IC-level results (such as decoupling instructions, alternative measure sets, risk rules, etc.) obtained from system-level EMC data asset analysis into PCB design rules that can be executed by PCB design software, based on system-level EMC data assets. Furthermore, they cannot achieve traceability, evolution, or targeted generation of rules for specific application scenarios. Summary of the Invention

[0012] The purpose of this invention is to provide a PCB design rule generation method based on system-level EMC data assets, in order to solve the problems in the prior art where PCB design rules rely on human experience, cannot be quantified, are difficult to generate for specific application scenarios, and lack traceability and evolution capabilities.

[0013] To achieve the above objectives, the present invention provides the following technical solution:

[0014] A method for generating PCB design rules based on system-level EMC data assets includes the following steps:

[0015] S1. Obtain at least one structured data asset extracted from system-level EMC data assets, wherein the structured data asset includes at least one of decoupling instruction set, alternative measure set, and risk guidance rules;

[0016] S2. The structured data assets are parsed through the rule parsing engine to generate at least one Design Constraint Unit (DCU). Each Design Constraint Unit contains the constraint object, constraint type, target value / range, and source metadata.

[0017] The source metadata includes at least the source identifier, instruction ID, version number, and confidence level. It is used to record the traceability relationship between the design constraint unit and the original data asset, provide priority basis for conflict arbitration, and provide traceability support for subsequent rule validity verification.

[0018] S3. Call the EMC-Physical Mapping Library to quantify the EMC performance indicators in the design constraint unit into PCB physical parameters, and generate an enhanced design constraint unit containing physical constraints.

[0019] S4. Detect conflicts among multiple enhanced design constraint units and arbitrate them based on the priority rule base to generate a fused constraint set;

[0020] S5. Convert the fused constraint set into PCB design rule data using a format adapter for output.

[0021] In this invention, "PCB design rule data" refers to rule information generated through step S5 that can be used directly or indirectly by PCB design software. This data can be output as a file (i.e., a PCB design rule file) or provided to design tools as API data streams, memory objects, etc. The PCB design rule file is a preferred implementation, including but not limited to the .DRU format of Altium Designer, the .RUL format of Cadence Allegro, the .tec format of Mentor PADS, or intermediate exchange formats conforming to the IPC-2581 standard.

[0022] Furthermore, the structured data assets also include component selection recommendations; the component selection recommendations include at least the component's packaging information, electrical parameters, and recommended layout location, which are used to generate corresponding component layout constraints and attribute setting rules in the design rule data.

[0023] Furthermore, the rule parsing engine's parsing process includes: identifying semantic tags in structured data assets, extracting constraint object identifiers, constraint type keywords, performance index values ​​and units, and associating them with corresponding source identifiers, instruction IDs, version numbers and confidence information to form a standardized design constraint unit data structure.

[0024] Furthermore, the EMC-physical mapping library includes at least one of the following mapping relationships: theoretical formula mapping, simulation calibration curve mapping, and measured empirical value mapping; the quantitative conversion maps EMC performance indicators to specific PCB geometric parameters or electrical parameters based on the current PCB's layer stack-up structure, material parameters, and manufacturing process capabilities.

[0025] Furthermore, the conflict detection is based on a constraint dependency graph, which uses design constraint units as nodes and the relationships between constraint objects as edges; the arbitration is automatically adjusted according to the priority order of predefined rule types in the priority rule base, and conflicts that cannot be resolved automatically generate conflict reports for user confirmation.

[0026] Furthermore, the format adapter calls the corresponding design rule template for different PCB design software, fills the fusion constraint set into the template, and generates a PCB design rule file that conforms to the syntax specification of the target software; the design rule file includes at least one of the following: Altium Designer's .DRU format, Cadence Allegro's .RUL format, Mentor PADS's .tec format, or intermediate exchange format conforming to the IPC-2581 standard.

[0027] Furthermore, while generating the PCB design rule file, a rule report and a rule metadata file are also generated. The rule report describes the source identifier, instruction ID, version number, confidence level, mapping basis, and priority of each rule in a readable format. The rule metadata file stores the traceability relationship between each rule and the original data assets in a structured format for subsequent rule validity verification and closed-loop optimization.

[0028] Furthermore, the method is applied to an EMC intelligent design instrument as a module for generating IC-level PCB design rules based on structured data assets. The instrument has a built-in rule parsing engine, an EMC-physical mapping library, a priority rule library, and a format adapter. Users can trigger the generation of design rules through the instrument interface and export the PCB design rule files for use by external PCB design software. The generated rule report and rule metadata file are stored in the user's local design knowledge base.

[0029] Furthermore, the method is implemented as a standalone computer software product or a plug-in to PCB design software; the software product provides a graphical user interface that supports users in importing structured data assets, selecting PCB design software types, previewing generated rule content, and exporting PCB design rule files; the plug-in can read the netlist and component information of the current design project, obtain the structured data assets for the project extracted from the system-level EMC data assets, generate and load PCB design rules into the current design environment in real time, and visually prompt the constrained objects and their source information, including at least one of highlighting, dynamic boundaries, floating labels, and icon markings.

[0030] Furthermore, the application results and subsequent test feedback of the generated PCB design rules after being applied to the design project are stored in the user's local design knowledge base. The rule application results and test feedback are used to optimize the mapping relationship in the EMC-Physical Mapping Library and the priority rules in the priority rule library, so as to realize the continuous self-growth of the data related to the PCB design rules in the user's local design knowledge base. Based on the historical rule application results and test feedback accumulated in the user's local design knowledge base, the generation logic of the fusion constraint set is continuously optimized, and the design rule template data assets are generated and updated. The design rule template data assets store the design rule template parameters, typical application scenarios and recommended rule combinations of different PCB design software in a structured form.

[0031] Beneficial effects

[0032] First, this invention transforms structured data assets (such as decoupling instruction sets, alternative measure sets, risk rules, etc.) into PCB design rules, realizing a closed loop from IC-level EMC analysis to PCB-level refined design, and solving the problem that traditional design rules rely on human experience and cannot be quantified.

[0033] Second, this invention unifies structured data assets from multiple sources into a standardized intermediate representation through a rule parsing engine and design constraint units, providing a unified data foundation for subsequent mapping, conflict detection, and format adaptation, thereby enhancing the system's scalability and compatibility.

[0034] Third, this invention uses an EMC-physical mapping library to quantitatively convert EMC performance indicators (such as isolation, impedance, and filtering effect) into PCB physical parameters (such as spacing and line width), transforming design rules from qualitative descriptions into executable quantitative constraints, significantly improving the accuracy and reliability of design rules. The mapping library integrates theoretical formulas (such as microstrip line impedance formulas), simulation calibration curves (such as the relationship between isolation and spacing), and measured empirical values ​​(such as the self-resonant frequency of decoupling capacitors), ensuring the accuracy and applicability of the mapping.

[0035] Fourth, this invention effectively resolves potential contradictions between instructions from different sources (such as decoupling instructions, alternative measure sets, etc.) through conflict detection and a priority rule base, generating a fused constraint set. It can also provide conflict reports for user confirmation when automatic resolution is not possible, ensuring the consistency and executability of the rules. The conflict detection mechanism, based on a constraint dependency graph, performs correlation analysis on constraint units acting on the same or related objects, quickly locating numerical conflicts, topological conflicts, and resource conflicts.

[0036] Fifth, this invention supports rule formats of various PCB design software through a format adapter. The generated PCB design rule files can be directly imported into PCB design software (such as Altium Designer, Cadence Allegro, Mentor PADS, etc.), simplifying the manual configuration work of engineers and significantly improving the configuration efficiency and accuracy of design rules.

[0037] Sixth, the rule reports and rule metadata files generated by this invention enable each rule to be traced back to its original data assets (including source identifier, instruction ID, version number, confidence level, etc.), providing quantifiable evidence for design decisions and laying the foundation for subsequent rule validity verification and closed-loop optimization. This traceability allows design experience to be preserved in data form, preventing the loss of experience.

[0038] Seventh, this invention continuously optimizes the mapping relationships in the EMC-Physical Mapping Library and the priority rules in the Priority Rule Library by storing the application results and test feedback in the user's local design knowledge base, thereby achieving self-growth of design rules. As project experience accumulates, the optimized mapping relationship parameters are continuously updated, and the confidence level of subsequent similar scenarios gradually increases, forming a continuous evolutionary capability based on experience iteration.

[0039] Eighth, the design rule template data assets generated by this invention store design rule template parameters, typical application scenarios and recommended rule combinations of different PCB design software in a structured form. This systematizes the layout rules scattered in design guidelines, engineer experience and enterprise specifications into callable rule assets, providing design references for designers and helping to realize the accumulation and reuse of design experience.

[0040] In this invention, the design rule template is stored as a data asset in the user's local design knowledge base, forming a design rule template data asset. This data asset stores design rule template parameters, typical application scenarios, and recommended rule combinations for different PCB design software in a structured format, such as... Figure 5 As shown.

[0041] Ninth, this invention can be integrated into EMC intelligent design instruments or implemented as a standalone computer software product or PCB design software plug-in, providing flexible application options for enterprises of different sizes and broadening the industrial application scenarios of the technical solution.

[0042] Tenth, the PCB design rules generated by this invention complement existing PCB design specifications, providing a refined supplement to the design specification system. As the physical carrier of ICs, the electromagnetic compatibility (EMC) performance of a PCB largely depends on the layout design quality of each IC and its surrounding circuits. This invention transforms IC-level analysis results derived from system-level EMC data assets into quantitative layout constraints for ICs and their surrounding circuits. Within the existing design specification framework, it achieves precise rule generation for specific application scenarios, enabling effective synergy between refined IC-level design and overall PCB design specifications. Attached Figure Description

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] Figure 1 This is a flowchart of the method of the present invention.

[0045] Figure 2 This is a diagram showing the interaction relationships between modules in the EMC intelligent design instrument of this invention.

[0046] Figure 3 This is a schematic diagram illustrating the application of the present invention as a standalone software tool.

[0047] Figure 4 This is a schematic diagram of the design constraint unit (DCU) structure, conflict detection, and arbitration of the present invention.

[0048] Figure 5 This is a schematic diagram of the data asset structure of the design rule template of this invention. Detailed Implementation

[0049] The overall process of this invention includes: S1, acquiring structured data assets extracted from system-level EMC data assets; S2, generating design constraint units (DCUs) through a rule parsing engine; S3, calling the EMC-physical mapping library to convert EMC performance indicators into PCB physical parameters, generating enhanced design constraint units; S4, performing conflict detection and arbitration on multiple enhanced design constraint units to generate a fused constraint set; S5, converting the data into PCB design rule data through a format adapter for output.

[0050] The following three embodiments illustrate the specific applications of this invention in three carriers: intelligent EMC design instruments, standalone software tools, and PCB design software plug-ins. They also demonstrate the interaction with structured data assets extracted from system-level EMC data assets, such as decoupling instruction sets, alternative measure sets, and risk guidance rules. The embodiments of this invention utilize three different fields: consumer electronics, medical electronics, and industrial control. The IC types cover PMICs, audio codecs, and isolated driver chips, fully demonstrating the broad applicability of this invention.

[0051]

Example 1

[0052] This embodiment uses the integration of the method of the present invention into an EMC intelligent design instrument as an example to illustrate its application in the design of a tablet computer power management unit (PMIC).

[0053] A consumer electronics company is developing a high-performance tablet PC. The main power supply uses a domestically produced PMIC (model IC8-1, operating at 1.5MHz) to power multiple loads, including the application processor, memory, and display. The IC8-1 integrates multiple DC-DC converters and LDOs, and its peripheral circuitry includes power inductors, input / output capacitors, and feedback resistors, with stringent layout requirements. The PCB is an 8-layer board, measuring 200mm × 120mm, with limited space. The IC8-1 area must also consider heat dissipation and EMC.

[0054] Engineers input the IC assembly information (IC8-1 only) and PCB stack-up information for the project into the EMC intelligent design instrument. The instrument analyzes the system-level EMC data assets and generates structured data assets for IC8-1, including:

[0055] Decoupling instruction set: For example, "The SW switch node of IC8-1 should be far away from sensitive analog circuits, with a distance of ≥50mil; the input capacitor should be close to the IC pin, with a layout radius of ≤1.5mm"; "The input capacitor should be as close as possible to the VIN pin of IC8-1, and the GND terminal of the capacitor should be directly connected to the GND pin of the IC through a short and wide trace to form the minimum thermal loop area".

[0056] Alternative measures: For example, "If the recommended large-package inductor cannot be used, a similar inductor of comparable size can be used instead, but bottom vias for heat dissipation must be added, and no other signal lines should be placed below the inductor";

[0057] Risk guidance rules: For example, "When the layout of the SW switch node of IC8-1 cannot meet the ≥50mil pitch requirement, the PCB level needs to add an RC buffer circuit (R=10Ω, C=470pF) between the SW node and ground to suppress switch ringing, which is expected to reduce the switch node noise by about 2dB."

[0058] In addition, the system also retrieves scenario coupling sensitivity data of IC8-1 with other ICs (such as application processors and DDR memory) from the system-level EMC data assets for priority judgment in subsequent rule generation.

[0059] Step S1: The instrument acquires the structured data assets generated above as input for subsequent steps.

[0060] Step S2: The rule parsing engine parses the above structured data assets to generate multiple Design Constraint Units (DCUs). For example, for the decoupling instruction "Input capacitors must be close to IC pins, layout radius ≤ 1.5mm", DCU-A is generated, containing the constraint object "IC8-1_VIN", constraint type "layout area", target value / range "radius ≤ 1.5mm", and source metadata "source identifier = decoupling instruction set, instruction ID = DEC-2026-003, version = 1.2, confidence level = 0.92". For the decoupling instruction "SW switch nodes must be far away from sensitive analog circuits, distance ≥ 50mil", DCU-B is generated, containing the constraint object "IC8-1_SW network", constraint type "spacing", target value / range "≥ 50mil", and source metadata "source identifier = decoupling instruction set, instruction ID = DEC-2026-004, version = 1.0, confidence level = 0.88". For the alternative measure set "No other signal lines shall be placed below the inductor", the DCU-C is generated by parsing, which includes the constraint object "area below L1", the constraint type "no-signal zone", the target value / range "no signal lines shall be placed", and the source metadata "source identifier = alternative measure set, instruction ID = ALT-PMIC-001, version = 1.0, confidence level = 0.85".

[0061] Step S3: Call the EMC-Physical Mapping Library to convert the EMC performance parameters in the DCU into PCB physical parameters. For DCU-A, directly convert to "Layout area: centered on the IC8-1_VIN pin, radius ≤ 1.5mm". For DCU-B, based on the current PCB stack-up and SW node characteristics, map out the requirement to lay ground copper foil under the SW node and add a heat dissipation via array, while requiring the SW node trace width to be no less than 30mil to carry current. For DCU-C, directly convert to "Signal lines are prohibited within the L1 projection area and its surrounding 0.5mm range".

[0062] Step S4: Conflict Detection and Arbitration. The system detects that DCU-A requires the input capacitor to be placed within a 1.5mm radius, while DCU-B requires the SW node to be away from sensitive circuits. However, the input capacitor itself is close to the IC, so there is no direct conflict between the two. The system also detects that DCU-A may have an indirect conflict with another decoupling instruction, "output capacitor must be close to the load" (the two may conflict due to layout space limitations). According to the predefined priority order in the priority rule base (input capacitors belong to the power supply critical path and have higher priority than output capacitors), the arbitration result is to prioritize satisfying the input capacitor layout, and optimize the output capacitor within the remaining space. Meanwhile, DCU-C and DCU-B have no conflict and are executed independently.

[0063] Step S5: The format adapter converts the arbitrated fusion constraint set into a .RUL rule file recognizable by Cadence Allegro. Simultaneously, it generates a readable rule report (e.g., PDF) and a structured rule metadata file (e.g., JSON), detailing the source, mapping basis, and priority of each rule. The rule report specifically points out that the input capacitor layout rules are derived from a high-confidence analysis of the decoupling instruction set and are recommended to be strictly followed; the recommended number and spacing of the SW node heat dissipation via array, based on thermal simulation results, is 12 vias with a spacing of 0.8mm.

[0064] The instrument exports the generated .RUL file, which engineers import into Allegro, and the rules are automatically loaded into the PCB project. During layout, engineers place the input capacitors within the designated area of ​​IC8-1 according to the rule prompts, lay ground copper foil and add vias below the SW node, and ensure there are no signal lines below the inductors, ultimately completing an IC8-1 layout that complies with EMC rules. Subsequent testing showed that power ripple and radiated emissions both meet design requirements.

[0065] This embodiment demonstrates the ability of the present invention to generate executable, refined PCB design rules based on structured data assets for PMICs (Power Microcontrollers), which are complex power ICs, in an instrument. This solves the difficulties in the layout of peripheral circuits for power ICs, especially in the generation of constraints for key components such as thermal loops, input capacitors, and switching nodes.

[0066]

Example 2

[0067] This embodiment uses the method of the present invention as an independent software tool ("PCB design rule generator") as an example to illustrate its application in the simulation front-end design of medical ultrasound equipment.

[0068] A medical equipment company is designing a portable ultrasound diagnostic instrument. Its analog front-end uses a domestically produced audio codec (model IC9-1, operating at 48kHz audio + 12MHz digital core). This IC integrates a high-precision ADC / DAC and is extremely sensitive to power supply noise and ground bounce. The peripheral circuitry includes differential input / output, microphone bias, and headphone amplification, requiring precise layout. The PCB is a 6-layer board, measuring 150mm × 100mm, and the analog area must be strictly isolated from the digital area.

[0069] Engineers used the "EMC Rule Generator" software for evaluation.

[0070] Step S1: Engineers acquire structured data assets for the project (such as decoupling instruction sets, alternative measures sets, etc., stored in JSON format) and import them into the software. The decoupling instructions include: "Analog power supplies and digital power supplies must be isolated in separate zones, with an isolation level ≥60dB@1MHz; differential input pairs must be of equal length and tightly coupled, with an error ≤5mil; analog input traces should avoid running parallel to digital clock lines and should be kept away from the switching power supply area."

[0071] Step S2: The software parses and generates design constraint units. For example, the decoupling instruction "Differential input pairs must maintain equal length and tight coupling" generates DCU-D, which includes the constraint object "IC9-1_AINP / AINN network", the constraint type "differential pair rule", the target value / range "equal length error ≤ 5mil, spacing ≤ 8mil", and the source metadata "source identifier = decoupling instruction set, instruction ID = DEC-2026-005". Another instruction "Analog input traces should be kept away from digital clock lines" generates DCU-E, which includes the constraint objects "AINP / AINN network" and "CLK network", the constraint type "spacing", the target value / range "≥ 40mil", and the source metadata "source identifier = risk guidance rule, instruction ID = RISK-001".

[0072] Step S3: The software calls the built-in EMC-Physical Mapping Library. Based on the current PCB stack-up (microstrip line, complete reference layer) and differential impedance requirement (100Ω), it calculates the required trace width of 6mil and trace spacing of 7mil using the microstrip line impedance formula. An enhanced DCU-D is generated, including the physical constraints "trace width = 6mil, trace spacing = 7mil, equal length error ≤ 5mil". For DCU-E, it is directly converted to "AINP / AINN network and CLK network spacing ≥ 40mil".

[0073] Step S4: Conflict detection revealed that the differential pair rule does not directly conflict with another risk guidance rule, "Audio input networks must be kept away from clock networks," but may indirectly conflict with layout space constraints. The priority rule base determined that "signal integrity rules have higher priority than regular layout rules," and the arbitration result prioritized satisfying the differential pair rule. Simultaneously, the software detected that DCU-D and DCU-E might impose constraints on the same area, but analysis showed that they can coexist without adjustment.

[0074] Step S5: Select Mentor PADS as the PCB design software in the format adapter to generate a .tec rule file. Simultaneously, a rule report and metadata file are generated, detailing the source and calculation basis of the differential pair rules.

[0075] Engineers imported the .tec file into PADS, and the rules were automatically loaded. The software also provides a preview function, displaying the generated rule list and its source information. Engineers completed the simulated front-end layout according to the rules, and subsequent tests showed that the audio signal-to-noise ratio met the expected target, and no clock noise coupling issues were found.

[0076] This embodiment demonstrates the application value of the present invention in fields such as medical electronics where signal quality requirements are extremely high. It reflects the ability to generate refined rules for analog / digital hybrid ICs, especially the accurate generation of rules for differential signals, isolation spacing, etc.

[0077]

Example 3

[0078] This embodiment uses the implementation of the method of the present invention as a PCB design software plugin (such as the Altium Designer plugin) as an example to illustrate its application in real-time rule generation and visualization in the design of isolated drives for industrial frequency converters.

[0079] An industrial automation company is designing a three-phase frequency converter. Its power module uses a domestically produced isolated driver chip (model IC10-1, operating frequency 20kHz PWM, rise time <100ns). The IC10-1 drives the IGBTs, and its layout directly affects switching characteristics and EMI, requiring strict adherence to rules such as short drive loops, isolation between power and control grounds, and minimizing drive output trace length. The PCB is a 4-layer board, measuring 150mm × 120mm, with clear separation between the power and digital sections.

[0080] After completing the schematic design in Altium Designer, the engineer activates the plugin for this invention. The plugin automatically reads the netlist and component information of the current design project and obtains the structured data assets for the project (such as decoupling instruction sets, alternative measure sets, etc.) as input for rule generation.

[0081] Steps S1-S2: The plugin backend acquires structured data assets and parses them to generate design constraint units. For example, the decoupling instruction "Drive output loop should be as short as possible, trace length ≤ 15mm" generates DCU-F, which includes the constraint object "IC10-1_OUT network", constraint type "trace length", target value / range "≤ 15mm", and source metadata "source identifier = decoupling instruction set, instruction ID = DEC-2026-006". Another instruction "Power ground and control ground should be single-point connected" generates DCU-G, which includes the constraint objects "GND_PWR" and "GND_CTRL", constraint type "connection method", target value / range "single-point connection", and source metadata "source identifier = alternative measures set, instruction ID = ALT-ISO-001".

[0082] Step S3: Call the EMC-Physical Mapping Library to map the "trace length ≤ 15mm" constraint to specific physical constraints based on the current PCB stack-up (2-layer board, no complete reference plane in the power area) and peak drive current. For the trace length requirement, the mapping library, considering the drive current rise time (<100ns) and loop inductance limitations, derives the layout guideline that "drive output traces must be directly connected to the IGBT gate to avoid detours." Simultaneously, based on the peak drive current and the IPC-2221 current density calculation formula, a trace width constraint of "trace width should be ≥ 20mil" is mapped.

[0083] Step S4: Conflict detection revealed a potential conflict between this length requirement and another decoupling instruction, "The drive input signal must be kept away from the power loop" (the input side must be kept away from the output side). Analysis showed that the input signal and output loop are naturally separated in their physical layout, with no substantial contradiction. The arbitration result was that both rules could be satisfied independently, requiring no adjustment.

[0084] Step S5: The plugin directly loads the rules into the rule manager of the current PCB design environment in real time via the Altium Designer API, without exporting files. Simultaneously, the plugin visually prompts the constrained objects:

[0085] Highlight the driver output network in orange and display a trace length limit warning;

[0086] When the mouse hovers over IC10-1, the range of "output circuit ≤ 15mm" is displayed with dynamic boundaries;

[0087] Between power ground and control ground, mark the single-point connection location with a green dashed box and display "Width of single-point connection ≥ 50mil";

[0088] Clicking on IC10-1 will bring up a floating label that displays "This rule comes from the decoupling instruction set, instruction ID=DEC-2026-006, confidence level 0.95, applicable to high-voltage isolation drive".

[0089] Engineers receive real-time visual guidance during layout, ensuring that drive output traces are directly connected to the IGBT gates to avoid detours, and that single-point copper bridges are set up at designated locations. Once all IC-level PCB design rules are met, the plugin displays "IC-level PCB design rule check passed."

[0090] After the design is completed, the plugin stores the rule application results (such as the measured value of the drive circuit length and the single-point connection impedance) and subsequent test feedback (manually entered by the engineer or automatically imported) to the user's local design knowledge base for optimizing the rule generation of subsequent frequency converter projects.

[0091] It should be noted that plugins can acquire structured data assets in various ways, such as by calling the data asset server via a network API, reading data files generated by standalone software, or querying from the user's local design knowledge base. This embodiment uses the example of a plugin directly calling the data asset interface, but it should not be construed as limiting the way the plugin acquires data.

[0092] This embodiment demonstrates the ability of the present invention as a plug-in to achieve real-time rule generation and visual feedback in the field of industrial power electronics, solving the layout difficulties of key ICs such as isolated drivers, especially the precise constraints on special rules such as drive circuit length and single-point connection.

[0093] Application Examples

[0094] The following application examples from three different fields—consumer electronics, medical electronics, and industrial control—further illustrate the technical effects of this invention.

[0095] 1. Application in EMC intelligent design instruments: Clock rule generation for smartwatch main control board

[0096] In the design of the smartwatch's main control board, engineers used an EMC intelligent design tool to generate rules for the main control chip (application processor) and the 32.768kHz clock crystal oscillator. The tool retrieves decoupling instructions (such as "no traces below the crystal oscillator, surround it with a ground ring, and the load capacitor should be close to the crystal oscillator pins") and a set of alternative measures from system-level EMC data assets to generate a PCB design rule file. After importing the rules, engineers complete the layout in the PCB design software, ensuring stable crystal oscillation and effective control of clock radiation. This rule file and its metadata are stored in the user's local design knowledge base for reference in subsequent low-power product designs.

[0097] 2. Application in standalone software tools: Generation of front-end PCB design rules using spectrum analyzer simulation.

[0098] A test and measurement company is developing a handheld spectrum analyzer with a multi-stage amplifier and a high-performance ADC in its analog front-end. Engineers are using a standalone software tool to import structured data assets for this analog front-end. The software then generates rule files for corresponding PCB design software, including amplifier input matching network layout rules (e.g., "input differential pairs must be symmetrical and of equal length," "feedback resistors should be close to amplifier pins") and ADC power supply decoupling rules (e.g., "each pair of power supply pins needs a 0.1μF and a 10μF capacitor, and the 0.1μF capacitor should be flush against the pin"). The generated rule files include rule reports explaining the source (e.g., from the decoupling instruction set) and confidence level of each rule. Engineers complete the design according to the rules, and the initial test results show that sensitivity and dynamic range meet the requirements.

[0099] 3. Application in PCB design software plugins: Generation of PCB design rules for industrial PLC power modules

[0100] During the design process of industrial PLC power modules, engineers use the plugin of this invention to obtain rules for multi-output power ICs (such as buck converters and LDOs), and highlight the constrained objects (such as input capacitor locations, inductor layout areas, and feedback path routing areas) in a visual manner in PCB design software. The plugin provides a rule source traceability function, allowing engineers to view the basis of the rules at any time (e.g., "This rule comes from the alternative measures set for this power IC, and it is recommended that the input capacitors use X7R material"). After the design is completed, the rule application results are fed back to the local knowledge base, optimizing the generation of PCB design rules for subsequent power modules.

[0101] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for generating PCB design rules based on system-level EMC data assets, characterized in that, Includes the following steps: S1. Obtain at least one structured data asset extracted from system-level EMC data assets, wherein the structured data asset includes at least one of decoupling instruction set, alternative measure set, and risk guidance rules; S2. The structured data assets are parsed through the rule parsing engine to generate at least one Design Constraint Unit (DCU). Each Design Constraint Unit contains the constraint object, constraint type, target value / range, and source metadata. S3. Call the EMC-Physical Mapping Library to quantify the EMC performance indicators in the design constraint unit into PCB physical parameters, and generate an enhanced design constraint unit containing physical constraints. S4. Detect conflicts among multiple enhanced design constraint units and arbitrate them based on the priority rule base to generate a fused constraint set; S5. Convert the fused constraint set into PCB design rule data using a format adapter for output.

2. The method according to claim 1, characterized in that, The structured data assets also include component selection recommendations; the component selection recommendations include at least the component's packaging information, electrical parameters, and recommended layout location, which are used to generate corresponding component layout constraints and attribute setting rules in the PCB design rule data.

3. The method according to claim 1, characterized in that, The rule parsing engine's parsing process includes: identifying semantic tags in structured data assets, extracting constraint object identifiers, constraint type keywords, performance index values ​​and units, and associating them with corresponding source identifiers, instruction IDs, version numbers and confidence information to form a standardized design constraint unit data structure.

4. The method according to claim 1, characterized in that, The EMC-Physical Mapping Library contains at least one of the following mapping relationships: theoretical formula mapping, simulation calibration curve mapping, and measured empirical value mapping; the quantitative conversion maps EMC performance indicators to specific PCB geometric parameters or electrical parameters based on the current PCB stack-up structure, material parameters, and manufacturing process capabilities.

5. The method according to claim 1, characterized in that, The conflict detection is based on a constraint dependency graph, which uses design constraint units as nodes and the relationships between constraint objects as edges. The arbitration is automatically adjusted according to the priority order of the rule types predefined in the priority rule base. Conflicts that cannot be resolved automatically will generate a conflict report for user confirmation.

6. The method according to claim 1, characterized in that, The format adapter calls the corresponding design rule template for different PCB design software, fills the fusion constraint set into the template, and generates a PCB design rule file that conforms to the syntax specification of the target software. The design rule file includes at least one of the following: Altium Designer's .DRU format, Cadence Allegro's .RUL format, Mentor PADS's .tec format, or intermediate exchange format conforming to the IPC-2581 standard.

7. The method according to claim 1, characterized in that, While generating the PCB design rule file, a rule report and a rule metadata file are also generated; the rule report describes the source identifier, instruction ID, version number, confidence level, mapping basis, and priority of each rule in a readable format; The rule metadata file stores the traceability relationship between each rule and the original data asset in a structured format, which is used for subsequent rule validity verification and closed-loop optimization.

8. The method according to claim 1, characterized in that, The method is applied to an EMC intelligent design instrument as a module for generating IC-level PCB design rules based on structured data assets; the instrument has built-in the rule parsing engine, the EMC-physical mapping library, the priority rule library, and the format adapter; Users can trigger the generation of design rules through the instrument interface and export the PCB design rule file for use by external PCB design software. The generated rule report and rule metadata file are stored in the user's local design knowledge base.

9. The method according to claim 1, characterized in that, The method is implemented as a standalone computer software product or a plug-in to PCB design software; the software product provides a graphical user interface that supports users in importing structured data assets, selecting PCB design software types, previewing generated rule content, and exporting PCB design rule files. The plugin can read the netlist and component information of the current design project, obtain the structured data assets for the project extracted from the system-level EMC data assets, generate and load PCB design rules into the current design environment in real time, and visually prompt the constrained objects and their source information, including at least one of the following: highlighting, dynamic boundaries, floating labels, and icon markings.

10. The method according to claim 1, characterized in that, The generated PCB design rules are applied to the design project, and the results of rule application and subsequent test feedback are stored in the user's local design knowledge base. The rule application results and test feedback are used to optimize the mapping relationships in the EMC-Physical Mapping Library and the priority rules in the Priority Rule Library, enabling continuous self-growth of PCB design rule-related data in the user's local design knowledge base. Based on the historical rule application results and test feedback accumulated in the user's local design knowledge base, the generation logic of the fusion constraint set is continuously optimized, and design rule template data assets are generated and updated. The design rule template data assets store design rule template parameters, typical application scenarios, and recommended rule combinations of different PCB design software in a structured form.

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