A border-aware macrocell layout optimization method
By constructing a boundary-aware macrocell layout optimization method, introducing a boundary attraction target term and improving the estimation of infill cell area, and combining a multi-stage weight scheduling strategy, the problem of macrocells clustering at the layout center is solved, thereby improving the layout's wiredability and timing performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTHWEAT UNIV OF SCI & TECH
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-12
AI Technical Summary
Existing technologies lack a dedicated boundary guidance mechanism in macro cell layout optimization, which causes macro cells to tend to cluster in the central area of the layout, leading to wiring congestion and timing violations. At the same time, the fill cell area estimation model is coarse, limiting the macro cell migration capability.
A boundary-aware macrocell layout optimization method is adopted. This method constructs a composite objective function that includes a boundary attraction objective term, improves the filling cell area estimation model, and combines a multi-stage adjustable boundary-guided weight scheduling strategy to optimize the macrocell distribution.
It effectively guides macrocells to distribute towards the edge of the layout region, improves the routing feasibility and timing performance of the layout, solves the macrocell aggregation problem, and improves the solution quality and stability of layout optimization.
Smart Images
Figure CN122197798A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit physical design technology, and in particular to a boundary-aware macrocell layout optimization method. Background Technology
[0002] Currently, the University of Texas at Austin and NVIDIA have jointly developed the open-source analytical layout optimization system DREAMPlace. This tool, for the first time, transforms the layout problem in integrated circuit physical design into a numerical optimization problem similar to deep learning training, and is built on the PyTorch framework, achieving full-process GPU acceleration. As a global layout optimization method, DREAMPlace leverages GPU parallel computing to significantly accelerate the density map construction, gradient calculation, and objective function evaluation processes, completing the initial layout of millions of cells within minutes. This demonstrates that DREAMPlace possesses excellent computational performance and high convergence efficiency when handling large-scale mixed-size designs. However, this technology still has two key technical limitations in macrocell layout: First, there is a lack of a dedicated macrocell boundary guidance mechanism. DREAMPlace employs a unified continuous optimization strategy, treating standard cells and macrocells as movable objects with the same driving force model, both subject only to the combined effects of line length and density forces. However, in actual layout, macrocells are much larger than standard cells, making their "interference" effect in the layout space more significant. Because DREAMPlace's objective function does not design an independent behavioral model or displacement driving force for macrocells, they tend to cluster at the center of the layout area during placement: severe macroblockage forms in the central region, dividing the placement space of standard cells and forcing them to be distributed only in narrow and discontinuous sub-regions; subsequent routing paths experience severe detours, increasing actual line length, routing layers, and delay burden; simultaneously, it makes local density adjustment difficult, affecting convergence stability and layout quality. Figure 1 As shown, the result of traditional mixed-size layout is usually that the intermediate macrocells are too concentrated. This not only limits the solution space for macrocell placement, but may also cause severe routing congestion in subsequent routing, making it difficult to optimize timing indicators and causing the chip to fail to achieve the expected performance.
[0003] Secondly, the filler cell area estimation model is too coarse, affecting the macrocell migration capability. To achieve density balance and target density constraints, DREAMPlace introduces filler cells in the layout region as "pseudo-cells" simulating unoccupied space to maintain the target region density. However, the formula for calculating the filler cell area is relatively simple, and the model does not consider that a halo region (i.e., a layout no-go zone) is usually reserved around macrocells to ensure wired routing, and this region is not eliminated during filler cell calculation. This leads to the halo region around macrocells being misjudged as a deployable region during layout optimization, resulting in a large number of filler cells being filled, forming a false high-density region. During gradient descent, macrocells are suppressed by pseudo-density forces, unable to effectively move away from the central region to the boundary, and may even experience positional oscillations or local jamming. This problem is particularly prominent in macrocell-dense designs, severely limiting the optimization freedom of macrocell positions and reducing the adjustability of the global layout space. Therefore, the coarse design of the filler cell model has become one of the main obstacles restricting the high-quality distribution of macrocells.
[0004] In summary, although DREAMPlace has high engineering maturity and computational efficiency among modern analytical layout optimization methods, it still has two serious shortcomings in macrocell layout optimization: the lack of a dedicated macrocell boundary guidance mechanism and the reliance on line length and density as optimization drivers by traditional analytical layout methods. This leads to macrocells tending to cluster in the layout center during the optimization process, blocking the available space of standard cells and causing wiring congestion and timing violations.
[0005] Therefore, how to provide a boundary-aware macrocell layout optimization method to solve the difficulties of the existing technology is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] In view of this, the present invention provides a boundary-aware macrocell layout optimization method, which can effectively guide macrocells to be distributed towards the edge of the layout region, thereby improving the routing feasibility and timing performance of the layout.
[0007] To achieve the above objectives, the present invention adopts the following technical solution: A boundary-aware macrocell layout optimization method includes the following steps: The chip layout is divided into a grid, and macrocells and standard cells are modeled as movable rectangular objects; An objective function is constructed based on the mesh line length, density, and macrocell boundary attraction. The center position of each cell is optimized separately until the objective function converges. An improved total area estimation model for filled cells is used to optimize the density objective function. The chip layout is optimized by using GPU-accelerated differentiable optimization methods for efficient solution and by employing a multi-stage adjustable boundary-guided weight scheduling strategy.
[0008] Optionally, the objective function can be formalized as a multi-objective continuous optimization problem, and a composite objective function can be constructed as follows: , in, This indicates the length of the weighted average line, used to shorten signal paths and reduce communication delays. This represents a density penalty term used to constrain the density distribution of the layout area. This represents the boundary attraction objective term, acting alone on the macrocell. , They are respectively , The weight.
[0009] Optional, A smooth approximation is performed using the soft-min function, and the corresponding expression is: , , , , , in: Hyperparameters for adjusting the smoothness , Represents the position vector of a macrocell; These represent the left, right, bottom, and top boundaries of the chip layout area, respectively.
[0010] Optionally, an improved total area estimation model for filled cells is used to exclude spaces around the macro that should not be filled, preventing density forces from misleading the macro's location. The corresponding expression is: , in, This represents the total area of the filled cells. This represents the area of the unused space excluding all fixed components. This represents the total area of all macro-external halo. Represents the area of all movable macros. This indicates the target density of the layout.
[0011] Optional, multi-stage adjustable boundary-guided weight scheduling strategies include: A phased boundary attraction scheduling mechanism is introduced to dynamically adjust the weights of the boundary attraction terms according to different optimization stages. This enables a continuous transition from strong guidance to weak guidance.
[0012] Optional, different stages of optimization include: Initial guidance phase: Set a large boundary attraction weight value to push macrocells towards the boundary direction first, breaking the initial central aggregation state; Density and line length harmonization stage: Appropriately reduce boundary attraction, enhance the dominant role of line length compression and density balance, and achieve macro- and unit collaborative optimization; Fine-tuning convergence phase: Selectively shut down the boundary attraction term, retaining only the spatial distribution inertia it brings, so that the layout enters the final stable phase.
[0013] As can be seen from the above technical solutions, compared with the prior art, the present invention provides a boundary-aware macrocell layout optimization method with the following beneficial effects: 1) The present invention introduces a penalty term based on the minimum boundary distance squared into the analytical macrocell layout objective function for the first time, which is used to actively guide macrocells to migrate towards the layout boundary, solving the problem of macrocells clustering in the chip center. This function form has a clear gradient direction, supporting efficient calculation and backpropagation in the GPU acceleration framework; 2) The present invention proposes to explicitly remove the area of the macrocell halo region in the calculation of the fill cell area, while reducing the total area of the fill cells, avoiding macrocell constraints caused by false high density, fundamentally improving the migration freedom of macrocells, and improving the solution quality of layout optimization; 3) The present invention sets a phased boundary attraction weight. This method strengthens boundary-driven optimization in the early stages and gradually weakens it during the convergence phase, thereby improving the stability, continuity, and engineering adaptability of the optimization process. It is a time-domain controllable dynamic objective function scheduling technique. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0015] Figure 1 This is a flowchart of a boundary-aware macrocell layout optimization method disclosed in this invention; Figure 2a This is a schematic diagram of the macro placement result without a macro attraction term in the objective function, as disclosed in an embodiment of the present invention; Figure 2b This is a schematic diagram of the macro placement result after adding macro attraction items as disclosed in an embodiment of the present invention; Figure 3a This is a layout result diagram of the total area of the filled cells calculated using the original method, as disclosed in an embodiment of the present invention. Figure 3b This is a layout result diagram after using the method for the total area of the filling cells proposed in this application, as disclosed in an embodiment of the present invention. Figure 4 The present invention discloses Schematic diagram of the changes. Detailed Implementation
[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] Reference Figure 1 As shown, this invention discloses a boundary-aware macrocell layout optimization method, comprising the following steps: The chip layout is divided into a grid, and macrocells and standard cells are modeled as movable rectangular objects; An objective function is constructed based on the mesh line length, density, and macrocell boundary attraction. The center position of each cell is optimized separately until the objective function converges. An improved total area estimation model for filled cells is used to optimize the density objective function. The chip layout is optimized by using GPU-accelerated differentiable optimization methods for efficient solution and by employing a multi-stage adjustable boundary-guided weight scheduling strategy.
[0018] Furthermore, the objective function is formalized into a multi-objective continuous optimization problem, and a composite objective function is constructed as follows: , in, This represents the weighted average line length, used to shorten signal paths and reduce communication latency. It is one of the most basic and widely used metrics in layout optimization. This term is usually calculated using differentiable approximations such as Log-Sum-Exp (LSE) or Weighted-Average (WA) to maintain first-order continuity during numerical optimization and adapt to GPU-accelerated environments. This represents a density penalty term used to constrain the density distribution of the layout area, preventing the formation of excessively high-density areas that could lead to congestion, routing failures, or violations of process rules. A global density balance target is constructed by squaring and summing the differences between the current cell occupancy rate and the target density for all bin regions. This represents the boundary attraction objective term, acting solely on macrocells. Its purpose is to guide macrocells to migrate towards the chip edge, mitigating the problem of macrocells tending to cluster in the central region. , They are respectively , The weight.
[0019] In one specific embodiment, the schematic diagram after adding the additional macro driving force term is as follows: Figures 2a-2b As shown: cyan represents macrocells; Figure 2a This indicates that the macro attraction term proposed in this application was not added to the objective function. The diagram illustrates the result of macro placement. Figure 2b This indicates the result after adding the macro attraction term proposed in this application. It can be seen that before adding the additional driving force, the macros were placed more concentratedly, which has a significant impact on subsequent chip routing and can even lead to routing failure.
[0020] Furthermore, the original boundary attraction objective term is defined as follows:
[0021] in, Represents the position vector of a macrocell; These represent the left, right, bottom, and top boundaries of the chip layout area, respectively. The function value represents the square of the nearest distance from the macrocell to the four boundaries.
[0022] During optimization, this component provides a guiding force towards the boundary. Its minimization effect is to push macrocells toward the nearest boundary, thereby preventing multiple macrocells from piling up at the chip center, freeing up central space, and improving the placement flexibility of standard cells and timing optimization space.
[0023] Furthermore, since the aforementioned min function is not differentiable when the boundary distances are equal (e.g., macrocells are located on the diagonal or at the center), it affects the continuity and stability of the gradient solution. A smooth approximation using the soft-min function is employed to obtain the boundary attraction objective term. The corresponding expression is: , , , , , in: Hyperparameters for adjusting the smoothness , The larger the value, the closer the approximation is to the true minimum.
[0024] Furthermore, in order to overcome the problem that the total area estimation of filled cells in the prior art does not take into account the macro-halo region, this application redefines the method for calculating the total area of filled cells.
[0025] The original method is: However, this method does not exclude the area occupied by the halo region around the macro, causing the density model to misjudge the area around the macro as a fillable region, filling it with a large number of fill cells and forming a false high density, thereby hindering the migration of macro cells. Therefore, this application involves an improved fill cell total area estimation model to exclude the space around the macro that should not be filled, preventing the density force from misleading the macro position. The corresponding expression is: , in, This represents the total area of the filled cells. This represents the area of the unused space excluding all fixed components. This represents the total area of all macro-external halo. Represents the area of all movable macros. This indicates the target density of the layout.
[0026] In one specific embodiment, such as Figures 3a-3b As shown, the layout results differ under different filler calculation methods. Figure 3a This represents the layout result after calculating the total area of the filled cells using the original method. Figure 3b This diagram shows the layout result after using the method for total area of filled cells proposed in this application. In the diagram, the cyan rectangles represent macro cells, the blue rectangles represent numerous standard cells, and the gray rectangles represent filled cells. It can be seen that within the red rectangle... Figure 3a In this context, due to the excessively large total area of the fill cells, macro cells are difficult to push and place to the boundaries of the layout area. Figure 3b In this application, the total area of the filling cells is significantly reduced after the calculation method is applied, which allows macro cells to effectively spread to the boundaries of the layout area. At the same time, standard cells can also be more dispersed.
[0027] Furthermore, such as Figure 4 As shown, the multi-stage adjustable boundary-guided weight scheduling strategy includes: A phased boundary attraction scheduling mechanism is introduced to dynamically adjust the weights of the boundary attraction terms according to different optimization stages. This enables a continuous transition from strong guidance to weak guidance, thereby improving the convergence and robustness of the optimization.
[0028] Furthermore, the different stages of optimization include: Initial guidance phase: Set a large boundary attraction weight value to push macrocells towards the boundary direction first, breaking the initial central aggregation state; Density and line length harmonization stage: Appropriately reduce boundary attraction, enhance the dominant role of line length compression and density balance, and achieve macro- and unit collaborative optimization; Fine-tuning convergence phase: Selectively shut down the boundary attraction term, retaining only the spatial distribution inertia it brings, so that the layout enters the final stable phase.
[0029] Furthermore, this strategy controls the process through "weight interpolation" or "stage jumps" during the optimization process. The change in value ensures that early macrocells can quickly break away from the central aggregation state, improves the stability of the position of later macrocells, avoids oscillations or unnecessary movements, and prevents boundary forces from continuously dominating throughout the process and disrupting the convergence path of other objective terms.
[0030] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A boundary-aware macrocell layout optimization method, characterized in that, Includes the following steps: The chip layout is divided into a grid, and macrocells and standard cells are modeled as movable rectangular objects; An objective function is constructed based on the mesh line length, density, and macrocell boundary attraction. The center position of each cell is optimized separately until the objective function converges. An improved total area estimation model for filled cells is used to optimize the density objective function. The chip layout is optimized by using GPU-accelerated differentiable optimization methods for efficient solution and by employing a multi-stage adjustable boundary-guided weight scheduling strategy.
2. The boundary-aware macrocell layout optimization method according to claim 1, characterized in that, The objective function is formalized as a multi-objective continuous optimization problem, and a composite objective function is constructed as follows: ， in, This indicates the length of the weighted average line, used to shorten signal paths and reduce communication delays. This represents a density penalty term used to constrain the density distribution of the layout area. This represents the boundary attraction objective term, acting alone on the macrocell. , They are respectively , The weight.
3. The boundary-aware macrocell layout optimization method according to claim 2, characterized in that, A smooth approximation is performed using the soft-min function, and the corresponding expression is: ， ， ， ， ， in: Hyperparameters for adjusting the smoothness , Represents the position vector of a macrocell; These represent the left, right, bottom, and top boundaries of the chip layout area, respectively.
4. The boundary-aware macrocell layout optimization method according to claim 1, characterized in that, The improved total area estimation model for filled cells is used to exclude spaces around the macro that should not be filled, preventing density forces from misleading the macro's location. The corresponding expression is: ， in, This represents the total area of the filled cells. This represents the area of the unused space excluding all fixed components. This represents the total area of all macro-external halo. This represents the area of all movable macros. This indicates the target density of the layout.
5. The boundary-aware macrocell layout optimization method according to claim 2, characterized in that, Multi-stage adjustable boundary-guided weight scheduling strategies include: A phased boundary attraction scheduling mechanism is introduced to dynamically adjust the weights of the boundary attraction terms according to different optimization stages. This enables a continuous transition from strong guidance to weak guidance.
6. The boundary-aware macrocell layout optimization method according to claim 2, characterized in that, The different stages of optimization include: Initial guidance phase: Set a large boundary attraction weight value to push macrocells towards the boundary direction first, breaking the initial central aggregation state; Density and line length harmonization stage: Appropriately reduce boundary attraction, enhance the dominant role of line length compression and density balance, and achieve macro- and unit collaborative optimization; Fine-tuning convergence phase: Selectively shut down the boundary attraction term, retaining only the spatial distribution inertia it brings, so that the layout enters the final stable phase.