Optical line terminal test system, method and computer readable storage medium
By combining FPGA chips and flow testing equipment, efficient and low-cost full-layer PON protocol stack simulation of the optical line terminal test system is realized, solving the problems of high hardware cost and incomplete testing in the existing technology, and improving the comprehensiveness and reliability of OLT testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TP-LINK
- Filing Date
- 2026-03-17
- Publication Date
- 2026-06-12
Smart Images
Figure CN122204166A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to an optical line terminal testing system, method, and computer-readable storage medium. Background Technology
[0002] Passive Optical Networks (PONs) employ a point-to-multipoint architecture, using passive optical splitters to achieve downlink broadcast and uplink Time Division Multiple Access (TDMA) transmission. Due to their one-to-many characteristic, Optical Line Terminals (OLTs) require a large number of external Optical Network Units (ONUs) as testing equipment during full-load performance testing, resulting in complex test topologies and high deployment costs.
[0003] Furthermore, traditional software-simulated ONU terminals cannot fully simulate the underlying behavior of the PON protocol stack, especially in terms of Physical Layer Operations, Administration and Maintenance (PLOAM) interaction, ONU online process, and precise control of uplink time slots, which are significantly lacking and cannot meet the requirements for high-fidelity protocol conformance testing.
[0004] Therefore, how to achieve more comprehensive and accurate PON protocol stack testing while reducing hardware costs has become a key technical problem that urgently needs to be solved in the current OLT equipment testing field. Summary of the Invention
[0005] This application provides an optical line terminal (OLT) testing system, method, and computer-readable storage medium. It can simulate multiple ONUs using a single optical module port, significantly reducing hardware costs. Combined with traffic testing equipment, it enables linked uplink and downlink traffic testing, improving the comprehensiveness and reliability of OLT testing.
[0006] In a first aspect, this application provides an optical line terminal testing system, comprising: a test control device for configuring simulation parameters; an FPGA chip connected to both the test control device and the optical line terminal under test, for simulating the logical behavior of multiple optical network units (ONUs) according to the simulation parameters; and a traffic testing device connected to both the optical line terminal under test and the FPGA chip, for performing service traffic testing and generating service traffic test results based on the logical behavior of the multiple ONUs.
[0007] In some implementations, the FPGA chip is connected to the optical line under test terminal through a single optical module port and transmits and receives all PON messages through the same single optical module port.
[0008] In some implementations, the FPGA chip includes: a downlink parsing module for receiving and parsing downlink PON signals sent by the optical line terminal under test and obtaining uplink time slot allocation information; an uplink construction module for constructing uplink PON messages based on the uplink time slot allocation information; a time slot control module for controlling the transmission time of uplink messages; and a configuration control module connected to the test control equipment for receiving and storing simulation parameters.
[0009] In some implementations, the FPGA chip further includes an uplink / downlink interaction module for storing uplink time slot allocation information and providing it to the uplink construction module.
[0010] In some implementations, before the ONU comes online, the uplink construction module is used to obtain the information required for ONU registration from the configuration control module, construct a registration response message according to the silent window time slot issued by the optical line terminal under test, and send it; after the ONU comes online, the downlink parsing module is used to forward the parsed control message to the test control device, and forward the data message to the traffic test device; the uplink construction module is used to obtain the response message from the test control device, and obtain the data message from the traffic test device; the uplink construction module is also used to encapsulate the response message and the data message into an uplink PON message, and send the uplink PON message through the time slot control module.
[0011] In some implementations, the traffic testing equipment is used to: construct uplink and downlink service traffic for traffic testing; and to statistically analyze the service traffic test results.
[0012] In some implementations, the FPGA chip is used to: construct and send registration requests according to the silent window time slots issued by the optical network unit under test before the optical network unit goes online, until all simulated optical network units complete online registration; after the optical network unit goes online, forward the control messages issued by the optical network unit under test to the test control equipment to simulate OMCI protocol interaction, and forward the data messages issued by the optical network unit under test to the traffic test equipment for service flow testing.
[0013] Second aspect, an embodiment of the present application provides an optical line terminal testing method, which is applied to the optical line terminal testing system in any one of the above first aspects, including: performing simulation parameter configuration on the FPGA chip through a test control device, where the simulation parameters include the number of simulated ONUs, the SN codes of each ONU, the simulated distance parameters of each ONU, and the fault simulation parameters; constructing PON messages before the ONUs go online using the FPGA chip, and sending them according to the silent window time slots given by the to-be-tested optical line terminal to confirm that all ONUs go online at the to-be-tested optical line terminal; after all ONUs go online, simulating OMCI interaction using the control traffic channel and performing traffic running tests using the data traffic channel, and all PON messages are sent from the same port of the FPGA chip; generating service traffic test results.
[0014] Third aspect, the present application provides a chip, which is used to execute the method in the above second aspect.
[0015] Fourth aspect, the present application provides an electronic device, including a processor and a memory, where the processor is used to execute the computer program stored in the memory to implement the method in the above second aspect. Or, The electronic device includes the chip in the above third aspect.
[0016] Fifth aspect, the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it implements the method in the above second aspect.
[0017] Sixth aspect, the present application provides a computer program product, which stores a computer program, and when the computer program is executed by a processor, it implements the method in the above second aspect.
[0018] The technical solution provided by the present application simulates multiple ONUs through a single optical module port of the FPGA chip, greatly reducing the hardware cost and simplifying the test topology. By connecting the ONU software simulator through the control traffic channel, full-level interaction simulation of the OMCI layer is achieved, making up for the deficiency of the pure hardware solution in protocol stack processing. By connecting an external traffic test device through the data traffic channel, it supports the construction and statistics of real service traffic and realizes up and down link joint testing. Through the configuration of fault simulation parameters, it supports the testing of various abnormal scenarios and enhances the robustness verification ability of the OLT. Description of the Drawings
[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of a PON structure provided in an embodiment of this application; Figure 2 This is a schematic diagram of a system structure of an optical line terminal testing system provided in an embodiment of this application; Figure 3 This is a schematic diagram of the internal structure of an FPGA chip in an optical line terminal testing system provided in this application embodiment; Figure 4 This is a schematic diagram of the internal data flow of an FPGA in an optical line terminal test system provided in an embodiment of this application; Figure 5 This is a schematic diagram of an uplink frame construction and transmission process of an optical line terminal testing system provided in this application embodiment; Figure 6 This is a schematic diagram of the overall interactive process of an optical line terminal testing system provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation
[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."
[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0027] With the rapid development and large-scale deployment of optical access network technology, PON has become one of the mainstream technologies for broadband access due to its advantages such as high bandwidth, wide coverage, and low operation and maintenance costs. PON adopts a point-to-multipoint architecture, using passive optical splitters to achieve downlink broadcasting and uplink time-division multiple access (TDMA) transmission. Its network structure is as follows: Figure 1 As shown.
[0028] Figure 1 This is a schematic diagram of a PON structure provided in an embodiment of this application. Wherein, Figure 1 (a) shows the downlink broadcast method: the OLT broadcasts data to all ONUs (including ONU1, ONU2 and ONU3), and each ONU selectively receives the data according to the identification information. Figure 1 (b) shows the uplink burst mode: each ONU (including ONU1, ONU2 and ONU3) sends data sequentially according to the time slots allocated by the OLT to avoid uplink conflicts.
[0029] During the R&D, testing, network access certification, and manufacturing of OLT devices, it is necessary to simulate scenarios where a large number of ONUs are simultaneously online and engaging in multi-dimensional business interactions to comprehensively verify the OLT's access capabilities, Dynamic Bandwidth Allocation (DBA) accuracy, OMCI management functions, and data forwarding performance. However, existing testing solutions have significant shortcomings in terms of cost, fidelity, and protocol coverage completeness, mainly in the following aspects: First, the physical topology testing solution based on real ONUs requires a large number of external ONU devices, optical splitters and optical fibers. The test topology is complex, the deployment cycle is long, and the hardware procurement and maintenance costs are high, making it difficult to meet the needs of large-scale and high-frequency testing.
[0030] Second, the ONU terminal solution based on software simulation: although it reduces hardware costs to some extent, it is limited by the real-time nature of software processing capabilities and cannot accurately simulate the timing control of the PON physical layer. In particular, it cannot realize the underlying protocol behaviors such as ONU registration process, physical layer operation management and maintenance (PLOAM) interaction, resulting in distorted test scenarios and incomplete protocol coverage.
[0031] Third, the simulation solution based on multi-port FPGA: Although it can achieve relatively precise time slot control through FPGA hardware, each simulated ONU requires an independent optical module port, resulting in high hardware costs. Furthermore, this type of solution lacks support for OMCI layer protocol interaction, cannot simulate the high-level management process between the ONU and OLT, and has functional blind spots.
[0032] In summary, traditional technical solutions struggle to balance low cost, high fidelity, and full protocol stack testing. How to achieve full-layer PON protocol stack simulation from the physical layer to the management layer while reducing hardware overhead has become a critical technical challenge that urgently needs to be addressed in the field of OLT equipment testing.
[0033] In view of this, embodiments of this application provide an optical line terminal (OLT) testing system. It can simulate multiple ONUs using a single optical module port, significantly reducing hardware costs. Combined with traffic testing equipment, it enables coordinated uplink and downlink traffic testing, improving the comprehensiveness and reliability of OLT testing.
[0034] The technical solutions of the embodiments of this application are described below with reference to the examples in the accompanying drawings.
[0035] Figure 2 This is a schematic diagram of a system structure for an optical line terminal testing system provided in an embodiment of this application. Figure 2As shown, the optical line terminal (OLT) testing system includes a test control device 210, an FPGA chip 220, a traffic testing device 230, and an OLT 240 under test. The test control device 210 is used to configure simulation parameters. The FPGA chip 220 is connected to both the test control device 210 and the OLT 240 (connected to the OLT 240 via an optical module), and is used to simulate the logical behavior of multiple optical network units (ONUs) according to the simulation parameters. The traffic testing device 230 is connected to both the OLT 240 and the FPGA chip 220, and is used to perform service traffic testing and generate service traffic test results based on the logical behavior of the multiple ONUs.
[0036] Specifically, the FPGA chip 220 can be connected to the optical line terminal under test (OPT) 240 through a single optical module port to simulate the logical behavior of multiple ONUs. In this embodiment, the FPGA chip 220 internally implements logical isolation and concurrent processing of multiple ONU instances. Each ONU instance has an independent SN code, registration status, and bandwidth request, but shares the same physical optical module port for transmission and reception. That is, the FPGA chip 220 is connected to the OPT 240 through a single optical module port and transmits and receives all PON messages through a single optical module port.
[0037] The test control device 210 may include a test control module 211 and an ONU software simulator 212. The test control module 211 can be used to configure simulation parameters (i.e., initial configuration) of the FPGA chip 220. Simulation parameters include, but are not limited to, one or more of the following: the number of simulated ONUs, the serial number (SN) of each ONU, the simulated distance parameters of each ONU, and fault simulation parameters (fault simulation parameters include at least one of encoding error parameters, abnormal emission parameters, and collision simulation parameters). The test control module 211 can run on a PC or embedded device and communicate with the FPGA chip 220 via interfaces such as PCIe, USB, or Ethernet.
[0038] The ONU software simulator 212 and the FPGA chip 220 can be connected via Ethernet port to transmit control plane messages in the PON protocol and realize interactive simulation of the OMCI layer. The ONU software simulator 212 runs on a PC or server, implements a complete OMCI protocol stack, and can respond to OMCI requests issued by the OLT and generate corresponding response messages.
[0039] The traffic testing device 230 and the FPGA chip 220 can be connected via a network port to transmit user plane data packets and support the construction and statistics of uplink and downlink service traffic. The traffic testing device 230 can be a professional network tester (such as Spirent, IXIA, etc.) or a general-purpose server running traffic generation software.
[0040] The FPGA chip 220 may include a downlink parsing module, an uplink construction module, a time slot control module, and a configuration control module. The downlink parsing module receives and parses the downlink PON signal sent by the optical line terminal under test, and obtains uplink time slot allocation information (including allocated uplink time slots and bandwidth). The uplink construction module constructs uplink PON messages (including control messages and data messages) based on the uplink time slot allocation information. The time slot control module controls the transmission timing of the uplink messages. The configuration control module, connected to the test control device 210, receives and stores simulation parameters. Control messages are output via the control flow channel, and data messages are output via the data flow channel.
[0041] For example, Figure 3 This is a schematic diagram of the internal structure of an FPGA chip for an optical line terminal testing system provided in an embodiment of this application. Figure 3 As shown, the FPGA chip 220 includes: a downlink parsing module 221, an uplink construction module 222, an uplink timeslot control module 223, and a configuration control module 224.
[0042] The downlink parsing module 221 is used to receive and parse the downlink PON signal sent by the OLT. The downlink PON signal contains the uplink time slot information and bandwidth information allocated by the OLT, as well as control messages and data messages.
[0043] Preferably, the FPGA chip 220 may also include an uplink / downlink interaction module 225. The downlink parsing module 221 extracts uplink-related configuration information from the downlink PON signal and stores it in the uplink / downlink interaction module 225. At the same time, it separates control messages and data messages and outputs them to the network port through the control flow channel 226 and the data flow channel 227, respectively.
[0044] The uplink construction module 222 is used to construct uplink PON messages based on the uplink time slot allocation information and bandwidth allocation information stored in the uplink and downlink interaction module 225, and send them through the uplink time slot control module 223 in the specified time slot.
[0045] The uplink / downlink interaction module 225 stores the uplink time slot allocation information and bandwidth allocation information extracted by the downlink parsing module 221 for use by the uplink construction module 222. This module can also maintain the current state of each ONU instance, such as registration status and authorized time slots.
[0046] The uplink time slot control module 223 is also used to control the transmission time and duration of uplink messages to ensure accurate transmission according to the time slots allocated by the OLT. The uplink time slot control module 223 is based on the high-precision clock of the FPGA to achieve nanosecond-level transmission timing control.
[0047] Configuration control module 224 and test control module 211 ( Figure 2 The module (as described in the corresponding embodiment) is connected to receive and store simulation parameters. Before the ONU goes online, the configuration control module 224 provides the upstream construction module 222 with the information required for ONU registration, such as the SN code and password, based on the simulation parameters, in order to construct a registration response message.
[0048] Preferably, the FPGA chip 220 may further include a fault simulation module 228, which can be used to generate and send fault simulation parameters (fault simulation parameters include one or more of coding error parameters, abnormal light emission parameters, and conflict simulation parameters) to the uplink construction module 222.
[0049] In the technical solution provided in this application embodiment, the data flow inside the FPGA chip 220 can be divided into downlink and uplink directions. Before the ONU goes online, the uplink construction module 222 is used to obtain the information required for ONU registration from the configuration control module 224, construct a registration response message according to the silent window time slot issued by the optical line terminal under test 240, and send it. After the ONU goes online, the downlink parsing module 221 is used to forward the parsed control message to the test control device 210, and forward the data message to the flow test device 230. The uplink construction module 222 is used to obtain the response message from the test control device 210, and obtain the data message from the flow test device 230, and encapsulate the response message and the data message into an uplink PON message and send it through the time slot control module 223.
[0050] The test control device 210 can simulate the protocol interaction of the ONU management and control interface OMCI layer through the ONU software simulator 212.
[0051] The traffic testing device 230 can be used to construct uplink and downlink traffic for traffic testing and to statistically analyze the results of traffic testing.
[0052] The FPGA chip is used in section 220 to construct and send registration requests according to the silent window time slots issued by the optical network unit under test (ONT) 240 before the ONT goes online, until all simulated ONTs complete online registration. After the ONTs are online, the control messages issued by the ONTs 240 are forwarded to the test control device 210 (specifically forwarded to the ONU software simulator 212 of the test control device 210) to simulate OMCI protocol interaction, and the data messages issued by the ONTs 240 are forwarded to the traffic test device 230 for service flow testing.
[0053] For example, Figure 4 This is a schematic diagram of the internal data flow of an FPGA in an optical line termination test system provided in an embodiment of this application. Figure 4As shown, the data flow inside the FPGA chip 220 can be divided into downlink and uplink directions.
[0054] Downlink data processing: Downlink parsing module 221 receives data from the optical line terminal 240 under test via the optical module. Figure 2 The downlink PON signal sent by the module in the corresponding embodiment. The downlink PON signal contains uplink time slot information and bandwidth information allocated by the OLT, as well as control messages and data messages.
[0055] Downlink parsing module 221 extracts uplink-related configuration information from the downlink PON signal and stores it in uplink / downlink interaction module 225; simultaneously, it separates control messages and data messages, outputting them to the network port via control flow channel 226 and data flow channel 227 respectively. The control message is output to ONU software simulator 212 via control flow channel 226. Figure 2 The data packets are processed by the module in the corresponding embodiment. The data packets are output to the flow test device 230 for processing through the data flow channel 227.
[0056] Uplink data processing: Before the ONU goes online (registration phase), the uplink construction module 222 obtains the information required for ONU registration (such as the SN code) from the configuration control module 224, constructs a registration response message according to the silent window time slot issued by the OLT, and sends it through the uplink time slot control module 223. At this time, the message content is entirely constructed internally by the FPGA.
[0057] After the ONU goes online, the uplink construction module 222 obtains control plane response messages (such as OMCI responses) generated by the ONU software simulator 212 from the control traffic channel 226, and data plane messages (such as user service data) generated by the traffic test device 230 from the data traffic channel 227. Based on the downlink time slot allocation information stored in the uplink-downlink interaction module 225, the uplink construction module 222 determines the message type and length to be sent in each time slot and constructs the uplink PON message. The uplink construction module 222 starts construction one time slot earlier than the actual transmission to ensure that the data is ready when the specified time slot arrives. The uplink time slot control module 223 controls the uplink message to be sent at a precise time based on the time slot information in the uplink-downlink interaction module 225.
[0058] The FPGA chip is used to: construct and send registration requests according to the silent window time slots issued by the optical network unit under test before the optical network unit goes online, until all simulated optical network units complete online registration; and after the optical network unit goes online, forward the control messages issued by the optical network unit under test to the ONU software simulator 212 to simulate OMCI protocol interaction, and forward the data messages issued by the optical network unit under test to the traffic testing equipment for service flow testing.
[0059] Figure 5 This is a schematic diagram illustrating an uplink frame construction and transmission process for an optical line terminal testing system provided in an embodiment of this application. Figure 5 As shown, the uplink frame construction and transmission process includes the following steps: First, obtain the allocation information for the next time slot from the uplink / downlink interaction module, including the time slot start time, time slot length, and corresponding ONU ID. Then, determine if the current ONU is registered. If not, obtain the ONU's registration information from the configuration control module and construct a registration response message (such as a sequence number response or password response). If registered, obtain the control plane messages to be sent (if any) from the control traffic channel and the data plane messages to be sent (if any) from the data traffic channel. Based on the time slot length and message priority, select the message to be sent and encapsulate it.
[0060] Then, an uplink PON frame is constructed, including a frame header, payload, and checksum field. The constructed uplink frame is stored in the transmit buffer, awaiting the transmission time. The time slot control module monitors the current time; when the time slot start time arrives, it reads data from the transmit buffer and transmits it through the optical module port.
[0061] If the report has been sent, update the relevant statistics and process the next time slot.
[0062] Figure 6 This is a schematic diagram of the overall interactive process of an optical line terminal testing system provided in an embodiment of this application. Figure 6 As shown, the overall process of the ONU simulation test method provided in this application embodiment includes: Set up the test topology: Connect the individual optical module port of the ONU simulation device to the PON port of the OLT via optical fiber. Connect the test control module (PC), ONU software simulator (PC), and external traffic testing equipment to the ONU simulation device via the network.
[0063] Initial Configuration: The test control module performs initial configuration on the FPGA, setting the number of simulated ONUs (e.g., 64), the serial number (SN) of each ONU, the simulated distance parameters (affecting equalization delay), and whether fault simulation is enabled. Simultaneously, the same number of ONUs and their SN codes are configured in the ONU software simulator.
[0064] ONU Registration: The OLT periodically issues discovery windows, and the FPGA sends a registration request within the discovery window based on the configuration information. After the OLT assigns an ONU-ID, the FPGA completes the registration process, including ranging and password verification. All PON messages during this stage are constructed internally by the FPGA.
[0065] OMCI Interaction: After the registration is completed, the OLT configures and manages the ONU through the OMCI channel (such as configuring service VLAN, bandwidth template, etc.). The OMCI requests sent by the OLT are sent to the ONU software simulator through the control traffic channel. The ONU software simulator generates OMCI responses and returns them to the OLT through the FPGA.
[0066] Service Traffic Running Test: The external traffic test device constructs upstream and downstream service traffic. The downstream traffic is forwarded by the OLT to the FPGA, and the upstream traffic is sent by the FPGA to the OLT according to the time slots allocated by the OLT. The traffic test device statistics performance metrics such as throughput, latency, packet loss rate, etc.
[0067] Fault Simulation Test: Configure fault simulation parameters through the test control module, such as constructing CRC error messages, simulating long light emission of ONU, simulating multiple ONU collision transmissions, etc., to verify the OLT's abnormal detection and handling capabilities.
[0068] Result Verification: Check whether all simulated ONUs are stably online and not kicked out by the OLT, which is used to check whether the traffic test results meet the expectations.
[0069] The technical solution provided by the embodiment of this application has been implemented and deployed on the self-developed FPGA board. The test results show that: a single optical module port can stably simulate 64 ONUs, and they are successively online on the OLT and continuously perform OMCI interactions, and the OLT management is normal; it can support the full-load traffic running test of the PON link (1Gbps for both upstream and downstream), and run continuously for 24 hours without packet loss; it can successfully simulate fault scenarios such as long light-emitting ONU and CRC error messages, and the OLT can correctly detect and isolate abnormal ONUs.
[0070] In the technical solution provided by this application, multiple ONUs are simulated through a single optical module port of the FPGA chip, which greatly reduces the hardware cost and simplifies the test topology. By connecting the ONU software simulator through the control traffic channel, the full-level interaction simulation of the OMCI layer is realized, which makes up for the deficiency of the pure hardware solution in protocol stack processing. By connecting the external traffic test device through the data traffic channel, it supports the construction and statistics of real service traffic, and realizes the upstream and downstream linkage test. By configuring the fault simulation parameters, it supports the test of multiple abnormal scenarios and enhances the OLT's robustness verification ability.
[0071] It should be understood that, on the premise of no logical conflict, the above-mentioned various application embodiments can be combined and implemented with each other to meet the actual application requirements. The specific embodiments or implementation schemes obtained after these combinations still fall within the protection scope of this application.
[0072] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.
[0073] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0074] Based on the same inventive concept, embodiments of this application also provide an electronic device.
[0075] Figure 7 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 7 As shown, the electronic device 70 of this embodiment includes: at least one processor 710 ( Figure 7 Only one is shown in the diagram), memory 720, and communication module 730. Memory 720 stores a computer program 740 that may run on processor 710. When processor 710 executes computer program 740, it implements the steps in the above-described optical line terminal testing method embodiment, for example... Figure 1 Steps S101 to S103 are shown. Alternatively, when the processor 710 executes the computer program 740, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 6 The data input module 610 to the processing module 620 shown have the same functions. The communication module 730 can be a separate communication unit used to communicate with external servers or terminal devices.
[0076] Electronic device 70 may include, but is not limited to, a processor 710 and a memory 720. Those skilled in the art will understand that... Figure 7 This is merely an example of electronic device 70 and does not constitute a limitation on electronic device 70. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 70 may also include input transmitting devices, network access devices, buses, etc.
[0077] The processor 710 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0078] In some embodiments, memory 720 may be an internal storage unit of electronic device 70, such as a hard disk or memory of electronic device 70. Memory 720 may also be an external storage device of electronic device 70, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on electronic device 70. Memory 720 may include both internal and external storage units of electronic device 70. Memory 720 is used to store operating system, applications, bootloader, data, and other programs, such as the program code of computer program 740. Memory 720 may also be used to temporarily store data that has been sent or will be sent.
[0079] Furthermore, those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. In the various embodiments of this application, each functional unit can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0080] This application provides a computer-readable storage medium storing a computer program that, when run on an electronic device, causes the electronic device to perform the steps described in the various method embodiments above.
[0081] This application provides a chip, which includes a processor and a memory. The memory stores a computer program, which, when executed by the processor, implements the steps in the various method embodiments described above.
[0082] This application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the steps described in the various method embodiments above.
[0083] It should be understood that the processor mentioned in the embodiments of this application can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.
[0084] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).
[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0087] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0088] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.
[0089] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0090] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0091] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a large-screen device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.
[0092] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An optical line terminal testing system, characterized in that, include: Test control equipment, used to configure simulation parameters; An FPGA chip is connected to the test control equipment and the optical line terminal under test, respectively, and is used to simulate the logical behavior of multiple optical network units (ONUs) according to the simulation parameters. The traffic testing device is connected to the optical line terminal under test and the FPGA chip respectively, and is used to perform service traffic testing and generate service traffic test results based on the logical behavior of the multiple optical network units (ONUs).
2. The optical line terminal testing system according to claim 1, characterized in that, The FPGA chip is connected to the optical line under test terminal through a single optical module port, and sends and receives all PON messages through the single optical module port.
3. The optical line terminal testing system according to claim 1, characterized in that, The FPGA chip includes: The downlink parsing module is used to receive and parse the downlink PON signal sent by the optical line terminal under test, and obtain uplink time slot allocation information; The uplink construction module is used to construct uplink PON messages based on the uplink time slot allocation information; The time slot control module is used to control the transmission time of uplink messages; A configuration control module is connected to the test control equipment to receive and store the simulation parameters.
4. The optical line terminal testing system according to claim 3, characterized in that, The FPGA chip also includes: The uplink and downlink interaction module is used to store the uplink time slot allocation information and to provide it to the uplink construction module.
5. The optical line terminal testing system according to claim 3, characterized in that, Before the ONU goes online, the uplink construction module is used to obtain the information required for ONU registration from the configuration control module, construct a registration response message according to the silent window time slot sent by the optical line terminal under test, and send it. After the ONU goes online, the downlink parsing module is used to forward the parsed control messages to the test control device and to forward the data messages to the traffic test device. The uplink construction module is used to obtain response messages from the test control device and data messages from the traffic test device; The uplink construction module is further configured to encapsulate the response message and the data message into an uplink PON message, and send the uplink PON message through the time slot control module.
6. The optical line terminal testing system according to claim 1, characterized in that, The flow testing equipment is used for: Construct uplink and downlink traffic for testing; The results of the business traffic test are statistically analyzed.
7. The optical line terminal testing system according to claim 1, characterized in that, The FPGA chip is used for: Before the optical network unit goes online, a registration request is constructed and sent according to the silent window time slot issued by the optical line terminal under test until all simulated optical network units complete the online registration. After the optical network unit goes online, the control messages sent by the optical line terminal under test are forwarded to the test control device to simulate OMCI protocol interaction, and the data messages sent by the optical line terminal under test are forwarded to the traffic test device for service flow testing.
8. A method for testing optical line terminations, applied to the optical line termination testing system according to any one of claims 1 to 7, characterized in that, include: The FPGA chip is configured with simulated parameters through test control equipment. The simulated parameters include the number of simulated ONUs, the serial number (SN) of each ONU, the simulated distance parameters of each ONU, and the fault simulation parameters. The FPGA chip is used to construct the PON message before the ONU goes online, and it is sent according to the silent window time slot given by the optical line terminal under test to confirm that all ONUs are online at the optical line terminal under test. After all ONUs are online, OMCI interaction is simulated using the control flow channel, and a streaming test is performed using the data flow channel. All PON messages are sent from the same port of the FPGA chip. Generate business traffic test results.
9. An electronic device, characterized in that, It includes a processor and a memory, the processor being used to execute a computer program stored in the memory to implement the optical line termination testing method as described in claim 8.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the optical line termination test method as described in claim 8 above.