Photonics chip testing method and optoelectronic integrated testing device

Abstract

The application provides a photonic chip testing method and an optoelectronic integrated testing device, which test the photonic chip in the form of optical pulses, and the design of the optoelectronic integrated testing device enhances the applicability to high-loss photonic chips, so that the testing of larger-scale photonic chips can be carried out. The device has a high optical pulse off ratio, the pulse width of the optical pulse can be adjusted, and stable micro delays can be maintained between multiple optical pulses, which ensures the testing and evaluation accuracy of the photonic chip and richer testing functions. The testing device is systematically integrated, and the pulsed light source system and the signal acquisition system can realize high-speed communication control with the upper computer, so that convenient and efficient testing of the photonic chip can be realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated photonic chip testing and evaluation technology, and in particular to a photonic chip testing method and optoelectronic integrated testing device. Background Technology

[0002] With the widespread application of artificial intelligence and machine learning technologies, the demand for high-performance, low-energy computing hardware in the field of intelligent data processing is becoming increasingly urgent. In recent years, photonic chips, due to their high bandwidth, low power consumption, and wavelength division multiplexing capabilities, have become a powerful alternative for solving the energy consumption problem in artificial intelligence computing. As an information carrier, photons, compared to electrons, have more multiplexing dimensions, greater bandwidth, faster speed, larger communication capacity, and lower energy consumption, thus exhibiting superior information processing capabilities. The rapid development of the photonic chip field has also spurred an urgent need for photonic chip testing methods and devices. Photonic chip testing started later than electronic chip testing, the testing systems are more complex, and their applicability to photonic chips with different characteristics is weak, requiring further development and improvement. The development of photonic chip testing methods and devices will help shorten the iteration cycle of photonic chip development. A fast and accurate automated testing platform can allow researchers to focus on design and development itself. This is expected to greatly accelerate the process of photonic chips from concept to prototype and then to product, pushing cutting-edge photonic technology from the laboratory to industrialization and large-scale application more quickly. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention provides a photonic chip testing method and an optoelectronic integrated testing device. It mainly realizes the optoelectronic integration of the pulse light source system and the signal acquisition system required for photonic chip testing, improves the testing capability for large-scale high-loss photonic chips, and provides a convenient and efficient solution for testing multiple functions of photonic chips.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] On one hand, the present invention provides a photonic chip testing method, comprising the following steps: (1) Determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple optical pulses. (2) Based on the combination of test parameters, N polarization-maintaining continuous lasers with stable power and linewidth less than 10MHz are generated by the pulse light source system, and the center wavelength of each polarization-maintaining continuous laser is locked to the 50GHz standard dense wavelength division multiplexing wavelength. (3) Each polarization-maintaining continuous laser beam is input to the corresponding semiconductor optical amplifier chip. By independently controlling the gain switching characteristics of each semiconductor optical amplifier chip, N-channel optical pulses with adjustable pulse width and adjustable power are generated. The pulse width of each optical pulse is adjustable in the range of 1ns to 20ns, and the turn-off ratio of each optical pulse power is above 40dB. (4) The N-channel optical pulses are vertically coupled through an optical fiber array and simultaneously enter the N input ports of the photonic chip under test. The delay difference between the N-channel optical pulses entering the photonic chip under test is less than 500ps. (5) Collect the N optical signals output after the photonic chip under test has completed the calculation and processing, and convert them into N electrical signals; (6) Collect N electrical signals and upload them to the host computer for storage and analysis.

[0006] Furthermore, in step (3), by applying a pulse signal to the driving current of each semiconductor optical amplifier chip, each semiconductor optical amplifier chip is rapidly turned on and off under the drive of the pulse current. The change in the carrier concentration in the active region causes the output optical power to generate pulse fluctuations, thereby realizing the control of the optical pulse.

[0007] On the other hand, the present invention provides an optoelectronic integrated testing device for implementing the aforementioned photonic chip testing method, comprising: The parameter configuration module is used to determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple channel optical pulses. A pulsed light source system is used to generate N-channel light pulses with adjustable wavelength, adjustable pulse width, and adjustable power that conform to the combination of the test parameters. An optical fiber array, whose N input ends are respectively connected to the N output ends of the pulsed light source system, and whose N output ends are perpendicularly coupled to the N input ports of the photonic chip under test; The signal acquisition system has N input terminals connected to the N output ports of the photonic chip under test, and synchronously acquires the N optical signals output by the photonic chip under test after calculation and processing. The signals are then converted into N electrical signals and uploaded to the host computer for storage and analysis.

[0008] Furthermore, the pulsed light source system includes: A distributed feedback laser array is used to generate N beams of polarization-maintaining continuous laser with stable power and a linewidth of less than 10 MHz. The current and temperature control chip is used to control the wavelength of each laser in the distributed feedback laser array, so that the center wavelength of each polarization-maintaining continuous laser beam output by the distributed feedback laser array is locked to the 50GHz standard dense wavelength division multiplexing wavelength. The semiconductor optical amplifier array consists of N semiconductor optical amplifier chips, and each laser in the distributed feedback laser array is connected to a semiconductor optical amplifier chip in the semiconductor optical amplifier array in the corresponding output optical path. A high-speed, high-precision control chip is connected to N semiconductor optical amplifier chips. By controlling the gain switching characteristics of each semiconductor optical amplifier chip, the semiconductor optical amplifier array generates N channels of optical pulses with adjustable pulse width and power. The pulse width of each channel is adjustable within the range of 1ns to 20ns, the maximum optical pulse power is above 20mW, and the turn-off ratio of the optical pulse power is above 40dB. The delay difference between each channel optical pulse is controlled within 500ps to meet the maximum allowable delay difference between multi-channel optical pulses in the test parameter combination.

[0009] Furthermore, the pulsed light source system also includes N pre-erbium-doped fiber amplifiers. The output terminal of each semiconductor optical amplifier chip is connected to a pre-erbium-doped fiber amplifier. The pre-erbium-doped fiber amplifier is used to further amplify the power of the optical pulse in the corresponding channel, and increase the peak power of the optical pulse to 1W while maintaining the optical pulse waveform of each channel.

[0010] Furthermore, the signal acquisition system includes N post-erbium-doped fiber amplifiers, an avalanche photodetector array, and a high-speed multi-channel data acquisition card; The input ends of the N post-erbium-doped fiber amplifiers are respectively connected to the N output ports of the photonic chip under test, and are used to amplify the N optical signals output after the photonic chip under test has completed the calculation and processing. The avalanche photodetector array consists of N avalanche photodetectors, with each of its N input terminals connected to the output terminal of a post-erbium-doped fiber amplifier, which is used to convert the amplified N optical pulse signals into N electrical signals. The high-speed multi-channel data acquisition card receives the electrical signals output by the avalanche photodetector array and uploads them to the host computer in real time.

[0011] Furthermore, the high-speed multi-channel data acquisition card is connected to the host computer via an Ethernet interface or a fiber optic interface to enable real-time data upload.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The photonic chip testing method provided by this invention tests the photonic chip in the form of light pulses. The design of the optoelectronic integrated device enhances the applicability to high-loss photonic chips, thereby enabling testing of larger-scale photonic chips.

[0013] The optoelectronic integrated testing device provided by this invention is used to implement the aforementioned photonic chip testing method. This device has a high optical pulse turn-off ratio, adjustable optical pulse width, and can maintain a stable small delay between multiple optical pulses, thus ensuring the testing and evaluation accuracy of photonic chips and providing richer testing functions.

[0014] The optoelectronic integrated testing device provided by this invention has achieved systematic integration, realizing the optoelectronic integration of the pulse light source system and signal acquisition system required for photonic chip testing, improving the testing capability for large-scale high-loss photonic chips. Both the pulse light source system and the signal acquisition system can achieve high-speed communication and control with the host computer, enabling convenient and efficient testing of photonic chips. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the photonic chip optoelectronic integration testing device in one embodiment; Figure 2 This is a test flowchart of a photonic chip in one embodiment. Detailed Implementation

[0017] The technical solution of the present invention will now be clearly and completely described through specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0018] In one embodiment, a photonic chip testing method is provided, comprising the following steps: (1) Determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple optical pulses. (2) Based on the combination of test parameters, N polarization-maintaining continuous laser beams with stable power and linewidth less than 10 MHz are generated by a pulsed light source system. The center wavelength of each polarization-maintaining continuous laser beam is locked to the 50 GHz standard dense wavelength division multiplexing wavelength.

[0019] (3) Each polarization-maintaining continuous laser beam is input to the corresponding semiconductor optical amplifier chip. By independently controlling the gain switching characteristics of each semiconductor optical amplifier chip, N-channel optical pulses with adjustable pulse width and adjustable power are generated. The pulse width of each optical pulse is adjustable in the range of 1ns to 20ns, and the turn-off ratio of each optical pulse power is above 40dB. (4) The N-channel optical pulses are vertically coupled through an optical fiber array and simultaneously enter the N input ports of the photonic chip under test. The delay difference between the N-channel optical pulses entering the photonic chip under test is less than 500ps. (5) Collect the N optical signals output after the photonic chip under test has completed the calculation and processing, and convert them into N electrical signals; (6) Collect N electrical signals and upload them to the host computer for storage and analysis.

[0020] The aforementioned photonic chip testing method achieves multi-channel parallel testing capabilities. In terms of testing accuracy, it eliminates measurement errors inherent in the testing system by employing techniques such as a linewidth of less than 10MHz, precise wavelength locking to the 50GHz standard dense wavelength division multiplexing (DWDM) wavelength, a delay difference of less than 500ps between N-channel optical pulses, and a turn-off ratio of over 40dB for each channel's optical pulse power, thus accurately reflecting the intrinsic performance of the photonic chip. Regarding testing efficiency, the N-channel parallel optical pulses are vertically coupled into the photonic chip under test through a fiber array in a single operation, decoupling the testing time from the number of channels and achieving an order-of-magnitude efficiency improvement compared to traditional single-channel point-by-point testing. In terms of compatibility, the 50GHz standard DWDM wavelength is fully aligned with mainstream communication bands, and the fiber array vertical coupling method utilizes various material platforms and grating coupler solutions, covering the entire lifecycle from wafer-level R&D testing to chip-level mass production screening. In summary, this method systematically solves the long-standing core bottlenecks of "inaccurate, slow, and incomplete testing" in photonic chip testing, providing crucial testing support for the R&D iteration and industrialization of photonic integration technology.

[0021] In step (3), a pulse signal is applied to the driving current of each semiconductor optical amplifier chip, causing the chips to rapidly turn on and off under the pulse current. The change in carrier concentration in the active region causes pulse-like fluctuations in the output optical power, thus achieving optical pulse control. Specifically, the pulse width of each channel's optical pulse is adjustable within the range of 1ns to 20ns, covering this range. This allows the method to test optical switches and modulators (1ns level) with extremely high requirements for high-speed transient response, as well as to meet the needs of long pulse accumulation or thermo-optical effect testing in optical computing (20ns level), greatly improving the flexibility of the testing method. The maximum optical pulse power of each channel reaches over 20mW, ensuring sufficient optical power to enter the photonic chip under test even with high coupling loss, effectively driving passive photonic devices. The turn-off ratio of each channel's optical pulse power is over 40dB. This extremely high signal-to-noise ratio effectively prevents residual light from interfering with the chip's computational state when the pulse is turned off, ensuring the accuracy of the photonic chip's logic judgment and avoiding bit errors.

[0022] Furthermore, in one embodiment, after step (3) and before step (4), that is, before entering the photonic chip under test, a pre-amplification step is also included: the optical pulses of each channel are amplified by the corresponding pre-erbium-doped fiber amplifier, and the peak power of the optical pulses is increased to 1W while maintaining the waveform of each channel optical pulse, which can drive the high insertion loss chip and support nonlinear effect testing.

[0023] Furthermore, by optimizing the control circuits and timing drives of each semiconductor optical amplifier chip, the optical pulse delay difference between the chips after multiple power-ups can be reduced to less than 500 ps. Specifically, by increasing the sampling and control frequency of the high-speed, high-precision control chip of the semiconductor optical amplifier chip, the control signal interval, rise time, and fall time can be made much less than 500 ps. This allows for stable optical pulse delay control during multiple power-ups, ensuring that the optical pulse delay between semiconductor optical amplifier chips is less than 500 ps. Consequently, the delay of the N-channel optical pulses entering the photonic chip under test is less than 500 ps. This maintains multi-channel consistency. In multi-input multi-output photonic chip testing, a channel delay difference of less than 500 ps ensures that the optical signals from all channels arrive at the photonic chip synchronously, allowing the test results to accurately reflect the chip's parallel processing capabilities.

[0024] Specifically, in one embodiment, the optoelectronic integration testing device includes: The parameter configuration module is used to determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple channel optical pulses. A pulsed light source system is used to generate N-channel light pulses with adjustable wavelength, adjustable pulse width, and adjustable power that conform to the combination of the test parameters. An optical fiber array, whose N input ends are respectively connected to the N output ends of the pulsed light source system, and whose N output ends are perpendicularly coupled to the N input ports of the photonic chip under test; The signal acquisition system has N input terminals connected to the N output ports of the photonic chip under test, and synchronously acquires the N optical signals output by the photonic chip under test after calculation and processing. The signals are then converted into N electrical signals and uploaded to the host computer for storage and analysis.

[0025] Reference Figure 1 In one embodiment, an optoelectronic integrated testing device is provided, comprising two main parts: a pulsed light source system and a signal acquisition system. In the pulsed light source system, a distributed feedback laser array generates multi-wavelength lasers, the wavelengths of which are precisely adjusted by current and temperature control chips. The optical signal then enters a semiconductor optical amplifier array, where the pulse width and power are controlled by a high-speed, high-precision control chip. It is then further amplified by a pre-amplified erbium-doped fiber amplifier, the gain of which is monitored and adjusted in real-time by a drive and power monitoring chip. Finally, the output optical pulse is coupled into the photonic chip under test. In the signal acquisition system, the weak optical signal output from the photonic chip under test is first amplified a second time by a post-amplified erbium-doped fiber amplifier, the gain of which is controlled by another drive and power monitoring chip. The amplified optical signal is then sent to an avalanche photodetector array for high-sensitivity photoelectric conversion. Finally, the electrical signal is captured by a high-speed multi-channel data acquisition card and transmitted to a host computer for data processing and analysis, thereby enabling the testing of the photonic chip's performance.

[0026] Reference Figure 2 First, the parameter configuration module (which can be integrated into the host computer or set separately) determines the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, the maximum allowable delay difference between multiple channels of optical pulse, etc., and triggers the pulse light source system to generate N channels of optical pulses with the required wavelength, required pulse width, and required power. The optical pulses are then injected into the photonic chip under test through fiber array coupling. The photonic chip under test performs calculations and processes on each optical pulse and outputs the output. The optical pulses of each channel output by the photonic chip under test are amplified, photoelectric converted and digitally acquired, and then uploaded to the host computer. The host computer receives the data and performs real-time analysis or storage.

[0027] The pulsed light source system includes: A distributed feedback laser array is used to generate N beams of polarization-maintaining continuous laser with stable power and a linewidth of less than 10 MHz. The current and temperature control chip is used to control the wavelength of each laser in the distributed feedback laser array, so that the center wavelength of each polarization-maintaining continuous laser beam output by the distributed feedback laser array is locked to the 50GHz standard dense wavelength division multiplexing wavelength. The semiconductor optical amplifier array consists of N semiconductor optical amplifier chips, and each laser in the distributed feedback laser array is connected to a semiconductor optical amplifier chip in the semiconductor optical amplifier array in the corresponding output optical path. A high-speed, high-precision control chip is connected to N semiconductor optical amplifier chips. By controlling the gain switching characteristics of each semiconductor optical amplifier chip, the semiconductor optical amplifier array generates N channels of optical pulses with adjustable pulse width and power. The pulse width of each channel is adjustable within the range of 1ns to 20ns, the maximum optical pulse power is above 20mW, and the turn-off ratio of the optical pulse power is above 40dB. The delay difference between each channel optical pulse is controlled within 500ps to meet the maximum allowable delay difference between multi-channel optical pulses in the test parameter combination.

[0028] In the above embodiments, the pulsed light source system further includes N pre-erbium-doped fiber amplifiers. The output terminal of each semiconductor optical amplifier chip is connected to a pre-erbium-doped fiber amplifier. The pre-erbium-doped fiber amplifier is used to further amplify the power of the optical pulse in the corresponding channel, and increase the peak power of the optical pulse to 1W while maintaining the optical pulse waveform of each channel.

[0029] In the above embodiments, the signal acquisition system includes N post-erbium-doped fiber amplifiers, an avalanche photodetector array, and a high-speed multi-channel data acquisition card; The input ends of the N post-erbium-doped fiber amplifiers are respectively connected to the N output ports of the photonic chip under test, and are used to amplify the N optical signals output after the photonic chip under test has completed the calculation and processing. In this way, the signal acquisition system can detect weak output signals and realize the complete link coverage from high power excitation to weak detection.

[0030] The avalanche photodetector array consists of N avalanche photodetectors, with each of its N input terminals connected to the output terminal of a post-erbium-doped fiber amplifier, which is used to convert the amplified N optical pulse signals into N electrical signals. The high-speed multi-channel data acquisition card receives the electrical signals output by the avalanche photodetector array and uploads them to the host computer in real time.

[0031] The high-speed multi-channel data acquisition card is connected to the host computer via an Ethernet interface or a fiber optic interface to enable real-time data upload.

[0032] Under the control of current and temperature control chips, the distributed feedback laser array generates N beams of polarization-maintaining continuous lasers with stable power and linewidths of less than 10MHz. At the same time, the wavelength of each laser in the distributed feedback laser array is controlled so that the center wavelength of each polarization-maintaining continuous laser beam output by the distributed feedback laser array is locked to the 50GHz standard dense wavelength division multiplexing wavelength.

[0033] A distributed feedback laser array is cascaded with a semiconductor optical amplifier array (SOA). The generation of optical pulses and the adjustment of output light intensity are achieved by changing the gain of the SOA chips. Under the control of its high-speed, high-precision control chip, the SOA array generates optical pulses with adjustable widths from 1ns to 20ns, achieving a maximum pulse power of over 20mW and a turn-off ratio of over 40dB. It also enables stable pulse delay control during multiple power-ups, ensuring that the pulse delay between multiple SOA chips is less than 500ps. Specifically, the high-speed, high-precision control chip includes a high-speed pulse drive circuit. The output of this circuit is connected to the drive electrode of the SOA chip, applying a pulsed current as an external drive signal to control the SOA chip to switch between gain and absorption states, thereby modulating the input continuous light into an output optical pulse signal. The SOA chip is in an absorption state with extremely low light transmittance when undriven (TTL low level). When driven (TTL high level), the semiconductor optical amplifier chip is in gain mode, amplifying and passing light. In this way, the TTL electrical pulse directly "carves" the optical pulse, realizing the conversion from continuous light to high-quality pulsed light. The absorption characteristics of the semiconductor optical amplifier chip (SOA) in the off state can result in a very high extinction ratio (typically exceeding 40dB), far superior to directly modulated DFB lasers. The pulse width of the optical pulse signal is mainly determined by the pulse width of the TTL electrical signal, which can be flexibly adjusted from nanoseconds to microseconds.

[0034] A high-speed erbium-doped fiber amplifier is cascaded at the back end of the semiconductor optical amplifier array. The distributed feedback laser array, the semiconductor optical amplifier array, and the erbium-doped fiber amplifier together form a pulsed light source system. The erbium-doped fiber amplifier can further increase the power of the optical pulse while ensuring the waveform of the optical pulse; the peak power of the optical pulse can reach up to 1W.

[0035] The multi-channel optical pulses generated by the pulsed light source system are output through optical fiber and vertically coupled into the photonic chip under test through an optical fiber array.

[0036] The host computer sends control and trigger signals to the pulse light source system. After setting the output optical power and pulse width of each channel of the pulse light source system, it generates optical pulse signals for photonic chip evaluation.

[0037] After the optical pulse signal completes the computational processing task by the photonic chip, it is input to the corresponding post-erbium-doped fiber amplifier. Each post-erbium-doped fiber amplifier amplifies the weak light signal output from the photonic chip. Preferably, the post-erbium-doped fiber amplifier provides a gain of more than 1000 times for small signals.

[0038] The optical pulses output by each post-erbium-doped fiber amplifier are received by the high-bandwidth, high-gain avalanche photodetectors in the avalanche photodetector array and converted into electrical signals. The electrical signals generated by each avalanche photodetector are recorded by a high-speed multi-channel acquisition system and uploaded to a host computer via an Ethernet / fiber optic interface, where the host computer stores the signals and performs further processing.

[0039] This invention tests photonic chips using optical pulses. The design of the optoelectronic integrated testing device enhances its applicability to high-loss photonic chips, enabling testing of larger-scale photonic chips. The device features a high optical pulse turn-off ratio, adjustable pulse width, and stable, minimal delay between multiple optical pulses, ensuring accurate testing and evaluation of photonic chips and providing richer testing functions. It supports effective testing of photonic chips with optical losses ranging from -0dB to -60dB. The testing device is systematically integrated; both the pulse light source system and signal acquisition system can achieve high-speed communication and control with a host computer, enabling convenient and efficient testing of photonic chips.

[0040] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A photonic chip testing method, characterized in that, Includes the following steps: (1) Determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple optical pulses. (2) Based on the combination of test parameters, N polarization-maintaining continuous lasers with stable power and linewidth less than 10MHz are generated by the pulse light source system, and the center wavelength of each polarization-maintaining continuous laser is locked to the 50GHz standard dense wavelength division multiplexing wavelength. (3) Each polarization-maintaining continuous laser beam is input to the corresponding semiconductor optical amplifier chip. By independently controlling the gain switching characteristics of each semiconductor optical amplifier chip, N-channel optical pulses with adjustable pulse width and adjustable power are generated. The pulse width of each optical pulse is adjustable in the range of 1ns to 20ns, and the turn-off ratio of each optical pulse power is above 40dB. (4) The N-channel optical pulses are vertically coupled through an optical fiber array and simultaneously enter the N input ports of the photonic chip under test. The delay difference between the N-channel optical pulses entering the photonic chip under test is less than 500ps. (5) Collect the N optical signals output after the photonic chip under test has completed the calculation and processing, and convert them into N electrical signals; (6) Collect N electrical signals and upload them to the host computer for storage and analysis.

2. The photonic chip testing method according to claim 1, characterized in that, After step (3) and before step (4), a pre-amplification step is also included, in which the optical pulses of each channel are amplified by the corresponding pre-amplified erbium-doped fiber amplifier, and the peak power of the optical pulses is increased to 1W while maintaining the waveform of each channel optical pulse.

3. The photonic chip testing method according to claim 1, characterized in that, In step (3), by applying a pulse signal to the driving current of each semiconductor optical amplifier chip, each semiconductor optical amplifier chip is turned on and off rapidly under the drive of the pulse current. The change in the carrier concentration in the active region causes the output optical power to fluctuate in a pulsed manner, thereby realizing the control of the optical pulse.

4. An optoelectronic integrated testing device, used to implement the photonic chip testing method as described in claim 1, characterized in that... include: The parameter configuration module is used to determine the combination of test parameters according to the test requirements of the photonic chip under test. The combination of test parameters includes the pulse width range of the optical pulse, the center wavelength of the optical pulse, the turn-off ratio of the optical pulse power of each channel, and the maximum allowable delay difference between multiple channel optical pulses. A pulsed light source system is used to generate N-channel light pulses with adjustable wavelength, adjustable pulse width, and adjustable power that conform to the combination of the test parameters. An optical fiber array, whose N input ends are respectively connected to the N output ends of the pulsed light source system, and whose N output ends are perpendicularly coupled to the N input ports of the photonic chip under test; The signal acquisition system has N input terminals connected to the N output ports of the photonic chip under test, and synchronously acquires the N optical signals output by the photonic chip under test after calculation and processing. The signals are then converted into N electrical signals and uploaded to the host computer for storage and analysis.

5. The optoelectronic integration testing device according to claim 4, characterized in that, The pulsed light source system includes: A distributed feedback laser array is used to generate N beams of polarization-maintaining continuous laser with stable power and a linewidth of less than 10 MHz. The current and temperature control chip is used to control the wavelength of each laser in the distributed feedback laser array, so that the center wavelength of each polarization-maintaining continuous laser beam output by the distributed feedback laser array is locked to the 50GHz standard dense wavelength division multiplexing wavelength. The semiconductor optical amplifier array consists of N semiconductor optical amplifier chips, and each laser in the distributed feedback laser array is connected to a semiconductor optical amplifier chip in the semiconductor optical amplifier array in the corresponding output optical path. A high-speed, high-precision control chip is connected to N semiconductor optical amplifier chips. By controlling the gain switching characteristics of each semiconductor optical amplifier chip, the semiconductor optical amplifier array generates N channels of optical pulses with adjustable pulse width and power. The pulse width of each channel is adjustable within the range of 1ns to 20ns, the maximum optical pulse power is above 20mW, and the turn-off ratio of the optical pulse power is above 40dB. The delay difference between each channel optical pulse is controlled within 500ps to meet the maximum allowable delay difference between multi-channel optical pulses in the test parameter combination.

6. The optoelectronic integration testing device according to claim 5, characterized in that, The pulsed light source system also includes N pre-erbium-doped fiber amplifiers. The output of each semiconductor optical amplifier chip is connected to a pre-erbium-doped fiber amplifier. The pre-erbium-doped fiber amplifier is used to further amplify the power of the optical pulse in the corresponding channel, and increase the peak power of the optical pulse to 1W while maintaining the waveform of the optical pulse in each channel.

7. The optoelectronic integration testing device according to claim 5 or 6, characterized in that, The signal acquisition system includes N post-erbium-doped fiber amplifiers, an avalanche photodetector array, and a high-speed multi-channel data acquisition card; The input ends of the N post-erbium-doped fiber amplifiers are respectively connected to the N output ports of the photonic chip under test, and are used to amplify the N optical signals output after the photonic chip under test has completed the calculation and processing. The avalanche photodetector array consists of N avalanche photodetectors, with each of its N input terminals connected to the output terminal of a post-erbium-doped fiber amplifier, which is used to convert the amplified N optical pulse signals into N electrical signals. The high-speed multi-channel data acquisition card receives the electrical signals output by the avalanche photodetector array and uploads them to the host computer in real time.

8. The optoelectronic integration testing device according to claim 7, characterized in that, The high-speed multi-channel data acquisition card is connected to the host computer via an Ethernet interface or a fiber optic interface to enable real-time data upload.

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