Microbolometer based on tgv for wafer level packaging and method of manufacturing the same

Abstract

The application discloses a micro thermal conductivity detector based on TGV and a preparation method thereof, and belongs to the technical field of gas detection. The micro thermal conductivity detector comprises a plurality of micro thermal conductivity detectors, the plurality of micro thermal conductivity detectors are arranged on a packaging wafer, the packaging wafer is composed of a silicon wafer and a glass wafer, a plurality of silicon substrates are arranged on the silicon wafer, and a plurality of glass plates are arranged on the glass wafer; a plurality of first half-pools are arranged on the silicon substrates, first half-groove channels are symmetrically arranged on the two sides of the first half-pools, a plurality of second half-pools are arranged on the glass plates, second half-groove channels are symmetrically arranged on the two sides of the second half-pools, the first half-groove channels and the second half-groove channels are matched to form through grooves, and the first half-pools and the second half-pools are matched to form thermal conductivity pools. The application realizes wafer-level packaging, improves the packaging density, expands the effective packaging area, improves the air tightness, shortens the heat dissipation path of the thermal element, effectively reduces heat loss, and improves the sensitivity of the device.

Description

Technical Field

[0001] This application belongs to the field of gas detection technology, and specifically relates to a miniature thermal conductivity detector wafer based on TGV and its fabrication method. Background Technology

[0002] With the continuous improvement of industrial levels, the use and emission of volatile organic compounds and permanent gases are constantly increasing. To ensure the safety of industrial gas use and environmental protection, gas detection is crucial during the use and emission process. A thermal conductivity detector (TCD) is a device that utilizes the differences in the thermal conductivity of gases to measure different gas components. Its key feature is that it responds to elemental gases, inorganic substances, and organic substances without destroying the original gas composition.

[0003] Traditional thermal conductivity detectors (TCDs) have significant limitations due to their large size, slow analysis speed, and low sensitivity, which restricts their miniaturization and low-power commercialization. Micro Thermal Conductivity Detectors (μTCDs) manufactured using MEMS technology are miniature gas detectors that integrate the Wheatstone bridge and mechanical structure of traditional TCDs onto a single chip, combining semiconductor manufacturing processes and precision machining techniques. They offer advantages such as simple structure, low cost, small size, and light weight, making them core detectors in miniaturized chromatographs and process analyzers, and are widely used in pharmaceuticals, petroleum, environmental monitoring, and organic compound analysis. In terms of manufacturing, wafer-level packaging technology, enabling low-cost, mass production of these devices, has become an inevitable trend in the development of µTCDs.

[0004] However, the current µTCD devices use a side-lead packaging method, which requires more lateral space during manufacturing and packaging. This lead method limits the effective packaging area and extends the heat dissipation path of the thermistor, resulting in more heat loss and limiting the device's sensitivity. On the other hand, the side-lead method increases the process complexity of wafer-level packaging, and the structural design limits the high-density integration of wafer-level manufacturing.

[0005] The paper (Micro thermal conductivity detector based on SOI substrate with low detection limit) uses MEMS technology to fabricate a suspended thermistor μTCD on a silicon-on-insulator (SOI) substrate. This device cleverly utilizes a 20 μm thick silicon layer on top of the SOI substrate as a support layer for the thermistor, exhibiting excellent mechanical stability. A thermal conductivity cell of approximately 200 nL was fabricated using deep silicon etching. Test results show that this μTCD exhibits extremely high sensitivity in detecting mixtures of n-alkanes (C14-C16), with a detection limit of 5 ppm. However, this device is packaged as a single, conventional device and connected to external circuitry via side leads.

[0006] The paper (Fabrication of thermal conductivity detector based on MEMS for monitoring dissolved gases in power transformer) describes the development of a high-performance, single-bridge, dual-sensitivity micro-thermal conductivity detector. This device is fabricated using MEMS technology, utilizing Pyrex glass with etched microfluidic channels as the top layer of the thermal conductivity cell. The detector is encapsulated using Si / Si3N4 / Pyrex glass anodic bonding technology. Test results show that this µTCD exhibits good stability, high sensitivity, and rapid gas detection with a detection limit of 10 ppm. Unfortunately, the device still employs traditional single-device packaging and connects to external circuitry via side leads.

[0007] Through Glass Via (TGV) is an advanced wafer-level packaging technology that involves drilling holes in a glass substrate and filling them with metal to achieve vertical interconnection of electrical signals. It offers advantages such as high-density vertical interconnection, excellent electrical performance, superior mechanical properties, high-precision processing, low transmission loss, and high insulation. It has broad application prospects in fields such as radio frequency chips and MEMS sensors. This technology provides new ideas for sensor structural design and enables high-precision, high-consistency integrated, and mass-produced wafer-level manufacturing. Summary of the Invention

[0008] To address the aforementioned issues, this application provides a TGV-based micro thermal conductivity detector wafer and its fabrication method.

[0009] The first objective of this application is to provide a TGV-based miniature thermal conductivity detector wafer, comprising: multiple miniature thermal conductivity detectors; Multiple of the aforementioned micro thermal conductivity detectors are disposed on a packaged wafer, which is composed of a silicon wafer and a glass wafer. Multiple silicon substrates are disposed on the silicon wafer, and multiple glass plates are disposed on the glass wafer. The silicon substrate is provided with a plurality of first half-cells, and first half-groove channels are symmetrically provided on both sides of the first half-cells. The glass plate is provided with a plurality of second half-cells, and second half-groove channels are symmetrically provided on both sides of the second half-cells. The first half-groove channels and the second half-groove channels cooperate with each other to form a through groove. The first half-cells and the second half-cells cooperate with each other to form a thermal conductivity cell. The packaged wafer also includes several microcircuits, each including a Wheatstone bridge and electrodes connected to both ends of the Wheatstone bridge, with pads on the top of the electrodes.

[0010] The Wheatstone bridge is disposed in the thermal conductivity cell, the electrode is disposed in the through hole of the glass plate, and the pad is located on the surface of the glass plate.

[0011] In a specific embodiment of this application, the silicon wafer is further provided with a first alignment mark and a second alignment mark, and the glass wafer is further provided with a third alignment mark and a fourth alignment mark; The position of the third alignment mark matches the position of the first alignment mark or the second alignment mark, and the position of the fourth alignment mark matches the position of the second alignment mark or the first alignment mark.

[0012] In a specific embodiment of this application, a heat insulation layer is also provided on the silicon substrate.

[0013] In a specific embodiment of this application, the heat insulation layer is a silicon oxide layer, and the thickness of the heat insulation layer is 300-1000nm.

[0014] In a specific embodiment of this application, a mask layer is also provided on the heat insulation layer.

[0015] In a specific embodiment of this application, the mask layer is a silicon nitride layer, and the thickness of the mask layer is 100-600 nm.

[0016] In a specific embodiment of this application, a gas pipe is inserted into the through groove.

[0017] In a specific embodiment of this application, the diameter of the through groove is 600-1000 μm.

[0018] In a specific embodiment of this application, the thickness of the Wheatstone bridge is 200-500 nm, and the diameter of the electrode is 100-300 μm.

[0019] In a specific embodiment of this application, the diameter of the thermal conductivity pool is 200-300 μm.

[0020] The second objective of this application is to provide a method for fabricating a TGV-based micro thermal conductivity detector wafer, comprising: Glass wafer processing: Through holes are processed on the glass wafer; sandblasting is performed on the glass wafer to obtain the second half-cell; sandblasting is performed on both sides of the second half-cell at symmetrical positions to obtain the second half-groove channel, thus completing the glass wafer processing. Silicon wafer fabrication: A Wheatstone bridge is fabricated on the silicon wafer; the first half-cell position is marked by photoresist coating, exposure, and development on the surface of the silicon wafer, and the silicon nitride and silicon oxide at the corresponding positions are removed by dry etching to expose the silicon at the first half-cell position; sandblasting is performed on symmetrical positions on both sides of the first half-cell position to obtain the first half-groove channel; the silicon wafer is then subjected to solution etching to obtain the first half-cell, completing the silicon wafer fabrication. Packaging: Align the processed glass wafer with the processed silicon wafer, and encapsulate using ultrafast laser welding to ensure that the first half-groove channel and the second half-groove channel cooperate with each other, and that the first half-cell and the second half-cell cooperate with each other; fill the through-hole with conductive material to obtain electrodes; plate pads on the surface of the glass wafer to obtain the encapsulated wafer; Laser is used to cut the packaged wafer to obtain individual devices.

[0021] In a specific embodiment of this application, prior to the step of "fabricating a Wheatstone bridge on a silicon wafer", the silicon substrate processing includes: Processing of the heat insulation layer: Surface deposition is performed on the surface of a silicon wafer to obtain the heat insulation layer; Mask layer processing: Surface deposition is performed on the surface of the insulation layer to obtain the mask layer.

[0022] In a specific embodiment of this application, the glass wafer has a thickness of 400-600 μm and a size of 4-8 inches.

[0023] In a specific embodiment of this application, the silicon wafer has a thickness of 400-600 μm and a size of 4-8 inches.

[0024] In a specific embodiment of this application, fabricating a Wheatstone bridge on a silicon substrate includes: A Wheatstone bridge pattern is obtained by homogenization, photolithography, and development on the surface of a silicon wafer. Metal electrodes are deposited on a silicon substrate using magnetron sputtering. The materials are Cr-Pt, Cr-Ni, Ti-Pt, and Ti-Ni. The Cr-Pt, Cr-Ni, Ti-Pt, and Ti-N are all composite layers, i.e., a Cr / Ti layer is first fabricated, followed by a Pt / Ni layer. The Cr and Ti layers serve as adhesion layers to enhance the adhesion between the Pt / Ni layer and the wafer. The thickness of the Cr / Ti adhesion layers is independently 10-40 nm, and the thickness of the Pt / Ni layers is independently 200-500 nm.

[0025] The preparation of metal electrodes by magnetron sputtering is a well-known operation in this technical field, and will not be described in detail here.

[0026] The photoresist is cleaned to achieve metal stripping and obtain a Wheatstone bridge. The solution used to clean the photoresist is an acetone solution.

[0027] In a specific embodiment of this application, the electrode material is one of Au, Ag, and Cu.

[0028] In a specific embodiment of this application, the material of the pad is TiAu.

[0029] The Ti-Au layer is a composite layer, that is, a Ti layer is first made and then an Au layer is made. The Ti layer is used as an adhesion layer to enhance the adhesion between Au and the wafer. The thickness of the adhesion layer Ti layer is 10-40nm and the thickness of the Au layer is 300-600nm.

[0030] In a specific embodiment of this application, the ultrafast laser welding includes: The silicon wafer and glass wafer are aligned before welding, and a preset pressure is applied to obtain an aligned sample. Fix the laser beam and move it to align with the sample, so that the laser beam sweeps across the sample. The preset pressure is 0.3 MPa-0.4 MPa, and the scanning speed is set to 20-30 mm / s; The laser beam is a picosecond laser with parameters of wavelength 1064 nm, repetition frequency 300 kHz, pulse width 15 ps, pulse energy 16.9 uJ, maximum output power 12.78 W, and spot size of 40 ± 2 μm.

[0031] Specifically, the implementation of fixing the laser beam and moving it to align with the sample includes: The microscope objective used to focus the laser beam is vertically mounted on a z-axis displacement stage, which allows it to adjust the position of the laser focus, which is the contact surface between the upper and lower wafers. The aligned sample is placed on a CNC two-axis precision displacement stage, which can scan in the xy plane according to a preset trajectory.

[0032] Compared with the prior art, this application has the following advantages: This application discloses a TGV-based miniature thermal conductivity detector wafer and its fabrication method. The wafer is formed by ultrafast laser welding and packaging of a glass wafer and a silicon wafer, which has the following advantages: First, it increases the effective packaging area, improves hermeticity, and shortens the heat dissipation path of the thermal element, effectively reducing heat loss and improving the sensitivity of the device; Second, it reduces the process complexity of wafer-level packaging and increases the chip density that can be integrated on the wafer.

[0033] The product in this application innovatively develops a wafer-level packaging process route based on TGV technology, wafer precision sandblasting technology, laser welding, laser cutting and other technologies, providing a new solution for traditional MEMS sensor structure design and wafer-level manufacturing.

[0034] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a miniature thermal conductivity detector according to an embodiment of this application is shown; Figure 2 An exploded view of a miniature thermal conductivity detector according to an embodiment of this application is shown; Figure 3 A side view of a miniature thermal conductivity detector according to an embodiment of this application is shown; Figure 4 A top view of a miniature thermal conductivity detector according to an embodiment of this application is shown; Figure 5 A schematic diagram of a TGV-based miniature thermal conductivity detector wafer according to an embodiment of this application is shown; Figure 6 A schematic diagram of a TGV-based miniature thermal conductivity detector wafer according to an embodiment of this application is shown; Figure 7 A schematic diagram of the encapsulation in Embodiment 1 of this application is shown; Figure 8 A physical diagram of the packaging wafer of Embodiment 1 of this application is shown; Figure 9 A physical image of a single μTCD according to Embodiment 1 of this application is shown; Figure 10 A microscope image of the laser welding surface of the μTCD in Embodiment 1 of this application is shown; Figure 11 Microscopic images of the bonding surfaces of the products obtained by hot-press bonding in Comparative Example 2 of this application are shown. Figure 12 A microscope image of the weld surface of the product obtained by anodic bonding in Comparative Example 3 of this application is shown; Figure 13 Microscopic images of the bonding surfaces of the products obtained by anodic bonding in Comparative Example 3 of this application are shown. In the picture: 10. Silicon substrate; 20. Glass plate; 30. Through slot; 31. First half-slot channel; 32. Second half-slot channel; 40. Thermal conductivity cell; 41. First half-cell; 42. Second half-cell; 50. Microcircuit; 51. Wheatstone bridge; 52. Electrode; 53. Bonding pad; 60. Packaging wafer; 61. Silicon wafer; 62. Glass wafer; 63. First alignment mark; 64. Third alignment mark; 65. Second alignment mark; 66. Fourth alignment mark; 70. Laser beam; 71. Microscope objective; 80. Bonding point. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] A wafer-level packaged micro thermal conductivity detector wafer according to certain embodiments of this application includes a plurality of micro thermal conductivity detectors (i.e., μTCDs). like Figure 5 As shown, multiple of the aforementioned micro thermal conductivity detectors are deployed on the packaged wafer 60 (see details). Figure 6 The packaged wafer 60 is composed of a silicon wafer 61 and a glass wafer 62. The silicon wafer 61 is provided with a plurality of silicon substrates 10, and the glass wafer 62 is provided with a plurality of glass plates 20. like Figure 1 As shown, the silicon substrate 10 has a plurality of first half-cells 41, and first half-groove channels 31 are symmetrically arranged on both sides of the first half-cells 41. The glass plate has a plurality of second half-cells 42, and second half-groove channels 32 are symmetrically arranged on both sides of the second half-cells 42 (see details). Figure 2 The first half-slot channel 31 and the second half-slot channel 32 cooperate to form a through-slot 30, and the first half-pool 41 and the second half-pool 42 cooperate to form a thermal conductivity pool 40 (see details). Figure 3 ); The packaged wafer 60 also includes several microcircuits 50, each microcircuit 50 including a Wheatstone bridge 51 and electrodes 52 connected to both ends of the Wheatstone bridge 51, with pads 53 on the top of each electrode 52. In some embodiments of this application, the Wheatstone bridge 51 is disposed in the thermal conductivity cell, the electrode 52 is disposed in the through hole of the glass plate, and the pad 53 is located on the surface of the glass plate.

[0039] In some embodiments of this application, the silicon wafer 61 is further provided with a first alignment mark 63 and a second alignment mark 65, and the glass wafer 62 is further provided with a third alignment mark 64 and a fourth alignment mark 66. The position of the third alignment mark 64 matches the position of the first alignment mark 63 or the second alignment mark 65, and the position of the fourth alignment mark 66 matches the position of the second alignment mark 65 or the first alignment mark 63. Figure 5 As shown, for example, the first alignment mark 63 and the third alignment mark 64 are positioned opposite each other, and the second alignment mark 65 is positioned opposite the fourth alignment mark 66.

[0040] In this embodiment of the application, the first half-groove channel 31 and the second half-groove channel 32 are coordinated by the position markings between the first alignment mark 63, the second alignment mark 65, the third alignment mark 64, and the fourth alignment mark 66.

[0041] In some embodiments of this application, the silicon substrate 10 is further provided with a heat insulation layer to reduce heat loss from the silicon substrate 10.

[0042] In some embodiments of this application, the heat insulation layer is a silicon oxide layer, and the thickness of the heat insulation layer is 300-1000 nm.

[0043] In some embodiments of this application, a mask layer is further provided on the heat insulation layer to prevent the etching solution from etching the heat insulation layer and the silicon substrate 10, and at the same time to serve as a support layer for the Wheatstone bridge 51.

[0044] In some embodiments of this application, the mask layer is a silicon nitride layer, and the thickness of the mask layer is 100-600 nm.

[0045] In some embodiments of this application, a plurality of gas pipes are inserted into the through groove 30 to guide the entry and exit of the gas to be tested and / or the carrier gas. For example, there are four gas pipes, two of which are inlet pipes and two are outlet pipes.

[0046] In a specific embodiment of this application, for example, in one μTCD, the number of microcircuits 50 is four. Every two microcircuits 50 are arranged side-by-side between two symmetrically arranged through-slots 30, facilitating the passage of the gas to be measured and / or the carrier gas through the Wheatstone bridge 51. The four microcircuits 50 are arranged in two rows and two paths, corresponding to four through-slots 30. The number of thermal conductivity cells 40 is also two. See details... Figure 4 ; In an embodiment, the thermal conductivity cell 40 includes a first thermal conductivity cell 41 and a second thermal conductivity cell 42. Hydrogen or helium is introduced into two pipes connected to the first thermal conductivity cell 41 as a carrier gas. Two electrodes 52 located on the first thermal conductivity cell 41 serve as reference electrodes 52. A mixture of the gas to be tested and the carrier gas is introduced into two pipes connected to the second thermal conductivity cell 42. Two electrodes 52 located on the second thermal conductivity cell 42 serve as reference electrodes 52. Due to the different thermal conductivity coefficients of the gas in the carrier gas channel and the gas mixture channel, the Wheatstone bridge 51 changes differently, causing the bridge to become unbalanced. The output voltage difference reflects the physical characteristics of the gas to be tested, such as concentration and flow rate.

[0047] In a specific embodiment of this application, the plane containing the pad 53 is parallel to the plane containing the Wheatstone bridge 51, and the plane containing the axis of the electrode 52 is perpendicular to the plane containing the Wheatstone bridge 51.

[0048] In a specific embodiment of this application, the first semi-cylindrical channel 31 and the second semi-cylindrical channel 32 are semi-cylindrical in shape, and the through groove 30 formed by the cooperation of the first semi-cylindrical channel 31 and the second semi-cylindrical channel 32 is circular in shape.

[0049] In a specific embodiment of this application, the diameter of the through groove 30 is 600-1000 μm.

[0050] In a specific embodiment of this application, the first half-pool 41 and the second half-pool 42 are semi-cylindrical in shape, and the thermal conductivity pool 40 formed by the cooperation of the first half-pool 41 and the second half-pool 42 is circular in shape.

[0051] In some embodiments of this application, the diameter of the thermal conductivity cell 40 is 200-300 μm.

[0052] In some embodiments of this application, the thickness of the Wheatstone bridge 51 is 200-500 nm, and the diameter of the electrode 52 is 100-300 μm.

[0053] In a specific embodiment of this application, a plurality of the μTCDs are arranged in an array on a package wafer 60 formed by sealing a silicon wafer 61 and a glass wafer 62, such as Figure 5 As shown, this facilitates the subsequent use of individual μTCDs; for example, the packaged wafer 60 contains 150 μTCDs.

[0054] A method for fabricating a wafer-level packaged micro thermal conductivity detector wafer according to certain embodiments of this application includes: Glass wafer 62 processing: Through holes, third alignment mark 64 and fourth alignment mark 66 are processed on glass wafer 62; sandblasting is performed on glass wafer 62 to obtain second half pool 42; sandblasting is performed on both sides of the second half pool 42 at symmetrical positions to obtain second half groove channel 32, thus completing the processing of glass wafer 62. Silicon wafer 61 fabrication: A Wheatstone bridge 51, a first alignment mark 63, and a second alignment mark 65 are fabricated on the silicon wafer 61; the first half-cell 41 position is identified by homogenization, exposure, and development on the surface of the silicon wafer 61, and the silicon nitride and silicon oxide at the corresponding positions are removed by dry etching to expose the silicon at the first half-cell 41 position; sandblasting is performed on symmetrical positions on both sides of the first half-cell 41 position to obtain the first half-groove channel 31; the silicon wafer 61 is then subjected to solution etching to obtain the first half-cell 41, thus completing the fabrication of the silicon wafer 61; Packaging: Align the processed glass wafer 62 with the processed silicon wafer 61, and encapsulate them using ultrafast laser welding to ensure that the first half-groove channel 31 and the second half-groove channel 32 cooperate with each other, and the first half-cell 41 and the second half-cell 42 cooperate with each other; fill the through-hole with electrode 52 material to obtain electrode 52; and use magnetron sputtering to deposit pads 53 on the surface of the glass wafer 62 to obtain the packaged wafer 60.

[0055] In a specific embodiment of this application, prior to the step of "fabricating the Wheatstone bridge 51 on the silicon wafer 61", the processing of the silicon substrate 10 includes: Processing of the heat insulation layer: Surface deposition is performed on the surface of silicon wafer 61 to obtain the heat insulation layer; Mask layer processing: Surface deposition is performed on the surface of the insulation layer to obtain the mask layer.

[0056] In some embodiments of this application, the glass wafer 62 has a thickness of 400-600 μm and a size of 4-8 inches.

[0057] In some embodiments of this application, the silicon wafer 61 has a thickness of 400-600 μm and a size of 4-8 inches.

[0058] Example 1 A method for fabricating a wafer-level packaged micro thermal conductivity detector wafer includes: First step: Manufacturing process of glass wafer 62: (Glass plate 20 is a component of glass wafer 62, that is, glass wafer 62 contains 150 glass plates 20). Step 1: First, select a 4, 6, or 8-inch, 600μm thick glass wafer 62, and use a laser to modify the micro-hole area and alignment marks of the glass; wherein, the laser is an infrared picosecond laser with a laser power of 60 W and a scanning speed of 200mm / s; Step 2: The modified glass wafer 62 is placed in an etching solution to etch glass micro-vias and alignment marks (third alignment mark 64 and fourth alignment mark 66); wherein, the etching solution is a 5% hydrofluoric acid solution, and ultrasonic etching is performed for 1 hour; Step 3: Sandblasting is performed using sandblasting equipment to obtain two second semi-cylindrical pools 42 with a diameter of 200μm; the sandblasting time is 15 min and the sandblasting pressure is 0.2-0.7 MPa. Step 4: Sandblasting is performed symmetrically on both sides of the second half-pool using sandblasting equipment to obtain a semi-cylindrical pipe second half-channel 32 with a diameter of 800μm; wherein, the sandblasting time is 45min and the sandblasting pressure is 0.2-0.7 MPa; Second step: Fabrication process of silicon wafer 61 Step 1: Select a 4, 6 or 8-inch silicon wafer 61 with crystal orientation (100) and a thickness of 400μm. Deposit 300 nm silicon oxide on the surface of the silicon wafer using thermal oxidation method, and then deposit 200 nm silicon nitride on the surface of silicon oxide using LPCVD. Step 2: Spin-coating, photolithography, and development are performed on the surface of silicon wafer 61 to obtain the Wheatstone bridge 51 pattern and alignment marks (first alignment mark 63 and second alignment mark 65). Step 3: Deposit metal electrode 52 on silicon substrate 10 using magnetron sputtering. The material is Cr-Pt, wherein the thickness of the Cr layer is 20 nm and the thickness of the Pt layer is 300 nm. Step 4: Clean the photoresist in acetone solution to achieve metal stripping and fabricate Wheatstone bridge 51; Step 5: Spin coat the silicon wafer 61 with photoresist, expose, and develop the thermal conductivity cells 40. Then, use dry etching to remove the silicon nitride and silicon oxide at the corresponding locations, exposing the silicon at the first half-cell 41 location. The pre-baking temperature is 90–120℃, and the exposure power is 30–80 mJ / cm. 2 Exposure wavelength 365nm (i-line), post-baking temperature 110-130℃, developer solution 2.38% TMAH aqueous solution, development time 30-90s, development temperature 20-25℃; Step 6: Sandblasting is performed on both sides of the first half-pool 41 using a sandblasting device to obtain a semi-cylindrical pipe first half-groove channel 31 with a diameter of 800μm; wherein, the sandblasting time is 45min and the sandblasting pressure is 0.2-0.7 MPa; Step 7: Immerse the silicon wafer 61 in KOH solution for etching to obtain a semi-cylindrical first half-cell 41 with a diameter of 200μm; Third process: Wafer-level packaging process Step 1: Wafer-level packaging is performed using ultrafast femtosecond lasers, specifically including: i. Before soldering, silicon wafer 61 and glass wafer 62 are aligned and a preset pressure of 0.3 MPa is applied. The alignment is judged by the overlap between the first alignment mark 63, the second alignment mark 65 and the third alignment mark 64, the fourth alignment mark 66. If the marks overlap well in pairs, it means that the sample is aligned well. ii. The microscope objective 71 for focusing the laser beam is vertically mounted on a z-axis displacement stage, allowing adjustment of the laser focal point position. The laser focal point position is the contact surface between the upper and lower wafers (i.e., forming the solder joint 80, see details). Figure 7 ); iii. The welding adopts a strategy of keeping the laser beam stationary while the sample moves. The aligned sample is fixed on a CNC two-axis precision displacement stage, which can scan in the xy plane according to a preset trajectory. The scanning speed is set to 30mm / s. The laser beam is a picosecond laser with parameters of wavelength 1064 nm, repetition frequency 300 kHz, pulse width 15 ps, pulse energy 16.9 uJ, maximum output power 12.78 W, and a spot size of approximately 40±2 μm. Step 2: The TGV electrode 52 is prepared by screen printing and electroplating to fill the blind holes with metal. Step 3: Use magnetron sputtering to deposit TiAu onto the glass surface to create metal pads 53, thus obtaining the completed packaged wafer 60; Step 4: Obtain individual μTCDs using laser cutting and abrasive wheel cutting methods. See attached image for a physical image of a single μTCD. Figure 9 .

[0059] The product diagram of the packaged wafer 60 obtained in Example 1 (containing 64 μTCDs) is as follows. Figure 8 As shown.

[0060] And from Figure 10 As can be seen from the microscopic image of the joint surface, the weld surface has a good morphology and the structure of the thermal element (i.e., the Wheatstone bridge) is good.

[0061] Comparative Example 1 A method for fabricating a wafer-level packaged micro thermal conductivity detector wafer includes: Compared with Example 1, the packaging process in the third step is replaced with long pulse welding, while the rest are the same. The parameters of long pulse welding are: single pulse energy 1-15J, pulse width 1-20ms, peak power 500-3000W, spot diameter 0.2-1.0mm, and the welding point molten pool temperature can reach 1800-4500℃.

[0062] Compared with the packaged wafer 60 obtained after packaging in Example 1 (which hardly damages MEMS, thin film, and sensor), the packaged wafer 60 obtained after packaging has microstructure loss, no thermal damage to the solder surface, no electrical breakdown, and no breakage of the thermal element.

[0063] Comparative Example 2 A method for fabricating a wafer-level packaged micro thermal conductivity detector wafer includes: Compared with Example 1, the encapsulation process in the third step is replaced with thermocompression bonding (diffusion / eutectic bonding), while the rest are the same. The parameters of thermocompression bonding are: pressure: 1-3 MPa, processing temperature: 400℃.

[0064] from Figure 11 As can be seen from the data, the bonding surface of the packaged wafer 60 after packaging shows that the thermal element is broken.

[0065] Comparative Example 3 A method for fabricating a wafer-level packaged micro thermal conductivity detector wafer includes: Compared with Example 1, the encapsulation process in the third step is replaced with anodic bonding, while the rest are the same. The anodic bonding parameters are: voltage: 1200 V, processing temperature: 350℃, and pressure: 0.2-1 MPa.

[0066] from Figure 12 It can be seen that the 60-sided solder joint of the packaged wafer after encapsulation exhibits electrical breakdown. Figure 13 It can be seen that the 60 bonding surface of the packaged wafer after packaging shows electrical breakdown and the fracture of the thermal element.

[0067] Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A miniature thermal conductivity detector wafer based on TGV, characterized in that, Includes multiple miniature thermal conductivity detectors; Multiple micro thermal conductivity detectors are disposed on a packaged wafer (60), which is composed of a silicon wafer (61) and a glass wafer (62). Multiple silicon substrates (10) are disposed on the silicon wafer (61), and multiple glass plates (20) are disposed on the glass wafer (62). The silicon substrate (10) is provided with a plurality of first half pools (41), and first half groove channels (31) are symmetrically provided on both sides of the first half pools (41). The glass plate (20) is provided with a plurality of second half pools (42), and second half groove channels (32) are symmetrically provided on both sides of the second half pools (42). The first half groove channels (31) and the second half groove channels (32) cooperate with each other to form a through groove (30). The first half pools (41) and the second half pools (42) cooperate with each other to form a thermal conductivity pool (40). The packaged wafer (60) also includes a number of microcircuits (50), the microcircuits (50) including a Wheatstone bridge (51) and electrodes (52) connected to both ends of the Wheatstone bridge (51), the top of the electrodes (52) being provided with pads (53). The Wheatstone bridge (51) is disposed in the thermal conductivity cell (40), the electrode (52) is disposed in the through hole of the glass plate (20), and the pad (53) is located on the surface of the glass plate (20).

2. The TGV-based micro thermal conductivity detector wafer according to claim 1, characterized in that, The silicon wafer (61) is further provided with a first alignment mark (63) and a second alignment mark (65), and the glass wafer (62) is further provided with a third alignment mark (64) and a fourth alignment mark (66). The position of the third alignment mark (64) matches the position of the first alignment mark (63) or the second alignment mark (65), and the position of the fourth alignment mark (66) matches the position of the second alignment mark (65) or the first alignment mark (63).

3. The TGV-based miniature thermal conductivity detector wafer according to claim 1, characterized in that, A heat insulation layer is also provided on the silicon substrate (10).

4. The TGV-based micro thermal conductivity detector wafer according to claim 3, characterized in that, The heat insulation layer is a silicon oxide layer, and the thickness of the heat insulation layer is 300-1000 nm; The heat insulation layer is also provided with a mask layer.

5. A TGV-based micro thermal conductivity detector wafer according to claim 4, characterized in that, The mask layer is a silicon nitride layer, and the thickness of the mask layer is 100-600 nm.

6. The TGV-based miniature thermal conductivity detector wafer according to claim 1, characterized in that, A gas pipe is inserted into the through groove (30), and the diameter of the through groove (30) is 600-1000μm.

7. A miniature thermal conductivity detector wafer based on TGV according to claim 1, characterized in that, The thickness of the Wheatstone bridge (51) is 200-500 nm, and the diameter of the electrode (52) is 100-300 μm; The diameter of the thermal conductivity pool (40) is 200-300 μm.

8. A method for fabricating a TGV-based micro thermal conductivity detector wafer according to any one of claims 1-7, characterized in that, include: Glass wafer (62) processing: Through holes are processed on the glass wafer (62); Sandblasting is performed on the glass wafer (62) to obtain the second half pool (42); Sandblasting is performed on both sides of the second half pool (42) to obtain the second half groove channel (32), thus completing the processing of the glass wafer (62); Silicon wafer (61) processing: A Wheatstone bridge (51) is processed on the silicon wafer (61); the first half-cell (41) position is obtained by homogenization, exposure and development on the surface of the silicon wafer (61), and the silicon nitride and silicon oxide at the corresponding positions are removed by dry etching to expose the silicon at the first half-cell (41) position; sandblasting is performed on the symmetrical positions on both sides of the first half-cell (41) position to obtain the first half-groove channel (31); the silicon wafer (61) is subjected to solution etching to obtain the first half-cell (41), thus completing the processing of the silicon wafer (61); Packaging: Align the processed glass wafer (62) with the processed silicon wafer (61) and encapsulate them using ultrafast laser welding to ensure that the first half-groove channel (31) and the second half-groove channel (32) cooperate with each other, and the first half-pool (41) and the second half-pool (42) cooperate with each other; fill the through hole with electrode (52) material to obtain electrode (52); plate the surface of the glass wafer (62) with pads (53) to obtain the packaged wafer (60).

9. The method for fabricating a TGV-based micro thermal conductivity detector wafer according to claim 8, characterized in that, Prior to the step of "fabricating a Wheatstone bridge (51) on a silicon wafer (61)," the processing of the silicon wafer (61) includes: Processing of the heat insulation layer: Surface deposition is performed on the surface of the silicon wafer (61) to obtain the heat insulation layer; Mask layer processing: Surface deposition is performed on the surface of the insulation layer to obtain the mask layer.

10. The method for fabricating a TGV-based micro thermal conductivity detector wafer according to claim 8, characterized in that, The ultrafast laser welding includes: The silicon wafer (61) and glass wafer (62) are aligned before welding and a preset pressure is applied to obtain an aligned sample; Fix the laser beam (70) and move it to align with the sample so that the laser beam (70) sweeps the sample horizontally; The preset pressure is 0.3 MPa-0.4 MPa, and the scanning speed is set to 20-30 mm / s; The laser beam (70) has the following parameters: wavelength 1064 nm, repetition frequency 300 kHz, pulse width 15 ps, pulse energy 16.9 uJ, maximum output power 12.78 W, and spot size 40±2 μm. The glass wafer (62) has a thickness of 400-600 μm and a size of 4-8 inches.

11. A method for fabricating a TGV-based micro thermal conductivity detector wafer according to any one of claims 8-10, characterized in that, The silicon wafer (61) has a thickness of 400-600 μm and a size of 4-8 inches.

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