High temperature coefficient thermoelectric conversion structure based on CMOS process and microbolometer

By designing a Schottky diode structure in CMOS technology and utilizing the N+ type doped layer of metal silicide and N-well layer, the problem of low temperature coefficient in CMOS microbolometers was solved, realizing an infrared detector with high responsivity and detectivity, suitable for large-scale production and civilian applications.

CN122270026APending Publication Date: 2026-06-23NANJING UNIV

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
NANJING UNIV
Filing Date
2024-12-20
Publication Date
2026-06-23

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Abstract

The application discloses a high-temperature-coefficient thermoelectric conversion structure and a micro-bolometer based on a CMOS process. The thermoelectric conversion structure comprises an N well, an N+ type doped layer, a shallow trench isolation, a metal silicide, a contact hole and a metal wire layer. The N well is annular, and the N+ type doped layer and the shallow trench isolation are arranged in the N well. The metal silicide is located on the surface of the N well, a part of which forms a Schottky contact with the N well as an anode, and another part of which forms an ohmic contact with the N+ type doped layer as a cathode, and the anode and the cathode are isolated by the shallow trench isolation. The metal silicides of the anode and the cathode are connected to the metal wire layer through the contact holes respectively. The structure has a large temperature coefficient and can significantly improve the sensitivity to temperature changes. The micro-bolometer prepared based on the thermoelectric conversion structure has high sensitivity, low noise and cost advantages, can be integrated with a readout circuit, and can realize efficient detection of infrared radiation.
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Description

Technical Field

[0001] This invention relates to the field of uncooled infrared imaging, specifically to a high temperature coefficient thermoelectric conversion structure and microbolometer based on CMOS technology. Background Technology

[0002] Uncooled infrared detectors are a crucial component of infrared thermal imaging technology, with wide applications in military, meteorology, environmental, and medical fields. Currently, most mass-produced uncooled infrared focal plane arrays (FPAs) use vanadium oxide (VOx) or amorphous silicon (α-Si) as the thermistor material. Both materials have a temperature coefficient of resistance (TCR) of 2%–3% / K. Due to the large variation in resistance with temperature, the fabricated resistance-type microbolometers exhibit high infrared light sensitivity, and these products currently dominate the commercial market. However, the complex manufacturing process and the requirement for specific production lines for these microelectromechanical systems (MEMS)-based calorimeters limit their large-scale use in the civilian sector.

[0003] Microbolometers based on standard CMOS technology can significantly reduce the production cost of field-controlled electrical amplifiers (FPAs) and enable large-scale production. Researchers have successively attempted to use various thermocouples from CMOS processes, such as n-well / p-well, PN diodes, SOI-type PN diodes, aluminum, tungsten, and polycrystalline silicon thermocouples, as thermistor materials. However, the temperature coefficient of resistance of these materials does not exceed 0.5% / K, resulting in low responsivity and detectivity in these products. Figure 1 The image shows a comparison of the detectivity of microbolometers using VOx, PN junction diodes, and Al materials as thermistors. Exploring and finding high thermoelectric conversion materials or structures within standard CMOS processes to achieve high-response-rate CMOS microbolometers is of great significance. Summary of the Invention

[0004] To address the issue of low temperature coefficients in the thermoelectric conversion structure of uncooled infrared detectors fabricated using CMOS technology, this invention fully utilizes metal silicides, N-well layers, and N+ doped layers in the CMOS process to design a novel Schottky diode thermoelectric conversion structure. This structure exhibits a large temperature coefficient, and the CMOS microbolometer fabricated based on this structure can significantly improve responsivity and detectivity.

[0005] The technical solution adopted by the thermoelectric conversion structure of this invention is as follows:

[0006] A high temperature coefficient thermoelectric conversion structure based on CMOS technology includes an N-well, an N+ type doped layer, a shallow trench isolation layer, a metal silicide, contact holes, and a metal conductor layer. The N-well is annular, and the N+ type doped layer and the shallow trench isolation layer are disposed within the N-well. The metal silicide is located on the surface of the N-well, with one part forming a Schottky contact with the N-well as the anode and the other part forming an ohmic contact with the N+ type doped layer as the cathode. The anode and cathode are separated by the shallow trench isolation layer. The metal silicides of the anode and cathode are respectively connected to the metal conductor layer through contact holes.

[0007] This invention also provides a method for fabricating the above-mentioned high temperature coefficient thermoelectric conversion structure based on CMOS technology, comprising the following steps:

[0008] (1) Define an active region on a P-type silicon substrate and prepare shallow trench isolation, then perform a double well process to form an N-well and fabricate a heavily doped N+ type doped layer therein.

[0009] (2) Deposit metal silicide on the surface of N well, and through annealing process, make a part of the metal silicide form a Schottky contact with the N well, and another part form an ohmic contact with the N+ type doped layer;

[0010] (3) Contact holes are made on the metal silicides on the surface of the N-well and N+ type doped layer, and electrical connections are established with the metal conductor layer.

[0011] The present invention also provides a microbolometer, which is fabricated by CMOS and post-CMOS processes and includes a silicon substrate, a thermal isolation cavity, and a detection element. The detection element includes an infrared absorber, a support arm, and the thermoelectric conversion structure described above. The silicon substrate is used to fabricate the signal readout circuit of the microbolometer. The thermal isolation cavity is located below the detection element and is used to separate the detection element from the silicon substrate. The infrared absorber is located above the thermoelectric conversion structure. The support arm is used to connect the detection element to the substrate of the microbolometer.

[0012] The present invention also provides a method for preparing a microbolometer, the method comprising the following steps:

[0013] (1) A silicon dioxide layer and a metal mask layer are sequentially deposited on top of the metal wire layer of the thermoelectric conversion structure, and a signal readout circuit and a silicon dioxide material of a certain thickness are prepared around it.

[0014] (2) Dry vertical etching or wet etching is performed on the structure prepared in step (1) until the etching depth reaches the sacrificial layer to form the shape of the support arm. In this step, a metal mask layer is used to protect the area that does not need to be etched.

[0015] (3) Remove the metal mask layer by dry or wet etching;

[0016] (4) Finally, the above-etched structure is etched away by dry etching or immersed in wet etching solution to remove the sacrificial layer, forming a thermal isolation cavity and the final microbolometer structure.

[0017] The thermoelectric conversion structure and microbolometer of this invention have wide application value in the field of uncooled infrared imaging, and their main advantages are:

[0018] (1) A high temperature coefficient Schottky diode compatible with standard CMOS process is used as the thermoelectric conversion structure. This device has both low electronic noise and a high temperature coefficient of resistance, which allows the detector performance to be much higher than that of other standard process detector structures.

[0019] (2) By using aluminum metal, which is compatible with standard CMOS processes, as a mask layer, devices can be fabricated through a simple Post-CMOS process, which further improves the cost advantage of the detector and the stability of post-processing.

[0020] (3) The present invention utilizes CMOS manufacturing process to achieve integrated integration with detector and readout circuit, which has the characteristics of high integration and low power consumption, making it suitable for large-scale production and reducing the production cost of uncooled infrared detectors. Attached Figure Description

[0021] Figure 1 This is a comparison chart of the detectivity of microbolometers using VOx, PN junction diodes, and Al materials as thermistors.

[0022] Figure 2 This is a schematic diagram of the high temperature coefficient thermoelectric conversion structure based on CMOS technology of the present invention.

[0023] Figure 3 This is a schematic diagram comparing the temperature coefficients of the thermoelectric conversion structure of this invention and a conventional polycrystalline silicon resistor under different voltages.

[0024] Figure 4 This is a schematic diagram of the CMOS microbolometer with a high temperature coefficient thermoelectric conversion structure according to the present invention.

[0025] Figure 5 This is a schematic diagram of the fabrication process of the CMOS microbolometer with a high temperature coefficient thermoelectric conversion structure of the present invention, wherein (a) is the basic structure of the detector fabricated by standard CMOS process; (b) is the basic structure after the first ICP etching; (c) is the structure after the second ICP etching to remove the metal mask layer; and (d) is the structure after wet etching to form a thermal isolation cavity. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The described embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0027] As attached Figure 2 As shown, the high temperature coefficient thermoelectric conversion structure based on CMOS technology of the present invention includes a metal silicide 105, an N-well 102, a shallow trench isolation (STI) 103, an N+ type doped region 104, a contact hole 106, and a metal conductive layer 107. The N-well 102 is annular, containing an N+ type doped region 104 and a shallow trench isolation 103. The metal silicide 105 is located on the surface of the N-well 102, partially forming a Schottky contact with the N-well 102 as the anode, and partially forming an ohmic contact with the N+ type doped region 104 as the cathode. The anode and cathode are separated by the shallow trench isolation 103, and both are connected to the metal conductive layer 107 through the contact hole 106. Common metal silicides in standard CMOS processes include WSi2, TiSi2, and CoSi2. In this embodiment, the metal silicide 105 is made of CoSi2, and the N-well 102 is made of n-type Si. The contact between the two forms a Schottky diode with a large temperature coefficient. The metal conductor layer 107 is made of aluminum. The entire structure is designed on a P-type silicon substrate 101 that is compatible with standard integrated circuits.

[0028] The specific fabrication process of the thermoelectric conversion structure in this embodiment is as follows:

[0029] An active region was defined and an STI isolation 103 was fabricated on a P-type silicon substrate 101 provided by a 0.18 μm standard CMOS process. Then, a dual-well process was performed to form an N-well 102 with a planar dimension of 40 μm × 40 μm. Next, an N+ doped region 104 was fabricated in the N-well 102 using a heavily doped ion implantation process. The N+ doped region has a planar dimension of 40 μm × 5 μm. After the above steps were completed, a metal silicide 105 was deposited on the surface of the N-well 102, and then annealed to achieve a size of 40 μm. A 40μm × 5μm metal silicide 105 forms a Schottky contact with the N-well 102 as the anode; a 40μm × 5μm metal silicide 105 forms an ohmic contact with the N+ type doped region 104 as the cathode; finally, multiple contact holes 106 with a length of 1μm, a width of 1μm, and a height of 0.65μm are formed on the metal silicide 105 of the N-well 102 and the N+ type doped region 104 to establish an electrical connection with the metal conductor layer 107, so that the anode and cathode are connected to the aluminum conductor layer 107 through multiple contact holes 106 respectively.

[0030] This invention compares the temperature coefficient of a high-temperature-coefficient thermoelectric conversion structure based on CMOS technology with that of a conventional polysilicon resistor under different voltages. Figure 3 As shown in the figure, for forward bias, the temperature coefficient of the thermoelectric conversion structure of this invention varies from 0.24% / K to 3.96% / K. Under lower forward bias, the temperature coefficient (TC) is relatively large. For reverse bias, the temperature coefficient remains almost entirely within the range of 3.14% / K to 4.8% / K, exhibiting excellent stability. Compared to the temperature coefficient of polysilicon resistors based on standard CMOS processes, which does not exceed 0.5% / K, the thermoelectric conversion structure of this invention significantly improves thermal performance.

[0031] This embodiment also provides a CMOS microbolometer with a high temperature coefficient thermoelectric conversion structure, such as... Figure 4 As shown, the device includes a silicon substrate 101, a thermal isolation cavity 115, an infrared absorber 108, a thermoelectric conversion structure, and a support arm 116, wherein the infrared absorber 108, the thermoelectric conversion structure, and the support arm 116 constitute the detection element. The silicon substrate 101 is used to fabricate the signal readout circuit of the microbolometer; the thermal isolation cavity 115 is located below the detection element and is used to separate the detection element from the silicon substrate; the infrared absorber 108 is located above the thermoelectric conversion structure and is composed of a silicon dioxide dielectric layer; the thermoelectric conversion structure adopts the structure of this invention and has a large temperature coefficient; the support arm 116 connects the detection element to the substrate of the microbolometer.

[0032] The aforementioned microbolometer is designed and manufactured using standard CMOS and simple Post-CMOS processes. Standard CMOS refers to complementary metal-oxide-semiconductor (CMOS) fabrication, which is used to fabricate the basic detector structure. Post-CMOS primarily involves simple subsequent processing of the basic detector structure fabricated using the standard CMOS process to complete the final fabrication of the high-absorptivity infrared absorber 108 and the detector structure. Specifically, this involves dry etching, including inductively coupled plasma (ICP) etching and reactive ion (RIE) etching, including isotropic and anisotropic etching, or wet etching, including isotropic or anisotropic etching using etching solutions prepared with tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), sodium hydroxide (NaOH), and other substances. The specific fabrication method includes the following steps:

[0033] (1) To prepare a thermoelectric conversion structure, a silicon dioxide layer and a metal mask layer are deposited sequentially above the metal conductor layer, and a readout circuit and a certain thickness of silicon dioxide material are prepared around it; the metal mask layer can be made of aluminum.

[0034] (2) Dry vertical etching or wet etching is performed on the structure prepared in step (1) until the etching depth reaches the sacrificial layer to form the shape of the support arm 116. During this process, a metal mask layer is used to protect the areas that do not need to be etched.

[0035] (3) Remove the metal mask layer by dry or wet etching;

[0036] (4) Finally, the above-etched structure is etched away by dry etching or immersed in wet etching solution to remove the sacrificial layer, forming the thermal isolation cavity 115 and the final microbolometer structure.

[0037] The CMOS microbolometer of this embodiment is mainly designed on a high temperature coefficient thermoelectric conversion structure. The second metal layer 109 is selected as the metal mask for the infrared absorber 108 and the support arm 116. The SiO2 dielectric layer 108 below the second metal layer 109 serves as the infrared absorber 108 of the detector. The infrared absorber 108 mask size is designed to be 50μm × 50μm. The support arm 116 is L-shaped, with a length of 77μm, a width of 7μm, and a height of 2.05μm. The gap width between the support arm 116 and the infrared absorber 108 is 4μm. The silicon substrate 101 at the bottom of the infrared absorber 108 is designed as a sacrificial layer, forming a thermally isolated cavity 115. The electrical signal is introduced into the readout circuit 114 through the first metal layer 107 in the support arm 116 as a metal wire. Then, the circuit is connected to the Pad of the sixth metal layer 112 through the via 113 between the metal layers, and finally the electrical signal is read out.

[0038] This embodiment provides a specific manufacturing method for a microbolometer:

[0039] (1) Based on the structural design of the microbolometer, a layout was drawn. On a P-type silicon substrate 101 provided by standard CMOS technology, a thermoelectric conversion structure, a support arm 116 mask, and a readout circuit 114 were sequentially fabricated. Then, a SiO2 layer 110 and a Si3N4 passivation layer 111 were deposited to complete the fabrication of the basic structure. Specifically, as shown below... Figure 5 As shown in (a) in the figure.

[0040] (2) The microbolometer with the above basic structure is placed in an inductively coupled plasma (ICP) device. A mixture of CF4 and CHF3 gas is used to etch the passivation layer 111 and dielectric layer 110 vertically from top to bottom until the etching depth reaches the silicon substrate 101. At this point, the passivation layer and dielectric layer above the mask (second metal layer 109) of the probe element and suspension support arm 116 have been completely etched. Specifically, as shown... Figure 5 As shown in (b) of the diagram.

[0041] (3) The structure obtained in step (2) is placed in a metal plasma etching machine. Using a mixture of BCl3 and Ar gas, the second metal layer 109, which protects the detection element and the suspension support arm 116, is etched away to complete the fabrication process of the microbolometer structure. Specifically, as follows... Figure 5 As shown in (c) in the figure.

[0042] (4) The structure obtained in step (3) above is placed in a wet etching solution prepared with TMAH solution, Si powder and ammonium persulfate, and the temperature is maintained at 85°C to etch the Si substrate. After 180 minutes, a T-shaped thermal isolation cavity 115 is formed at the bottom of the detector, as shown in the figure. Figure 5 As shown in (d) in the figure, the microbolometer is finally obtained.

[0043] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of preferred examples of a certain preparation method and are not intended to limit the present invention. The present invention is not limited to the application of the current preparation method. Any modifications, equivalent substitutions, improvements, etc., made within the theory and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high temperature coefficient thermoelectric conversion structure based on CMOS technology, characterized in that, The thermoelectric conversion structure includes an N-well, an N+ type doped layer, a shallow trench isolation layer, a metal silicide, contact holes, and a metal wire layer. The N-well is annular, and the N+ type doped layer and the shallow trench isolation layer are disposed within the N-well. The metal silicide is located on the surface of the N-well, with one part forming a Schottky contact with the N-well as the anode, and the other part forming an ohmic contact with the N+ type doped layer as the cathode. The anode and cathode are separated by the shallow trench isolation layer. The metal silicides of the anode and cathode are respectively connected to the metal wire layer through contact holes.

2. The high temperature coefficient thermoelectric conversion structure based on CMOS technology according to claim 1, characterized in that, The thermoelectric conversion structure is located on a P-type silicon substrate.

3. The high temperature coefficient thermoelectric conversion structure based on CMOS technology according to claim 1, characterized in that: There are multiple contact holes, all of which are connected to the metal conductor layer.

4. The method for fabricating a high temperature coefficient thermoelectric conversion structure based on CMOS technology as described in claim 1, characterized in that, Includes the following steps: (1) Define an active region on a P-type silicon substrate and prepare shallow trench isolation, then perform a double well process to form an N-well and fabricate a heavily doped N+ type doped layer therein. (2) Deposit metal silicide on the surface of N well, and through annealing process, make a part of the metal silicide form a Schottky contact with the N well, and another part form an ohmic contact with the N+ type doped layer; (3) Contact holes are made on the metal silicides on the surface of the N-well and N+ type doped layer, and electrical connections are established with the metal conductor layer.

5. A microbolometer, characterized in that, The microbolometer is fabricated using CMOS and post-CMOS processes and includes a silicon substrate, a thermally isolated cavity, and a detection element. The detection element includes an infrared absorber, a support arm, and a thermoelectric conversion structure as described in any one of claims 1-4. The silicon substrate is used to fabricate the signal readout circuit of the microbolometer. The thermally isolated cavity is located below the detection element and is used to separate the detection element from the silicon substrate. The infrared absorber is located above the thermoelectric conversion structure. The support arm is used to connect the detection element to the substrate of the microbolometer.

6. The method for preparing the microbolometer as described in claim 5, characterized in that, The preparation method includes the following steps: (1) A silicon dioxide layer and a metal mask layer are sequentially deposited on top of the metal wire layer of the thermoelectric conversion structure, and a signal readout circuit and a silicon dioxide material of a certain thickness are prepared around it. (2) Dry vertical etching or wet etching is performed on the structure prepared in step (1) until the etching depth reaches the sacrificial layer to form the shape of the support arm. In this step, a metal mask layer is used to protect the area that does not need to be etched. (3) Remove the metal mask layer by dry or wet etching; (4) Finally, the above-etched structure is etched away by dry etching or immersed in wet etching solution to remove the sacrificial layer, forming a thermal isolation cavity and the final microbolometer structure.

7. The preparation method according to claim 6, characterized in that, The material of the metal mask layer is aluminum.