An optical proximity correction pattern inspection method
By accurately defining and hierarchically screening feature patterns, the problem of missed detection caused by exempted areas in the inspection after optical proximity effect correction is solved, and the effective detection and correction of high-risk patterns is realized, thereby improving lithography accuracy and chip yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GEKKO SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2026-04-15
- Publication Date
- 2026-06-16
AI Technical Summary
In the current inspection after optical proximity effect correction, corner areas are set as inspection-exempt areas, which makes it impossible to detect potential process weaknesses, resulting in the risk of missed detection and affecting lithography accuracy and chip yield.
By precisely defining and grading feature graphics, high-risk graphics that were originally exempted are screened out and targeted inspections are carried out. This includes detailed definitions of geometric parameters such as corners, steps, line ends, grooves, and protrusions, and setting screening thresholds based on line length, corner angle, and graphic width to cancel exemptions and conduct edge placement error checks.
It effectively identifies and corrects potential process weaknesses, improves lithography precision and chip yield, significantly enhances the accuracy and comprehensiveness of OPC verification, and avoids wafer defects caused by missed detections.
Smart Images
Figure CN122219010A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing, specifically to an optical proximity effect correction pattern inspection method. Background Technology
[0002] In integrated circuit manufacturing, due to factors such as light diffraction and interference phenomena, as well as the chemical reactions of photoresist, there is often a certain degree of distortion between the actual pattern on the wafer and the circuit layout design. To eliminate this error, optical proximity correction technology is widely used. This technology preprocesses the design pattern to generate a compensation pattern, compensating for the optical proximity effect during photolithography, ensuring that the exposed wafer image meets the circuit design requirements as closely as possible. After optical proximity correction is completed, post-correction verification is usually required. This involves using a model database to simulate and examine the corrected layout to identify potential process weaknesses.
[0003] like Figure 1 As shown, in existing inspection procedures after optical proximity correction, corner patterns in the layout are typically defined as two-dimensional regions. Due to the unavoidable rounding of corners during photolithography, to reduce invalid errors, current practices generally do not perform edge placement error checks on these two-dimensional regions, thus classifying them as exempt areas. However, in actual layout design, when both ends of a geometric line are corners and the line length is less than twice the defined corner length, the line is classified as an exempt area; furthermore, if the line width is large, it may not trigger other checks such as breakpoints, relative values, and mask error enhancement factors. This approach results in potential process weaknesses in such specific geometries going undetected, posing a risk of allowing the process to proceed. Therefore, how to achieve comprehensive and effective inspection of the layout to avoid missing potential process weaknesses is a problem that those skilled in the art need to solve.
[0004] The statements herein provide only background information in relation to the present invention and do not necessarily constitute prior art. Summary of the Invention
[0005] The purpose of this invention is to provide an optical proximity effect correction pattern inspection method, which has the advantages of eliminating blind spots and improving inspection coverage.
[0006] To achieve the above objectives, the present invention provides a method for inspecting optical proximity effect correction patterns, comprising: S10. Obtain the target layer, the original layer, and the optical proximity effect corrected layer of the circuit layout; S20. Define layout feature graphics based on the geometric parameters of the circuit layout; S30. According to the definition, select graphics belonging to the pre-set inspection-free area from the circuit layout, and further select a subset of target graphics from the graphics in the inspection-free area according to the preset screening conditions. S40. Perform optical proximity correction on the target graphic subset and then check it.
[0007] In some embodiments, the definition of the layout feature graphics in step S20 includes defining the geometric parameters of at least one of the following feature graphics: corner, step, line end, groove, and protrusion.
[0008] In some embodiments, the geometric parameters include at least one of angle range, length, width, and height.
[0009] In some embodiments, in step S30, the pre-defined inspection-free area includes a corner graphic that is identified as a two-dimensional area.
[0010] In some embodiments, the preset filtering conditions in step S30 include setting a filtering threshold based on at least one of the parameters of line length, corner angle, and graphic width of the graphic in the inspection-free area.
[0011] In some embodiments, the preset filtering conditions include: filtering out graphics with line lengths greater than a first preset length and less than a second preset length from the graphics in the exempt area, and defining them as the target graphic subset.
[0012] In some embodiments, the first set length is one time the corner definition length, and the second set length is twice the corner definition length.
[0013] In some embodiments, the preset filtering conditions include: filtering out graphics whose corner angle is an integer multiple of a set angle and whose length is less than a set length from the graphics in the exempt area, and defining them as the target graphic subset.
[0014] In some embodiments, step S40, after performing optical proximity effect correction on the target graphic subset, includes performing edge placement error checks.
[0015] In some embodiments, it also includes: Step S50: Output the weakness information that failed the inspection after the optical proximity effect correction, the weakness information including weakness type and location information; Step S60: Perform local optical proximity effect correction on the circuit layout based on the weakness information.
[0016] In some embodiments, step S30 specifically includes: inspecting the circuit layout according to the definition to obtain a set of feature graphic information; and then filtering the target graphic subset from the set of feature graphic information according to the preset filtering conditions.
[0017] In summary, compared with the prior art, the optical proximity effect correction pattern inspection method provided by the present invention has the following beneficial effects: The technical solution of this application effectively breaks through the blind spots caused by the setting of exempt areas in traditional OPC verification by accurately defining and hierarchically screening feature patterns. It can accurately screen out specific high-risk patterns that were originally exempted (such as lines between corners of a certain length) from the 2D area for targeted inspection. Without introducing a large number of false alarms, it can effectively capture and correct potential process weaknesses, significantly improving the accuracy and comprehensiveness of OPC verification, thereby providing key technical support for improving lithography precision and chip yield. Attached Figure Description
[0018] Figure 1 This is a flowchart for verifying optical proximity effect correction in existing technologies.
[0019] Figure 2 This is a flowchart of the optical proximity effect correction pattern inspection method of this application.
[0020] Figure 3 This is a schematic diagram illustrating the definition of the feature graphics involved in the present invention.
[0021] Figure 4 A schematic diagram is precisely defined for the feature graphics.
[0022] Figure 5 and Figure 6 This is a simulation comparison diagram of the method of the present invention and the prior art. Detailed Implementation
[0023] The optical proximity effect correction pattern inspection method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.
[0024] This invention provides an optical proximity effect correction pattern inspection method, aiming to solve the problem in existing technologies where potential process weaknesses are missed due to corner areas being designated as exemption areas. This method, through precise definition and hierarchical screening of specific feature patterns in the layout, identifies patterns that were originally exempt from inspection and performs targeted checks, thereby improving lithography accuracy and chip yield.
[0025] Specifically, such as Figure 2 As shown, the method in this embodiment includes the following steps: Step S10: Obtain the target layer, original layer, and optical proximity correction layer of the circuit layout. In this step, the layout data to be processed must first be read in. The layout information specifically includes three key layers: the original layer, the target layer, and the optical proximity correction layer.
[0026] The original layer is the layout data initially generated for the circuit design, representing the ideal geometry of the design. The target layer is the desired pattern target to be formed on the wafer according to process requirements and optical proximity correction strategies. In some embodiments, this layer may be obtained from the original layer after certain preprocessing. The optical proximity correction layer, i.e., the corrected layer, is the layout data processed by OPC (Optical Proximity Correction) software, containing various auxiliary graphics used to compensate for optical proximity effects and adjusted graphic outlines. The above layer data can be obtained through a standard layout data reading interface. The obtained layer data serves as the basis for subsequent graphic definition, comparison, and inspection operations.
[0027] Step S20: Define layout feature graphics based on the geometric parameters of the circuit layout. Based on the acquired layout information, the geometric graphics in the layout are defined in a characteristic manner. Existing technologies typically only simply distinguish between one-dimensional and two-dimensional graphics, while this embodiment performs a more detailed identification and definition of the layout geometric dimensions.
[0028] like Figure 3 As shown, Figure 3 This invention relates to a schematic diagram of the definition of feature graphics. The definition of layout feature graphics includes defining the geometric parameters of at least one of the following feature graphics: Corner: Defines its type (including internal and external corners), angle range, and the length of the area affected by the corner (i.e., the defined length of the corner). Step: Defines its height and length; Line end: Defines its width and length; Groove: Defines its width and length; Small protrusion: Defines its height and length.
[0029] The definition of corner graphics is one of the core aspects of this step. Due to the complexity of the layout structure, corners are specifically classified into Corner Type 1 (corresponding to...) based on their concave and convex shapes at the edges of the graphics. Figure 3 The outer corner shown in the image) and corner type two (corresponding to Figure 3 (As shown in the diagram, the internal corner). For these two corner types, corresponding geometric parameters need to be set: first, the angle range, used to define which angle transitions are identified as the corresponding type of corner (such as a specific acute angle or right angle range); second, the corner definition length, that is, the distance range extending from the corner vertex along the edge of the graphic to both sides. By clearly dividing corner type one and corner type two and quantifying their angle and length parameters, the boundary range of all corner areas can be accurately marked on the layout, providing a basic data set for subsequent filtering.
[0030] Geometric parameters specifically include at least one of angle range, length, width, and height. For example, for a corner feature, a length threshold L_corner is set, and the area within L_corner surrounding the corner vertex is defined as the corner region. Through the above definition, the position and attributes of various feature graphics can be identified and marked on the map, forming a preliminary set of feature graphic information.
[0031] Step S30: Based on the feature graphic definition obtained in step S20, select graphics belonging to the pre-set inspection-free area from the circuit layout, and further select a subset of target graphics from the graphics in the inspection-free area according to the preset screening conditions.
[0032] Step S30 is the core step of the applied technical solution. In the inspection procedure after optical proximity effect correction in the prior art, corner patterns are usually defined as two-dimensional (2D) regions. Due to the corner rounding phenomenon during the lithography process, the conventional practice usually does not perform edge placement error (EPE) inspection on this region, thus forming an exemption inspection area. However, this results in some lines located between corners and having specific dimensions being mistakenly released.
[0033] The specific implementation process of this step includes, first, traversing and identifying the circuit layout according to the definition of the characteristic patterns in step S20, identifying all patterns marked as "corners" or other two-dimensional features, and obtaining a set of characteristic pattern information. Among them, the patterns located within the defined length range of the corners are classified as the exemption inspection area.
[0034] Secondly, from the set of characteristic pattern information, a subset of target patterns is screened out according to preset screening conditions. The subset of target patterns refers to the patterns that, although belonging to the exemption inspection area, may pose risks in the actual process. The screening conditions are set based on geometric parameters, specifically including setting a screening threshold according to at least one of the line length, corner angle, and pattern width of the patterns in the exemption inspection area.
[0035] In this embodiment, the screening conditions specifically include screening based on the line length and the corner angle. Among them, the screening based on the line length includes: screening out the patterns with a line length greater than the first set length and less than the second set length from the patterns in the exemption inspection area and classifying them into the subset of target patterns.
[0036] As a specific implementation manner, taking Figure 4 the patterns shown as an example, the first set length is one-fold of the corner definition length, and the second set length is two-fold of the corner definition length. If the corner definition length is L, then the patterns with a line length L_line satisfying L < L_line < 2L are screened out. Such patterns (such as Figure 4 line A shown in) have corners at both ends and a short length, and are easily missed in the conventional inspection. However, after lithography, abnormalities such as thinning in the middle part are likely to occur, so they need to be inspected key points.
[0037] Among them, the screening based on the corner angle and the length includes: screening out the patterns with a corner angle that is an integer multiple of the set angle and a length less than the set length from the patterns in the exemption inspection area and defining them as the subset of target patterns.
[0038] As a specific implementation manner, the set angle is 45 degrees. The patterns with a corner angle that is an integer multiple of 45 degrees (such as 45°, 90°, 135°, etc.) and a length range less than one-fold of the corner definition length are screened out (such as Figure 4 line B shown in).
[0039] In addition, to avoid detection overlap with existing small-size disconnection checks, further restrictions can be placed on the graphic width. For example, only graphics with line widths greater than a preset safety threshold can be filtered into the target graphic subset.
[0040] Through the process of precise definition and hierarchical screening of the above-mentioned feature graphics, graphics that were originally broadly classified as exempt from inspection can be finely divided, and potentially high-risk graphics can be extracted to form a new set of inspection objects, that is, to form a subset of target graphics.
[0041] Step S40: Perform optical proximity correction on the target image subset. After selecting the target image subset, cancel the exemption from inspection for that image subset and perform inspection using conventional optical proximity correction methods.
[0042] Specifically, the inspection includes performing an edge placement error check. The EPE check calculates the deviation value between the edges by comparing the simulated post-exposure contours of the target layer and the corrected layer. If the deviation value exceeds the preset allowable range, it is determined to be a process weakness.
[0043] Because this embodiment includes certain lines that are normally exempt from inspection, it can effectively discover potential risk points that cannot be detected in the prior art, such as the problem that the middle part of short lines between corners is too narrow or too wide.
[0044] In some embodiments, a processing flow for the inspection results is further included, specifically including: Step S50: Output information on weaknesses that failed the inspection after optical proximity effect correction. The weakness information includes the type and location of the weakness.
[0045] When an anomaly violating the release rules is found during the inspection of a subset of the target graphics, the system will generate and output a weakness report. The weakness report records the type of weakness (such as EPE exceeding the limit, line thinning, etc.) and its specific coordinates (point information) on the layout, providing clear modification guidance for subsequent modifications.
[0046] Furthermore, in some embodiments, step S60 is also included: performing local optical proximity correction on the circuit layout based on the weakness information.
[0047] Based on the output weakness information, engineers or automated correction tools perform localized optimizations on specific anomalies. For example, they might adjust the size or position of auxiliary graphics or modify the edge offset of the main graphic. After correction, the above inspection process can be repeated until all weaknesses meet the release rules, thus ensuring the accuracy of the photomask data.
[0048] Through the above steps, this embodiment of the invention identifies and inspects potential risk patterns from the inspection-free area by accurately defining and classifying feature patterns, filling the blind spots of the existing OPC verification process, effectively avoiding wafer defects caused by missed inspections, and improving the yield and reliability of semiconductor manufacturing.
[0049] The technical effects brought about by this invention can be further verified by simulation data. Figure 5 and Figure 6 This is a simulation comparison diagram of the method of the present invention and the prior art. For example... Figure 5 As shown, certain lines in the layout with corners at both ends and inwardly concave line widths, i.e., potential weaknesses, cannot be detected in existing technologies because they are classified as two-dimensional inspection-free areas, resulting in blind spots. However, by using the precise definition and hierarchical screening method of this invention to screen these lines and then perform mandatory inspection, the deviation between the actual and target graphics at these points can be clearly captured in the simulation contour. The simulation results objectively demonstrate that this method can effectively eliminate the blind spots of existing inspection processes and accurately obtain OPC correction anomalies. It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0050] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0051] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0052] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0053] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for inspecting optical proximity effect-corrected patterns, characterized in that, Includes the following steps: S10. Obtain the target layer, the original layer, and the optical proximity effect corrected layer of the circuit layout; S20. Define layout feature graphics based on the geometric parameters of the circuit layout; S30. According to the definition, select graphics belonging to the pre-set inspection-free area from the circuit layout, and further select a subset of target graphics from the graphics in the inspection-free area according to the preset screening conditions. S40. Perform optical proximity correction on the target graphic subset and then check it.
2. The optical proximity effect correction pattern inspection method according to claim 1, characterized in that, The definition of the layout feature graphics in step S20 includes defining the geometric parameters of at least one of the following feature graphics: corner, step, line end, groove, and protrusion.
3. The optical proximity effect correction pattern inspection method according to claim 2, characterized in that, The geometric parameters include at least one of the following: angle range, length, width, and height.
4. The optical proximity effect correction pattern inspection method according to claim 1, characterized in that, In step S30, the pre-defined inspection-free area includes corner graphics that are identified as two-dimensional areas.
5. The optical proximity effect correction pattern inspection method according to claim 1 or 4, characterized in that, The preset filtering conditions in step S30 include setting a filtering threshold based on at least one of the parameters of line length, corner angle, and graphic width of the graphic in the inspection-free area.
6. The optical proximity effect correction pattern inspection method according to claim 5, characterized in that, The preset filtering conditions include: filtering out graphics with line lengths greater than a first preset length and less than a second preset length from the graphics in the exempt area, and defining them as the target graphic subset.
7. The optical proximity effect correction pattern inspection method according to claim 6, characterized in that, The first set length is one time the corner definition length, and the second set length is twice the corner definition length.
8. The optical proximity effect correction pattern inspection method according to claim 5, characterized in that, The preset filtering conditions include: selecting graphics whose corner angle is an integer multiple of a set angle and whose length is less than a set length from the graphics in the exempt area, and defining them as the target graphic subset.
9. The optical proximity effect correction pattern inspection method according to claim 1, characterized in that, In step S40, the target graphic subset is checked after optical proximity effect correction, including performing edge placement error checks.
10. The optical proximity effect correction pattern inspection method according to claim 1, characterized in that, It also includes: step S50: outputting the weakness information that failed the inspection after the optical proximity effect correction, the weakness information including weakness type and location information; step S60: performing local optical proximity effect correction on the circuit layout according to the weakness information.
11. The optical proximity effect correction pattern inspection method according to claim 1, characterized in that, Step S30 specifically includes: inspecting the circuit layout according to the definition to obtain a set of feature graphic information; and then selecting the target graphic subset from the set of feature graphic information according to the preset filtering conditions.