A deep neural network hierarchical structure analysis method based on side channel timing characteristics

By acquiring the timing signals of the graphics card side channel and constructing context-dependent representations, the problem of parsing the hierarchical structure of deep neural networks under complex network structures and noise interference is solved, achieving stable and reliable hierarchical structure recognition and parameter acquisition.

CN122221918APending Publication Date: 2026-06-16SHANGHAI UNIVERSITY OF FINANCE AND ECONOMICS
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI UNIVERSITY OF FINANCE AND ECONOMICS
Filing Date
2026-01-28
Publication Date
2026-06-16

AI Technical Summary

Technical Problem

Existing technologies struggle to accurately analyze the hierarchical structure of deep neural networks from continuous side-channel timing features under complex network structures and diverse conditions, and their robustness is insufficient, especially when subjected to noise interference and changes in execution modes, resulting in unstable analysis results.

Method used

By acquiring the side-channel timing signals during the deep neural network inference process executed by the graphics card, a timing representation containing context-related information is constructed. The neural network is used to parse the hierarchical structure, and the structural parameter information is determined by combining the execution interval and the hierarchical type.

Benefits of technology

It achieves stable parsing of the hierarchical structure of deep neural networks under complex network structures and noise interference conditions, improves the completeness and reliability of the parsing results, expands the scope of application, reduces the dependence on additional prior information, and enhances robustness.

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Abstract

The application discloses a deep neural network hierarchical structure analysis method based on side channel timing characteristics, which realizes stable analysis of the deep neural network hierarchical structure by processing the side channel timing signals generated during the execution of the deep neural network inference process of a graphics card, and further determines the structure parameter information of the network layer on the basis. The application models the side channel timing characteristics, so that the analysis process is not dependent on the fixed network layer number or the preset structure form, thereby enabling effective analysis of the deep neural network hierarchical structure under the condition of high diversity of the network layer number, layer type combination and execution order, expanding the application range of the side channel structure analysis method. The network hierarchical structure identification and network layer structure parameter acquisition are simultaneously realized in the unified analysis process, and the analysis robustness of the side channel timing signals under the condition of noise interference and execution mode change is improved.
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