Timing detection circuit and level conversion device

Abstract

This application discloses a timing detection circuit and a level conversion device. The circuit includes: a voltage detection module for receiving a first scan control voltage, a second scan control voltage, and an input voltage; outputting a polarity indication signal based on the polarity relationship between the first and second scan control voltages; and outputting a voltage indication signal based on the voltage relationship between the input voltage and a preset reference voltage. An output control module, connected to the voltage detection module, generates a first enable control signal based on the polarity indication signal and a second enable control signal based on the polarity indication signal and the voltage indication signal. The first enable control signal controls the output state of the source drive circuit, and the second enable control signal controls the output state of the gate drive circuit. This effectively avoids abnormal boot screen issues caused by improper timing design, improving product display quality and development efficiency.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a timing detection circuit and a level conversion device. Background Technology

[0002] In Liquid Crystal Display (LCD) technology, the display panel includes an array of pixel units. Each pixel unit includes a thin-film transistor (TFT), a pixel electrode, and a common electrode. The TFT acts as the switching element of the pixel unit; its gate is controlled by a gate drive voltage output from a gate drive circuit, its source receives a data voltage output from a source drive circuit, and its drain outputs the data voltage to the pixel electrode. The common electrode is driven by a common voltage (VCOM).

[0003] When the display panel is powered on, the startup sequence of the gate drive circuit, source drive circuit, and common voltage must be strictly controlled. If there is a voltage difference between the common electrode voltage and the source data voltage, and the TFT is still in a conducting state because the gate is not completely closed, it will cause the liquid crystal molecules to be abnormally driven, resulting in abnormal screen phenomena such as white flickering during startup.

[0004] In existing technologies, level shifting devices are mainly used to convert logic control signals to generate timing control signals that meet the voltage requirements of the gate drive circuit and the source drive circuit. During the early design phase of a display module, designers primarily rely on level shifting devices to generate timing control signals for drive verification without a complete display module. However, existing level shifting devices lack the ability to detect abnormal power-on states and actively control the output timing, failing to dynamically adjust the output timing of the common voltage, source data voltage, and gate drive voltage according to the actual operating state of the display panel.

[0005] Specifically, in display panels employing Gate In Array (GIA) or Gate On Array (GOA) technologies, the gate driving circuit typically includes a first group of GIA / GOA and a second group of GIA / GOA operating alternately, driven by a first scan control voltage and a second scan control voltage, respectively. During normal operation, the first scan control voltage and the second scan control voltage have opposite polarities, and the two groups of GIA / GOA scan alternately to achieve line-by-line driving. However, in the initial power-on phase, before the logic control module has stabilized its output, the first scan control voltage and the second scan control voltage may be in an abnormal state with the same polarity. At this time, the gate driving circuit cannot generate the scan timing correctly. If the gate driving voltage is not pulled down to the off level synchronously with the clock signal, the TFT will not be completely turned off. If a voltage difference exists between the common electrode voltage and the source data voltage at this time, abnormal screen display such as flickering white upon power-on will occur.

[0006] Furthermore, in existing technologies, designers can only measure and adjust the timing after obtaining the complete display module, making it impossible to achieve correct power-on timing control at the beginning of the design process, thus avoiding abnormal panel startup screens and increasing design difficulty and development cycle.

[0007] Therefore, it is necessary to provide improved technical solutions to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention

[0008] The purpose of this application is to provide a timing detection circuit and a level conversion device to solve the problem of abnormal screen display caused by improper timing control when the display panel is powered on.

[0009] To achieve the above objectives: In a first aspect, embodiments of this application provide a timing detection circuit, including: The voltage detection module is used to receive a first scan control voltage, a second scan control voltage, and an input voltage, and output a polarity indication signal according to the polarity relationship between the first scan control voltage and the second scan control voltage, and output a voltage indication signal according to the voltage relationship between the input voltage and a preset reference voltage. An output control module, connected to the voltage detection module, is used to generate a first enable control signal based on the polarity indication signal, and to generate a second enable control signal based on the polarity indication signal and the voltage indication signal. The first enable control signal is used to control the output state of the source drive circuit, and the second enable control signal is used to control the output state of the gate drive circuit.

[0010] In one embodiment, the voltage detection module includes a first detection unit and a second detection unit; The first detection unit is used to output a polarity indication signal of a first level state when the polarity of the first scan control voltage and the second scan control voltage are the same, and to output a polarity indication signal of a second level state when the polarity of the first scan control voltage and the second scan control voltage are opposite. The second detection unit is used to output a voltage indication signal at a first level when the input voltage is greater than the reference voltage, and to output a voltage indication signal at a second level when the input voltage is less than the reference voltage.

[0011] In one embodiment, the first detection unit includes a NAND gate logic unit and a first inverter; The first input terminal of the NAND gate logic unit is used to receive the first scan control voltage; The second input terminal of the NAND gate logic unit is connected to the output terminal of the first inverter, and the input terminal of the first inverter is used to receive the second scan control voltage. The output of the NAND gate logic unit is used to output the polarity indication signal.

[0012] In one embodiment, the second detection unit includes a comparator, a first input terminal of which is used to receive the input voltage, a second input terminal of which is used to receive the reference voltage, and an output terminal of which is used to output the voltage indication signal.

[0013] In one embodiment, the output control module includes a first enabling unit, a second enabling unit, and a power-on control unit; The first enabling unit is used to output a first enabling control signal to control the source drive circuit to enter the discharge enabling state when it receives the polarity indication signal of the first level state. The second enabling unit is used to output a second enabling control signal for controlling the gate drive circuit to enter the discharge enabling state when it receives the polarity indication signal of the second level state and the voltage indication signal of the second level state. The power-on control unit is used to control the second enable unit to be in a power-off state when it receives the polarity indication signal of the first level state, so that the second enable unit outputs a second enable control signal to prevent the gate drive circuit from entering the discharge enable state.

[0014] In one embodiment, the first enabling unit includes a first switching transistor and a first current-limiting resistor; The control terminal of the first switch is used to receive the polarity indication signal. The first path terminal of the first switch is connected to the first terminal of the first current limiting resistor and the discharge enable terminal of the source drive circuit. The second path terminal of the first switch is grounded. The second end of the first current-limiting resistor is connected to the voltage input terminal.

[0015] In one embodiment, the first enabling unit further includes a second switching transistor, a second current-limiting resistor, and a first pull-down resistor; The control terminal of the second switch is used to receive the polarity indication signal. The first path terminal of the second switch is connected to the common voltage output terminal through the second current limiting resistor, and the second path terminal of the second switch is grounded. The first end of the first pull-down resistor is connected to the control terminal of the second switch, and the second end of the first pull-down resistor is grounded.

[0016] In one embodiment, the second enabling unit includes a second inverter, a third switching transistor, a second pull-down resistor, and a third current-limiting resistor; The input terminal of the second inverter is used to receive the voltage indication signal, and the output terminal of the second inverter is connected to the control terminal of the third switch. The first path terminal of the third switch is connected to the first terminal of the third current-limiting resistor and the discharge enable terminal of the gate drive circuit, and the second path terminal of the third switch is grounded. The second end of the third current-limiting resistor is connected to the voltage input terminal; The first end of the second pull-down resistor is connected to the control terminal of the third switch, and the second end of the second pull-down resistor is grounded.

[0017] In one embodiment, the power-on control unit includes a third inverter, a fourth switch, a fifth switch, and a first pull-up resistor; The input terminal of the third inverter is used to receive the polarity indication signal, and the output terminal of the third inverter is connected to the control terminal of the fourth switch. The first path terminal of the fourth switch is connected to the control terminal of the fifth switch, and the second path terminal of the fourth switch is grounded. The first path terminal of the fifth switch is connected to the voltage input terminal, and the second path terminal of the fifth switch is connected to the power input terminal of the second inverter. The first pull-up resistor is connected between the control terminal of the fifth switch and the voltage input terminal.

[0018] Secondly, embodiments of this application provide a level conversion device, including the timing detection circuit described above.

[0019] The timing detection circuit and level conversion device provided in this application include a voltage detection module and an output control module. The voltage detection module receives a first scan control voltage, a second scan control voltage, and an input voltage, and outputs a polarity indication signal based on the polarity relationship between the first and second scan control voltages, and outputs a voltage indication signal based on the voltage relationship between the input voltage and a preset reference voltage. The output control module generates a first enable control signal for controlling the output state of the source drive circuit based on the polarity indication signal, and generates a second enable control signal for controlling the output state of the gate drive circuit based on the polarity indication signal and the voltage indication signal. Thus, by actively detecting the polarity relationship between the first and second scan control voltages and the establishment state of the input voltage during power-on, and using the output control module to generate corresponding enable control signals based on the detection results to control the outputs of the source drive circuit and the gate drive circuit, the voltage detection module effectively avoids abnormal power-on screen problems caused by improper timing design, simplifies the design complexity of the display panel's power-on timing, and improves the product's display quality and development efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a block diagram of the timing detection circuit provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of the circuit connection of the timing detection circuit provided in the embodiment of this application.

[0023] Figure 3 This is a schematic diagram illustrating the operation of the timing detection circuit provided in the embodiments of this application.

[0024] Figure 4 This is a schematic diagram of the level conversion device provided in an embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0026] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0027] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0028] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0029] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0030] Figure 1This is a structural block diagram of the timing detection circuit provided in an embodiment of this application. Figure 1 As shown, this application embodiment provides a timing detection circuit, which can be integrated into or externally connected to a level conversion device, for detecting relevant voltages and signals when the display panel is powered on, and thereby controlling the output timing of the source drive circuit and the gate drive circuit. The timing detection circuit 100 provided in this embodiment mainly includes a voltage detection module 110 and an output control module 120.

[0031] The voltage detection module 110 receives a first scan control voltage, a second scan control voltage, and an input voltage. The first and second scan control voltages are complementary clock signals for the gate drive circuit, used to control the alternating scan timing of the two sets of gate drive units in the display panel. The input voltage is the operating voltage of the display module.

[0032] The voltage detection module 110 generates a polarity indication signal based on the polarity relationship between the first scan control voltage and the second scan control voltage, and outputs a voltage indication signal based on the comparison result between the input voltage and the preset reference voltage.

[0033] Specifically, the voltage detection module 110 may include a first detection unit 111 and a second detection unit 112. The first detection unit 111 is configured to output a first-level polarity indication signal when the polarities of the first scan control voltage and the second scan control voltage are the same, and to output a second-level polarity indication signal when the polarities of the first scan control voltage and the second scan control voltage are opposite. The second detection unit 112 is configured to output a first-level voltage indication signal when the input voltage is greater than a reference voltage, and to output a second-level voltage indication signal when the input voltage is less than a reference voltage. In this embodiment, the first level state is a high-level state, and the second level state is a low-level state.

[0034] The output control module 120 is connected to the voltage detection module 110 and receives a polarity indication signal and a voltage indication signal. The output control module 120 generates a first enable control signal for controlling the output state of the source drive circuit based on the polarity indication signal, and generates a second enable control signal for controlling the output state of the gate drive circuit based on the polarity indication signal and the voltage indication signal.

[0035] Specifically, during the initial power-on phase, when the voltage detection module 110 detects that the first scan control voltage and the second scan control voltage have the same polarity (abnormal state), it generates a high-level polarity indication signal. The output control module 120 sets the first enable control signal to an active state (e.g., a low-level state), forcing the source drive circuit to enter the discharge enable mode (i.e., activating the XON function). This shorts the source drive circuit output terminal with the common voltage output terminal, or pulls the voltage at the source drive circuit output terminal to the same potential as the common voltage to eliminate voltage difference and prevent flashing. Simultaneously, the output control module 120 sets the second enable control signal to an inactive state (e.g., a high-level state), disabling the gate drive circuit from outputting the gate drive voltage.

[0036] When the voltage detection module 110 detects that the first scan control voltage and the second scan control voltage have opposite polarities (normal state), it generates a low-level polarity indication signal. The output control module 120 sets the first enable control signal to an invalid state (e.g., high-level state). The source drive circuit outputs the corresponding data voltage normally according to the display data, and the common voltage output terminal outputs the common voltage normally. At this time, if the voltage detection module 110 detects that the input voltage is lower than the reference voltage (the working voltage has not reached the stable working threshold), it generates a low-level voltage indication signal. The output control module 120 sets the second enable control signal to an valid state (e.g., low-level), forcing the gate drive circuit to enter the discharge enable mode (i.e., enabling the XON function), controlling the TFT to turn on simultaneously, forming a discharge path to pre-discharge the display panel and ensure that the display panel can start displaying from a clean state. If the voltage detection module 110 detects that the input voltage reaches the reference voltage (i.e., the working voltage reaches the stable working threshold), it generates a high-level voltage indication signal. The output control module 120 sets the second enable control signal to an invalid state (e.g., high-level state), and the gate drive circuit resumes normal timing output.

[0037] The timing detection circuit provided in this application actively detects the polarity relationship between the first and second scan control voltages and the establishment status of the input voltage using a voltage detection module 110, and generates a corresponding enable control signal based on the detection results using an output control module 120. During power-on, if an abnormal scan control voltage polarity or an insufficient input voltage is detected, this circuit forces the source drive circuit into a discharge enable state, eliminating the voltage difference between the source data voltage and the common voltage, while simultaneously disabling or controlling the operation of the gate drive circuit. This effectively avoids abnormal power-on screen issues caused by improper timing design. The circuit solution provided in this application simplifies the design complexity of the display panel's power-on timing sequence, improving product display quality and development efficiency.

[0038] Figure 2This is a schematic diagram of the circuit connection of the timing detection circuit provided in the embodiment of this application. Figure 3 This is a schematic diagram illustrating the operation of the timing detection circuit provided in an embodiment of this application. The following is in conjunction with... Figure 2 and Figure 3 The implementation and operation of the timing detection circuit in the embodiments of this application will be described in detail.

[0039] In this embodiment, the voltage detection module 110 includes a first detection unit 111 and a second detection unit 112.

[0040] The first detection unit 111 is used to detect the polarity relationship between the first scan control voltage V1 and the second scan control voltage V2.

[0041] In this embodiment, the first detection unit 111 includes a NAND gate logic unit U1 and a first inverter U2. The input terminal of the first inverter U2 receives a second scan control voltage V2, and the output terminal of the first inverter U2 is connected to the second input terminal of the NAND gate logic unit U1. The first inverter U2 inverts the received second scan control voltage V2 and transmits it to the second input terminal of the NAND gate logic unit U1. The first input terminal of the NAND gate logic unit U1 receives a first scan control voltage V1. The NAND gate logic unit U1 performs a NAND logic operation on the received first scan control voltage V1 and the inverted second scan control voltage V2, and outputs a polarity indication signal Pn through its output terminal according to the operation result.

[0042] For example, when the display panel is working normally, the first scan control voltage V1 and the second scan control voltage V2 are level signals with opposite polarities (e.g., V1 is high and V2 is low). After being inverted by the first inverter U2, both inputs of the NAND gate logic unit U1 are high, and its output outputs a polarity indication signal Pn indicating a low-level state (i.e., the second level state). When the display panel is in an abnormal power-on state, i.e., when the first scan control voltage V1 and the second scan control voltage V2 have the same polarity (e.g., both are high), after being inverted by the first inverter U2, one input of the NAND gate logic unit U1 is high and the other is low, and its output outputs a polarity indication signal Pn indicating a high-level state (i.e., the first level state). Therefore, in this example, when the polarity indication signal Pn is high, it indicates that the control signal of the gate drive unit is detected to be in an abnormal state.

[0043] The second detection unit 112 is used to detect whether the input voltage Vin has reached the stable operating threshold. In this embodiment, the second detection unit 112 is implemented using a comparator U3. The first input terminal of the comparator U3 receives the input voltage Vin, and the second input terminal of the comparator U3 receives the reference voltage Vref. When the input voltage Vin is greater than the reference voltage Vref, it indicates that the operating voltage of the display module has reached the stable operating threshold, and the comparator U3 outputs a voltage indication signal Pq in the first level state (high level state). When the input voltage Vin is less than the reference voltage Vref, it indicates that the power supply voltage has not been established or is abnormal, and the comparator U3 outputs a voltage indication signal Pq in the second level state (low level state).

[0044] In this embodiment, the output control module 120 includes a first enabling unit 121, a second enabling unit 122, and a power-on control unit 123.

[0045] The first enabling unit 121 is used to generate a first enabling control signal XON_S for controlling the source drive circuit. In this embodiment, the first enabling unit 121 includes a first switching transistor Q1 and a first current-limiting resistor R1. The first switching transistor Q1 is preferably an N-type metal-oxide-semiconductor field-effect transistor. The control terminal of the first switching transistor Q1 is connected to the output terminal of the NAND gate logic unit U1 to receive a polarity indication signal Pn. The first pass terminal of the first switching transistor Q1 is connected to the first terminal of the first current-limiting resistor R1 and the discharge enable terminal of the source drive circuit, and the second pass terminal of the first switching transistor Q1 is grounded to GND. The second terminal of the first current-limiting resistor R1 is connected to the voltage input terminal VIN.

[0046] When the polarity indicator signal Pn is in the first level state (high level, i.e., abnormal state), the first switch Q1 is turned on, forcibly pulling down the discharge enable terminal of the source drive circuit to a low level state, that is, outputting a valid discharge enable command to the source drive circuit, forcing the source drive circuit to enter the discharge mode (i.e., activating the XON function). In this embodiment, when the source drive circuit activates the XON function, it pulls the voltage Source at the output terminal of the source drive circuit to the same potential as the common voltage VCOM to eliminate the voltage difference and prevent flashing. When the polarity indicator signal Pn is in the second level state (low level, i.e., normal state), the first switch Q1 is turned off, and the discharge enable terminal of the source drive circuit is connected to the voltage input terminal VIN through the first current limiting resistor R1. The source drive circuit exits the discharge enable state, and the output terminal of the source drive circuit outputs the data voltage corresponding to the display data normally according to the gate scan timing.

[0047] In this embodiment, the first enabling unit 121 further includes a second switch Q2, a second current-limiting resistor R2, and a first pull-down resistor R3. The second switch Q2 is preferably an N-type metal-oxide-semiconductor field-effect transistor. The control terminal of the second switch Q2 is also connected to the output terminal of the NAND gate logic unit U1 to receive a polarity indication signal Pn. The first path terminal of the second switch Q2 is connected to the common voltage output terminal through the second current-limiting resistor R2, and the second path terminal of the second switch Q2 is grounded to GND. The first terminal of the first pull-down resistor R3 is connected to the control terminal of the second switch Q2, and the second terminal of the first pull-down resistor R3 is grounded to GND.

[0048] When the polarity indicator signal Pn is in the first level state (high level, i.e., abnormal state), the second switch Q2 is also turned on. Through the second current-limiting resistor R2 and the turned-on second switch Q2, the common voltage VCOM output from the common voltage output terminal is pulled to the same potential as the source voltage Source at the source drive circuit output terminal (in this embodiment, both Source and VCOM are pulled low to GND). When the polarity indicator signal Pn is in the second level state (low level, i.e., normal state), the second switch Q2 is turned off, and the common voltage output terminal normally outputs the common voltage VCOM. When the control signal of the gate drive unit is in the normal state, the first pull-down resistor R3 pulls the control terminal of the second switch Q2 low to ground level GND, forcing the second switch Q2 to remain off to prevent malfunction.

[0049] The second enabling unit 122 is used to generate a second enabling control signal XON_G for controlling the gate drive circuit. In this embodiment, the second enabling unit 122 includes a second inverter U4, a third switch Q3, a third current-limiting resistor R4, and a second pull-down resistor R5. The third switch Q3 is preferably an N-type metal-oxide-semiconductor field-effect transistor. The input terminal of the second inverter U4 is connected to the output terminal of the comparator U3 to receive a voltage indication signal Pq, and the output terminal of the second inverter U4 is connected to the control terminal of the third switch Q3. The second inverter U4 inverts the received voltage indication signal Pq and transmits it to the control terminal of the third switch Q3. The first pass terminal of the third switch Q3 is connected to the first terminal of the third current-limiting resistor R4 and the discharge enable terminal of the gate drive circuit, and the second pass terminal of the third switch Q3 is grounded to GND. The second terminal of the third current-limiting resistor R4 is connected to the voltage input terminal VIN. The first terminal of the second pull-down resistor R5 is connected to the control terminal of the third switch Q3, and the second terminal of the second pull-down resistor R5 is grounded to GND.

[0050] When the polarity indicator signal Pn is in the second level state (low level, i.e., normal state), if the voltage indicator signal Pq is also in the second level state (low level state, the input voltage Vin has not reached the stable operating threshold), the voltage indicator signal Pq, after being inverted by the second inverter U4, becomes a high level signal and is transmitted to the control terminal of the third switch Q3, controlling the third switch Q3 to conduct. Simultaneously, the conducting third switch Q3 forces the discharge enable terminal of the gate drive circuit to a low level state, i.e., outputs a valid discharge enable command to the gate drive circuit, forcing the gate drive circuit to enter discharge mode (i.e., activate the XON function). In this embodiment, when the gate drive circuit activates the XON function, it outputs a high-level signal to the gates of all TFTs on the display panel, controlling the TFTs to turn on for pre-discharge of the display panel. If the voltage indication signal Pq is in the first level state (when it is in the high level state, the input voltage Vin recovers to the stable working threshold), after being inverted by the second inverter U4, the voltage indication signal Pq becomes a low level signal and is transmitted to the control terminal of the third switch Q3, causing the third switch Q3 to be turned off. The discharge enable terminal of the gate drive circuit is connected to the voltage input terminal VIN through the third current limiting resistor R4. The gate drive circuit exits the discharge enable state, and its output terminal outputs the gate drive voltage normally according to the clock signal.

[0051] The power-on control unit 123 is used to control the second enable unit 122 to be in a power-off state when it receives the polarity indication signal Pn of the first level state, so that the second enable unit 122 outputs a second enable control signal XON_G to prevent the gate drive circuit from entering the discharge enable state, that is, the power supply of the second enable unit 122 is cut off when the control signal of the gate drive unit is abnormal, and the normal output of the gate drive circuit is prohibited.

[0052] In this embodiment, the power-on control unit 123 includes a third inverter U5, a fourth switch Q4, a fifth switch Q5, and a first pull-up resistor R6. The fourth switch Q4 is preferably an N-type metal-oxide-semiconductor field-effect transistor, and the fifth switch Q5 is preferably a P-type metal-oxide-semiconductor field-effect transistor. The input terminal of the third inverter U5 is connected to the output terminal of the NAND gate logic unit U1 to receive a polarity indication signal Pn. The output terminal of the third inverter U5 is connected to the control terminal of the fourth switch Q4. The first pass terminal of the fourth switch Q4 is connected to the control terminal of the fifth switch Q5, and the second pass terminal of the fourth switch Q4 is grounded (GND). The first pass terminal of the fifth switch Q5 is connected to the voltage input terminal VIN, and the second pass terminal of the fifth switch Q5 is connected to the power input terminal of the second inverter U4. The first pull-up resistor R6 is connected between the control terminal of the fifth switch Q5 and the voltage input terminal VIN.

[0053] When the polarity indicator signal Pn is in the first level state (high level, i.e., abnormal state), the third inverter U5 inverts the high-level polarity indicator signal Pn to a low-level signal and outputs it to the control terminal of the fourth switch Q4, causing the fourth switch Q4 to turn off. At this time, the voltage input terminal VIN pulls the control terminal of the fifth switch Q5 to a high level through the first pull-up resistor R6, controlling the fifth switch Q5 to turn off. The turned-off fifth switch Q5 cuts off the power supply to the subsequent second inverter U4. At this time, regardless of the state of the voltage indicator signal Pq, the second inverter U4 has no output. The control terminal of the third switch Q3, which is connected to the output terminal of the second inverter U4, discharges through the second pull-down resistor R5, thereby ensuring that the third switch Q3 is reliably turned off. The discharge enable terminal of the gate drive circuit is connected to the voltage input terminal VIN through the third current-limiting resistor R4, putting the gate drive circuit in a state of discharging disabled, that is, the gate drive circuit cannot enable the XON function.

[0054] When the polarity indicator signal Pn returns to the second level (low level, i.e., normal state), the third inverter U5 inverts the low-level polarity indicator signal Pn to a high-level signal and outputs it to the control terminal of the fourth switch Q4, turning on the fourth switch Q4. The control terminal of the fifth switch Q5 discharges through the turned-on fourth switch Q4, pulling down the voltage at the control terminal of the fifth switch Q5, turning on the fifth switch Q5. The second inverter U4 receives the input voltage Vin provided by the voltage input terminal VIN through the turned-on fifth switch Q5, so that the second inverter U4 returns to its normal operating state, enabling the second enable unit 122 to control whether the gate drive circuit enables the XON function according to the state of the voltage indicator signal Pq.

[0055] The timing detection circuit provided in this embodiment detects the polarity of the control signal of the gate driving unit and the input voltage Vin in real time through the NAND gate logic unit U1 and comparator U3 in the voltage detection module 110. The output control module 120 actively controls the discharge enable state of the source driving circuit and the gate driving circuit. Thus, in an abnormal power-on state, the common voltage VCOM and the source driving circuit output voltage Source can be forcibly pulled to the same potential to eliminate the voltage difference between them, fundamentally eliminating the voltage condition for power-on flashing. Simultaneously, when the operating voltage is abnormal, the gate driving circuit is actively prevented from entering the discharge enable state, thereby preventing the gate driving circuit from entering the working state and ensuring that the TFT is reliably off.

[0056] Based on the same inventive concept as the foregoing embodiments, this application also provides a level conversion device, including the timing detection circuit 100 described in the above embodiments.

[0057] Figure 4 This is a schematic diagram of the level conversion device provided in an embodiment of this application. Figure 4 As shown, the level conversion device provided in this embodiment includes a logic control module 200, a level conversion module 300, a gate pulse modulation module 400, and the timing detection circuit 100 described in the above embodiment.

[0058] Specifically, the logic control module 200 is used to receive the frame start signal STVx, the clock signal CLKx, and the scan signal of the gate driving unit, and output control logic signals. The frame start signal STVx is the start vertical scan signal, the clock signal CLKx is the gate clock signal, and the scan signal of the gate driving unit includes the first scan control voltage V1 and the second scan control voltage V2.

[0059] The level conversion module 300 is used to perform level conversion on the control logic signals and output the frame start output signal STVx_O and the clock output signal CLKx_O.

[0060] The gate pulse modulation module 400 is used to modulate the first scan control voltage V1 and the second scan control voltage V2 to output the first scan output signal V1_O and the second scan output signal V2_O with correct timing.

[0061] The voltage detection module 110 of the timing detection circuit 100 is used to detect the polarity relationship of the first scan control voltage V1 and the second scan control voltage V2, as well as whether the input voltage Vin has reached the stable operating threshold. The output control module 120 outputs the first enable control signal XON_S to the discharge enable terminal of the source drive circuit and the second enable control signal XON_G to the discharge enable terminal of the gate drive circuit according to the detection results.

[0062] In summary, the timing detection circuit and level conversion device provided in this application embodiment realize automatic detection and active intervention of abnormal power-on states through hardware circuitry. Without relying on complex software debugging and external timing controllers, it can ensure that the display panel can obtain a clean and abnormal screen under various startup conditions, significantly reducing the design difficulty of the display device, shortening the product development cycle, and improving the reliability of mass-produced products.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A timing detection circuit, characterized in that, include: The voltage detection module is used to receive a first scan control voltage, a second scan control voltage, and an input voltage, and output a polarity indication signal according to the polarity relationship between the first scan control voltage and the second scan control voltage, and output a voltage indication signal according to the voltage relationship between the input voltage and a preset reference voltage. An output control module, connected to the voltage detection module, is used to generate a first enable control signal based on the polarity indication signal, and to generate a second enable control signal based on the polarity indication signal and the voltage indication signal. The first enable control signal is used to control the output state of the source drive circuit, and the second enable control signal is used to control the output state of the gate drive circuit.

2. The timing detection circuit according to claim 1, characterized in that, The voltage detection module includes a first detection unit and a second detection unit; The first detection unit is used to output a polarity indication signal of a first level state when the polarity of the first scan control voltage and the second scan control voltage are the same, and to output a polarity indication signal of a second level state when the polarity of the first scan control voltage and the second scan control voltage are opposite. The second detection unit is used to output a voltage indication signal at a first level when the input voltage is greater than the reference voltage, and to output a voltage indication signal at a second level when the input voltage is less than the reference voltage.

3. The timing detection circuit according to claim 2, characterized in that, The first detection unit includes a NAND gate logic unit and a first inverter; The first input terminal of the NAND gate logic unit is used to receive the first scan control voltage; The second input terminal of the NAND gate logic unit is connected to the output terminal of the first inverter, and the input terminal of the first inverter is used to receive the second scan control voltage. The output of the NAND gate logic unit is used to output the polarity indication signal.

4. The timing detection circuit according to claim 2, characterized in that, The second detection unit includes a comparator, a first input terminal of which is used to receive the input voltage, a second input terminal of which is used to receive the reference voltage, and an output terminal of which is used to output the voltage indication signal.

5. The timing detection circuit according to claim 2, characterized in that, The output control module includes a first enabling unit, a second enabling unit, and a power-on control unit; The first enabling unit is used to output a first enabling control signal to control the source drive circuit to enter the discharge enabling state when it receives the polarity indication signal of the first level state. The second enabling unit is used to output a second enabling control signal for controlling the gate drive circuit to enter the discharge enabling state when it receives the polarity indication signal of the second level state and the voltage indication signal of the second level state. The power-on control unit is used to control the second enable unit to be in a power-off state when it receives the polarity indication signal of the first level state, so that the second enable unit outputs a second enable control signal to prevent the gate drive circuit from entering the discharge enable state.

6. The timing detection circuit according to claim 5, characterized in that, The first enabling unit includes a first switching transistor and a first current-limiting resistor; The control terminal of the first switch is used to receive the polarity indication signal. The first path terminal of the first switch is connected to the first terminal of the first current limiting resistor and the discharge enable terminal of the source drive circuit. The second path terminal of the first switch is grounded. The second end of the first current-limiting resistor is connected to the voltage input terminal.

7. The timing detection circuit according to claim 6, characterized in that, The first enabling unit further includes a second switching transistor, a second current-limiting resistor, and a first pull-down resistor; The control terminal of the second switch is used to receive the polarity indication signal. The first path terminal of the second switch is connected to the common voltage output terminal through the second current limiting resistor, and the second path terminal of the second switch is grounded. The first end of the first pull-down resistor is connected to the control terminal of the second switch, and the second end of the first pull-down resistor is grounded.

8. The timing detection circuit according to claim 5, characterized in that, The second enabling unit includes a second inverter, a third switching transistor, a second pull-down resistor, and a third current-limiting resistor; The input terminal of the second inverter is used to receive the voltage indication signal, and the output terminal of the second inverter is connected to the control terminal of the third switch. The first path terminal of the third switch is connected to the first terminal of the third current-limiting resistor and the discharge enable terminal of the gate drive circuit, and the second path terminal of the third switch is grounded. The second end of the third current-limiting resistor is connected to the voltage input terminal; The first end of the second pull-down resistor is connected to the control terminal of the third switch, and the second end of the second pull-down resistor is grounded.

9. The timing detection circuit according to claim 8, characterized in that, The power-on control unit includes a third inverter, a fourth switch, a fifth switch, and a first pull-up resistor; The input terminal of the third inverter is used to receive the polarity indication signal, and the output terminal of the third inverter is connected to the control terminal of the fourth switch. The first path terminal of the fourth switch is connected to the control terminal of the fifth switch, and the second path terminal of the fourth switch is grounded. The first path terminal of the fifth switch is connected to the voltage input terminal, and the second path terminal of the fifth switch is connected to the power input terminal of the second inverter. The first pull-up resistor is connected between the control terminal of the fifth switch and the voltage input terminal.

10. A level conversion device, characterized in that, Includes the timing detection circuit as described in any one of claims 1 to 9.

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