An information processing method, device, equipment, computer storage medium and computer program product

Abstract

This application discloses an information processing method, the method comprising: acquiring a stream of instructions to be processed and a result identifier of the output result of the instructions in the stream of instructions to be processed; determining the memory space required for the output result; adding modifier information to the result identifier to obtain a processed result identifier; and generating a target instruction stream based on the processed result identifier, the memory space size, and the stream of instructions to be processed. This application also discloses an information processing apparatus, device, computer storage medium, and computer program product.

Description

Technical Field

[0001] This application relates to information processing technology in the field of communications, and more particularly to an information processing method, apparatus, device, computer storage medium, and computer program product. Background Technology

[0002] With the development of deep learning neural network technology, intelligent computing is rapidly becoming widespread in all aspects of production and daily life. However, due to the deep layers and complex structure of deep learning networks, large-scale network structures generate numerous operators, resulting in enormous computational scale and time consumption. Currently, deep learning neural networks can be unfolded into a computational graph structure during the compilation phase. Generally, artificial intelligence (AI) compilation frameworks optimize the generated computational graph through a compiler front-end to obtain an optimized intermediate representation. This intermediate representation is then used to complete back-end optimization at the hardware device layer, ultimately generating hardware-executable machine code. Furthermore, the demands of ultra-large-scale computing on intelligent computing centers have led to the emergence of hybrid heterogeneous systems primarily composed of various heterogeneous acceleration chips. Several application programming interface (API)-based solutions have been proposed for hybrid heterogeneous systems. However, both traditional AI compilation optimization schemes and API-based solutions for hybrid heterogeneous systems have shortcomings and are unlikely to meet the demands of the future trend of widespread adoption of hybrid heterogeneous acceleration chips in large-scale intelligent computing centers.

[0003] Based on the aforementioned issues, SPIR-V is currently the intermediate representation (or virtual instruction set) shared by many Khronos projects. Using SPIR-V as a virtual instruction set for program compilation allows for compilation using front-ends of general-purpose languages. Furthermore, SPIR-V's hardware independence offers advantages in enabling various languages ​​and front-end frameworks to run on different hardware architectures, improving kernel reliability and cross-platform portability. However, deep learning neural networks have deep layers, and when unfolded into a computational graph, they involve numerous operator operations, generating a large number of common temporary variables. Since the parameter operations of each layer in a neural network depend on the output of the previous layer, and the input parameters and output results of operator instructions are high-dimensional tensor data, this consumes a significant amount of memory, leading to resource waste and impacting execution efficiency. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide an information processing method, apparatus, device, computer storage medium, and computer program product, which solves the problem in related technologies that instruction information occupies a large amount of memory space during processing, avoids waste of resources, and improves execution efficiency.

[0005] To achieve the above objectives, the technical solution of this application embodiment is implemented as follows:

[0006] An information processing method, the method being applied to a first device, comprising:

[0007] Obtain the result identifier of the instruction stream to be processed and the output result of the instructions in the instruction stream to be processed;

[0008] Determine the amount of memory space required for the output;

[0009] Add modifier information to the result identifier to obtain the processed result identifier;

[0010] Based on the processed result identifier, the memory space size, and the instruction stream to be processed, a target instruction stream is generated.

[0011] In the above scheme, determining the memory space required for the output result includes:

[0012] Determine the shape and data type of the input data corresponding to the instruction;

[0013] The memory space size is calculated based on the shape, the data type, and the operator type corresponding to the instruction.

[0014] In the above scheme, adding modification information to the result identifier to obtain the processed result identifier includes:

[0015] Generate a first instruction for adding modifier information to the result identifier;

[0016] Based on the first instruction, modifying information is added to the result identifier to obtain the processed result identifier.

[0017] In the above scheme, generating the target instruction stream based on the processed result identifier, the memory space size, and the instruction stream to be processed includes:

[0018] Determine the pointer type of the second device;

[0019] Generate a second instruction to indicate the pointer type, the processed result identifier, the memory space size and output data, and the mapping relationship with the modification information;

[0020] The target instruction stream is generated based on the first instruction, the second instruction, and the instruction stream to be processed.

[0021] An information processing method, applied to a second device, comprising:

[0022] Obtain the target instruction stream; wherein, the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device adding modification information to the result identifier of the output result;

[0023] Based on the target instruction stream, a first correspondence between the result identifier and the modification information is determined;

[0024] Based on the target instruction stream, a second correspondence between the modification information and the pointer variable is determined, and the target memory space corresponding to the output result is determined;

[0025] Based on the first and second correspondences, a third correspondence between the result identifier and the pointer variable is determined;

[0026] The instruction is executed based on the third correspondence, the result identifier, and the target memory space.

[0027] In the above scheme, determining the first correspondence between the result identifier and the modification information based on the target instruction stream includes:

[0028] Determine the first instruction in the target instruction stream;

[0029] Based on the first instruction, a first correspondence is determined between the result identifier and the modification information.

[0030] In the above scheme, determining the second correspondence between the modification information and the pointer variable based on the target instruction stream, and determining the target memory space corresponding to the output result, includes:

[0031] Based on the second instruction in the target instruction stream, determine the modification information, pointer type, and the memory space required for the output result;

[0032] Define the pointer variable based on the pointer type;

[0033] Based on the second instruction, the second correspondence between the modification information and the pointer variable is determined;

[0034] The target memory space is determined based on the memory space size;

[0035] Accordingly, the method further includes:

[0036] Establish the mapping relationship between the pointer variable and the target memory space.

[0037] In the above scheme, executing the instruction based on the third correspondence, the result identifier, and the target memory space includes:

[0038] Based on the third correspondence and the result identifier, the target pointer variable is determined;

[0039] The output result is obtained from the target memory space based on the target pointer variable, and the instruction is executed based on the output result.

[0040] A first information processing apparatus, comprising:

[0041] The first acquisition unit is used to acquire the instruction stream to be processed and the result identifier of the output result of the instruction in the instruction stream to be processed;

[0042] The first determining unit is used to determine the memory space required for the output result;

[0043] The first processing unit is used to add modification information to the result identifier to obtain the processed result identifier;

[0044] The generation unit is used to generate a target instruction stream based on the processed result identifier, the memory space size, and the instruction stream to be processed.

[0045] A second information processing device, comprising:

[0046] The second acquisition unit is used to acquire the target instruction stream; wherein, the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device adding modification information to the result identifier of the output result;

[0047] The second determining unit is used to determine a first correspondence between the result identifier and the modification information based on the target instruction stream;

[0048] The second determining unit is further configured to determine a second correspondence between the modification information and the pointer variable based on the target instruction stream, and to determine the target memory space corresponding to the output result;

[0049] The second determining unit is further configured to determine a third correspondence between the result identifier and the pointer variable based on the first correspondence and the second correspondence;

[0050] The second processing unit is used to execute the instructions based on the third correspondence, the result identifier, and the target memory space.

[0051] A first device, the first device comprising: a first processor, a first memory, and a first communication bus;

[0052] The first communication bus is used to establish a communication connection between the first processor and the first memory;

[0053] The first processor is used to execute the information processing program in the first memory to implement the steps of the above-described information processing method.

[0054] A second device, the second device comprising: a second processor, a second memory, and a second communication bus;

[0055] The second communication bus is used to establish a communication connection between the second processor and the second memory;

[0056] The second processor is used to execute the information processing program in the second memory to implement the steps of the above-described information processing method.

[0057] A computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the steps of the information processing method described above.

[0058] A computer program product comprising a computer program that, when executed by a processor, implements the above-described method.

[0059] The information processing method, apparatus, device, computer storage medium, and computer program product provided in the embodiments of this application can obtain the result identifiers of the output results of the instructions to be processed and the output results of the instructions in the instruction stream, determine the memory space required for the output results, add modification information to the result identifiers to obtain the processed result identifiers, and finally generate a target instruction stream based on the processed result identifiers, the memory space size, and the instruction stream to be processed. In this way, the result identifiers of the output results of the instructions in the instruction stream can be determined, and the final instruction stream can be generated according to the processed result identifiers, the memory space size, and the instruction stream. The generated final instruction stream does not include the output results of the instructions, which greatly reduces the memory space requirement and solves the problem in related technologies where instruction information occupies a large amount of memory space during processing, thus avoiding resource waste. Furthermore, the addition of modification information to each result identifier ensures the uniqueness of the result identifier corresponding to the output result of each instruction, ensuring that subsequent instructions can better find the output results through the result identifiers, thereby improving execution efficiency. Attached Figure Description

[0060] Figure 1 A flowchart illustrating an information processing method provided for an embodiment of this application;

[0061] Figure 2 A schematic diagram illustrating instruction optimization corresponding to an information processing method provided in an embodiment of this application;

[0062] Figure 3 A flowchart illustrating another information processing method provided for an embodiment of this application;

[0063] Figure 4 A schematic diagram of the structure of a first information processing device provided for an embodiment of this application;

[0064] Figure 5 A schematic diagram of the structure of a second information processing device provided for an embodiment of this application;

[0065] Figure 6 A schematic diagram of the structure of a first device provided for an embodiment of this application;

[0066] Figure 7 This is a schematic diagram of the structure of a second device provided for an embodiment of this application. Detailed Implementation

[0067] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0068] It should be understood that the phrases "embodiments of this application" or "foreign embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "embodiments of this application" or "in the foreign embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0069] Unless otherwise specified, any step in the embodiments of this application performed by the electronic device may be executed by the processor of the electronic device. It is also worth noting that the embodiments of this application do not limit the order in which the electronic device performs the following steps. Furthermore, the methods used to process data in different embodiments may be the same or different methods. It should also be noted that any step in the embodiments of this application can be executed independently by the electronic device; that is, when the electronic device performs any step in the following embodiments, it may not depend on the execution of other steps.

[0070] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0071] This application provides an information processing method, which can be applied to a first device, as described above. Figure 1 As shown, the method may include the following steps:

[0072] Step 101: Obtain the instruction stream to be processed and the result identifier of the output result of the instruction in the instruction stream to be processed.

[0073] In the embodiments of this application, the instruction stream to be processed can refer to various instruction streams (i.e., instruction sets) that need to be compiled and executed; in one feasible implementation, the instruction stream to be processed can be the instruction stream in the model application. Furthermore, the output result can refer to the operation result corresponding to each instruction in the instruction stream to be processed, and can be the output result of the operator instruction recorded during the traversal of the instruction stream in the model application; and the result identifier can refer to an identifier used to uniquely identify the output result of the instruction, which can be represented by ResultId.

[0074] Specifically, it can be done through, for example Figure 2 The operator instruction analysis module shown in the diagram first compiles the computation graph part of the model application into a SPIR-V raw instruction stream during the compilation stage. This instruction stream sequentially completes the operation of all operators in the computation graph. Each operator instruction copies the operation result from the first device to the memory of the second device. When the next instruction is executed, the result is copied from the memory of the second device to the first device as a parameter.

[0075] Step 102: Determine the amount of memory space required for the output results.

[0076] The memory space size refers to the amount of memory space required to store the output results (i.e., the operation results) of the instructions in the instruction stream to be processed. Specifically, this memory space size can be determined by the first device based on the attribute information of the input data corresponding to the instruction and the attribute information of the operator corresponding to the instruction.

[0077] Step 103: Add modifier information to the result identifier to obtain the processed result identifier.

[0078] The modification information refers to the modification content used to make the result identifier unique. In this way, after adding the modification information to the result identifier, the processed result identifier corresponding to the output result of each instruction is unique, which makes it convenient to obtain accurate output results later.

[0079] Step 104: Generate the target instruction stream based on the processed result identifier, memory space size, and instruction stream to be processed.

[0080] Specifically, the process can first generate a stream of instructions to be converted based on the processed result identifier, memory space size, and the instruction stream to be processed, and then perform format conversion on the instruction stream to be converted to obtain the target instruction stream; more specifically, the corresponding instructions can be generated based on the processed result identifier and memory space size, and the instruction stream to be converted can be generated based on the corresponding instructions and the instruction stream to be processed.

[0081] Based on the foregoing embodiments, in other embodiments of this application, step 102 can be implemented in the following ways:

[0082] A1. Determine the shape and data type of the input data corresponding to the instruction.

[0083] The shape and data type of the input data can refer to what the first device obtains during the process of traversing the instructions in the instruction stream to be processed. Specifically, this can be achieved through... Figure 2 The operator instruction analysis module shown records the shape of the input data (i.e., Tensor data) and the data element type of the Tensor data during the traversal of the SPIR-V raw instruction stream.

[0084] A2. Calculate the memory space size based on the shape, data type, and operator type corresponding to the instruction.

[0085] In the embodiments of this application, the operator type corresponding to the instruction in the instruction stream to be processed can be determined, and then the memory space size TensorSize(ResultId) occupied by the output result (i.e., the output Tensor) pointed to by ResultId can be calculated based on the shape of the input Tensor, the data element Type information and the operator type.

[0086] In other embodiments of this application, step 103 described above can be implemented in the following ways:

[0087] B1. Generate the first instruction to add decorative information to the result identifier.

[0088] The first instruction can be Figure 2The instruction generation module shown in the figure generates the instruction; in one possible implementation, the first instruction may refer to OpDecorateId, and the decoration information may be represented by DecorationId.

[0089] B2. Based on the first instruction, add modifier information to the result identifier to obtain the processed result identifier.

[0090] The first instruction can be used to add decorative information to the result identifier; specifically, the processed result identifier can be obtained using the following instruction format: OpDecorateId ResultId TensorAddrHintId DecorationId. The mapping relationship between the result identifier and the decorative information is also defined.

[0091] In other embodiments of this application, step 104 described above can be implemented in the following ways:

[0092] C1. Determine the pointer type of the second device.

[0093] The pointer type of the second device can refer to the memory pointer type in the second device; it should be noted that the memory pointer type can be represented by DevicePtrType.

[0094] C2. Generate a second instruction that indicates the pointer type, the identifier of the processed result, the size of the memory space and the output data, and the mapping relationship with the modification information.

[0095] Among them, it can be achieved through Figure 2 The instruction generation module shown generates a second instruction based on the pointer type, the processed result identifier, the memory space size, and the output result. Specifically, the second instruction OpSpecConstant can be generated using the following instruction format: DecorationId = OpSpecConstant DevicePtrType TensorSize(ResultId). It should be noted that this second instruction also defines the mapping relationship between OpSpecConstant, DevicePtrType, TensorSize(ResultId), the output Tensor, and the decoration information.

[0096] C3. Generate the target instruction stream based on the first instruction, the second instruction, and the instruction stream to be processed.

[0097] In this embodiment, the first device can package the first instruction, the second instruction, and the instruction stream to be processed to generate the final target instruction stream; wherein, the target instruction stream can be the final SPIR-V instruction stream; the first instruction, the second instruction, and the instruction stream to be processed, after being combined, can be called the optimized SPIR-V instruction. Furthermore, the instruction generation module can generate the SPIR-VOpDecorateId instruction and the OpSpecConstant instruction based on the analysis results of the operator instruction analysis module, providing memory reuse address information for the SPIR-V instruction interpretation and execution stage. In addition, the target instruction stream can be in the form of binary code that can be executed across architectures on the device side.

[0098] It should be noted that this application reduces memory resource consumption and saves a significant amount of time spent copying Tensor data by analyzing and optimizing SPIR-V instructions, thereby improving the inference and training efficiency of model applications.

[0099] The information processing method provided in the embodiments of this application can determine the result identifier of the output result of the instruction in the instruction stream, and generate the final instruction stream based on the processed result identifier, the memory space size, and the instruction stream. The generated final instruction stream does not include the output result of the instruction, which greatly reduces the demand for memory space. This solves the problem in related technologies where instruction information occupies a large amount of memory space during processing, and avoids waste of resources. Furthermore, the addition of modifier information to the result identifier ensures the uniqueness of the result identifier corresponding to the output result of each instruction, ensuring that subsequent instructions can better find the output result through the result identifier, thus improving execution efficiency.

[0100] Based on the foregoing embodiments, embodiments of this application provide an information processing method that can be applied to a second device, as described above. Figure 3 As shown, the method includes the following steps:

[0101] Step 201: Obtain the target instruction stream.

[0102] The target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device after adding modification information to the result identifier of the output result.

[0103] Step 202: Based on the target instruction stream, determine the first correspondence between the result identifier and the modification information.

[0104] The second device can parse the target instruction stream to obtain the first correspondence between the result identifier and the modification information; specifically, it can be done through... Figure 2The instruction information initialization module shown determines the first correspondence; and, the first correspondence can be determined based on the first instruction in the target instruction stream. It should be noted that the first correspondence can be represented using ResultIdToDecIdMap.

[0105] Step 203: Determine the second correspondence between the modification information and the pointer variable based on the target instruction stream, and determine the target memory space corresponding to the output result.

[0106] The second device can parse the target instruction stream to obtain a second correspondence between the modification information and the pointer variables; specifically, it can be done through... Figure 2 The instruction information initialization module shown determines the first correspondence; and the second correspondence can be determined based on the second instruction in the target instruction stream. It should be noted that the second correspondence can be represented using DecIdToDevPtrMap.

[0107] Step 204: Based on the first and second correspondences, determine the third correspondence between the result identifier and the pointer variable.

[0108] In this embodiment of the application, the first correspondence ResultIdToDecIdMap and the second correspondence DecIdToDevPtrMap can be analyzed to construct a third correspondence between the result identifier ResultId and the pointer variable DevicePtr. It should be noted that the third correspondence can be represented by ResultIdToDevPtrMap.

[0109] Step 205: Execute instructions based on the third correspondence, result identifier, and target memory space.

[0110] In the embodiments of this application, the target pointer variable can be determined according to the third correspondence and the result identifier, and the instructions in the instruction stream to be processed can be executed according to the target pointer variable and the target memory space, that is, the SPIR-V instruction can be executed.

[0111] Based on the foregoing embodiments, in other embodiments of this application, step 202 can be implemented in the following ways:

[0112] D1. Determine the first instruction in the target instruction stream.

[0113] The second device can directly read the OpDecorateId instruction from the final SPIR-V instruction stream (i.e., the target instruction stream) through the instruction information initialization module.

[0114] D2. Determine the first correspondence between the result identifier and the modification information based on the first instruction.

[0115] The instruction information initialization module can construct a mapping table ResultIdToDecIdMap from the ResultId identifier to the Decoration information DecorationId by reading the OpDecorateId instruction, thus determining the first correspondence.

[0116] In other embodiments of this application, step 203 described above can be implemented in the following ways:

[0117] E1. Based on the second instruction in the target instruction stream, determine the modification information, pointer type, and the memory space required for the output result.

[0118] The second device can read the OpSpecConstant instruction (i.e., the second instruction) in the final SPIR-V instruction stream (i.e., the target instruction stream) through the instruction information initialization module, and determine the decoration information DecorationId, the pointer type DevicePtrType, and the memory space size TensorSize (ResultId) required for the output result through the read OpSpecConstant instruction.

[0119] E2. Define pointer variables based on pointer types.

[0120] Specifically, the instruction information initialization module defines a pointer variable DevicePtr of type DevicePtrType.

[0121] E3. Based on the second instruction, determine the second correspondence between the modification information and the pointer variable.

[0122] Specifically, the instruction information initialization module constructs a mapping relationship DecIdToDevPtrMap from the decoration information DecorationId to the pointer variable DevicePtr by reading the OpSpecConstant instruction, thus determining the second correspondence.

[0123] E4. Determine the target memory space based on the size of the memory space, and establish a mapping relationship between pointer variables and the target memory space.

[0124] It should be noted that the runtime device memory allocation function is called to request a memory space of size TensorSize(ResultId); at the same time, the return value is assigned to DevicePtr to determine the mapping relationship between the pointer variable and the target memory space.

[0125] In other embodiments of this application, step 205 described above can be implemented in the following ways:

[0126] F1. Based on the third correspondence and the result identifier, determine the target pointer variable.

[0127] When the SPIR-V interpreter interprets and executes operator computation instructions, the instruction format is as follows: ResultId = OpTensorCompute % ParamId_1 % ParamId_2...; In the above instruction, OpTensorCompute is an extended representation of the SPIR-V instruction, indicating the execution of operator computation operations. ResultId is the result ID value, and ParamId is the parameter ID value. ParamId needs to be defined in the preceding instruction. Furthermore, Figure 2 The address information parsing module shown reads the instruction parameter list to obtain all ParamIds. Based on the third correspondence ResultIdToDevPtrMap, it searches by the result identifier ParamId to obtain the actual address of the instruction parameter (i.e., the target pointer variable). This address is then returned to the interpreter as the instruction parameter for transmission. It should be noted that if no result is found when searching for ParamId, the corresponding input parameter still needs to be copied from the host memory to complete the calculation.

[0128] It should be noted that pointers are typically 64-bit or 32-bit unsigned integers, which saves a significant amount of memory compared to the massive data size of Tensors, and also eliminates the time spent copying data. After an instruction is executed, the ResultPtrMap is searched using ResultId as the key to obtain the pointer information of the operator result. Finally, the result is written to this address as an operand for subsequent instructions.

[0129] F2. Obtain the output result from the target memory space based on the target pointer variable, and execute the instruction based on the output result.

[0130] The second device can retrieve the actual output from the corresponding target memory space based on the target pointer variable, and use this output as the input parameter for the instruction to execute it. It should be noted that all instructions in the SPIR-V instruction stream are executed using this method. Furthermore, after all instructions in the SPIR-V instruction stream have been executed, the memory release function can be called to return the allocated memory resources to the operating system based on the memory allocation record.

[0131] It should be noted that during the SPIR-V interpreter's interpretation and execution of operator computation instructions, the address information parsing module parses the instruction input parameters based on the mapping between ResultId and shared memory space, passing parameters using pointers instead of Tensor variables; simultaneously, it parses the instruction results and writes them to the device memory address, avoiding copying to host memory. Furthermore, this application's solution has the advantage of cross-architecture across heterogeneous platforms, allowing application to different hardware acceleration platforms without requiring modification or recompilation of the model application's source code, thus improving project development and deployment efficiency.

[0132] The information processing method provided in the embodiments of this application can determine a third correspondence between the result identifier and the target pointer variable based on a first correspondence between the determined result identifier and the modification information, and a second correspondence between the modification information and the target pointer variable. Then, it executes the instructions in the instruction stream to be processed based on the third correspondence, the result identifier, and the target memory space. This greatly reduces the memory space requirement, thereby solving the problem in related technologies where instruction information occupies a large amount of memory during processing, and avoiding resource waste. Furthermore, the addition of modification information to the result identifier ensures the uniqueness of the result identifier corresponding to the output result of each instruction, guaranteeing successful execution of the instruction and improving execution efficiency.

[0133] Based on the foregoing embodiments, embodiments of this application provide a first information processing apparatus, which can be applied to... Figure 1 In the information processing method provided in the corresponding embodiment, refer to Figure 4 As shown, the first information processing device may include: a first acquisition unit 31, a first determination unit 32, a first processing unit 33, and a generation unit 34, wherein:

[0134] The first acquisition unit 31 is used to acquire the instruction stream to be processed and the result identifier of the output result of the instruction in the instruction stream to be processed;

[0135] The first determining unit 32 is used to determine the size of the memory space required for the output result;

[0136] The first processing unit 33 is also used to add modifier information to the result identifier to obtain the processed result identifier;

[0137] The generation unit 34 is used to generate a target instruction stream based on the processed result identifier, memory space size, and instruction stream to be processed.

[0138] In other embodiments of this application, the first determining unit 32 is further configured to perform the following steps:

[0139] Determine the shape and data type of the input data corresponding to the instruction;

[0140] The memory space size is calculated based on the shape, data type, and operator type corresponding to the instruction.

[0141] In other embodiments of this application, the first processing unit 33 is further configured to perform the following steps:

[0142] Generate the first instruction for adding decorative information to the result identifier;

[0143] Based on the first instruction, modifying information is added to the result identifier to obtain the processed result identifier.

[0144] In other embodiments of this application, the generation unit 34 is further configured to perform the following steps:

[0145] Determine the pointer type of the second device;

[0146] Generate a second instruction to indicate the pointer type, the identifier of the processed result, the size of the memory space and the output data, and the mapping relationship with the modification information;

[0147] Based on the first instruction, the second instruction, and the instruction stream to be processed, the target instruction stream is generated.

[0148] It should be noted that a detailed explanation of the steps performed by each unit can be found in [reference needed]. Figure 1 The information processing methods provided in the corresponding embodiments will not be described in detail here.

[0149] The first information processing apparatus provided in the embodiments of this application can determine the result identifier of the output result of the instruction in the instruction stream, and generate the final instruction stream based on the processed result identifier, the memory space size, and the instruction stream. The generated final instruction stream does not include the output result of the instruction, which greatly reduces the demand for memory space and solves the problem in related technologies where instruction information occupies a large amount of memory space during processing, thus avoiding waste of resources. In addition, the result identifier is modified with additional information, which ensures the uniqueness of the result identifier corresponding to the output result of each instruction, ensuring that subsequent instructions can better find the output result through the result identifier, thereby improving execution efficiency.

[0150] Based on the foregoing embodiments, embodiments of this application provide a second information processing apparatus, which can be applied to... Figure 3 In the information processing method provided in the corresponding embodiment, refer to Figure 5 As shown, the second information processing device may include: a second acquisition unit 41, a second determination unit 42, and a second processing unit 43, wherein:

[0151] The second acquisition unit 41 is used to acquire the target instruction stream; wherein, the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instruction in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device after adding modification information to the result identifier of the output result;

[0152] The second determining unit 42 is used to determine the first correspondence between the result identifier and the modification information based on the target instruction stream;

[0153] The second determining unit 42 is also used to determine the second correspondence between the modification information and the pointer variable based on the target instruction stream, and to determine the target memory space corresponding to the output result;

[0154] The second determining unit 42 is also used to determine a third correspondence between the result identifier and the pointer variable based on the first correspondence and the second correspondence;

[0155] The second processing unit 43 is used to execute instructions based on the third correspondence, the result identifier, and the target memory space.

[0156] In other embodiments of this application, the second determining unit 42 is further configured to perform the following steps:

[0157] Determine the first instruction in the target instruction stream;

[0158] The first correspondence between the result identifier and the modification information is determined based on the first instruction.

[0159] In other embodiments of this application, the second determining unit 42 is further configured to perform the following steps:

[0160] Based on the second instruction in the target instruction stream, determine the modification information, pointer type, and the memory space required for the output result;

[0161] Define pointer variables based on pointer types;

[0162] Based on the second instruction, a second correspondence between the modification information and the pointer variable is determined;

[0163] The target memory space is determined based on the size of the memory space.

[0164] In other embodiments of this application, the second determining unit 42 is also used to establish a mapping relationship between pointer variables and target memory space.

[0165] In other embodiments of this application, the second processing unit 43 is further configured to perform the following steps:

[0166] Based on the third correspondence and the result identifier, the target pointer variable is determined;

[0167] The output is obtained from the target memory space based on the target pointer variable, and the instruction is executed based on the output.

[0168] It should be noted that a detailed explanation of the steps performed by each unit can be found in [reference needed]. Figure 3 The information processing methods provided in the corresponding embodiments will not be described in detail here.

[0169] The second information processing device provided in the embodiments of this application can determine a third correspondence between the result identifier and the target pointer variable based on a first correspondence between the determined result identifier and the modification information and a second correspondence between the modification information and the target pointer variable. It then executes the instructions in the instruction stream to be processed based on the third correspondence, the result identifier, and the target memory space. This greatly reduces the memory space requirement, thereby solving the problem in related technologies where instruction information occupies a large amount of memory during processing, and avoiding resource waste. Furthermore, the addition of modification information to the result identifier ensures the uniqueness of the result identifier corresponding to the output result of each instruction, guaranteeing successful execution of the instruction and improving execution efficiency.

[0170] Based on the foregoing embodiments, embodiments of this application provide a first device that can be applied to... Figure 1 In the information processing method provided in the corresponding embodiment, refer to Figure 6 As shown, the first device 5 may include: a first processor 51, a first memory 52, and a first communication bus 53, wherein:

[0171] The first communication bus 53 is used to realize the communication connection between the first processor 51 and the first memory 52;

[0172] The first processor 51 is used to execute the information processing program in the first memory 52 to perform the following steps:

[0173] Acquire the result identifier of the instruction stream to be processed and the output result of the instructions in the instruction stream;

[0174] Determine the amount of memory required for the output;

[0175] Add descriptive information to the result identifier to obtain the processed result identifier;

[0176] The target instruction stream is generated based on the processed result identifier, memory space size, and instruction stream to be processed.

[0177] In other embodiments of this application, the first processor 51 is used to determine the memory space required for the output result of the information processing program in the first memory 52, in order to implement the following steps:

[0178] Determine the shape and data type of the input data corresponding to the instruction;

[0179] The memory space size is calculated based on the shape, data type, and operator type corresponding to the instruction.

[0180] In other embodiments of this application, the first processor 51 is used to execute the information processing program in the first memory 52 to add modification information to the result identifier to obtain the processed result identifier, so as to implement the following steps:

[0181] Generate the first instruction for adding decorative information to the result identifier;

[0182] Based on the first instruction, modifying information is added to the result identifier to obtain the processed result identifier.

[0183] In other embodiments of this application, the first processor 51 is used to execute the information processing program in the first memory 52 to generate a target instruction stream based on the processed result identifier, memory space size, and instruction stream to be processed, in order to implement the following steps:

[0184] Determine the pointer type of the second device;

[0185] Generate a second instruction to indicate the pointer type, the identifier of the processed result, the size of the memory space and the output data, and the mapping relationship with the modification information;

[0186] Based on the first instruction, the second instruction, and the instruction stream to be processed, the target instruction stream is generated.

[0187] It should be noted that a detailed description of the steps performed by the first processor can be found in [reference needed]. Figure 1 The information processing methods provided in the corresponding embodiments will not be described in detail here.

[0188] The first device provided in the embodiments of this application can determine the result identifier of the output result of the instruction in the instruction stream, and generate the final instruction stream based on the processed result identifier, the memory space size, and the instruction stream. The generated final instruction stream does not include the output result of the instruction, which greatly reduces the demand for memory space and solves the problem in related technologies where instruction information occupies a large amount of memory space during processing, thus avoiding waste of resources. In addition, the result identifier is modified with additional information, which ensures the uniqueness of the result identifier corresponding to the output result of each instruction, ensuring that subsequent instructions can better find the output result through the result identifier, thereby improving execution efficiency.

[0189] Based on the foregoing embodiments, embodiments of this application provide a second device that can be applied to... Figure 3 In the information processing method provided in the corresponding embodiment, refer to Figure 7 As shown, the second device 6 may include: a second processor 61, a second memory 62, and a second communication bus 63, wherein:

[0190] The second communication bus 63 is used to realize the communication connection between the second processor 61 and the second memory 62;

[0191] The second processor 61 is used to execute the information processing program in the second memory 62 to perform the following steps:

[0192] Obtain the target instruction stream; wherein, the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device after adding modification information to the result identifier of the output result;

[0193] Based on the target instruction stream, determine the first correspondence between the result identifier and the modification information;

[0194] The second correspondence between the modifier information and the pointer variable is determined based on the target instruction stream, and the target memory space corresponding to the output result is determined.

[0195] Based on the first and second correspondences, determine the third correspondence between the result identifier and the pointer variable;

[0196] Based on the third correspondence, the result identifier, and the target memory space, the instructions are executed.

[0197] In other embodiments of this application, the second processor 61 is used to execute the target instruction stream of the information processing program in the second memory 62 to determine the first correspondence between the result identifier and the modification information, so as to implement the following steps:

[0198] Determine the first instruction in the target instruction stream;

[0199] The first correspondence between the result identifier and the modification information is determined based on the first instruction.

[0200] In other embodiments of this application, the second processor 61 is used to execute the information processing program in the second memory 62 to determine the second correspondence between the modification information and the pointer variable based on the target instruction stream, and to determine the target memory space corresponding to the output result, so as to implement the following steps:

[0201] Based on the second instruction in the target instruction stream, determine the modification information, pointer type, and the memory space required for the output result;

[0202] Define pointer variables based on pointer types;

[0203] Based on the second instruction, a second correspondence between the modification information and the pointer variable is determined;

[0204] The target memory space is determined based on the size of the memory space.

[0205] In other embodiments of this application, the second processor 61 is used to execute the information processing program in the second memory 62, and can also implement the following steps:

[0206] Establish a mapping relationship between pointer variables and target memory spaces.

[0207] In other embodiments of this application, the second processor 61 is used to execute instructions based on the third correspondence, result identifier, and target memory space of the information processing program in the second memory 62 to achieve the following steps:

[0208] Based on the third correspondence and the result identifier, the target pointer variable is determined;

[0209] The output is obtained from the target memory space based on the target pointer variable, and the instruction is executed based on the output.

[0210] It should be noted that a detailed description of the steps performed by the second processor can be found in [reference needed]. Figure 3 The information processing methods provided in the corresponding embodiments will not be described in detail here.

[0211] The second device provided in the embodiments of this application can determine a third correspondence between the result identifier and the target pointer variable based on a first correspondence between the determined result identifier and the modification information, and a second correspondence between the modification information and the target pointer variable. It then executes the instructions in the instruction stream to be processed based on the third correspondence, the result identifier, and the target memory space. This greatly reduces the memory space requirement, thereby solving the problem in related technologies where instruction information occupies a large amount of memory during processing, and avoiding resource waste. Furthermore, the addition of modification information to the result identifier ensures the uniqueness of the result identifier corresponding to the output result of each instruction, guaranteeing successful execution of the instruction and improving execution efficiency.

[0212] Based on the foregoing embodiments, embodiments of this application provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement... Figure 1 and Figure 3 The corresponding embodiments provide the steps of the information processing method.

[0213] Based on the foregoing embodiments, embodiments of this application provide a computer program product, including a computer program that can be executed by a first processor 51 and a second processor 61 to perform... Figure 1 and Figure 3 The corresponding embodiments provide the steps of the information processing method.

[0214] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0215] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0216] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0217] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0218] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An information processing method, characterized in that, The method is applied to a first device and includes: Obtain the result identifier of the instruction stream to be processed and the output result of the instructions in the instruction stream to be processed; Determine the amount of memory space required for the output; Add modifier information to the result identifier to obtain the processed result identifier; Based on the processed result identifier, the memory space size, and the instruction stream to be processed, a target instruction stream is generated.

2. The method according to claim 1, characterized in that, Determining the memory space required for the output result includes: Determine the shape and data type of the input data corresponding to the instruction; The memory space size is calculated based on the shape, the data type, and the operator type corresponding to the instruction.

3. The method according to claim 1, characterized in that, The step of adding modifier information to the result identifier to obtain the processed result identifier includes: Generate a first instruction for adding modifier information to the result identifier; Based on the first instruction, modifying information is added to the result identifier to obtain the processed result identifier.

4. The method according to claim 3, characterized in that, The step of generating a target instruction stream based on the processed result identifier, the memory space size, and the instruction stream to be processed includes: Determine the pointer type of the second device; Generate a second instruction to indicate the pointer type, the processed result identifier, the memory space size and output data, and the mapping relationship with the modification information; The target instruction stream is generated based on the first instruction, the second instruction, and the instruction stream to be processed.

5. An information processing method, characterized in that, The method is applied to a second device, including: Obtain the target instruction stream; wherein the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device adding modification information to the result identifier of the output result; Based on the target instruction stream, a first correspondence between the result identifier and the modification information is determined; Based on the target instruction stream, a second correspondence between the modification information and the pointer variable is determined, and the target memory space corresponding to the output result is determined; Based on the first and second correspondences, a third correspondence between the result identifier and the pointer variable is determined; The instruction is executed based on the third correspondence, the result identifier, and the target memory space.

6. The method according to claim 5, characterized in that, Determining the first correspondence between the result identifier and the modification information based on the target instruction stream includes: Determine the first instruction in the target instruction stream; Based on the first instruction, a first correspondence is determined between the result identifier and the modification information.

7. The method according to claim 5, characterized in that, The step of determining the second correspondence between the modification information and the pointer variable based on the target instruction stream, and determining the target memory space corresponding to the output result, includes: Based on the second instruction in the target instruction stream, determine the modification information, pointer type, and the memory space required for the output result; Define the pointer variable based on the pointer type; Based on the second instruction, the second correspondence between the modification information and the pointer variable is determined; The target memory space is determined based on the memory space size; Accordingly, the method further includes: Establish the mapping relationship between the pointer variable and the target memory space.

8. The method according to claim 7, characterized in that, The step of executing the instruction based on the third correspondence, the result identifier, and the target memory space includes: Based on the third correspondence and the result identifier, the target pointer variable is determined; The output result is obtained from the target memory space based on the target pointer variable, and the instruction is executed based on the output result.

9. A first information processing device, characterized in that, include: The first acquisition unit is used to acquire the instruction stream to be processed and the result identifier of the output result of the instruction in the instruction stream to be processed; The first determining unit is used to determine the memory space required for the output result; The first processing unit is used to add modification information to the result identifier to obtain the processed result identifier; The generation unit is used to generate a target instruction stream based on the processed result identifier, the memory space size, and the instruction stream to be processed.

10. A second information processing device, characterized in that, include: The second acquisition unit is used to acquire the target instruction stream; wherein, the target instruction stream is generated by the first device based on the processed result identifier, the memory space required for the output result of the instructions in the instruction stream to be processed, and the instruction stream to be processed; the processed result identifier is obtained by the first device adding modification information to the result identifier of the output result; The second determining unit is used to determine a first correspondence between the result identifier and the modification information based on the target instruction stream; The second determining unit is further configured to determine a second correspondence between the modification information and the pointer variable based on the target instruction stream, and to determine the target memory space corresponding to the output result; The second determining unit is further configured to determine a third correspondence between the result identifier and the pointer variable based on the first correspondence and the second correspondence; The second processing unit is used to execute the instructions based on the third correspondence, the result identifier, and the target memory space.

11. A first device, characterized in that, The first device includes: a first processor, a first memory, and a first communication bus; The first communication bus is used to establish a communication connection between the first processor and the first memory; The first processor is used to execute an information processing program in the first memory to implement the steps of the information processing method as described in any one of claims 1 to 4.

12. A second device, characterized in that, The second device includes: a second processor, a second memory, and a second communication bus; The second communication bus is used to establish a communication connection between the second processor and the second memory; The second processor is used to execute an information processing program in the second memory to implement the steps of the information processing method as described in any one of claims 5 to 8.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the steps of the information processing method as described in any one of claims 1 to 4 or 5 to 8.

14. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method according to any one of claims 1 to 4 or claims 5 to 8.

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