Verification method and device, electronic equipment and readable storage medium

Abstract

This invention provides a verification method, apparatus, electronic device, and readable storage medium. The method involves acquiring timing constraint information for each timing parameter corresponding to a target device. The timing constraint information is determined based on the device version of the target device. In a general verification environment, for any timing parameter to be configured in the target device, the timing parameter is configured based on a target configuration component, according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter. The general verification environment includes a target configuration component for dynamic timing configuration and a target verification component with static verification logic. The target device with configured timing parameters is verified based on the target verification component. Thus, through a standardized parameter configuration process and a unified verification flow, the configuration method and verification environment can be efficiently reused among target devices of different device versions, improving development efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a verification method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] With the rapid development of high-performance processors, the demands on memory have also increased dramatically. Therefore, Double Data Rate (DDR) memory controllers have become widely used in various mobile devices and server systems. The main function of a DDR memory controller is to receive various memory access requests from the user host (such as the processor), process them through protocol conversion and arbitration scheduling, and then generate DDR commands to access DDR memory, thereby completing data transfer between the user host and the DDR memory.

[0003] In related technologies, since the command processing methods and interface characteristics of different DDR version protocols are different, the verification of DDR memory controllers requires configuring relevant parameters separately for each version protocol, and writing initialization and data transmission verification scripts for DDR memory controllers to cover all operation scenarios specified by the protocol. This results in low verification efficiency and high maintenance costs for DDR memory controllers. Summary of the Invention

[0004] To overcome the problems existing in related technologies, the present invention provides a verification method, apparatus, electronic device, and readable storage medium.

[0005] In a first aspect, the present invention provides a verification method, the method comprising: Obtain timing constraint information for each timing parameter corresponding to the target device; the timing constraint information is determined based on the device version corresponding to the target device; In a general verification environment, for any timing parameter to be configured in the target device, the timing parameter to be configured is configured based on the target configuration component, according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic; The target device with the timing parameters configured is verified based on the target verification component.

[0006] Secondly, the present invention provides a verification device, the device comprising: The first acquisition module is used to acquire timing constraint information of each timing parameter corresponding to the target device; the timing constraint information is determined according to the device version corresponding to the target device. The first configuration module is used in a general verification environment to configure any timing parameter to be configured in the target device, based on the target configuration component and according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic. The first verification module is used to verify the target device after the timing parameters are configured based on the target verification component.

[0007] Thirdly, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the verification method described in any one of the first aspects above.

[0008] Fourthly, the present invention provides a readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform steps in the verification method as described in any of the embodiments of the first aspect above.

[0009] In this embodiment of the invention, timing constraint information of each timing parameter corresponding to the target device is obtained. The timing constraint information is determined according to the device version corresponding to the target device. In a general verification environment, for any timing parameter to be configured in the target device, based on the target configuration component, the timing parameter to be configured is configured according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured. The general verification environment includes a target configuration component for dynamic timing configuration and a target verification component with static verification logic. The target device after the timing parameter is configured is verified based on the target verification component. In this way, by obtaining the timing constraint information of each timing parameter of the target device, the timing requirements of different versions of memory controllers can be accurately grasped. Then, by using the target configuration component to configure the timing parameter to be configured according to its parameter configuration rules and timing constraint information, the timing differences of different versions of memory controllers can be flexibly adapted to, realizing a unified configuration process for timing parameters. At the same time, by using the target configuration component to configure the timing parameters first, the timing constraint configuration and verification logic are decoupled, so that target devices of different device versions can be verified in a general verification environment, and the verification process is unified. Through standardized parameter configuration processes and unified verification procedures, configuration methods and verification environments can be efficiently reused across target devices of different device versions, improving development efficiency, reducing development costs, and fully demonstrating compatibility and high reusability for target devices of different device versions. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of the steps of a verification method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of an abstract framework for a general verification environment provided in an embodiment of the present invention; Figure 3 This is a structural diagram of a verification device provided in an embodiment of the present invention; Figure 4 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Figure 1 This is a flowchart of the verification method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the method may include: Step 101: Obtain the timing constraint information of each timing parameter corresponding to the target device; the timing constraint information is determined according to the device version corresponding to the target device.

[0014] In this embodiment of the invention, the target device can be a Double Data Rate (DDR) memory controller. The read and write operations of the DDR memory controller rely on precise timing control. Therefore, during the verification process of the target device, it is necessary to clarify the timing constraint information corresponding to the target device in order to cover different verification scenarios.

[0015] The timing constraint information for each timing parameter corresponding to the target device is used to characterize the baseline range of the timing parameters. The timing constraint information can be determined according to the device version corresponding to the target device. Timing parameters refer to the key variables in the target device that affect signal timing, and may include CL (CAS Latency, the delay from issuing a read command to starting to receive read data), CWL (CAS Write Latency, the delay from issuing a write command to starting to send write data), tRCD (RAS to CASDelay, the row address to column address delay time), and tRP (RAS Precharge Time, the memory row address controller precharge time), etc. Their value range can be defined by the DDR protocol specification corresponding to the device version of the target device. For example, assuming the device version of the target device is DDR4, then CL (CAS Latency) can be 10-24 clock cycles, tRCD / tRP can be 10-24 clock cycles, and tRAS can be 28-54 clock cycles.

[0016] Step 102: In the general verification environment, for any timing parameter to be configured in the target device, based on the target configuration component, the timing parameter to be configured is configured according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic.

[0017] In this embodiment of the invention, the universal verification environment can be constructed using UVM (Universal Verification Methodology) technology. It adopts a parameterized layered architecture, achieving dynamic timing configuration through independent target configuration components. These components then collaborate with target verification components possessing static verification logic, using a timing parameter injection verification method to achieve automated verification and adaptation of memory controllers for different device versions based on the same universal verification environment. The universal verification environment can be used to simulate various situations that the target device may encounter during actual operation. Through operation and evaluation, it ensures that the functionality and performance of the target device meet design requirements. For any timing parameter to be configured in the target device, based on the target configuration component, the timing parameter is configured according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter. The target configuration component can include fixed configuration components and random configuration components. During the verification process of the DDR memory controller, the target configuration component can be selected from the fixed configuration components and random configuration components according to the current verification requirements. The current verification requirements can be divided into a first verification requirement, namely, locating basic functional errors for functional verification, and a second verification requirement, namely, verifying whether the dynamic calculation capability of the timing parameters meets the protocol requirements. In other words, during the verification of the target device, the timing parameters to be configured can be configured sequentially through fixed configuration components or random configuration components to verify the function and performance of the target device under different timing conditions.

[0018] Accordingly, the first verification requirement can correspond to a fixed configuration component, which aims to minimize key timing parameters (e.g., tCK is set to 1.25ns) to bring the controller to its theoretically optimal performance state, thereby verifying the functional correctness of the target device in extreme high-speed scenarios. The parameter configuration rule for the fixed configuration component can be to set the timing parameter to be verified to the minimum value of its corresponding timing constraint information. The second verification requirement can correspond to a random configuration component, which generates random values ​​to cover the entire parameter space, verifying whether the target device's dynamic calculation capability for timing parameters meets the protocol requirements. The parameter configuration rule for the second verification requirement can be to randomly generate a value between the minimum and maximum values ​​of the timing constraint information corresponding to the timing parameter to be configured, using this value as the numerical value of the timing parameter to be configured.

[0019] After determining the values ​​of each timing parameter to be configured, the target configuration component can configure each timing parameter through the Configuration Manager in the memory controller.

[0020] Step 103: Verify the target device after configuring the timing parameters based on the target verification component.

[0021] In this embodiment of the invention, within a general verification environment constructed by a target configuration component and a target verification component, functional and protocol verification are performed on the target device after timing parameter configuration based on the target verification component. The target verification component may consist of an stimulus generator, a driver, a monitor, and a scoreboard. The specific verification logic of the stimulus generator, driver, monitor, and scoreboard can be predefined during the compilation phase according to different device versions. During verification by the target verification component, the timing specification of the target device version can be loaded using the configured timing parameters, automatically generating verification stimuli and inspection rules that conform to the protocol requirements of that device version.

[0022] The stimulus generator is responsible for generating stimulus signals that conform to specific rules and requirements. These stimulus signals can simulate various inputs received by the target device in actual applications. For example, in communication device verification, the stimulus generator can generate data packets of different formats and rates as stimuli. The driver transmits the stimulus signals generated by the stimulus generator to the target device, ensuring that the stimulus can act on the target device in the correct form and at the right time. The monitor is used to monitor the output response of the target device in real time after receiving the stimulus signal, capturing various data and status information output by the target device. The scoring board is used to evaluate and judge the output response of the target device, compare and analyze the actual output obtained by the monitor with the expected output, give the verification result according to the preset evaluation criteria, and then determine whether the target device passes the verification.

[0023] For example, in a general verification environment built on a target verification component, the verification process can unfold as follows: An stimulus generator generates stimulus signals, and a driver transmits these signals to the input port of the target device, enabling the target device to start running and process these stimuli. A monitor continuously tracks various output data and state changes generated by the target device during stimulus signal processing, monitors the target device's output response, and feeds back the monitored actual output information to the scoring board in real time. Upon receiving the actual output information, the scoring board compares it in detail with the pre-set expected output to determine whether the target device's operation meets design requirements. For example, if the actual output matches the expected output, the target device passes verification in this scenario; if there are discrepancies, it indicates that the target device may have problems and requires further analysis and debugging. Through this iterative process, a comprehensive and in-depth verification of the target device can be performed, thereby ensuring its quality and reliability.

[0024] In summary, in this embodiment of the invention, timing constraint information of each timing parameter corresponding to the target device is obtained; the timing constraint information is determined according to the device version corresponding to the target device; in a general verification environment, for any timing parameter to be configured in the target device, based on the target configuration component, the timing parameter to be configured is configured according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes a target configuration component for dynamic timing configuration and a target verification component with static verification logic; the target device after the timing parameter configuration is performed based on the target verification component. Thus, by obtaining the timing constraint information of each timing parameter of the target device, the timing requirements of different versions of memory controllers can be accurately grasped. Then, by using the target configuration component to configure the timing parameter to be configured according to its parameter configuration rules and timing constraint information, the timing differences of various versions of memory controllers can be flexibly adapted to, realizing a unified configuration process for timing parameters. Simultaneously, by configuring the timing parameters first using the target configuration component, the timing constraint configuration and verification logic are decoupled, enabling target devices of different device versions to be verified in a general verification environment, thus unifying the verification process. Through standardized parameter configuration processes and unified verification procedures, configuration methods and verification environments can be efficiently reused across target devices of different device versions, improving development efficiency, reducing development costs, and fully demonstrating compatibility and high reusability for target devices of different device versions.

[0025] Optionally, embodiments of the present invention may further include the following steps: Step 201: When the current verification requirement is the first verification requirement, the fixed configuration component is determined as the target configuration component; the fixed configuration component is used to configure the timing parameter to be verified to the minimum value.

[0026] Step 202: When the current verification requirement is the second verification requirement, the random configuration component is determined as the target configuration component; the random configuration component is used to randomly configure the timing parameters to be verified.

[0027] In this embodiment of the invention, the current verification requirements can be divided into a first verification requirement, namely, locating basic functional errors for functional verification, and a second verification requirement, namely, verifying whether the dynamic calculation capability of timing parameters meets the protocol requirements. That is, during the verification of the target device, the timing parameters to be configured can be configured sequentially using either a fixed configuration component or a random configuration component to verify the functionality and performance of the target device under different timing conditions.

[0028] Correspondingly, the first verification requirement can correspond to a fixed configuration component, which aims to minimize key timing parameters (e.g., tCK is set to 1.25ns) to bring the controller to its theoretically optimal performance state, thereby verifying the functional correctness of the target device in extreme high-speed scenarios. The parameter configuration rule for the fixed configuration component can be to set the timing parameter to be verified to the minimum value of its corresponding timing constraint information; that is, the fixed configuration component is used to configure the timing parameter to be verified to the minimum value. The second verification requirement can correspond to a random configuration component, which generates random values ​​to cover the entire parameter space, verifying whether the target device's dynamic calculation capability for timing parameters meets the protocol requirements. The parameter configuration rule for the second verification requirement can be to randomly generate a value between the minimum and maximum values ​​of the timing constraint information corresponding to the timing parameter to be configured, using it as the value of the timing parameter to be configured; that is, the random configuration component is used to configure the timing parameter to be verified to a random value.

[0029] Accordingly, step 101 may include the following steps: Step 203: Based on the fixed configuration component, determine the minimum value corresponding to the timing parameter to be configured according to the timing constraint information corresponding to the timing parameter to be configured, and configure the value of the timing parameter to be configured in the target device to the minimum value.

[0030] In this embodiment of the invention, the fixed configuration component can be a module with pre-defined parameter configuration rules and procedures. Since the minimum value typically represents the most stringent setting for the timing parameter while meeting timing requirements, it ensures that the target device can function normally even under extreme conditions and detects potential timing issues in advance. Therefore, the fixed configuration component can configure the value of the timing parameter to be configured in the target device to the minimum value within the timing constraint range defined by the timing constraint information corresponding to the timing parameter to be configured.

[0031] Alternatively, in step 204, based on the random configuration component, a first random value is randomly selected within the timing constraint range defined by the timing constraint information corresponding to the timing parameter to be configured, and the value of the timing parameter to be configured in the target device is configured as the first random value.

[0032] In this embodiment of the invention, the random configuration component can be a module capable of pre-setting parameter configuration rules and generating random configuration values ​​according to a random algorithm. When configuring based on the random configuration component, a first random value is generated within the timing constraint range defined by the timing constraint information of the timing parameter to be configured. The value of the timing parameter to be configured in the target device is then configured as this first random value to simulate various complex timing situations that the target device may encounter during actual use, since timing interference in the real environment is often random. In this way, the performance and stability of the target device under different timing conditions can be verified more comprehensively, improving the reliability and adaptability of the device.

[0033] In this embodiment of the invention, based on a fixed configuration component, the value of the timing parameter to be configured in the target device is configured to the minimum value according to the timing constraint information corresponding to the timing parameter to be configured; or, based on a random configuration component, the value of the timing parameter to be configured in the target device is configured to a first random value according to the timing constraint information corresponding to the timing parameter to be configured. The two components configure the timing parameter from two perspectives: extreme strictness (minimum value) and random variability (first random value), complementing each other to achieve testing of the memory controller under different configurations such as frequency, chip width, and number of channels. This comprehensively covers various timing situations that the target device may encounter, thereby effectively improving the verification coverage and ensuring the quality and reliability of the target device.

[0034] Optionally, step 101 may include the following steps: Step 301: Obtain the device configuration information of the target device by parsing the macro parameters corresponding to the target device; the device configuration information includes device version, device operating frequency, particle bit width and particle capacity.

[0035] In this embodiment of the invention, device configuration information of the target device is obtained based on the macro parameters corresponding to the target device. The device configuration information is a key data set describing the hardware and software characteristics of the target device. The macro parameters can be pre-set in the Makefile script during the compilation phase. The device version identifies the specific model and iteration version of the target device; different versions differ in functionality, performance, and interfaces. The device operating frequency refers to the operating clock frequency of the target device during normal operation, affecting its processing speed and data transfer rate. The chip width indicates the data bit width of the storage chips in the target device, affecting the connection method between the memory controller and the storage chips. The chip capacity indicates the amount of data that the storage chips can store.

[0036] For example, device configuration information may include DDR5 3200MHz, chip width x8, chip capacity of 8Gb (1Gbx8), that is, the device version is DDR5, the device operating frequency is 3200MHz, the chip width is x8, and the chip capacity is 8Gb (1Gbx8).

[0037] Step 302: Based on the target protocol corresponding to the device version, the device operating frequency, the particle bit width, and the particle capacity, determine the timing constraint information of each timing parameter corresponding to the target device.

[0038] In this embodiment of the invention, after obtaining the device configuration information, the timing constraints corresponding to the target device are determined based on the target protocol corresponding to the device version, the device operating frequency, the granular bit width, and the granular capacity. The target protocol is a specification and standard formulated for a specific device version, which stipulates the timing requirements of the target device in terms of data transmission, signal interaction, etc. According to the target protocol corresponding to the device version, the device operating frequency, granular bit width, and granular capacity can be converted into timing constraint information. For example, combined with the device operating frequency, the time of each clock cycle can be determined, and thus the timing constraints can be determined. The granular bit width and granular capacity affect data transmission efficiency and row / column addressing time; for example, different granular bit widths may result in different row / column addressing times; different granular capacities may also result in different row / column addressing times.

[0039] For example, assuming the device configuration information is that the device version is DDR5, the device operating frequency is 3200MHz, the chip width is x8, and the chip capacity is 8Gb (1Gbx8), the timing constraint information can be determined according to the DDR5 protocol.

[0040] In this embodiment of the invention, timing constraints are determined based on device configuration information and the corresponding target protocol, ensuring that timing requirements are highly compatible with the actual device. Different versions of device protocols differ; by combining operating frequency and granular parameters, timing can be accurately calculated, avoiding data errors or device malfunctions caused by improper timing. This provides a reliable basis for subsequent device timing configuration and verification, effectively improving the stability and reliability of device operation and ensuring normal operation of the device in various scenarios.

[0041] Furthermore, the device configuration information of the target device can be adjusted by modifying macro parameters, which can effectively cover the various configuration and timing parameter requirements of DDR memory controllers of different device versions and configurations, thereby improving the universality and accuracy of the verification.

[0042] Optionally, embodiments of the present invention may include the following steps: Step 401: Based on the initialization procedure, perform calibration training on the target device according to the training method that matches the device version of the target device.

[0043] In this embodiment of the invention, the general verification environment may further include an initialization program, meaning the general verification environment can be jointly constructed by a target configuration component, a target verification component, and an initialization program. Before verifying the target device, the target device can be initialized and calibrated based on the initialization program. Since the initialization training process is not consistent for different device versions, the initialization program will pre-define different initialization training processes corresponding to different target device versions according to the protocol specification. That is, after the target configuration component completes the configuration of various timing parameters and registers of the target device, the target device enters the initialization training phase. At this time, the initialization program will select different calibration training methods based on information such as device version, memory module (DIMM) type, number of channels, and channel bit width, and perform calibration training on the target device according to the training process of the selected calibration training method.

[0044] For example, assuming the target device corresponds to DDR5, UDIMM (Unbuffered Dual Inline Memory Module), and single-channel 32-bit information, the specific training process for calibration training of this target device can consist of the following multiple training modes: 1. Chip Select Signal Training Mode (CSTM): In scenarios with multiple memory chips (ranks), clock signal skew can occur due to differences in physical layout, causing the chip select signal (CS) to be out of sync with the clock signal (CK). In this training mode, the DDR memory controller sends a pulse sequence, and the DRAM (Dynamic Random Access Memory) feeds back the phase difference between CK and CS via the DQS (Data Strobe Signal). The memory controller calculates a latency compensation value based on this feedback information, thereby ensuring the synchronization of the chip select signal and the clock signal, providing a stable foundation for subsequent data transmission and operation.

[0045] 2. Command Signal Training Mode (CATM): During high-speed data transmission, the command signal (CA) may experience signal integrity degradation. This training mode optimizes the reference voltage (VrefCA) and sampling phase of the command signal. The DRAM samples the CA signal and generates a check value through XOR logic operation, which is then sent back to the DQ pin. The DDR memory controller adjusts the phase relationship between CA and CK based on these check values, improving the accuracy and reliability of command signal transmission.

[0046] 3. Per DRAM Addressability (PDA): During DDR5 training, the core role of PDA is to enable independent configuration and optimized control of individual DRAM chips within the memory module. For example, in DDR5 UDIMMs, each DRAM chip may have manufacturing differences, such as response time variations. PDA technology allows the memory controller to configure timing parameters individually for each chip during the training phase, such as CL (Column Address Strobe Latency), tRCD (Row Address to Column Address Latency), and tRP (Row Precharge Time), thereby better adapting to the characteristics of different chips and improving overall memory performance.

[0047] 4. Write Leveling Training Mode: Due to differences in physical routing, timing offsets may occur, affecting signal alignment during write operations. The DDR memory controller sends a pulse sequence, and the DRAM chip samples the CK signal through DQS and feeds back the phase difference to the DQ (data signal) pin. The DDR memory controller adjusts the delay value of DQS based on the feedback until CK and DQS edges are aligned, ensuring the accuracy and stability of the written data.

[0048] 5. Read Preamble Training Mode: Used to calibrate the DQS preamble timing, ensuring the memory controller correctly captures the data synchronization signal from the DRAM before a read operation. By adjusting the preamble duration (typically 1-2 clock cycles), the effective edge of the DQS is aligned with the controller's expected sampling point, improving the accuracy and efficiency of the read operation.

[0049] 6. Read Training Pattern: Generates a standardized data eye diagram template for precise calibration of the sampling window position of the DQ (data signal). The DDR memory controller sends a specific pattern (such as alternating 1010 or 111000 sequences), and the DRAM returns the same pattern. The DDR memory controller detects the left and right boundaries of the valid data window by horizontally scanning the DQS delay, and finally adjusts the sampling point to the center of the eye diagram, ensuring accurate capture of the valid signal during data reading and improving the reliability of data reading.

[0050] In this embodiment of the invention, by using fixed configuration components, random configuration components, and initialization procedures, it is possible to ensure that the working state of the target device meets the requirements of the corresponding protocol, effectively covering various configuration and parameter requirements of DDR memory controllers of different versions and configurations, thereby improving the universality and accuracy of the verification.

[0051] Optionally, the target verification components include an stimulus generator, a driver, a monitor, and a scoreboard. By designing verification components such as the stimulus generator, driver, monitor, and scoreboard, steps such as instruction generation, instruction sending, data reception, and result verification are completed sequentially, forming a complete verification process to ensure accurate evaluation of the target device's performance and functional correctness during read and write operations.

[0052] Step 103 may include the following steps: Step 501: Based on the stimulus generator, generate write instructions and read instructions; the write instructions are used to indicate the target write address, the target write data, and the write transaction identifier, and the read instructions are used to indicate the target read address and the read transaction identifier.

[0053] In this embodiment of the invention, a stimulus generator is used to generate write and read instructions. Since the target device and the CPU communicate via a bus protocol (such as the AXI protocol), the stimulus generator generates operation instructions and related data that conform to the bus protocol to simulate a wide variety of memory access scenarios in real-world applications, covering data read and write operations in both normal and streaming modes. In normal mode, the stimulus generator randomly generates memory access addresses and data, and these memory access addresses are independent of each other; while in streaming mode, memory access addresses within the same stream must be consecutive in units of cache lines, meaning the current memory access address is based on the previous memory access address plus the address of one cache line.

[0054] Based on this, the stimulus generator generates write and read instructions. The write instruction is used to indicate the target write address (the memory location where the data is to be written), the target write data (the data content to be written), and the write transaction identifier (used to uniquely identify the write operation); the read instruction is used to indicate the target read address (the location where the data is to be read from memory) and the read transaction identifier (used to uniquely identify the read operation).

[0055] Step 502: Based on the driver, the write instruction and the read instruction are sent to the target device through a general virtual interface; the target device responds to the write instruction by writing the target write data to the target write address, and responds to the read instruction by obtaining the read data to be verified from the target read address.

[0056] In this embodiment of the invention, the driver can send the data packets generated by the stimulus generator to the target device via the AXI interface (between the general virtual interface and the DDR memory controller). For example, if the bus between the target device and the CPU is an AXI bus, then the aforementioned virtual interface is the AXI interface, i.e., the target verification component (also called the AXI master). Through the general virtual interface, the target device can receive read and write instructions generated by the AXI master. Thus, by designing a general virtual interface, the output signals of the AXI master and the receiving signals of the target device can be abstracted and unified, improving the versatility of data interaction between the AXI master and the target device. Simultaneously, the driver has the ability to receive return signals from the target device, such as write handshake signals (e.g., wready, indicating that the target device is ready to receive write data) and write response signals (e.g., bvalid and bid, confirming whether the write operation is complete). Based on these signals, it can be determined whether the communication between the AXI master and the target device has successfully handshaked and whether a memory access instruction has been completed. Furthermore, the driver also sends the read address, write address, write data, write transaction identifier, and read transaction identifier from the data packets generated by the stimulus generator to the buffer component to prepare for subsequent data comparison on the scoring board.

[0057] Furthermore, after receiving read and write commands from the driver, the target device will respond accordingly. For write commands, the target device will accurately write the target write data to the target write address; for read commands, the target device will retrieve the read data to be verified from the target read address.

[0058] Step 503: Based on the monitor, receive the read data to be verified returned by the target device.

[0059] In this embodiment of the invention, a monitor receives the read data to be verified and the read transaction identifier returned by the target device. Simultaneously, the monitor can receive read handshake signals (e.g., rvalid, indicating that the target device has valid read data) and read response signals (e.g., rlast and bid, indicating the end of the read operation and related information) returned by the target device, and has the ability to record and analyze abnormal situations. For example, if the monitor does not receive the corresponding read data (rid) returned by the target device for a certain read operation, a timeout error will be reported.

[0060] Step 504: Based on the scoring board, according to the verification rules corresponding to the matching result of the target read address and the historical write address corresponding to the historical write instruction, the read data to be verified is verified to obtain the verification result corresponding to the target device.

[0061] In this embodiment of the invention, the write data sent by the target verification component is compared with the read data returned by the DDR memory collected by the monitor to determine whether the data is correct. The scoring board defines verification rules, and the correctness of the read data to be verified is verified according to these rules to obtain the verification result corresponding to the target device. For example, addresses in memory can be divided into written addresses and unwritten addresses. For unwritten addresses, the memory is initialized to a fixed value (e.g., ff). For written addresses, the cache stores historical write data, historical write addresses, and corresponding write transaction identifiers from previous write instructions. During a write operation, the cache stores the written data, write addresses, and write transaction identifiers for comparison of data correctness during read operations. Specifically, when comparing the read data to be verified, if the target read address has been written (e.g., the target read address is the same as the target write address that was previously written), and the read transaction identifier corresponding to the target read address is the same as the write transaction identifier corresponding to the target write address, then the data corresponding to the target write address is compared; if the address has not been written (e.g., the target read address is different from all previously written historical write addresses), then the read data to be verified is compared with the initial memory value ff; if neither of the above two conditions is met, then the data is determined to be erroneous; in addition, all read operations that compare write addresses before the write return signal returns will be invalidated.

[0062] In this embodiment of the invention, a stimulus generator generates write and read instructions, clearly defining the operation address, data, and transaction identifier, providing clear instructions for verification and creating the prerequisite for verification. The driver accurately sends instructions through a general virtual interface, ensuring that the target device correctly executes read and write operations. The monitor receives the read data to be verified, and the scoring board performs comprehensive comparison and verification, achieving comprehensive verification from instruction generation to data acquisition and verification, and ensuring the accurate and reliable functioning of the device.

[0063] Furthermore, since the stimulus generator can drive different test sequences, by setting multiple different commands in the test sequences, diverse verification scenarios for different commands and various memory access scenarios can be realized. For example, it can process various commands specified in the protocol and complete the tasks of each command, ensuring accurate data collection, processing, and response under various commands, and ensuring that the functions and performance of the memory controller meet the specification requirements. At the same time, by generating verification of diverse memory access scenarios, the comprehensiveness and accuracy of the verification process can be ensured.

[0064] Optionally, step 504 may include the following steps: Step 601: If the target read address is the same as any historical write address and the read transaction identifier corresponding to the target read address is the same as the write transaction identifier corresponding to the historical write address, determine the verification rule as the first verification rule, and based on the first verification rule, compare the read data to be verified with the write data matching the target read address to obtain the first verification result.

[0065] In this embodiment of the invention, memory addresses can be divided into written addresses and unwritten addresses. Unwritten addresses are initialized to fixed values; written addresses contain previously written data. The write status can be defined as an attribute indicating whether a memory address has been written to; a write status of "not written" indicates that the memory address has not been accessed by any write operation. The target value can be a pre-set fixed value, set according to actual needs, such as all 0s, all 1s (e.g., ff), or a specific hexadecimal value.

[0066] In this embodiment of the invention, when performing a read operation based on a read command, the write status of the target read address is obtained. If the target read address is the same as any historical write address, that is, the write status of the target read address is "write," it indicates that the address has previously undergone a write operation, and the cache should store the historical write data corresponding to the historical write instruction. Furthermore, the write transaction identifier corresponding to the historical write instruction is compared with the read transaction identifier corresponding to the read data to be verified. If they match, the verification rule can be determined as the first verification rule. At this time, based on the first verification rule, the read data to be verified (i.e., the data read from the target read address) and the write data matching the target read address (i.e., the historical write data previously written to that address) are compared. That is to say, the matching of the target read address with the historical write address corresponding to the historical write instruction can mean that the historical write data and the read data to be verified correspond to the same memory address and the read transaction identifier corresponding to the read data to be verified is consistent with the write transaction identifier corresponding to the target write address, so as to determine whether the write operation successfully wrote the expected data to the correct memory address and whether the read operation accurately read the data at that address. If the two are consistent, it indicates that the read and write operations are normal, and the first verification result is passed; if they are inconsistent, it indicates that an error occurred during the read and write process, and the first verification result is failed.

[0067] Step 603: If the target read address is different from each of the historical write addresses, determine the verification rule as the second verification rule, and compare the read data to be verified with the target value based on the second verification rule to obtain the second verification result; the target value is the initial value of the memory address that has not been written.

[0068] In this embodiment of the invention, if the target read address is different from all historical write addresses, that is, the write state of the target read address is "not written," it indicates that no data has been written to that address before, and according to the initialization settings, the data in its memory is the pre-set target value. The verification rule is determined as the second verification rule. At this time, based on the second verification rule, the data to be verified is compared with the target value to check whether the data read without any data being written conforms to the expected initial value. If the data to be verified matches the target value, it indicates that the initial state of the memory is correct, and the second verification result is passed; if they do not match, there may be an error in the initial memory value setting or an abnormal reading process, and the second verification result is failed.

[0069] In this embodiment of the invention, by setting the initial value of the unwritten memory address as the target value, when the target read address is in the write state, comparing the read data to be verified with the matching write data can determine whether the write operation was successful and whether the read operation accurately read valid data; when the write state is not written, comparing the read data to be verified with the target value can check the initial state of the memory. Thus, from both the write state and the unwritten state, the memory read and write scenarios are comprehensively covered, effectively ensuring data accuracy and improving system stability and reliability.

[0070] For example, Figure 2 A schematic diagram of an abstract framework for a general verification environment is shown, such as... Figure 2 As shown in the schematic diagram of this abstract framework, the arrows indicate the direction of data transmission. For example, the fixed configuration component and the random configuration component are used to configure the timing parameters of the target device, and the initprogram is used to perform initial calibration training on the target device. Through the stimulus generator (sequencer) in the general verification environment, read and write commands are generated based on test cases and test sequences and sent to the driver. The driver caches the relevant data in a buffer and sends the read and write commands to the target device (MC) via the axiinterface. The monitor is used to obtain the read data to be verified returned by the target device and send it to the scoreboard. The scoreboard verifies the read data to be verified based on the write data stored in the buffer and the first value, according to the write status of the read address, and obtains the verification result.

[0071] Figure 3 This is a schematic diagram of the structure of a verification device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the device may specifically include: The first acquisition module 701 is used to acquire timing constraint information of each timing parameter corresponding to the target device; the timing constraint information is determined according to the device version corresponding to the target device. The first configuration module 702 is used in a general verification environment to configure any timing parameter to be configured in the target device, based on the target configuration component and according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic. The first verification module 703 is used to verify the target device after the timing parameters are configured based on the target verification component.

[0072] Optionally, the target configuration component includes a fixed configuration component and a random configuration component; the device further includes: The first determining module is used to determine the fixed configuration component as the target configuration component when the current verification requirement is the first verification requirement; the fixed configuration component is used to configure the timing parameter to be verified to the minimum value; The second determining module is used to determine the random configuration component as the target configuration component when the current verification requirement is the second verification requirement; the random configuration component is used to randomly configure the timing parameters to be verified. The first configuration module 701 includes: The first configuration submodule is used to determine the minimum value corresponding to the timing parameter to be configured based on the fixed configuration component and the timing constraint information corresponding to the timing parameter to be configured, and configure the value of the timing parameter to be configured in the target device as the minimum value. The second configuration submodule is used to randomly select a first random value within the timing constraint range defined by the timing constraint information corresponding to the timing parameter to be configured, based on the random configuration component, and configure the value of the timing parameter to be configured in the target device as the first random value.

[0073] Optionally, the first acquisition module 701 includes: The first acquisition submodule is used to obtain the device configuration information of the target device by parsing the macro parameters corresponding to the target device; the device configuration information includes device version, device operating frequency, particle bit width and particle capacity; The third determining module is used to determine the timing constraint information of each timing parameter corresponding to the target device based on the target protocol corresponding to the device version, the device operating frequency, the particle bit width, and the particle capacity.

[0074] Optionally, the general verification environment further includes an initialization program; the apparatus further includes: The first training module is used to perform calibration training on the target device based on the initialization program and according to a training method that matches the device version of the target device.

[0075] Optionally, the target verification component includes an stimulus generator, a driver, a monitor, and a scoreboard; the first verification module 703 includes: The first generation module is used to generate write instructions and read instructions based on the stimulus generator; the write instructions are used to indicate the target write address, the target write data, and the write transaction identifier, and the read instructions are used to indicate the target read address and the read transaction identifier. The first sending module is configured to send the write instruction and the read instruction to the target device via a general virtual interface based on the driver; the target device responds to the write instruction by writing the target write data to the target write address, and responds to the read instruction by obtaining the read data to be verified from the target read address; The first receiving module is used to receive the read data to be verified returned by the target device based on the monitor; The first verification submodule is used to verify the read data to be verified based on the scoring board and according to the verification rules corresponding to the matching result of the target read address and the historical write address corresponding to the historical write instruction, so as to obtain the verification result corresponding to the target device.

[0076] Optionally, the first verification submodule includes: The first comparison module is used to determine the verification rule as the first verification rule when the target read address is the same as any historical write address and the read transaction identifier corresponding to the target read address is the same as the write transaction identifier corresponding to the historical write address, and to compare the read data to be verified and the write data matching the target read address based on the first verification rule to obtain the first verification result. The second comparison module is used to determine the verification rule as the second verification rule when the target read address is different from each of the historical write addresses, and to compare the read data to be verified with the target value based on the second verification rule to obtain the second verification result; the target value is the initial value of the memory address that has not been written.

[0077] The present invention also provides an electronic device, see [link to relevant documentation]. Figure 4 It includes: a processor 801, a memory 802, and a computer program 8021 stored in the memory and executable on the processor, wherein the processor executes the program to implement the verification method of the foregoing embodiments.

[0078] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the verification method of the foregoing embodiments.

[0079] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0080] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0081] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0082] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0083] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0084] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention can also be implemented as a device or apparatus program for performing part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0085] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0086] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0087] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0089] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A verification method, characterized in that, The method includes: Obtain timing constraint information for each timing parameter corresponding to the target device; the timing constraint information is determined based on the device version corresponding to the target device; In a general verification environment, for any timing parameter to be configured in the target device, the timing parameter to be configured is configured based on the target configuration component, according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic; The target device with the timing parameters configured is verified based on the target verification component.

2. The method according to claim 1, characterized in that, The target configuration component includes a fixed configuration component and a random configuration component; the method further includes: When the current verification requirement is the first verification requirement, the fixed configuration component is determined as the target configuration component; the fixed configuration component is used to configure the timing parameter to be verified to the minimum value; When the current verification requirement is the second verification requirement, the random configuration component is determined as the target configuration component; the random configuration component is used to randomly configure the timing parameters to be verified. The step of configuring the timing parameters to be configured in the target device based on the target configuration component, according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameters to be configured, includes: Based on the fixed configuration component, according to the timing constraint information corresponding to the timing parameter to be configured, the minimum value corresponding to the timing parameter to be configured is determined, and the value of the timing parameter to be configured in the target device is configured to the minimum value; Alternatively, based on the random configuration component, a first random value is randomly selected within the timing constraint range defined by the timing constraint information corresponding to the timing parameter to be configured, and the value of the timing parameter to be configured in the target device is configured as the first random value.

3. The method according to claim 1, characterized in that, The acquisition of timing constraint information for each timing parameter corresponding to the target device includes: By parsing the macro parameters corresponding to the target device, the device configuration information of the target device is obtained; the device configuration information includes the device version, device operating frequency, particle bit width, and particle capacity. Based on the target protocol corresponding to the device version, the device operating frequency, the particle bit width, and the particle capacity, the timing constraint information of each timing parameter corresponding to the target device is determined.

4. The method according to claim 1, characterized in that, The general verification environment also includes an initialization procedure; the method further includes: Based on the initialization procedure, the target device is calibrated and trained according to a training method that matches the device version of the target device.

5. The method according to any one of claims 1 to 4, characterized in that, The target verification component includes an excitation generator, a driver, a monitor, and a scoreboard; the verification of the target device with configured timing parameters based on the target verification component includes: Based on the stimulus generator, write instructions and read instructions are generated; the write instructions are used to indicate the target write address, the target write data, and the write transaction identifier, and the read instructions are used to indicate the target read address and the read transaction identifier. The driver sends the write command and the read command to the target device through a general virtual interface; the target device responds to the write command by writing the target write data to the target write address, and responds to the read command by retrieving the read data to be verified from the target read address; Based on the monitor, receive the read data to be verified returned by the target device; Based on the scoring board, the read data to be verified is verified according to the verification rules corresponding to the matching result of the target read address and the historical write address corresponding to the historical write instruction, so as to obtain the verification result corresponding to the target device.

6. The method according to claim 5, characterized in that, The step of verifying the read data to be verified according to the verification rules corresponding to the matching result between the target read address and the historical write address corresponding to the historical write instruction, and obtaining the verification result corresponding to the target device, includes: If the target read address is the same as any historical write address and the read transaction identifier corresponding to the target read address is the same as the write transaction identifier corresponding to the historical write address, the verification rule is determined to be the first verification rule. Based on the first verification rule, the read data to be verified and the write data matching the target read address are compared to obtain the first verification result. When the target read address is different from each of the historical write addresses, the verification rule is determined to be the second verification rule, and based on the second verification rule, the read data to be verified is compared with the target value to obtain the second verification result; the target value is the initial value of the memory address that has not been written.

7. A verification device, characterized in that, The device includes: The first acquisition module is used to acquire timing constraint information of each timing parameter corresponding to the target device; the timing constraint information is determined according to the device version corresponding to the target device. The first configuration module is used in a general verification environment to configure any timing parameter to be configured in the target device, based on the target configuration component and according to the parameter configuration rules of the target configuration component and the timing constraint information corresponding to the timing parameter to be configured; the general verification environment includes the target configuration component for dynamic timing configuration and the target verification component with static verification logic. The first verification module is used to verify the target device after the timing parameters are configured based on the target verification component.

8. The apparatus according to claim 7, characterized in that, The target configuration component includes a fixed configuration component and a random configuration component; the device further includes: The first determining module is used to determine the fixed configuration component as the target configuration component when the current verification requirement is the first verification requirement; the fixed configuration component is used to configure the timing parameter to be verified to the minimum value. The second determining module is used to determine the random configuration component as the target configuration component when the current verification requirement is the second verification requirement; the random configuration component is used to randomly configure the timing parameters to be verified. The first configuration module includes: The first configuration submodule is used to determine the minimum value corresponding to the timing parameter to be configured based on the fixed configuration component and the timing constraint information corresponding to the timing parameter to be configured, and configure the value of the timing parameter to be configured in the target device as the minimum value. The second configuration submodule is used to randomly select a first random value within the timing constraint range defined by the timing constraint information corresponding to the timing parameter to be configured, based on the random configuration component, and configure the value of the timing parameter to be configured in the target device as the first random value.

9. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the verification method as described in any one of claims 1-6.

10. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the verification method according to any one of claims 1-6.

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