Serial communication system and method, dual-mode serial interface circuit and beamforming chip

By introducing a global synchronization trigger signal line and a data buffering mechanism, the problem of configuration synchronization of multiple slave devices in a serial communication system is solved, achieving synchronous updates with nanosecond-level precision, improving system design flexibility and reliability, and optimizing hardware resources and communication efficiency.

CN122240548APending Publication Date: 2026-06-19DIYIXIN (SHANGHAI) MICROELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
DIYIXIN (SHANGHAI) MICROELECTRONICS CO LTD
Filing Date
2026-03-18
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

Existing serial communication systems suffer from a lack of configuration synchronization in multi-slave applications, resulting in significant time discrepancies in the effective time of configurations for each slave device. This makes it impossible to achieve synchronized configuration updates for all slave devices, impacting system functionality and performance.

Method used

A global synchronization trigger signal line and data buffering mechanism are introduced to enable the configuration data of all slave devices to take effect synchronously at the same time through control logic blocks. It supports both physical addressing and daisy chain modes, reducing pin occupation and enhancing system flexibility.

Benefits of technology

It achieves multi-device configuration synchronization with nanosecond-level precision, provides system design flexibility, optimizes hardware resources and communication efficiency, enhances system reliability and robustness, and maintains good backward compatibility and ease of integration.

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Abstract

This disclosure provides a serial communication system and method, a dual-mode serial interface circuit, and a beamforming chip. The system includes a master device and multiple slave devices, and is further configured with a synchronization trigger signal line driven by the master device and connected to all slave devices. Each slave device includes: a configuration register for implementing the synchronization function; a data buffer unit connected between the serial data line and the configuration register for temporarily storing configuration data from the master device; and a control logic block for controlling the synchronization of the temporarily stored configuration data in the data buffer unit to the configuration register in response to a valid signal on the synchronization trigger signal line, so that the configuration updates of all slave devices take effect at the same time. This disclosure fundamentally solves the technical problem of time discrepancies in the configuration activation times of multiple slave devices by introducing a global synchronization trigger signal line, enabling the configuration updates of all slave devices to take effect at the same time.
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