Anti-interference magnetic tunnel junction spiking neuron circuit
By introducing synchronous resistance changes of the vertical magnetic anisotropic spin-transfer torque magnetic tunnel junction and the reference magnetic tunnel junction into the magnetic tunnel junction spiking neuron circuit, common-mode noise is canceled, solving the problem of the magnetic neuron circuit being sensitive to temperature drift and process deviation, and realizing a high-density integrated and low-power neural network array.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-03-18
- Publication Date
- 2026-06-19
AI Technical Summary
Magnetic neuron circuits are sensitive to process variations and temperature drift, and are susceptible to read/write interference, resulting in poor reliability when the circuit is arrayed on a large scale, and excessively large peripheral circuit area, which does not meet the requirements of high-density integration.
An anti-interference magnetic tunnel junction pulse neuron circuit is adopted. The synchronous resistance change of the vertical magnetic anisotropic spin-transfer torque magnetic tunnel junction and the reference magnetic tunnel junction is used to cancel common-mode noise. Integration, ignition and reset operations are realized through the read and write drive module. The reference junction is used as a twin reference to stabilize the ignition threshold and avoid current miswriting.
It improves the ignition accuracy of neuron circuits under harsh operating conditions, significantly saves chip area and power consumption, and is suitable for large-scale spiking neural network array integration.
Smart Images
Figure CN122242589A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of spintronics and brain-like computing technology, specifically relating to a spiking neural network (SNN) neuron circuit implemented using a spin-transfer torque magnetic tunnel junction (STT-MTJ). Background Technology
[0002] With the rapid development of artificial intelligence (AI) technology, the traditional von Neumann architecture faces bottlenecks in power consumption and efficiency when processing large-scale neural networks due to the "memory wall" problem. Neuromorphic computing, by mimicking the neuronal and synaptic mechanisms of the biological brain, has become an important approach to achieving low-power, high-efficiency intelligent computing.
[0003] As a third-generation artificial neural network, spiking neural networks (SNNs) introduce a spatiotemporal coding mechanism, utilizing event-driven sparse pulse signals for the transmission and processing of various types of information. Compared to traditional artificial neural networks based on continuous analog values, SNNs exhibit extremely high biological realism and energy efficiency when processing temporal signals and sensory data.
[0004] Spin-transfer torque magnetic tunnel junctions (STT-MTJs) are considered ideal core devices for building high-density neuromorphic chips due to their non-volatility, nanoscale size, near-zero quiescent power consumption, and good compatibility with CMOS processes. The tunneling magnetoresistivity (TMR) and flip-flop threshold of magnetic devices are extremely sensitive to temperature changes. In single-ended circuits lacking an effective reference mechanism, fluctuations in chip operating temperature can cause read voltage drift. Once the drift exceeds the sensing margin determined by the finite TMR, the circuit will experience ignition failure or misjudgment, which is fatal for large-scale arrayed neural network chips. Summary of the Invention
[0005] This invention addresses the technical problems of existing magnetic neuron circuits being sensitive to process deviations and temperature drift, susceptible to read / write interference, and having excessively large peripheral circuit areas that fail to meet high-density integration requirements in order to improve reliability. It proposes an anti-interference magnetic tunnel junction pulse neuron circuit.
[0006] The technical solution adopted in this invention is as follows:
[0007] An anti-interference magnetic tunneling junction spiking neuron circuit, comprising:
[0008] The core computing unit is used to integrate the neuronal membrane potential. The core computing unit consists of at least one spin-transfer torque magnetic tunnel junction (STT-MTJ), which has a parallel state with low resistance and an antiparallel state with high resistance.
[0009] The reference read branch includes a reference magnetic tunnel junction and a read isolation switch connected in series. The reference read branch is connected to one end of the core computing unit and is used to provide a fixed reference resistance.
[0010] The read / write driver module, connected to the core computing unit and the reference read branch, is used to control the on / off state and direction of current to achieve integration, ignition and reset operations.
[0011] Furthermore, both the spin-transfer torque magnetic tunnel junction and the reference magnetic tunnel junction are perpendicular magnetic anisotropy (PMA) magnetic tunnel junctions, with identical materials and structures. The resistance of the reference magnetic tunnel junction is fixed in a low-resistance state, while the resistance of the spin-transfer torque magnetic tunnel junction switches between a low-resistance state and a high-resistance state as driven by the current.
[0012] Furthermore, the spin-transfer torque magnetic tunnel junction and the reference magnetic tunnel junction include a bottom electrode, a free layer, a barrier layer, a reference layer, and a top electrode arranged sequentially from bottom to top; the diameter of the spin-transfer torque magnetic tunnel junction and the reference magnetic tunnel junction is 20nm~60nm, and the tunneling magnetoresistivity is greater than 100%.
[0013] Preferably, the reference layer is CoFeB with a thickness of 1.0 nm to 1.7 nm; the barrier layer is MgO with a thickness of 0.8 nm to 0.9 nm; and the free layer is CoFeB with a thickness of 0.8 nm to 1.5 nm.
[0014] Furthermore, during ignition, the isolating switch is turned on, and the reference magnetic tunnel junction and the spin-transfer torque magnetic tunnel structure form a series voltage divider structure. The synchronous change of their resistance values with the environment is used to cancel common-mode noise. The change of the voltage divider level, i.e., the ratio of their resistance values, causes the inverter to output a pulse signal.
[0015] Furthermore, during the integration process, the isolation switch is turned off, and current is injected into the core computing unit to drive the magnetic moment to precession during integration.
[0016] Furthermore, during the reset process, the direction of the current flowing through the core computing unit is completely opposite to that of the integration process, forcing the magnetization state of the core computing unit back to the initial low-resistance state, thus completing the reset.
[0017] Furthermore, the core computing unit includes a second magnetic tunnel junction MTJ2; the reference read branch includes a first magnetic tunnel junction MTJ1 as a reference magnetic tunnel junction and a second transistor M2 as a read isolation switch. The first magnetic tunnel junction MTJ1 is fixed in a low-resistance state as a reference resistor, and the second transistor M2 serves as a control switch for the first magnetic tunnel junction MTJ1; the read / write drive module includes a first transistor M1, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and an inverter Invert. The four transistors are used to control the on / off state and direction of current to achieve integration, ignition, and reset operations, and the inverter serves as the output terminal of the pulse signal.
[0018] Furthermore, the power supply voltage VDD is connected to the source of the first transistor M1 and the top electrode of the first magnetic tunnel junction MTJ1, respectively; the drain of the first transistor M1 is directly connected to the common node A; the bottom electrode of the first magnetic tunnel junction MTJ1 is connected to the drain of the second transistor M2, and the source of the second transistor M2 is also connected to the common node A; the drain of the third transistor M3, the top electrode of the second magnetic tunnel junction MTJ2, and the input of the inverter Invert are all connected to the common node A, and the source of the third transistor M3 is grounded; the bottom electrode of the second magnetic tunnel junction MTJ2 is connected to the common node B, and the common node B is connected to the drain of the fourth transistor M4 and the drain of the fifth transistor M5, respectively; the source of the fourth transistor M4 is connected to the power supply VDD, and the source of the fifth transistor M5 is grounded.
[0019] Furthermore, by controlling the conduction states of the first transistor M1 to the fifth transistor M5, the integration, ignition, and reset processes of the neuron circuit are realized:
[0020] Integration process: Turn on the first transistor M1 and the fifth transistor M5, turn off the second transistor M2, the third transistor M3 and the fourth transistor M4. The current starts from the power supply VDD, flows through the first transistor M1, the common node A, the second magnetic tunnel junction MTJ2, the common node B, and the fifth transistor M5 in sequence, and finally flows into ground GND. The spin torque generated by the current drives the free layer magnetic moment of the second magnetic tunnel junction MTJ2 to deflect.
[0021] Ignition process: The second transistor M2 and the fifth transistor M5 are turned on, while the first transistor M1, the third transistor M3, and the fourth transistor M4 are turned off. The current starts from the power supply VDD and flows sequentially through the first magnetic tunnel junction MTJ1, the second transistor M2, the common node A, the second magnetic tunnel junction MTJ2, the common node B, and the fifth transistor M5, finally flowing into ground GND. When the integral reaches the threshold, the second magnetic tunnel junction MTJ2 switches to a high-resistance state. The first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 form a series voltage divider structure, the voltage of the common node A increases, and the inverter outputs a pulse signal.
[0022] During the reset process, the third transistor M3 and the fourth transistor M4 are turned on, while the first transistor M1, the second transistor M2, and the fifth transistor M5 are turned off. The current starts from the power supply VDD and flows sequentially through the fourth transistor M4, the common node B, the second magnetic tunnel junction MTJ2, the common node A, and the third transistor M3, finally flowing into ground GND. The direction of the current flowing through the second magnetic tunnel junction is opposite to that of the integration process, forcing the magnetization state of the second magnetic tunnel junction MTJ2 back to the initial low-resistance state, thus completing the reset.
[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0024] 1. This invention utilizes a physically homogeneous reference magnetic tunnel junction (Ref-MTJ) as a "twin reference." When faced with temperature drift or process variations, the resistance values of the reference and computational magnetic tunnel junctions change in the same direction, maintaining a stable resistance ratio between them, thus canceling common-mode interference and stabilizing the neuron's firing threshold. This self-reference mechanism effectively suppresses environmental noise without requiring complex temperature compensation circuitry, significantly improving the firing accuracy of the neuron circuit under harsh conditions. The read / write path separation design, achieved through a read isolation switch, ensures that large currents do not flow through the reference path during the integration (write) phase, protecting the reference junction's state; simultaneously, it restricts the current path during the read phase, preventing accidental rewriting of the neuron's integration state by the read current.
[0025] 2. This invention eliminates the need for large-area analog devices such as operational amplifiers, achieving highly robust differential readout simply by adding a reference junction (MTJ) and a simple switching transistor. This minimalist circuit structure maximizes the high-density advantage of magnetic components, significantly saving chip area and reducing power consumption, making it suitable for integrated applications of large-scale spiking neural network arrays. Attached Figure Description
[0026] Figure 1 A schematic diagram of the spin-transfer torque magnetic tunnel junction (STT-MTJ) in an anti-interference magnetic tunnel junction pulse neuron circuit provided by the present invention;
[0027] Figure 2 This invention provides a schematic diagram of the structure of an anti-interference magnetic tunnel junction pulse neuron circuit.
[0028] Figure 3 This is a simulation waveform diagram of the leakage integral (LIF) characteristics of the neuron circuit under a subcritical pulse sequence in an embodiment of the present invention;
[0029] Figure 4 This is a timing waveform diagram of the triggering, ignition, and reset process of the neuron circuit in an embodiment of the present invention. Detailed Implementation
[0030] The technical solution of the present invention will be described in detail below with reference to specific embodiments. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and are therefore only examples, and should not be used to limit the scope of protection of the present invention.
[0031] like Figure 1 The diagram shown is a schematic representation of the spin-transfer torque magnetic tunneling junction (STT-MTJ) in an anti-interference magnetic tunneling junction pulse neuron circuit provided by this invention. The spin-transfer torque magnetic tunneling junction is a magnetic tunneling junction with perpendicular magnetic anisotropy (PMA), comprising a reference layer, a barrier layer, and a free layer stacked sequentially.
[0032] Reference layer: Has a fixed magnetization direction, serving as a reference for spin polarization. The preferred material is CoFeB, with a thickness of 1.0 nm to 1.7 nm. Barrier layer: Serves as an insulating layer for electron tunneling. MgO is preferred to achieve high tunneling magnetoresistance (TMR), with a thickness of 0.8 nm to 0.9 nm. Free layer: The magnetization direction can be reversed by current drive or thermal perturbation. The preferred material is CoFeB, with a thickness of 0.8 nm to 1.5 nm. This spin-transfer torque magnetic tunnel junction (STT-MTJ) possesses two stable magnetization states: a parallel state (P-state, low resistance) and an antiparallel state (AP-state, high resistance). Electrodes are placed on the top and bottom layers for connection to the circuit.
[0033] Figure 2 The present invention provides a schematic diagram of an anti-interference magnetic tunnel junction pulse neuron circuit, which includes three parts: a core computing unit, a reference reading branch, and a read / write driver module.
[0034] The core computing unit includes the second magnetic tunnel junction MTJ2, which switches between high and low resistance values according to the current drive of the read / write drive module, and performs state judgment in conjunction with the reference read branch.
[0035] The reference read branch includes a first magnetic tunnel junction MTJ1 and a second transistor M2, wherein the first magnetic tunnel junction MTJ1 is fixed in a low-resistance state and serves as a reference resistor; the second transistor M2 serves as a control switch for the first magnetic tunnel junction MTJ1.
[0036] The read / write driver module includes a first transistor M1, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and an inverter Invert; four of the transistors are used to control the on / off state and direction of current to achieve integration, ignition, and reset operations; the inverter serves as the output terminal of the pulse signal.
[0037] Specifically, the anti-interference magnetic tunnel junction pulse neuron circuit includes two MTJ devices, five MOS transistors, and one inverter. For ease of description, the common node connected to the inverter input in the middle of the circuit is called "common node A," and the node below MTJ2 is called "node B." The power supply voltage VDD is connected to the source of the first transistor M1 and the top electrode of the first magnetic tunnel junction MTJ1, respectively. The drain of the first transistor M1 is directly connected to common node A. The bottom electrode of the first magnetic tunnel junction MTJ1 is connected to the drain of the second transistor M2, and the source of the second transistor M2 is also connected to common node A. The drain of the third transistor M3, the top electrode of the second magnetic tunnel junction MTJ2, and the input of the inverter Invert are all connected to common node A, and the source of the third transistor M3 is connected to ground GND. In the lower half of the circuit, the bottom electrode of the second magnetic tunnel junction MTJ2 is connected to a common node B, which is connected to the drain of the fourth transistor M4 and the drain of the fifth transistor M5. The source of the fourth transistor M4 is connected to the power supply VDD, and the source of the fifth transistor M5 is connected to ground GND. Finally, the inverter Invert outputs a corresponding pulse signal by detecting the potential change of the common node A.
[0038] The present invention provides an anti-interference magnetic tunnel junction pulse neuron circuit, which realizes the integration, ignition and reset processes of the neuron circuit by controlling the conduction state of the first transistor M1 to the fifth transistor M5 respectively.
[0039] Integration Phase: During this phase, the gates of the first transistor M1 and the fifth transistor M5 are connected to an external excitation signal, driving the precession accumulation of the magnetic moment of the second magnetic tunnel junction MTJ2, such as... Figure 3 As shown, under the action of pulsed current, the z-axis component of the magnetic moment exhibits a step-like increase, gradually changing. At this time, M1 and M5 are turned on; M2, M3, and M4 are turned off. The current starts from the power supply VDD, flows sequentially through M1, common node A, MTJ2, common node B, and M5, and finally flows into ground GND. This path bypasses the high-impedance reference read branch (MTJ1 / M2), providing sufficient write current density. The spin-transfer torque (STT) generated by the current drives the free-layer magnetic moment of MTJ2 to gradually deflect, simulating an increase in the film potential.
[0040] Ignition Phase: During this phase, M2 and M5 are turned on; M1, M3, and M4 are turned off. At this time, current flows from the power supply VDD, sequentially through MTJ1, M2, common node A, MTJ2, common node B, and M5, finally flowing into ground GND. When the integral reaches the threshold, the z-axis component of the magnetic moment flips (e.g., ...). Figure 3 As shown), MTJ2 switches to the high impedance state, and MTJ1 and MTJ2 form a series voltage divider at the common node A, which causes the voltage at the common node A to increase, and the inverter outputs a pulse signal.
[0041] Reset Phase: In this phase, the MTJ2 is forcibly restored to its initial state, such as... Figure 4 The diagram shows the process of switching the flipped magnetic moment back to its original state. At this point, M3 and M4 are turned on; M1, M2, and M5 are turned off. Current flows from the power supply VDD, sequentially through M4, common node B, MTJ2, common node A, and M3, finally flowing into ground GND. The current now flows from node B to node A, i.e., from bottom to top through MTJ2. This current, flowing in the opposite direction to the integration phase (injected from VDD into node B via M4, and then discharged to ground via M3), forces the magnetization state of MTJ2 back to its initial low-resistance state, completing the reset.
[0042] With the above design, the circuit can achieve bidirectional read and write operations on MTJ2 using only a unipolar power supply (VDD / GND), and the structure is simple and has anti-interference capability.
Claims
1. An anti-interference magnetic tunneling junction pulse neuron circuit, characterized in that, include: The core computing unit includes a computational magnetic tunnel junction with switchable resistance states, used to integrate the neuronal membrane potential; The reference read branch includes a reference magnetic tunnel junction and a read isolation switch connected in series. The reference read branch is connected to one end of the core computing unit and is used to provide a fixed reference resistance. The read / write driver module connects the core computing unit and the reference read branch, and is used to control the on / off state and direction of current to achieve integration, ignition and reset operations.
2. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 1, characterized in that, The computational magnetic tunnel junction and the reference magnetic tunnel junction have exactly the same material and structure. The resistance of the reference magnetic tunnel junction is fixed in a low-resistance state, while the resistance of the computational magnetic tunnel junction switches between a low-resistance state and a high-resistance state as driven by the current.
3. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 1, characterized in that, The computational magnetic tunnel junction and the reference magnetic tunnel junction include, from bottom to top, a bottom electrode, a free layer, a barrier layer, a reference layer, and a top electrode.
4. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 1, characterized in that, The diameters of the calculated magnetic tunnel junction and the reference magnetic tunnel junction are 20 nm to 60 nm, and the tunneling magnetoresistivity is greater than 100%.
5. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 3, characterized in that, The reference layer is CoFeB with a thickness of 1.0 nm to 1.7 nm; the barrier layer is MgO with a thickness of 0.8 nm to 0.9 nm; and the free layer is CoFeB with a thickness of 0.8 nm to 1.5 nm.
6. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 1, characterized in that, During integration, the disconnect switch is turned off, and current is injected into the computational magnetic tunnel junction to drive the magnetic moment precession during integration. During ignition, the disconnect switch is turned on, and the reference magnetic tunnel junction and the computational magnetic tunnel junction form a series voltage divider structure, and the inverter outputs a pulse signal. During reset, the direction of current flowing through the computational magnetic tunnel junction is completely opposite to that during integration, resetting the magnetization state of the computational magnetic tunnel junction to its initial low-resistance state.
7. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 1, characterized in that, The core computing unit includes a second magnetic tunnel junction (MTJ2); the reference read branch includes a first magnetic tunnel junction (MTJ1) as a reference magnetic tunnel junction and a second transistor (M2) as a read isolation switch. The first magnetic tunnel junction (MTJ1) is fixed in a low-resistance state as a reference resistor, and the second transistor (M2) acts as a control switch for the first magnetic tunnel junction (MTJ1); the read / write drive module includes a first transistor (M1), a third transistor (M3), a fourth transistor (M4), a fifth transistor (M5), and an inverter. The four transistors are used to control the on / off state and direction of current to achieve integration, ignition, and reset operations, and the inverter serves as the output terminal of the pulse signal.
8. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 7, characterized in that, The power supply is connected to the source of the first transistor and the top electrode of the first magnetic tunnel junction, respectively; the drain of the first transistor is directly connected to the common node A; the bottom electrode of the first magnetic tunnel junction is connected to the drain of the second transistor, and the source of the second transistor is connected to the common node A; the drain of the third transistor, the top electrode of the second magnetic tunnel junction, and the input of the inverter are connected to the common node A, and the source of the third transistor is grounded; the bottom electrode of the second magnetic tunnel junction is connected to the common node B, and the common node B is connected to the drain of the fourth transistor and the drain of the fifth transistor, respectively; the source of the fourth transistor is connected to the power supply, and the source of the fifth transistor is grounded.
9. The anti-interference magnetic tunneling junction pulse neuron circuit according to claim 7, characterized in that, By controlling the conduction states of the first to fifth transistors, the integration, ignition, and reset processes of the neuron circuit are realized: Integration process: The first and fifth transistors are turned on, and the second, third and fourth transistors are turned off. The current starts from the power supply and flows sequentially through the first transistor, common node A, second magnetic tunnel junction, common node B, and fifth transistor, and finally flows into the ground. The spin torque generated by the current drives the free layer magnetic moment of the second magnetic tunnel junction to deflect. Ignition process: The second and fifth transistors are turned on, and the first, third and fourth transistors are turned off. The current starts from the power supply and flows sequentially through the first magnetic tunnel junction, the second transistor, common node A, the second magnetic tunnel junction, common node B, and the fifth transistor, and finally flows into the ground. When the integral reaches the threshold, the second magnetic tunnel junction switches to a high-resistance state, and the first magnetic tunnel junction and the second magnetic tunnel structure form a series voltage divider structure, and the inverter outputs a pulse signal. During the reset process, the third and fourth transistors are turned on, while the first, second, and fifth transistors are turned off. Current flows from the power supply, sequentially through the fourth transistor, common node B, the second magnetic tunnel junction, common node A, and the third transistor, and finally flows into ground. The direction of the current flowing through the second magnetic tunnel junction is opposite to that of the integration process, which resets the magnetization state of the second magnetic tunnel junction to its initial low-resistance state.