Spin orbit torque magnetic neuron circuit based on double port cooperative regulation and all pulse neural network chip
By using a dual-port collaborative control of spin-orbit torque magnetic neuron circuit based on three-terminal SOT-MRAM, the problems of large hardware area and high power consumption of CMOS neural networks were solved, achieving efficient integration and low-power operation of the neuron circuit, and constructing a full-pulse neural network chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
- Filing Date
- 2026-04-16
- Publication Date
- 2026-06-19
AI Technical Summary
In the existing technology, the hardware implementation of spiking neural networks based on CMOS computing platforms has problems such as large area, high power consumption and difficulty in high-density integration, and the existing MRAM technology does not fully utilize the potential value of magnetization dynamics in information processing.
A dual-port synergistic control of spin-orbit torque magnetic neuron circuit based on a three-terminal SOT-MRAM structure is adopted. By synergistically controlling the magnetization flipping of the free layer through the spin-orbit torque effect and the spin-transfer torque effect, the threshold control and dynamic integration of the neuron are realized, and a full pulsatile neural network chip is constructed.
It achieves a significant reduction in hardware overhead for neural circuits, maintains a near-zero power consumption state, significantly compresses the area of neural network chips and improves integration, and possesses non-volatile storage and computing integration characteristics.
Smart Images
Figure CN122242592A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the interdisciplinary field of spintronics and neuromorphic computing, specifically involving a spin-orbit torque magnetic neuron circuit and a full-pulse neural network chip based on dual-port collaborative control. Background Technology
[0002] As Moore's Law approaches its physical limits, traditional CMOS computing platforms based on the von Neumann architecture face significant challenges in terms of energy efficiency and integration density, especially in implementing spiking neural networks (SNNs), where power consumption and area overhead become increasingly prominent. SNNs achieve efficient encoding and processing of time information by simulating the "leakage-accumulation-emission-reset" dynamics of biological neurons, placing higher demands on hardware implementation in terms of timing accuracy and energy efficiency.
[0003] In existing technologies, SNN neurons are typically implemented using CMOS circuits, requiring multiple functional modules, such as capacitor charging and discharging circuits, comparators, and reset logic, to work together to approximate the dynamic behavior of neurons. This implementation often relies on a large number of transistor devices, resulting in a large neuron unit area and significant static leakage current, which limits the high-density integration capability of neurons and synapses, and also increases the overall system's energy consumption.
[0004] In recent years, spintronic devices have attracted widespread attention due to their non-volatility, high durability, and nanosecond-level response speed. Among them, magnetic random access memory (MRAM) is considered an important candidate device for realizing in-memory computing and neuromorphic computing. However, existing MRAM-related technologies mainly focus on its application as a binary storage unit, typically using only the magnetization state to represent logic "0" or "1", without fully exploring the potential value of the inherent spin precession, spin damping, and various torque coupling effects in the magnetization dynamics process for information processing.
[0005] Therefore, there is still a lack of an effective hardware solution in the current technology that can directly utilize the spin dynamics characteristics inside magnetic devices to achieve threshold control and dynamic integration behavior of spiking neurons while reducing circuit complexity and power consumption. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a spin-orbit torque magnetic neuron circuit and a full-pulse neural network chip based on dual-port collaborative control. By using magnetization dynamics to simulate the neuronal membrane potential change process, near-zero power consumption state maintenance is achieved while greatly reducing hardware overhead. The dual-port characteristics of the three-terminal SOT-MRAM (Three-Terminal Spin-Orbit Torque MRAM) structure are used to achieve bidirectional control of excitation and inhibition.
[0007] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:
[0008] A spin-orbit torque magnetic neuron circuit based on dual-port collaborative control includes:
[0009] The heavy metal layer, serving as the bottom layer of the neuron circuit, exhibits a spin-orbit coupling effect, with its two ends being the first input terminal and the common ground terminal, respectively.
[0010] A magnetic tunnel junction stacked structure is disposed above the heavy metal layer, comprising a stacked free layer, a barrier layer and a fixed layer, with its top electrode being the second input terminal;
[0011] The neuron circuit receives external input signals through the first and second input terminals. It utilizes the spin orbital moment effect generated by the transverse current flowing through the first input terminal of the heavy metal layer and the spin shift moment effect generated by the longitudinal current flowing through the second input terminal of the magnetic tunnel junction stack to vector superimpose and coordinately regulate the magnetization reversal process of the free layer.
[0012] By controlling the direction and magnitude of the current at the first input terminal, the magnetization reversal process of the free layer driven by the second input terminal can be accelerated or hindered, so as to simulate the threshold regulation, excitatory and inhibitory integral functions of neurons at the physical level.
[0013] To optimize the above technical solution, the specific measures also include:
[0014] When the spin current polarization direction generated by the current direction of the first input terminal is consistent with the target magnetization reversal direction of the free layer, the magnetization reversal barrier of the free layer is reduced, so that under the same second input terminal drive, the energy or time required for the magnetization reversal of the free layer is reduced, corresponding to the accumulation of membrane potential and threshold reduction process of the neuron.
[0015] When the spin current polarization direction generated by the current direction at the first input terminal is opposite to the target magnetization reversal direction of the free layer, the magnetization reversal barrier of the free layer is increased or the precession damping in the opposite direction is generated, so that the magnetization reversal of the free layer is delayed or suppressed, which corresponds to the lateral inhibition mechanism of the neuron.
[0016] The aforementioned neuron circuit possesses complete leakage-accumulation-emission-reset functions;
[0017] During the membrane potential leakage stage, write the enable signal V. w When the circuit is turned on, there is no input current at the first and second input terminals. At this time, the magnetic tunnel junction is not driven by current, and the magnetization state of the free layer gradually returns to its initial state.
[0018] During the membrane potential accumulation phase, write the enable signal V. w When turned on, the first and second input terminals receive input currents respectively, which together act on the magnetic tunnel junction to adjust the magnetization state of the free layer.
[0019] After the accumulation phase ends, write the enable signal V. w Shutdown, enter the transmit phase, read enable signal CLK_R to enable, external voltage V read. R Applying this to a magnetic tunnel junction stack structure, the voltage drop V of the magnetic tunnel junction at this time is detected. m and threshold voltage V th Compare the results and generate the corresponding output spike.
[0020] When a high-level output pulse is detected, it indicates that the magnetic tunnel junction has flipped, the free layer magnetization state has changed, and then the reset phase begins. The reset voltage V... r It acts on the magnetic tunnel junction, restoring the magnetization state of its free layer to its initial state, thus completing the entire process of accumulation-emission-reset of a single neuron.
[0021] A fully spiking neural network chip based on the aforementioned neuron circuit, the spiking neural network chip comprising an input layer, a hidden layer, and an output layer, each layer employing the aforementioned neuron circuit;
[0022] The input layer receives the signal generated by hybrid encoding, and the result of multiplying it with the synaptic weight matrix is injected into the first and second input terminals of the neuron circuit in the hidden layer, respectively.
[0023] In the neuron circuits of the hidden layer and the output layer, the first input terminal receives the sum of the output pulse of the previous neuron circuit and the current after synaptic weighting, which is used to adjust the membrane potential state of the neuron. The second input terminal is connected to the global clock drive signal or the feedforward drive signal, which is used to trigger the neuron in a highly excited state to complete the magnetization flip and emit pulses.
[0024] Multidimensional feature extraction and parallel encoding are performed on the original input data to generate two forms of encoded output signals, which serve as the excitation source for the input layer. After being processed with the weight matrix, they are fed into the first and second input terminals of the neuron circuit in the hidden layer in parallel.
[0025] The aforementioned hybrid coding methods include combinations of direct coding, rate coding, and time coding.
[0026] The aforementioned neuron circuit features non-volatile storage and computation integration. When the chip is in standby mode, the membrane potential state of the neuron is physically preserved through the magnetization angle of the free layer, without the need for an external power supply, thus achieving zero static power consumption.
[0027] The aforementioned chip employs unified write, read, and reset timing control to ensure the synchronization of neuron state updates across layers and the stability of the computation process.
[0028] The present invention has the following beneficial effects:
[0029] This invention proposes a novel magnetic neuron circuit based on a three-terminal spin orbital moment structure. By redefining and functionalizing the physical structure of its input port, a dual-port collaborative control mechanism is introduced to achieve physical-level modeling and control of neuronal excitability and inhibition at the magnetization dynamics level, and based on this, a fully hardware spiking neural network is constructed.
[0030] Specifically, this invention utilizes the geometric asymmetry of three-terminal SOT-MRAM devices to define two functionally orthogonal input ports:
[0031] HM control terminal: Current flows through the heavy metal layer, generating a pure spin current injected into the magnetic layer through the spin Hall effect. The spin-orbit torque provided by this spin current does not directly cause magnetization reversal, but rather modulates the energy barrier of the magnetic free layer. Specifically, when the current is positive, the spin-orbit torque assists in the deflection of the magnetic moment, which is equivalent to lowering the reversal threshold; when the current is negative, the spin-orbit torque inhibits the deflection of the magnetic moment, which is equivalent to raising the reversal threshold.
[0032] MTJ drive terminal: Current flows vertically through the tunnel junction. When the current provided by the HM terminal is high enough, the MTJ terminal can provide a small trigger current to drive the free layer magnetic moment to flip, causing the MTJ resistance to change abruptly.
[0033] After the currents at both ports act together, the voltage drop value V of MTJ is obtained using the reading circuit. m and compare it with the preset threshold V th Real-time comparisons are performed to determine whether a flip has occurred and an output pulse is generated accordingly. If an output pulse is generated, the signal serves as the enable signal for the reset circuit, controlling the neuron to perform a reset operation, restoring its magnetization state to its initial position, thus completing the entire process of "accumulation-emission-reset" for a single neuron.
[0034] The neuron circuit of this invention utilizes the intrinsic evolution of micromagnetic dynamics to simulate the "leakage-accumulation-emission-reset" process of a neuron, eliminating the need for complex CMOS membrane potential integration and comparison circuits, thereby achieving a direct physical mapping between neuron integral and threshold characteristics. Using this neuron circuit as a standard processing unit to construct a deep spiking neural network can significantly reduce the number of transistors in the neuron circuit, thereby achieving a substantial reduction in the overall network chip area and an increase in integration density. Attached Figure Description
[0035] Figure 1 A schematic diagram of a spin-orbit-moment magnetic neuron circuit based on dual-port collaborative modulation provided in an embodiment of the present invention;
[0036] Figure 2 The graph shows the variation of the MTJ flipping critical current density under the action of Input_HM current in different directions, as provided in the embodiments of the present invention.
[0037] Figure 3 The diagram shows the connection topology of a spiking neural network constructed based on a dual-port collaboratively controlled spin-orbit-moment magnetic neuron circuit, as provided in an embodiment of the present invention. Detailed Implementation
[0038] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0039] This invention proposes a spin orbital moment magnetic neuron circuit based on dual-port collaborative control and a full spin spiking neural network chip based on the circuit. This addresses the problem that current mainstream CMOS neuron implementations require the integration of dozens of transistors, such as capacitor charging and discharging circuits, comparators, and reset circuits, resulting in a large overall chip area and severe static leakage current. It also limits the feasibility of high-density synapse integration. The proposed neuron circuit receives external input through a dual-port interface. The bottom heavy metal layer (HM) serves as the first input, and the top electrode of the magnetic tunnel junction (MTJ) serves as the second input. The synergistic effect of the two inputs drives the magnetic moment flip of the free layer. In the proposed all-pulse neural network chip, each network layer adopts a spin-orbit moment magnetic neuron circuit based on dual-port synergistic control. The input layer receives the input data after hybrid encoding processing, performs multiplication and addition operations with the corresponding weights, and injects the results into the two input ports of the neuron circuit. The first input of the hidden layer and output layer neurons receives the weighted current signal from the output pulse of the previous layer neuron, while the second input receives external control input. By controlling the direction of the current at the first input, the triggering process at the second input is accelerated or hindered, thereby simulating the threshold regulation, excitability, and inhibition integral functions of the neuron at the physical level. This overcomes the problems of large area, high power consumption, and volatility of traditional CMOS neuron circuits.
[0040] Specifically, the present invention is based on a spin-orbit torque magnetic neuron circuit with dual-port coordinated control, comprising:
[0041] The heavy metal layer HM, located at the bottom layer of the neuron circuit, exhibits a spin-orbit coupling effect. Spin-orbit coupling is the fundamental physical effect of spin-orbit angular momentum coupling, providing the prerequisite for the conversion of "charge flow to spin flow" for spin-orbit moments. The two ends of the heavy metal layer HM are defined as the first input terminal Input_HM and the common ground terminal GND, respectively.
[0042] A magnetic tunnel junction (MTJ) stacked structure is disposed above the heavy metal layer and includes, in sequence, a free layer, a barrier layer, and a fixed layer, with its top electrode defined as the second input terminal Input_MTJ.
[0043] The neuron circuit has a complete "leak-accumulation-emission-reset" function, can receive two external inputs, and is suitable for spiking neural networks of any size;
[0044] The neuron circuit utilizes the spin orbital moment effect generated by the transverse current flowing through the first input terminal. This spin orbital moment effect refers to the conversion of charge flow into spin current in heavy metal materials, which then acts on the free layer. This effect is vector-superimposed with the spin-transfer torque effect generated by the longitudinal current flowing through the second input terminal. The spin-transfer torque effect refers to the direct transfer of the angular momentum of the spin-polarized current to the magnetic moment of the free layer, thus reversing magnetization. The spin orbital moment effect and the spin-transfer torque effect are parallel magnetic moment reversal mechanisms.
[0045] By controlling the direction and magnitude of the current at the first input terminal, the magnetization and reversal process of the free layer driven by the second input terminal is accelerated or hindered, thereby realizing the threshold regulation and signed synaptic integral function of the neuron.
[0046] In the embodiment, when the spin current polarization direction generated by the current direction of the first input terminal is consistent with the target flipping direction of the free layer, the flipping barrier of the free layer is reduced, so that under the same second input terminal drive, the energy or time required for the magnetization flipping of the free layer is reduced, corresponding to the accumulation of membrane potential and threshold reduction process of the neuron.
[0047] When the spin current polarization direction generated by the current direction at the first input terminal is opposite to the target flip direction of the free layer, the flip barrier of the free layer is increased or the reverse precession damping is generated, so that the magnetization flip of the free layer is delayed or suppressed, corresponding to the lateral inhibition mechanism of the neuron.
[0048] See Figure 1 The figure shows a neuron circuit with a complete "leak-accumulation-emission-reset" function. Figure 1In this circuit, the neuron contains three ports: Input_HM, Input_MTJ, and GND.
[0049] During the membrane potential leakage stage, write the enable signal V. w When the port is turned on, there is no input current in ports Input_HM and Input_MTJ. At this time, MTJ is not driven by current, and the magnetization state of the free layer gradually returns to the initial state.
[0050] During the membrane potential accumulation phase, write the enable signal V. w When enabled, ports Input_HM and Input_MTJ receive input current and work together on MTJ to adjust the magnetization state of the free layer.
[0051] After the membrane potential accumulation phase ends, V w Shut down, proceeding to the launch phase.
[0052] During the transmit phase, the read enable signal CLK_R is activated, and the external read voltage V is activated. R This is applied to the MTJ, and the partial voltage V of the MTJ at this time is detected. m and compare it with the threshold voltage V th The comparison is then used to generate the corresponding output spike.
[0053] When the output pulse Spike is detected to be '1', it indicates that the MTJ has flipped and the free layer magnetization state has changed.
[0054] Then it will immediately enter the reset phase, with the reset voltage V. r It acts on the MTJ, restoring its free layer magnetization state to its initial state.
[0055] Figure 2 This is a graph showing the variation of the MTJ flip-over critical current under different directions of Input_HM current. Rightward current is considered the forward current, and leftward current the reverse current. Figure 2 As shown in (a), under positive current conditions, the critical current density for magnetization reversal of the MTJ gradually decreases with increasing current amplitude. At this time, the spin orbital moment generated by the Input_HM current promotes the free layer magnetic moment, causing it to tilt towards the target reversal direction, thereby reducing the driving current threshold required to achieve magnetization reversal. Figure 2 As shown in (b), under reverse current conditions, the critical current density for magnetization reversal of the MTJ gradually increases with the increase of the current amplitude. At this time, the spin orbital moment generated by the Input_HM current suppresses the reversal process of the free layer magnetic moment, requiring a larger driving current to achieve a change in the magnetization state.
[0056] The above scheme yielded a novel magnetic neuron circuit based on a three-terminal spin orbital moment structure. By redefining and functionalizing the physical structure of its input port and introducing a dual-port collaborative control mechanism, it achieves physical-level modeling and control of neuronal excitability and inhibition at the magnetization dynamics level, and constructs a fully hardware spiking neural network based on this.
[0057] This invention utilizes the geometric asymmetry of three-terminal SOT-MRAM devices to define two functionally orthogonal input ports:
[0058] HM control terminal: Current flows through the heavy metal layer, generating a pure spin current injected into the magnetic layer through the spin Hall effect. The spin-orbit torque provided by this spin current does not directly cause magnetization reversal, but rather modulates the energy barrier of the magnetic free layer. Specifically, when the current is positive, the spin-orbit torque assists in the deflection of the magnetic moment, which is equivalent to lowering the reversal threshold; when the current is negative, the spin-orbit torque inhibits the deflection of the magnetic moment, which is equivalent to raising the reversal threshold.
[0059] MTJ drive terminal: Current flows perpendicularly through the tunnel junction. When the current supplied at the HM terminal is high enough, a small trigger current at the MTJ terminal is sufficient to drive the free layer magnetic moment to flip, causing a sudden change in the MTJ resistance.
[0060] After the currents at both ports act together, the voltage drop value V of MTJ is obtained using the reading circuit. m and compare it with the preset threshold V th Real-time comparisons are performed to determine whether a flip has occurred and an output pulse is generated accordingly. If an output pulse is generated, the signal serves as the enable signal for the reset circuit, controlling the neuron to perform a reset operation, restoring its magnetization state to its initial position, thus completing the entire process of "accumulation-emission-reset" for a single neuron.
[0061] The aforementioned neuron circuit utilizes the intrinsic evolution of micromagnetic dynamics to simulate the "leakage-accumulation-emission-reset" process of neurons, eliminating the need for complex CMOS membrane potential integration and comparison circuits, thereby achieving a direct physical mapping between neuron integral and threshold characteristics.
[0062] Using the aforementioned neuron circuits as standard processing units to construct deep spiking neural networks can significantly reduce the number of transistors in the neuron circuits, thereby achieving a substantial reduction in the overall network chip area and an increase in integration.
[0063] This invention also proposes a hybrid coding method for the input layer in a spiking neural network, comprising:
[0064] Multidimensional feature extraction and parallel encoding processing are performed on the original input data to generate two forms of encoded output signals;
[0065] The hybrid coding method includes, but is not limited to, combinations of direct coding, rate coding, and time coding;
[0066] The encoded output signal serves as the excitation source for the input layer. After being processed with the weight matrix, it is fed into the dual input ports of the next layer of magnetic neuron circuit in parallel.
[0067] The present invention proposes a full pulsatile neural network chip architecture based on the above-mentioned neuron circuit, including an input layer, a hidden layer and an output layer, each layer adopting the above-mentioned dual-port collaboratively controlled spin-orbit-moment magnetic neuron circuit.
[0068] The input layer is configured to receive the encoded input generated by the above-mentioned hybrid encoding method, and inject the result of multiplying it with the synaptic weight matrix into the first input end and the second input end of the neuron, respectively.
[0069] In the neuron circuits of the hidden layer and the output layer, the first input terminal receives the sum of the output pulse of the previous layer neuron and the current after weighting by the synaptic weights, which is used to adjust the membrane potential state of the neuron.
[0070] In the neuron circuits of the hidden layer and the output layer, the second input terminal is connected to a global clock drive signal or a feedforward drive signal to trigger the neuron in a highly excited state to complete the magnetization flip and emit pulses.
[0071] In this embodiment, the spin-orbit-moment magnetic neuron device has the characteristics of non-volatile storage and computing integration. When the chip architecture is in standby mode, the membrane potential state of the neuron is physically preserved through the magnetization angle of the free layer of the magnetic tunnel junction, without the need for an external power supply, thus achieving zero static power consumption.
[0072] Specifically, Figure 3 This is a topology diagram of a spiking neural network constructed based on a dual-port collaboratively modulated spin-orbit-moment magnetic neuron circuit. (Example:) Figure 3 As shown, this spiking neural network adopts a typical three-layer architecture, including an input layer, a hidden layer, and an output layer.
[0073] The input layer is responsible for receiving the input data after hybrid encoding processing. In this embodiment, both direct encoding and rate encoding are used for the input image to achieve parallel representation of temporal and spatial features.
[0074] Both the hidden layer and the output layer employ the proposed three-terminal spin orbital moment magnetic neuron circuit based on dual-port collaborative modulation to replace the traditional single-port input "leaky-integrate-fire" (LIF) neuron.
[0075] In the connection path from the input layer to the hidden layer, the encoded input signal is mixed with the weight W. ij The results of the computation are injected in parallel into the two input terminals of the hidden layer neurons. The magnetic moment of the free layer is flipped through the coordinated regulation of the two inputs, thereby realizing the excitation of the pulse signal.
[0076] In the connection path from the hidden layer to the output layer, the pulse sequence emitted by the hidden layer neurons corresponds to the connection weight W. jk The weighted accumulated current is applied to the first input terminal of the output layer neuron, while an external driving signal is injected into the second input terminal.
[0077] The entire network operates according to a unified "write-read-reset" operation sequence to ensure the synchronization of neuron state updates in each layer and the stability of the computation process.
[0078] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.
Claims
1. A spin-orbit torque magnetic neuron circuit based on dual-port co-regulation, characterized in that, include: The heavy metal layer, serving as the bottom layer of the neuron circuit, exhibits a spin-orbit coupling effect, with its two ends being the first input terminal and the common ground terminal, respectively. A magnetic tunnel junction stacked structure is disposed above the heavy metal layer, comprising a stacked free layer, a barrier layer and a fixed layer, with its top electrode being the second input terminal; The neuron circuit receives external input signals through the first and second input terminals. It utilizes the spin orbital moment effect generated by the transverse current flowing through the first input terminal of the heavy metal layer and the spin shift moment effect generated by the longitudinal current flowing through the second input terminal of the magnetic tunnel junction stack to vector superimpose and coordinately regulate the magnetization reversal process of the free layer. By controlling the direction and magnitude of the current at the first input terminal, the magnetization reversal process of the free layer driven by the second input terminal can be accelerated or hindered, so as to simulate the threshold regulation, excitatory and inhibitory integral functions of neurons at the physical level.
2. The spin-orbit torque magnetic neural circuit based on two-port co-regulation according to claim 1, wherein: When the spin current polarization direction generated by the current direction of the first input terminal is consistent with the target magnetization reversal direction of the free layer, the magnetization reversal barrier of the free layer is reduced, so that under the same second input terminal drive, the energy or time required for the magnetization reversal of the free layer is reduced, corresponding to the accumulation of membrane potential and threshold reduction process of the neuron.
3. The spin-orbit torque magnetic neural circuit based on two-port co-regulation according to claim 1, wherein: When the spin current polarization direction generated by the current direction at the first input terminal is opposite to the target magnetization reversal direction of the free layer, the magnetization reversal barrier of the free layer is increased or the precession damping in the opposite direction is generated, so that the magnetization reversal of the free layer is delayed or suppressed, which corresponds to the lateral inhibition mechanism of the neuron.
4. The spin-orbit torque magnetic neural circuit based on two-port co-regulation according to claim 1, wherein: The neuron circuit has complete leakage-accumulation-emission-reset functions; In the film potential leakage stage, the write enable signal V w When the write enable signal V is turned on, no input current exists in the first input terminal and the second input terminal, at this time, the magnetic tunnel junction is not driven by the current, and the magnetization state of the free layer gradually recovers to the initial state. During the film potential accumulation stage, the write enable signal V w The first input end and the second input end receive input currents respectively, and jointly act on the magnetic tunnel junction for adjusting the magnetization state of the free layer. After the accumulation phase ends, write the enable signal V. w Shutdown, enter the transmit phase, read enable signal CLK_R to enable, external voltage V read. R Applying this to a magnetic tunnel junction stack structure, the voltage drop V of the magnetic tunnel junction at this time is detected. m and threshold voltage V th Compare the results and generate the corresponding output spike. When the output pulse is detected as high, it indicates that the magnetic tunnel junction has been flipped, the free layer magnetization state has changed, and then enters the reset phase, the reset voltage V r acts on the magnetic tunnel junction, so that the free layer magnetization state returns to the initial state, and the whole process of accumulation-firing-reset of a single neuron is completed.
5. An all-spiking neural network chip based on the neuron circuit according to any one of claims 1 to 4, characterized in that: The spiking neural network chip comprises an input layer, a hidden layer, and an output layer, with each layer employing the neuron circuit described above. The input layer receives the signal generated by hybrid encoding, and the result of multiplying it with the synaptic weight matrix is injected into the first and second input terminals of the neuron circuit in the hidden layer, respectively. In the neuron circuits of the hidden layer and the output layer, the first input terminal receives the sum of the output pulse of the previous neuron circuit and the current after synaptic weighting, which is used to adjust the membrane potential state of the neuron. The second input terminal is connected to the global clock drive signal or the feedforward drive signal, which is used to trigger the neuron in a highly excited state to complete the magnetization flip and emit pulses.
6. The all-pulse neural network chip of claim 5, wherein: The hybrid encoding is as follows: multi-dimensional feature extraction and parallel encoding processing are performed on the original input data to generate two forms of encoded output signals, which serve as the excitation source of the input layer. After being processed with the weight matrix, they are fed into the first and second input terminals of the neuron circuit of the hidden layer in parallel.
7. The all-pulse neural network chip of claim 5, wherein: The hybrid coding method includes a combination of direct coding, rate coding, and time coding.
8. The all-pulse neural network chip according to claim 5, characterized in that: The neuron circuit has the characteristics of non-volatile storage and computing integration. When the chip is in standby mode, the membrane potential state of the neuron is physically preserved by the magnetization angle of the free layer, without the need for an external power supply, thus achieving zero static power consumption.
9. The all-pulse neural network chip according to claim 5, characterized in that: The chip employs unified write, read, and reset timing control to ensure the synchronization of neuron state updates across layers and the stability of the computation process.