A standby control system for a primary side feedback AC-DC switching power supply

Abstract

This invention relates to the field of switching power supply control technology, specifically a standby control system for a primary-side feedback AC-DC switching power supply, comprising: signal acquisition and processing, mode control, condition judgment, pulse modulation, and power drive modules. The signal acquisition and processing module acquires and preprocesses the auxiliary winding voltage sampling signal and the main winding current detection signal. The mode control module switches between low-power detection modes based on external commands. The condition judgment module cyclically compares the feedback voltage and primary-side current characterization signals with preset thresholds to determine the deep standby entry conditions. The pulse modulation module employs an improved sleep algorithm based on fuzzy logic to dynamically adjust the pulse and sleep window ratio, generating variable duty cycle and variable frequency drive pulses. This system can accurately determine standby trigger conditions, reduce standby state misjudgments, maintain a constant output voltage, reduce standby power consumption of the switching power supply, and improve the control adaptability of intermittent operation.

Description

Technical Field

[0001] This invention relates to the field of switching power supply control technology, and in particular to a standby control system for a primary-side feedback AC-DC switching power supply. Background Technology

[0002] Standby control in primary-side feedback AC-DC switching power supplies often employs a fixed-parameter pulse sleep modulation structure. Standby triggering is determined by a preset single voltage threshold, and the duty cycle and operating frequency of the drive pulse are fixed values. This type of scheme only collects the auxiliary winding voltage signal as the basis for standby condition judgment. Low-power mode switching of the switching power supply relies on an external fixed trigger command, and the primary winding current signal is not involved in the comprehensive judgment of standby conditions. The switching of the power transistors is controlled by a fixed pulse sequence, and the time ratio between the pulse operating window and the sleep window cannot be adjusted according to the power supply operating conditions.

[0003] Single-signal threshold comparison is prone to misjudgment or omission of standby conditions; fixed-parameter pulse modulation cannot adapt to dynamic load changes; and power consumption control in deep standby mode is limited. A fixed ratio of pulse to sleep window results in unnecessary energy loss; the drive pulse adjustment lacks flexibility during output voltage maintenance; and the mode switching response speed in low-power detection mode is insufficient to meet actual operational requirements.

[0004] The dual-channel electrical signal joint cyclic comparison method was not applied, and the dynamic pulse ratio control method based on fuzzy logic was not integrated into the standby control process of the primary-side feedback switching power supply. The drive pulse sequence could not achieve dynamic variable adjustment of duty cycle and frequency, the determination accuracy of the deep standby state entry condition was insufficient, and the switching power supply could not simultaneously meet the requirements of output voltage stability and low power consumption operation when switching between pulse and sleep states intermittently. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and propose a standby control system for a primary-side feedback AC-DC switching power supply.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a standby control system for a primary-side feedback AC-DC switching power supply, comprising: The signal acquisition and processing module acquires the auxiliary winding voltage sampling signal at the auxiliary winding end of the switching power supply and performs preprocessing to obtain the feedback voltage signal. At the main winding end of the switching transformer, it acquires the current detection signal and performs shaping and conditioning to obtain the primary side current characterization signal. The mode control module receives an external trigger command from the control loop, which instructs the switching power supply to enter or exit the low-power detection mode. The condition judgment module cyclically compares the feedback voltage signal and the primary side current characterization signal with a preset reference threshold to determine whether the switching power supply meets the conditions for entering a deep standby state. The pulse modulation module, when it determines that the condition is met, starts the improved pulse sleep modulation algorithm. The improved pulse sleep modulation algorithm is based on the fuzzy logic control principle, dynamically decides the time ratio of the pulse working window and the sleep window, and generates a driving pulse sequence with variable duty cycle and variable frequency according to the decision parameters output by the improved pulse sleep modulation algorithm. The power drive module uses the drive pulse sequence to control the on and off of the power switching transistor in the switching power supply, so that the switching power supply can work intermittently in pulse state and sleep state while maintaining a basically constant output voltage.

[0007] As a further aspect of the present invention, the auxiliary winding voltage sampling signal is acquired and preprocessed to obtain a feedback voltage signal, including: The auxiliary winding voltage sampling signal is subjected to RC filtering to remove high-frequency switching noise and obtain a preliminary smooth sampling voltage. The initially smoothed sampled voltage is input into a programmable gain amplifier, and the gain factor is automatically adjusted according to the current operating mode of the switching power supply to obtain a voltage signal with normalized amplitude. The amplitude-normalized voltage signal is subjected to analog-to-digital conversion to obtain a digital voltage sample value; The digital voltage sample value is processed using digital filtering technology to suppress power frequency ripple and random interference, and finally output as a steady-state digital voltage quantity as the feedback voltage signal.

[0008] As a further aspect of the present invention, receiving an external trigger command from the control loop, the external trigger command instructing the switching power supply to enter or exit the low-power detection mode, includes: Continuously monitor the load status indication signal from the main power circuit of the switching power supply or the communication command from the secondary controller; When the load status indication signal shows that the load current is lower than the preset light load threshold, or when a clear communication command to enter standby mode is received from the secondary controller, an enable signal indicating entry into the low power detection mode is generated as the external trigger command. In the low-power detection mode, the system continuously monitors load changes or new communication commands. When the load status indicator signal is detected to show that the load current has risen and exceeded the preset wake-up threshold, or when a communication command to exit standby mode is received from the secondary controller, a disable signal indicating exiting the low-power detection mode is generated as a new external trigger command.

[0009] As a further aspect of the present invention, the feedback voltage signal and the primary side current characterization signal are cyclically compared with a preset reference threshold to determine whether the switching power supply meets the conditions for entering a deep standby state, including: Set the lower limit threshold and upper limit threshold of the output voltage corresponding to the feedback voltage signal, and set the light load current threshold corresponding to the primary side current characterization signal; During a continuous detection cycle, it is monitored whether the feedback voltage signal remains within the narrow voltage band defined by the lower threshold of the output voltage and the upper threshold of the output voltage. Within the same detection period, the peak value of the primary current characterization signal is continuously monitored to see if it remains below the light load current threshold. The conditions for entering the deep standby state are met only when the feedback voltage signal is continuously within the narrow voltage band and the peak value of the primary current characterization signal is continuously lower than the light load current threshold, and the conditions are met and exceed the preset number of continuous cycles.

[0010] As a further aspect of the present invention, the improved pulse sleep modulation algorithm is based on the fuzzy logic control principle, dynamically determining the time ratio between the pulse working window and the sleep window, including: The input variables for fuzzy logic control are defined as the deviation between the feedback voltage signal and the center reference voltage and its rate of change, and the output variables are defined as the reference duration of the pulse working window and the reference duration of the sleep window. Membership functions with multiple semantic levels are defined for the deviation and rate of change of the input variables, and membership functions with multiple semantic levels are defined for the pulse working window baseline duration and the sleep window baseline duration of the output variables, respectively. Establish a fuzzy rule base based on expert experience, wherein each rule in the fuzzy rule base takes the semantic level combination of the input variables as a premise and the semantic level combination of the output variables as a conclusion; In each control cycle, the membership degree of the actual value of the input variable to each semantic level is calculated. Based on the fuzzy rule base, the centroid method is used to defuzzify the operation and calculate the values ​​of the reference duration of the pulse working window and the reference duration of the sleep window. The calculated baseline duration of the pulse working window and the baseline duration of the sleep window are finely adjusted in conjunction with the historical load trend of the switching power supply to finally determine the actual duration of the pulse working window and the actual duration of the sleep window for the current cycle, which are then used as the decision parameters.

[0011] As a further aspect of the present invention, the step of fine-tuning the calculated reference duration of the pulse working window and the reference duration of the sleep window in conjunction with the load history trend of the switching power supply includes: Record the reference duration of the pulse working window calculated by the fuzzy logic control in the most recent multiple control cycles to form a reference duration sequence; Perform trend analysis on the reference duration sequence to determine whether the reference duration of the pulse working window shows an increasing trend, a decreasing trend, or a stable trend; If the trend is determined to be upward, a positive time adjustment amount is added to the baseline duration of the dormancy window calculated in the current cycle. If the trend is determined to be downward, then a negative time adjustment amount is reduced from the baseline duration of the sleep window calculated in the current cycle. The duration of the dormant window after trend fine-tuning and the corresponding baseline duration of the pulse working window are used together as the actual duration of the pulse working window and the actual duration of the dormant window.

[0012] As a further aspect of the present invention, based on the decision parameters output by the improved pulse sleep modulation algorithm, a drive pulse sequence with variable duty cycle and variable frequency is generated, including: Based on the actual duration of the pulse working window in the decision parameters, determine the number of driving pulses to be generated within the pulse working window and the preset duty cycle of each driving pulse. Based on the actual duration of the sleep window in the decision parameters, it is determined that no drive pulses will be generated within the sleep window; When the actual duration of the pulse working window is open, the high-frequency clock counter is started, and a corresponding number of drive pulses with fixed pulse widths are generated according to the preset number of pulses and the preset duty cycle. After the last drive pulse is sent, the high-frequency clock counter is turned off, and a silent period with a duration equal to the actual duration of the sleep window is entered. At the end of the quiet period, the actual duration of the pulse working window for the next cycle is restarted, and the number of drive pulses and the preset duty cycle are updated according to the latest decision parameters, thereby forming the drive pulse sequence with variable period and duty cycle.

[0013] As a further aspect of the present invention, based on the actual duration of the pulse working window in the decision parameters, the number of driving pulses to be generated within the pulse working window and the preset duty cycle of each driving pulse are determined, including: The minimum and maximum allowable pulse widths for a single drive pulse, as well as the minimum protection interval between drive pulses, are preset. The theoretical maximum number of pulses is obtained by dividing the actual duration of the pulse working window by the sum of the minimum allowable pulse width and the minimum protection interval. The theoretical minimum number of pulses is obtained by dividing the actual duration of the pulse working window by the sum of the maximum allowable pulse width and the minimum protection interval. Between the theoretical minimum number of pulses and the theoretical maximum number of pulses, an integer is dynamically selected as the actual number of driving pulses in the current window based on the magnitude of the deviation between the feedback voltage signal and the center reference voltage. After deducting the total protection time calculated based on the actual number of drive pulses and the minimum protection interval from the actual duration of the pulse working window, the remaining time is evenly distributed to each drive pulse to obtain the pulse width corresponding to the preset duty cycle of each drive pulse.

[0014] As a further aspect of the present invention, the step of monitoring whether the feedback voltage signal remains within the narrow voltage band defined by the lower threshold and the upper threshold of the output voltage during a continuous detection period includes: Set up a state shift register with multiple memory cells, each memory cell corresponding to a detection cycle; At the end of each detection cycle, the average value of the feedback voltage signal in the current cycle is compared with the lower threshold and the upper threshold of the output voltage. If the average value is greater than the lower threshold of the output voltage and less than the upper threshold of the output voltage, then a logic high level representing that the condition is met is shifted into the state shift register. If the average value is less than or equal to the lower limit threshold of the output voltage or greater than or equal to the upper limit threshold of the output voltage, then a logic low level representing that the condition is not met is shifted into the state shift register; When the values ​​of multiple consecutive storage cells in the state shift register are all at the logic high level, it is determined that the feedback voltage signal is continuously within the narrow voltage band.

[0015] As a further aspect of the present invention, the step of controlling the on and off of the power switching transistor in the switching power supply using the driving pulse sequence includes: The driving pulse sequence is input to the gate driving circuit; The gate driving circuit amplifies the current and converts the level of the driving pulse sequence to generate a gate control voltage that meets the driving requirements of the power switch. The gate control voltage is directly applied to the gate terminal of the power switch to control the power switch's on and off states. Within the pulse operating window, each effective pulse in the drive pulse sequence turns on the power switch once, transferring energy from the input side to the transformer; During the sleep window, the drive pulse sequence has no valid pulses, the gate control voltage remains at the off level, causing the power switch to remain off, and the power stage circuit of the switching power supply stops energy transfer.

[0016] Compared with the prior art, the advantages and positive effects of the present invention are as follows: The feedback voltage signal and the primary side current characterization signal are synchronously involved in a cyclic comparison process of a preset reference threshold. This dual-signal joint judgment method reduces the possibility of false triggering of standby conditions, and improves the matching degree between the standby state judgment result and the actual operating conditions of the switching power supply. The cyclic comparison execution method shortens the response time of standby condition judgment, the timing of entering deep standby state can be adjusted in real time according to load changes, the judgment deviation caused by single signal judgment is reduced, the smoothness of switching power supply mode switching is improved, and the state switching in low-power detection mode is more in line with the actual operating state of the power supply.

[0017] An improved pulse sleep modulation algorithm based on fuzzy logic control can dynamically determine the time ratio between the pulse working window and the sleep window. The drive pulse sequence generated based on the algorithm's decision parameters has the characteristics of variable duty cycle and variable frequency. The drive pulse parameters can be adjusted in real time according to the standby conditions of the switching power supply, and the on / off control of the power switching transistors is more adapted to the requirements of deep standby operation. When the switching power supply intermittently switches between pulse and sleep states, the stability of the output voltage is better maintained, the energy loss redundancy caused by fixed pulse parameters is reduced, the continuity of the switching between pulse and sleep states is improved, the range of drive pulse regulation is expanded, the adaptability of standby control under different load conditions is enhanced, and the energy consumption of the power supply during the standby phase is reasonably controlled. Attached Figure Description

[0018] Figure 1 This is a timing diagram of a standby control system for a primary-side feedback AC-DC switching power supply according to the present invention. Figure 2 A flowchart for the preprocessing of auxiliary winding voltage sampling signals; Figure 3 This is a flowchart for determining the conditions for deep standby state. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] In the description of this invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, in the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] See Figure 1 This invention provides a standby control system for a primary-side feedback AC-DC switching power supply, specifically comprising: The signal acquisition and processing module acquires the auxiliary winding voltage sampling signal at the auxiliary winding end of the switching power supply and performs preprocessing to obtain the feedback voltage signal. At the main winding end of the switching transformer, it acquires the current detection signal and performs shaping and conditioning to obtain the primary side current characterization signal. The mode control module receives an external trigger command from the control loop, which instructs the switching power supply to enter or exit the low-power detection mode. The condition judgment module compares the feedback voltage signal, the primary side current characterization signal, and a preset reference threshold in a loop to determine whether the switching power supply meets the conditions for entering the deep standby state. When the pulse modulation module determines that the conditions are met, it starts an improved pulse sleep modulation algorithm. This algorithm is based on the fuzzy logic control principle, dynamically decides the time ratio of the pulse working window and the sleep window, and generates a drive pulse sequence with variable duty cycle and variable frequency according to the decision parameters output by the algorithm. The power drive module uses the drive pulse sequence to control the on and off of the power switching transistors in the switching power supply, so that the switching power supply operates intermittently in pulse state and sleep state while maintaining a basically constant output voltage.

[0022] In one embodiment of the present invention, the signal acquisition and processing module acquires the auxiliary winding voltage sampling signal and performs preprocessing to obtain a feedback voltage signal, including: (see reference) Figure 2 The auxiliary winding voltage sampling signal is subjected to RC filtering to remove high-frequency switching noise and obtain a preliminary smoothed sampling voltage. The preliminary smoothed sampling voltage is input into a programmable gain amplifier, and the gain is automatically adjusted according to the current operating mode of the switching power supply to obtain a voltage signal with normalized amplitude. The normalized voltage signal is converted from analog to digital to obtain a digital voltage sampling value. Digital filtering technology is used to process the digital voltage sampling value to suppress power frequency ripple and random interference, and the output is a steady-state voltage digital quantity as a feedback voltage signal.

[0023] In the mode control module, an external trigger command is received from the control loop. This external trigger command instructs the switching power supply to enter or exit the low-power detection mode. This includes: continuously monitoring the load status indication signal from the main power circuit of the switching power supply or the communication command from the secondary controller; when the load status indication signal shows that the load current is lower than a preset very light load threshold, or when a clear communication command to enter standby mode is received from the secondary controller, an enable signal indicating entry into the low-power detection mode is generated as an external trigger command; in the low-power detection mode, the load changes or new communication commands are continuously monitored; when the load status indication signal shows that the load current rises and exceeds a preset wake-up threshold, or when a communication command to exit standby mode is received from the secondary controller, a disable signal indicating exit from the low-power detection mode is generated as a new external trigger command.

[0024] In practice, the process of acquiring the auxiliary winding voltage sampling signal and preprocessing it to obtain the feedback voltage signal is achieved through a multi-stage processing link to obtain high-precision signal acquisition. The auxiliary winding voltage sampling signal is filtered by an RC filter network to remove high-frequency switching noise and obtain a preliminary smooth sampling voltage. This sampling voltage is then connected to the input of a programmable gain amplifier. The programmable gain amplifier automatically adjusts the gain factor according to the current operating mode of the switching power supply and outputs a voltage signal with normalized amplitude. This normalized voltage signal is sent to an analog-to-digital converter to be converted into a digital voltage sampling value. The digital filtering unit performs power frequency ripple suppression and random interference filtering on the digital voltage sampling value and outputs a steady-state voltage digital quantity as the feedback voltage signal. In some embodiments, the RC filter network consists of series resistors and parallel capacitors, and its cutoff frequency is configured to be more than ten times higher than the switching frequency of the switching power supply to retain voltage envelope information. The gain switching logic of the programmable gain amplifier is associated with the operating mode of the switching power supply. When the switching power supply is operating in normal mode, the gain is set to a low level. When entering standby detection mode, the gain is switched to a high level to accommodate small-amplitude voltage sampling. The analog-to-digital converter samples and quantizes the normalized voltage signal at a frequency not less than twice the power frequency. The digital filtering unit uses a moving average filtering algorithm to smooth the digital voltage sample value, eliminate voltage fluctuations caused by the power frequency cycle, and outputs a steady-state voltage digital quantity for subsequent condition judgment.

[0025] In practical implementation, the mode control module receives external trigger commands from the control loop to manage the low-power detection mode state. The load status indicator signal reflects the load current of the main power circuit in real time through the current sampling resistor and differential amplifier circuit. The secondary controller sends communication commands through the optocoupler isolation channel. When the load current value displayed by the load status indicator signal is lower than the preset extremely light load threshold, the comparator output level flips to generate an enable signal indicating entry into the low-power detection mode. Alternatively, when the decoding circuit recognizes the communication command to enter standby mode sent by the secondary controller, it directly generates the enable signal as an external trigger command. During the activation of the low-power detection mode, the mode control module continuously monitors the changing trend of the load status indicator signal and the secondary communication channel. When the load current displayed by the load status indicator signal rises above the preset wake-up threshold, or when it receives the communication command to exit standby mode from the secondary controller, the mode control module generates a disable signal indicating exit from the low-power detection mode, which triggers the system state switch as an updated external trigger command.

[0026] In practical implementation, the gain adjustment strategy of the programmable gain amplifier is tied to the operating mode of the switching power supply. When the switching power supply is under heavy load or normal operation, the auxiliary winding voltage amplitude is high, and the programmable gain amplifier adopts unity gain or low gain to prevent signal saturation. When the switching power supply enters light load or standby detection mode, the auxiliary winding voltage amplitude is significantly reduced, and the programmable gain amplifier switches to high gain to improve the resolution of small signals. The gain switching trigger condition can be realized through an internal state machine. When the feedback voltage signal is lower than the set threshold for several consecutive cycles, the gain upgrade is automatically triggered to ensure that an effective feedback voltage signal can be obtained under different load conditions.

[0027] In practical implementation, the digital filtering process employs a weighted moving average algorithm. This algorithm sums and averages the digital voltage samples over N consecutive cycles. The weighting coefficients are related to the sampling time, with more recent samples given higher weights to reduce hysteresis. The update frequency of the filtered output is synchronized with the switching cycle of the power supply, updating the filtering result once per switching cycle to ensure the real-time performance and stability of the feedback voltage signal. The moving average window length N is matched to the power frequency cycle, satisfying the following relationship:

[0028] in: This indicates the switching frequency of the switching power supply. This represents the power grid frequency. By setting the window length, the power frequency ripple component can be effectively suppressed, and DC and low-frequency voltage information can be extracted.

[0029] In practical implementation, the logic for generating external trigger commands is integrated into the digital processing unit of the mode control module. The extremely light load threshold and wake-up threshold are configurable through registers to adapt to the needs of different power supply specifications. The sampling rate of the load status indication signal is synchronized with the switching frequency. The load current is sampled once in each switching cycle and compared with the threshold. The comparison result is latched into the status register. Only when multiple consecutive sampling results meet the trigger conditions is the enable signal or disable signal generated to avoid false triggering due to instantaneous disturbances. The communication commands of the secondary controller are transmitted in Manchester encoding format and transmitted to the primary side through optocoupler isolation. The decoding circuit extracts the command content after verifying the frame header and check bit to ensure the correct recognition of the communication command.

[0030] In one embodiment of the present invention, the feed voltage signal, the primary side current characterization signal, and a preset reference threshold are cyclically compared to determine whether the switching power supply meets the conditions for entering a deep standby state. (See also...) Figure 3 Set the lower and upper threshold values ​​of the output voltage corresponding to the feedback voltage signal, and set the light load current threshold value corresponding to the primary side current characterization signal. During a continuous detection cycle, monitor whether the feedback voltage signal is continuously within the narrow voltage band defined by the lower and upper threshold values ​​of the output voltage. During the same detection cycle, synchronously monitor whether the peak value of the primary side current characterization signal is continuously lower than the light load current threshold value. Only when the conditions of the feedback voltage signal being continuously within the narrow voltage band and the peak value of the primary side current characterization signal being continuously lower than the light load current threshold value are met and exceed the preset number of continuous cycles, it is determined that the conditions for entering the deep standby state are met.

[0031] During a continuous detection cycle, monitoring whether the feedback voltage signal remains within a narrow voltage band defined by the lower and upper thresholds of the output voltage includes: setting up a state shift register with multiple storage units, each corresponding to a detection cycle; at the end of each detection cycle, comparing the average value of the feedback voltage signal in the current cycle with the lower and upper thresholds of the output voltage; if the average value is greater than the lower threshold and less than the upper threshold, shifting a logic high level representing that the condition is met into the state shift register; if the average value is less than or equal to the lower threshold or greater than or equal to the upper threshold, shifting a logic low level representing that the condition is not met into the state shift register; when the values ​​of multiple consecutive storage units in the state shift register are all logic high, it is determined that the feedback voltage signal remains within the narrow voltage band.

[0032] In practice, the condition judgment module performs a cyclic comparison of the feedback voltage signal, the primary current characterization signal, and a preset reference threshold to assess whether the deep standby condition is met. The lower and upper limits of the output voltage are set through internal registers and matched with the dimensions of the feedback voltage signal. The light load current threshold is configured according to the rated capacity of the switching power supply and uses the peak value of the primary current characterization signal as a reference. In a continuous detection cycle, the condition judgment module synchronously acquires the periodic sample value of the feedback voltage signal and the peak sample value of the primary current characterization signal. The sample value of the feedback voltage signal is compared with the lower and upper limits of the output voltage, and the peak sample value of the primary current characterization signal is compared with the light load current threshold. When the feedback voltage signal is in a narrow voltage band between the lower and upper limits of the output voltage and the peak value of the primary current characterization signal is lower than the light load current threshold in the same detection cycle, the detection cycle is marked as a candidate cycle. Only when more than a preset number of detection cycles are marked as candidate cycles, the condition judgment module determines that the condition for entering the deep standby state is met and outputs an enable signal.

[0033] In practical implementation, the function of monitoring whether the feedback voltage signal is continuously within a narrow voltage band is implemented through a state shift register. The state shift register contains M binary storage units, each corresponding to the judgment result of a detection cycle. The duration of the detection cycle is aligned with the power frequency cycle of the switching power supply to ensure sampling consistency. At the end of each detection cycle, the calculation module calculates the arithmetic mean of the sampling sequence of the feedback voltage signal in the current cycle to obtain the cycle average voltage. The comparator compares the cycle average voltage with the lower threshold and the upper threshold of the output voltage at the same time. If the cycle average voltage is greater than the lower threshold and less than the upper threshold, a logic high level representing that the condition is met is shifted into the state shift register; otherwise, a logic low level representing that the condition is not met is shifted in. The state shift register uses a first-in-first-out strategy to update the stored content. When the latest shifted-in logic high level makes the values ​​of N consecutive storage units in the state shift register all logic high, it is determined that the feedback voltage signal is continuously within a narrow voltage band.

[0034] In some embodiments, the total number of bits M of the state shift register is set to be greater than or equal to a preset number of duration cycles to ensure that enough historical states can be recorded for continuous judgment. The update timing of the state shift register is synchronized with the end edge of the detection cycle. Only one shift operation is performed in each detection cycle to avoid multiple updates within a detection cycle that could lead to misjudgment of the state. The initial state of the state shift register is reset to all logic low levels to ensure that the system will not be immediately misjudged as meeting the conditions at the initial power-up stage.

[0035] In some embodiments, the preset number of duration cycles is stored in non-volatile memory and can be adjusted online to adapt to the response characteristics of different power supply systems. The range of the preset number of duration cycles is related to the number of power frequency cycles, and usually covers at least several power frequency cycles to filter instantaneous voltage fluctuations. The average value of the feedback voltage signal is calculated using lossless fixed-point arithmetic to avoid floating-point errors affecting the accuracy of the judgment. The comparator output is written to the state shift register after glitching filtering to prevent comparator jitter from causing state jumps.

[0036] In specific implementation, the decision logic for continuous high-level logic in the state shift register is implemented through combinational logic circuits. The criterion for the number of consecutive cycles that meet the condition is configured through parameter N. When the value of the latest N bits in the state shift register matches the mask template, a decision-making signal is output. This decision-making signal is logically ANDed with the result of the continuous judgment of the peak value of the primary side current characterization signal to finally generate a deep standby condition satisfaction flag. It can be understood that the number of bits M in the state shift register and the number of consecutive cycles N required for the decision satisfy the constraint relationship N≤M to ensure the feasibility of the decision logic.

[0037] In practice, the persistence determination of the primary current characterization signal peak value adopts an independent state recording mechanism. Within each detection cycle, the maximum value is captured as the periodic peak value within the peak sampling window of the primary current characterization signal. The result of comparing the periodic peak value with the light load current threshold is stored in the peak state queue. The length of the peak state queue is equal to the preset number of duration cycles. When all records in the peak state queue indicate that the periodic peak value is lower than the light load current threshold, it is determined that the primary current characterization signal peak value continuously meets the condition. The update strategy of the peak state queue is synchronized with the state shift register, and the two together determine the achievement of the deep standby condition.

[0038] It is understandable that the hardware implementation of the state shift register can adopt a flip-flop chain structure, with each storage cell consisting of a D flip-flop. The clock signal is provided by a detection period timer, the data input is connected to the comparator output, and the outputs of each flip-flop are connected to the continuous state detection logic. The continuous state detection logic is implemented through a multi-input AND gate. When the corresponding consecutive N bit outputs are all high, the effective level of the AND gate output indicates that the feedback voltage signal is continuously within a narrow voltage band. This implementation method has a simple structure and fast response.

[0039] In one embodiment of the present invention, the improved pulse sleep modulation algorithm is based on the principle of fuzzy logic control, dynamically deciding the time ratio of the pulse working window and the sleep window, including: defining the input variables of the fuzzy logic control as the deviation between the feedback voltage signal and the center reference voltage and its rate of change, and defining the output variables as the reference duration of the pulse working window and the reference duration of the sleep window; defining membership functions including multiple semantic levels for the deviation and its rate of change of the input variables, and defining membership functions including multiple semantic levels for the reference duration of the pulse working window and the reference duration of the sleep window of the output variables; establishing a model based on expert experience. A fuzzy rule base is used, where each rule takes the semantic level combination of the input variables as a premise and the semantic level combination of the output variables as a conclusion. In each control cycle, the membership degree of the actual value of the input variable with respect to each semantic level is calculated. Based on the fuzzy rule base, the centroid method is used to defuzzify the operation and calculate the reference duration of the pulse working window and the reference duration of the sleep window. The calculated reference duration of the pulse working window and the reference duration of the sleep window are then fine-tuned in conjunction with the historical load trend of the switching power supply to finally determine the actual duration of the pulse working window and the actual duration of the sleep window for the current cycle, which serve as decision parameters.

[0040] The calculated baseline duration of the pulse working window and the baseline duration of the sleep window are fine-tuned in conjunction with the historical load trend of the switching power supply. This includes: recording the baseline duration of the pulse working window calculated by fuzzy logic control in the most recent control cycles to form a baseline duration sequence; performing trend analysis on the baseline duration sequence to determine whether the baseline duration of the pulse working window shows an increasing trend, a decreasing trend, or a stable trend; if it is determined to be an increasing trend, a positive time fine-tuning amount is added to the baseline duration of the sleep window calculated in the current cycle; if it is determined to be a decreasing trend, a negative time fine-tuning amount is reduced to the baseline duration of the sleep window calculated in the current cycle; the sleep window duration after trend fine-tuning and the corresponding baseline duration of the pulse working window are used together as the actual duration of the pulse working window and the actual duration of the sleep window.

[0041] In its implementation, the improved pulse sleep modulation algorithm dynamically determines the time ratio of the pulse working window and the sleep window based on the fuzzy logic control principle. The input variables of the fuzzy logic control are defined as the deviation between the feedback voltage signal and the center reference voltage, and the rate of change of the deviation between the feedback voltage signal and the center reference voltage. The output variables are defined as the reference duration of the pulse working window and the reference duration of the sleep window. The deviation of the input variables is divided into five semantic levels: negative large, negative small, zero, positive small, and positive large. The rate of change of the deviation of the input variables is divided into three semantic levels: negative, zero, and positive. The reference duration of the pulse working window of the output variables is divided into three semantic levels: short, medium, and... The duration of the output variable's sleep window reference is divided into three semantic levels: short, medium, and long. A triangular membership function is used to describe the membership distribution of each semantic level. The membership function parameter of the input variable deviation covers the maximum expected offset range between the feedback voltage signal and the center reference voltage. The membership function parameter of the input variable deviation change rate covers the maximum change amplitude of the deviation between adjacent control cycles. The membership function parameter of the output variable pulse working window reference duration covers the minimum to maximum allowable pulse working window duration range of the switching power supply. The membership function parameter of the output variable sleep window reference duration covers the minimum to maximum allowable sleep window duration range of the switching power supply.

[0042] In practical implementation, a fuzzy rule base based on expert experience is established. Each rule in the fuzzy rule base takes the semantic level of the input variable deviation and the semantic level combination of the input variable deviation change rate as premises, and the semantic level combination of the output variable pulse working window baseline duration and the output variable dormant window baseline duration as conclusions. The fuzzy rule base contains fifteen rules; some rules are shown in Table 1. Table 1: Partial Rule Tables of the Fuzzy Rule Base

[0043] In each control cycle, the membership degree of the actual value of the input variable deviation to each semantic level is calculated, as is the membership degree of the actual value of the rate of change of the input variable deviation to each semantic level. Rule matching is performed according to the fuzzy rule base, activating all rules that meet the prerequisites. The centroid method is used for defuzzification to calculate the precise values ​​of the pulse working window reference duration and the sleep window reference duration. The centroid method calculation formula is as follows:

[0044] in: This indicates the output variable value of the solution, namely the duration of the pulse working window reference or the duration of the sleep window reference. This indicates the total number of active rules. This represents the membership product of the i-th activation rule, i.e., the antecedent matching degree. This represents the output semantic level center value corresponding to the conclusion of the i-th activation rule.

[0045] In practical implementation, the calculated pulse working window reference duration and sleep window reference duration are fine-tuned by combining them with the historical load trend of the switching power supply. The pulse working window reference duration calculated by fuzzy logic control in the last ten control cycles is recorded to form a reference duration sequence. Linear regression analysis is performed on the reference duration sequence, and the fitting slope characterizes the changing trend of the pulse working window reference duration. If the fitting slope is greater than zero, it is judged as an increasing trend; if the fitting slope is less than zero, it is judged as a decreasing trend; if the absolute value of the fitting slope is less than the set tolerance, it is judged as a stable trend. If it is judged as an increasing trend, a positive time fine-tuning amount is added to the sleep window reference duration calculated in the current cycle; if it is judged as a decreasing trend, a negative time fine-tuning amount is reduced to the sleep window reference duration calculated in the current cycle. The absolute value of the time fine-tuning amount is proportional to the absolute value of the fitting slope. The sleep window duration after trend fine-tuning and the corresponding pulse working window reference duration are used together as the actual pulse working window duration and sleep window duration of the current cycle and output to the pulse modulation module.

[0046] In some embodiments, the input variable deviation of fuzzy logic control is defined by the difference between the feedback voltage signal and the center reference voltage. The deviation change rate is calculated by subtracting the deviation of the previous control cycle from the deviation of the current control cycle and then dividing by the control cycle duration. The control cycle duration is fixed as an integer multiple of the power frequency cycle of the switching power supply to ensure the consistency of the control response. The center reference voltage is set according to the equivalent voltage value of the target output voltage of the switching power supply converted to the auxiliary winding side, and is calibrated and stored in non-volatile memory at the factory.

[0047] In some embodiments, the parameters of the membership function are determined through simulation optimization and stored in the read-only memory of the control chip. In practical applications, they can be adjusted through the configuration interface according to the power supply model. The membership function parameter setting of the deviation change rate makes it insensitive to small changes caused by power frequency ripple, and only produces a significant response to rapid deviation changes caused by load mutations, thereby enhancing the anti-interference capability of fuzzy control. It can be understood that the design of the fuzzy rule base follows the physical law of output voltage regulation. When the feedback voltage signal is lower than the center reference voltage and the deviation is large, it is necessary to extend the pulse working window and shorten the sleep window to improve energy transfer. Conversely, the pulse working window is shortened and the sleep window is extended to reduce output. The introduction of the deviation change rate can predict the direction of voltage change in advance and adjust the time ratio before the deviation increases significantly, thereby improving dynamic response performance. It is understandable that the load history trend fine-tuning mechanism is equivalent to superimposing integral correction on the basis of fuzzy control. When the duration of the pulse working window benchmark continues to increase, it indicates that the load is on the rise. At this time, increasing the amount of sleep window fine-tuning is essentially reserving more energy reserves to cope with possible future load increases. Conversely, reducing the sleep window can speed up the response speed. This design can improve the adaptability of standby control without significantly increasing computational complexity.

[0048] In one embodiment of the present invention, the pulse modulation module generates a drive pulse sequence with variable duty cycle and variable frequency based on decision parameters output by the improved pulse sleep modulation algorithm. This includes: determining the number of drive pulses to be generated within the pulse working window and the preset duty cycle of each drive pulse based on the actual duration of the pulse working window in the decision parameters; determining that no drive pulses will be generated within the sleep window based on the actual duration of the sleep window in the decision parameters; starting a high-frequency clock counter when the actual duration of the pulse working window is open, and generating a corresponding number of drive pulses with fixed pulse widths based on the preset number of pulses and the preset duty cycle; turning off the high-frequency clock counter after the last drive pulse is sent, entering a silent period with a duration equal to the actual duration of the sleep window; and reopening the actual duration of the pulse working window for the next cycle at the end of the silent period, updating the number of drive pulses and the preset duty cycle based on the latest decision parameters, thereby forming a drive pulse sequence with variable period and duty cycle.

[0049] Based on the actual duration of the pulse working window in the decision parameters, determine the number of drive pulses to be generated within the pulse working window and the preset duty cycle of each drive pulse, including: the preset minimum and maximum allowable pulse width of a single drive pulse, and the minimum protection interval between drive pulses; divide the actual duration of the pulse working window by the sum of the minimum allowable pulse width and the minimum protection interval to obtain the theoretical maximum number of pulses; divide the actual duration of the pulse working window by the sum of the maximum allowable pulse width and the minimum protection interval to obtain the theoretical minimum number of pulses; between the theoretical minimum number of pulses and the theoretical maximum number of pulses, dynamically select an integer as the actual number of drive pulses in the current window based on the magnitude of the deviation between the feedback voltage signal and the center reference voltage; after deducting the total protection time calculated based on the actual number of drive pulses and the minimum protection interval from the actual duration of the pulse working window, distribute the remaining time evenly to each drive pulse to obtain the pulse width corresponding to the preset duty cycle of each drive pulse.

[0050] In practical implementation, the pulse modulation module generates a drive pulse sequence based on the decision parameters output by the improved pulse sleep modulation algorithm. These decision parameters include the actual duration of the pulse working window and the actual duration of the sleep window. Based on the actual duration of the pulse working window, the module determines the number of drive pulses to be generated within the current pulse working window and the preset duty cycle for each drive pulse. Based on the actual duration of the sleep window, the module determines that no drive pulses will be generated within the corresponding sleep window. At the start of the actual duration of the pulse working window, the pulse modulation module starts its internal high-frequency clock counter and, based on the preset number of drive pulses and the preset duty cycle, generates a corresponding number of drive pulses with specific characteristics. A drive pulse with a fixed pulse width is used, and the rising and falling edges of the drive pulse are aligned with the count value of the high-frequency clock counter to ensure timing accuracy. After the last drive pulse is sent, the pulse modulation module turns off the high-frequency clock counter and enters a silent period with a duration strictly equal to the actual duration of the sleep window. During the silent period, all drive pulse output ports remain at an invalid level. At the end of the silent period, the pulse modulation module restarts the pulse working window for the next cycle and updates the number of drive pulses and the preset duty cycle of the current window according to the latest decision parameters, thereby forming a drive pulse sequence with a variable overall period and duty cycle.

[0051] In practical implementation, the process of determining the number of driving pulses and the preset duty cycle of each driving pulse based on the actual duration of the pulse working window adopts a parameterized calculation method. The minimum and maximum allowable pulse widths of a single driving pulse, as well as the minimum protection interval between adjacent driving pulses, are preset in the register. The calculation unit of the pulse modulation module performs two steps: dividing the actual duration of the pulse working window by the sum of the minimum allowable pulse width and the minimum protection interval to obtain the theoretical maximum number of pulses in the current window; and then dividing the actual duration of the pulse working window by the sum of the maximum allowable pulse width and the minimum protection interval to obtain the theoretical maximum number of pulses in the current window. Theoretical minimum number of pulses; within the integer range formed by the theoretical minimum number of pulses and the theoretical maximum number of pulses, an integer is dynamically selected as the actual number of drive pulses in the current window based on the absolute value of the deviation between the feedback voltage signal and the center reference voltage; after selecting the actual number of drive pulses, the total protection time calculated based on the actual number of drive pulses and the minimum protection interval is subtracted from the actual duration of the pulse working window, and the remaining time is evenly distributed to each drive pulse to obtain the actual pulse width corresponding to the preset duty cycle of each drive pulse. The ratio of the actual pulse width to the switching cycle is the duty cycle of the drive pulse.

[0052] In some embodiments, the selection mapping rule for the actual number of drive pulses is implemented through a lookup table. The absolute value of the deviation between the feedback voltage signal and the center reference voltage is divided into several intervals. Each interval corresponds to a specific integer between the theoretical minimum number of pulses and the theoretical maximum number of pulses. The larger the absolute value of the deviation, the more actual drive pulses are selected to enhance the regulation capability. The smaller the absolute value of the deviation, the fewer actual drive pulses are selected to reduce switching losses. The contents of the lookup table can be adjusted according to the dynamic response characteristics of the power supply. Refer to Table 2, which shows the selection mapping relationship under a certain configuration: Table 2: Mapping Table for Selecting the Actual Number of Driving Pulses Absolute range of feedback voltage deviation (mV) Actual number of driving pulses [0,50) 2 [50,100) 3 [100,200) 4 ≥200 5 In some embodiments, the minimum protection interval setting takes into account the turn-off delay of the power switch and the recovery time of the buffer circuit. The typical value of the minimum protection interval is greater than the sum of the maximum turn-off time of the power switch and the reset time of the buffer circuit to ensure that the power switch is reliably turned off between adjacent drive pulses and avoid common phenomena. The clock frequency of the high-frequency clock counter is much higher than the normal switching frequency of the switching power supply, and the clock period is on the nanosecond level, which enables the pulse width adjustment of the drive pulse to have high resolution. The pulse width calculation adopts fixed-point arithmetic and is rounded to the nearest integer multiple of the clock period to ensure that the total duration of the actually generated drive pulse does not exceed the actual duration of the pulse working window. It can be understood that the distribution of drive pulses within the actual duration of the pulse working window is equally spaced, and the start time interval between adjacent drive pulses is equal to the actual pulse width of a single drive pulse plus the minimum protection interval. The utilization rate of the entire pulse working window can be calculated by multiplying the actual number of drive pulses by the actual pulse width and dividing by the total window duration. The higher the utilization rate, the higher the energy transfer efficiency. The characteristic of not generating any drive pulses within the actual duration of the sleep window means that the switching power supply has almost no switching losses during the sleep phase. Combined with the sparse switching action of the pulse working window, the overall standby power consumption is significantly reduced. It can be understood that the variable duty cycle of the drive pulse sequence is reflected in the fact that the pulse width of each drive pulse may be different between different pulse working windows, while the variable frequency is reflected in the dynamic adjustment of the total cycle duration of the entire pulse working window plus the sleep window according to the load. The interface between the drive pulse sequence output by the pulse modulation module and the power drive module adopts a standard digital level signal. The high-level or low-level active drive pulse can be selected through the polarity configuration bit to adapt to the driving requirements of different types of power switching transistors.

[0053] In one embodiment of the present invention, the power drive module uses a drive pulse sequence to control the on / off state of the power switch in the switching power supply, including: inputting the drive pulse sequence to the gate drive circuit; the gate drive circuit amplifies and levels the drive pulse sequence to generate a gate control voltage that meets the driving requirements of the power switch; the gate control voltage is directly applied to the gate terminal of the power switch to control the on / off state of the power switch; within the pulse working window, each effective pulse in the drive pulse sequence turns the power switch on once, transferring energy from the input side to the transformer; within the sleep window, there are no effective pulses in the drive pulse sequence, the gate control voltage remains at the off level, causing the power switch to remain continuously off, and the power stage circuit of the switching power supply stops energy transfer.

[0054] In practical implementation, the power drive module uses a drive pulse sequence to control the turn-on and turn-off of the power switch in the switching power supply. The drive pulse sequence is directly input to the signal input terminal of the gate drive circuit. The gate drive circuit integrates a push-pull output stage and a level shifting circuit to amplify the current and convert the logic level of the input drive pulse sequence, generating a gate control voltage that meets the driving requirements of the power switch. The gate control voltage is directly applied to the gate terminal of the power switch through a low-impedance trace, controlling the switching of the power switch's turn-on and turn-off states. Within the pulse working window, each valid pulse in the drive pulse sequence corresponds to a high-level period. During the high-level period, the gate control voltage is maintained at a voltage value sufficient to turn on the power switch. The power switch turns on once, transferring energy from the input side to the transformer. Within the sleep window, there are no valid pulses in the drive pulse sequence, and the gate control voltage remains at the turn-off level. This turn-off level is lower than the threshold voltage of the power switch, causing the power switch to remain off, and the power stage circuit of the switching power supply stops energy transfer.

[0055] In practical implementation, the current amplification capability of the gate drive circuit is designed to meet the rapid charging and discharging requirements of the gate charge of the power switch. The pull-up and pull-down current capabilities of the push-pull output stage are symmetrical, ensuring that the rise and fall times of the gate control voltage are matched, thus reducing switching waveform distortion. The level conversion circuit converts the low-voltage logic signal output by the pulse modulation module into a high-voltage drive signal suitable for the power switch. The amplitude of the high-voltage drive signal has a certain margin based on the gate-source breakdown voltage of the power switch. The turn-off level of the gate control voltage is set to a negative voltage or zero voltage. The negative voltage turn-off level can enhance the turn-off reliability of the power switch and prevent false turn-on due to the Miller effect.

[0056] In some embodiments, a gate resistor is connected in series in the connection path between the gate drive circuit and the power switch. The resistance value of the gate resistor is selected based on a trade-off between the switching speed requirements and electromagnetic compatibility requirements of the power switch. A metal film resistor with a small temperature coefficient is used to ensure stable drive characteristics under different ambient temperatures. The power switch is selected as either a MOSFET or an IGBT. When a MOSFET is used, the on-state level of the gate control voltage is set between 10V and 15V, and the off-state level is set between -5V and 0V. When an IGBT is used, the voltage range is adjusted according to the specific model. In some embodiments, the gate control voltage remains at a constant high level for the duration of each effective pulse within the pulse working window. The duration of this high level is equal to the pulse width of the drive pulse. After the pulse width ends, the voltage is immediately pulled down to the off-state level to ensure precise and controllable on-time of the power switch. The start time of the sleep window is aligned with the end edge of the last effective pulse. During the sleep window, the gate drive circuit stops all switching operations, and the output stage remains in a pull-down state, consuming only static holding current. It is understandable that the execution timing of the power drive module is strictly synchronized with the output of the pulse modulation module. Each transition edge of the drive pulse sequence triggers a state update of the gate drive circuit. The alternation between the pulse operating window and the sleep window is achieved through the effective level distribution of the drive pulse sequence. The switching losses of the power switch are concentrated in a few turn-on and turn-off processes within the pulse operating window, while there are no switching losses within the sleep window, thus achieving low-power operation in standby mode. It is also understandable that the power supply voltage of the gate drive circuit is generated through an independent bias winding or auxiliary power supply, electrically isolated from the main power circuit to prevent high-voltage interference with the drive signal. The waveform quality of the gate control voltage is verified through probe testing, requiring steep rising and falling edges without ringing, and crisp turn-on and turn-off actions of the power switch to avoid voltage spikes and heat loss caused by poor driving.

[0057] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A standby control system for a primary-side feedback AC-DC switching power supply, characterized in that, The system includes: The signal acquisition and processing module acquires the auxiliary winding voltage sampling signal at the auxiliary winding end of the switching power supply and performs preprocessing to obtain the feedback voltage signal. At the main winding end of the switching transformer, it acquires the current detection signal and performs shaping and conditioning to obtain the primary side current characterization signal. The mode control module receives an external trigger command from the control loop, which instructs the switching power supply to enter or exit the low-power detection mode. The condition judgment module cyclically compares the feedback voltage signal and the primary side current characterization signal with a preset reference threshold to determine whether the switching power supply meets the conditions for entering a deep standby state. The pulse modulation module, when it determines that the condition is met, starts the improved pulse sleep modulation algorithm. The improved pulse sleep modulation algorithm is based on the fuzzy logic control principle, dynamically decides the time ratio of the pulse working window and the sleep window, and generates a driving pulse sequence with variable duty cycle and variable frequency according to the decision parameters output by the improved pulse sleep modulation algorithm. The power drive module uses the drive pulse sequence to control the on and off of the power switching transistor in the switching power supply, so that the switching power supply can work intermittently in pulse state and sleep state while maintaining a basically constant output voltage.

2. The standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, The auxiliary winding voltage sampling signal is acquired and preprocessed to obtain the feedback voltage signal, including: The auxiliary winding voltage sampling signal is subjected to RC filtering to remove high-frequency switching noise and obtain a preliminary smooth sampling voltage. The initially smoothed sampled voltage is input into a programmable gain amplifier, and the gain factor is automatically adjusted according to the current operating mode of the switching power supply to obtain a voltage signal with normalized amplitude. The amplitude-normalized voltage signal is subjected to analog-to-digital conversion to obtain a digital voltage sample value; The digital voltage sample value is processed using digital filtering technology to suppress power frequency ripple and random interference, and finally output as a steady-state digital voltage quantity as the feedback voltage signal.

3. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, The receiving of an external trigger command from the control loop, wherein the external trigger command instructs the switching power supply to enter or exit the low-power detection mode, includes: Continuously monitor the load status indication signal from the main power circuit of the switching power supply or the communication command from the secondary controller; When the load status indication signal shows that the load current is lower than the preset light load threshold, or when a clear communication command to enter standby mode is received from the secondary controller, an enable signal indicating entry into the low power detection mode is generated as the external trigger command. In the low-power detection mode, the system continuously monitors load changes or new communication commands. When the load status indicator signal is detected to show that the load current has risen and exceeded the preset wake-up threshold, or when a communication command to exit standby mode is received from the secondary controller, a disable signal indicating exiting the low-power detection mode is generated as a new external trigger command.

4. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, The feedback voltage signal and the primary side current characterization signal are cyclically compared with a preset reference threshold to determine whether the switching power supply meets the conditions for entering a deep standby state, including: Set the lower limit threshold and upper limit threshold of the output voltage corresponding to the feedback voltage signal, and set the light load current threshold corresponding to the primary side current characterization signal; During a continuous detection cycle, it is monitored whether the feedback voltage signal remains within the narrow voltage band defined by the lower threshold of the output voltage and the upper threshold of the output voltage. Within the same detection period, the peak value of the primary current characterization signal is continuously monitored to see if it remains below the light load current threshold. The conditions for entering the deep standby state are met only when the feedback voltage signal is continuously within the narrow voltage band and the peak value of the primary current characterization signal is continuously lower than the light load current threshold, and the conditions are met and exceed the preset number of continuous cycles.

5. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, The improved pulse sleep modulation algorithm is based on the principle of fuzzy logic control, dynamically determining the time ratio between the pulse working window and the sleep window, including: The input variables for fuzzy logic control are defined as the deviation between the feedback voltage signal and the center reference voltage and its rate of change, and the output variables are defined as the reference duration of the pulse working window and the reference duration of the sleep window. Membership functions with multiple semantic levels are defined for the deviation and rate of change of the input variables, and membership functions with multiple semantic levels are defined for the pulse working window baseline duration and the sleep window baseline duration of the output variables, respectively. Establish a fuzzy rule base based on expert experience, wherein each rule in the fuzzy rule base takes the semantic level combination of the input variables as a premise and the semantic level combination of the output variables as a conclusion; In each control cycle, the membership degree of the actual value of the input variable to each semantic level is calculated. Based on the fuzzy rule base, the centroid method is used to defuzzify the operation and calculate the values ​​of the reference duration of the pulse working window and the reference duration of the sleep window. The calculated baseline duration of the pulse working window and the baseline duration of the sleep window are finely adjusted in conjunction with the historical load trend of the switching power supply to finally determine the actual duration of the pulse working window and the actual duration of the sleep window for the current cycle, which are then used as the decision parameters.

6. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 5, characterized in that, The step of fine-tuning the calculated reference duration of the pulse working window and the reference duration of the sleep window, combined with the load history trend of the switching power supply, includes: Record the reference duration of the pulse working window calculated by the fuzzy logic control in the most recent multiple control cycles to form a reference duration sequence; Perform trend analysis on the reference duration sequence to determine whether the reference duration of the pulse working window shows an increasing trend, a decreasing trend, or a stable trend; If the trend is determined to be upward, a positive time adjustment amount is added to the baseline duration of the dormancy window calculated in the current cycle. If the trend is determined to be downward, then a negative time adjustment amount is reduced from the baseline duration of the sleep window calculated in the current cycle. The duration of the dormant window after trend fine-tuning and the corresponding baseline duration of the pulse working window are used together as the actual duration of the pulse working window and the actual duration of the dormant window.

7. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, Based on the decision parameters output by the improved pulse sleep modulation algorithm, a drive pulse sequence with variable duty cycle and variable frequency is generated, including: Based on the actual duration of the pulse working window in the decision parameters, determine the number of driving pulses to be generated within the pulse working window and the preset duty cycle of each driving pulse. Based on the actual duration of the sleep window in the decision parameters, it is determined that no drive pulses will be generated within the sleep window; When the actual duration of the pulse working window is open, the high-frequency clock counter is started, and a corresponding number of drive pulses with fixed pulse widths are generated according to the preset number of pulses and the preset duty cycle. After the last drive pulse is sent, the high-frequency clock counter is turned off, and a silent period with a duration equal to the actual duration of the sleep window is entered. At the end of the quiet period, the actual duration of the pulse working window for the next cycle is restarted, and the number of drive pulses and the preset duty cycle are updated according to the latest decision parameters, thereby forming the drive pulse sequence with variable period and duty cycle.

8. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 7, characterized in that, Based on the actual duration of the pulse working window in the decision parameters, determine the number of drive pulses to be generated within the pulse working window and the preset duty cycle of each drive pulse, including: The minimum and maximum allowable pulse widths for a single drive pulse, as well as the minimum protection interval between drive pulses, are preset. The theoretical maximum number of pulses is obtained by dividing the actual duration of the pulse working window by the sum of the minimum allowable pulse width and the minimum protection interval. The theoretical minimum number of pulses is obtained by dividing the actual duration of the pulse working window by the sum of the maximum allowable pulse width and the minimum protection interval. Between the theoretical minimum number of pulses and the theoretical maximum number of pulses, an integer is dynamically selected as the actual number of driving pulses in the current window based on the magnitude of the deviation between the feedback voltage signal and the center reference voltage. After deducting the total protection time calculated based on the actual number of drive pulses and the minimum protection interval from the actual duration of the pulse working window, the remaining time is evenly distributed to each drive pulse to obtain the pulse width corresponding to the preset duty cycle of each drive pulse.

9. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 4, characterized in that, Monitoring whether the feedback voltage signal remains within the narrow voltage band defined by the lower and upper threshold values ​​of the output voltage during a continuous detection period includes: Set up a state shift register with multiple memory cells, each memory cell corresponding to a detection cycle; At the end of each detection cycle, the average value of the feedback voltage signal in the current cycle is compared with the lower limit threshold and the upper limit threshold of the output voltage. If the average value is greater than the lower threshold of the output voltage and less than the upper threshold of the output voltage, then a logic high level representing that the condition is met is shifted into the state shift register. If the average value is less than or equal to the lower limit threshold of the output voltage or greater than or equal to the upper limit threshold of the output voltage, then a logic low level representing that the condition is not met is shifted into the state shift register; When the values ​​of multiple consecutive storage cells in the state shift register are all at the logic high level, it is determined that the feedback voltage signal is continuously within the narrow voltage band.

10. A standby control system for a primary-side feedback AC-DC switching power supply according to claim 1, characterized in that, The method of controlling the on and off of the power switching transistor in the switching power supply using the drive pulse sequence includes: The driving pulse sequence is input to the gate driving circuit; The gate driving circuit amplifies the current and converts the level of the driving pulse sequence to generate a gate control voltage that meets the driving requirements of the power switch. The gate control voltage is directly applied to the gate terminal of the power switch to control the power switch's on and off states. Within the pulse operating window, each effective pulse in the drive pulse sequence turns on the power switch once, transferring energy from the input side to the transformer; During the sleep window, the drive pulse sequence has no valid pulses, the gate control voltage remains at the off level, causing the power switch to remain off, and the power stage circuit of the switching power supply stops energy transfer.

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