Harmonic suppression method for T-type three-level inverter with active reconfiguration switch combination modulation

Abstract

This invention provides a harmonic suppression method for a T-type three-level inverter using active reconfiguration of switch combinations, relating to the field of power electronics technology. Addressing the shortcomings of existing methods that rely on precise modeling and have poor dynamic adaptability, this method acquires the three-phase output voltage in real time and extracts the harmonic deviation vector. Based on its direction angle, a lookup table is used to select the corresponding switch combination as the modulation mode. The drive pulses of the selected switches are actively shielded to change the available set of the basic voltage vector. A linear equation system for the modulation time correction is established, and the SVPWM modulation time is reconstructed. A compensation voltage opposite to the original harmonic deviation is synthesized, and this process is iterated in a closed loop until the harmonic deviation is below a threshold. This method does not change the main circuit, does not rely on precise mathematical models, and does not affect the fundamental frequency control. It achieves directional harmonic cancellation through dynamic reconfiguration of switch combinations, effectively reducing the total harmonic distortion rate and adapting to high power quality scenarios such as motor drives and new energy grid integration.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a harmonic suppression method for a T-type three-level inverter using active reconfiguration switching combination modulation. Background Technology

[0002] T-type three-level inverters have become core power conversion devices in fields such as motor drives, new energy grid connection, and uninterruptible power supplies due to their advantages such as high output waveform quality, low switching losses, and low voltage stress. However, in actual operation, due to the inherent characteristics of the modulation strategy, dead-zone effect, and DC bus voltage fluctuations, the inverter output voltage inevitably suffers from harmonic distortion, especially low-order harmonics and harmonics near the switching frequency. In severe cases, this can affect load operating efficiency, increase system losses, and even cause equipment overheating or resonance problems.

[0003] To suppress output voltage harmonics, existing technologies are mainly divided into three categories. The first category is passive filtering methods, which filter high-frequency harmonics by adding an LC or LCL filter at the output. This method is simple in structure and highly reliable, but suffers from drawbacks such as large size, high cost, and limited low-frequency harmonic suppression. Furthermore, the filter parameters are greatly affected by load changes, making it difficult to adapt to wide operating conditions. The second category is active harmonic control methods, such as repetitive control and proportional resonant control. These methods embed harmonic suppression elements into the fundamental control loop by optimizing the control algorithm. These methods can accurately compensate for specific harmonics, but the algorithm design relies on accurate system modeling, is sensitive to parameter changes, and the controller structure is complex and parameter tuning is difficult when suppressing multiple harmonics simultaneously. Moreover, harmonic suppression is coupled with fundamental control, which may affect the system's dynamic response performance. The third category is topology reconfiguration methods, which reduce harmonic content by changing the inverter topology or modulation strategy, such as selective harmonic cancellation pulse width modulation. These methods require pre-calculation of switching angles, demanding high computational accuracy, and are difficult to adapt to dynamic operating conditions such as sudden load changes.

[0004] In summary, existing harmonic suppression technologies generally suffer from technical defects during implementation, such as reliance on precise modeling, complex parameter tuning, and poor dynamic adaptability, making it difficult to simultaneously achieve both harmonic suppression effectiveness and system dynamic performance.

[0005] In view of the above, this application is hereby submitted. Summary of the Invention

[0006] This invention provides a harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation, which can at least partially improve the above-mentioned problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation, comprising: Step S1: Acquire the three-phase output voltage of the three-level inverter, preprocess the three-phase output voltage to obtain the voltage vector sequence; Step S2: Perform Fourier decomposition on the voltage vector sequence to obtain the actual harmonic vector and the reference harmonic vector, and calculate the harmonic deviation amplitude and harmonic deviation direction angle based on the actual harmonic vector and the reference harmonic vector. Step S3: Determine the fixed voltage vector deviation direction generated by each power switch combination in the T-type three-level inverter after the drive pulse is actively shielded, construct a harmonic deviation direction angle-modulation mode mapping table, and select the corresponding power switch combination according to the harmonic deviation direction angle and the harmonic deviation direction angle-modulation mode mapping table, and shield its drive pulse. Step S4: Based on the selected power switch combinations, determine the set of basic voltage vectors available for the corresponding sector, establish a linear equation set for the modulation time correction, solve for the modulation time correction, and reconstruct the modulation time. Step S5: Generate PWM pulses according to the reconstructed modulation time, shield the drive pulses of the switching transistor combination corresponding to the selected modulation mode, and turn on the remaining switching transistors normally according to the reconstructed modulation time to perform harmonic compensation. Step S6: Repeat steps S2 to S5 until the harmonic deviation amplitude is less than the preset threshold.

[0009] In summary, this method actively reconstructs the switching combination modulation strategy, dynamically selects different switching combinations (modulation modes), and changes the available set of basic voltage vectors to synthesize a compensation voltage opposite to the original harmonic deviation. Specifically, it includes: real-time acquisition of three-phase output voltage, followed by filtering, normalization, and Clarke transform to obtain a voltage vector sequence; extraction of target harmonic components through Fourier decomposition, and calculation of the harmonic deviation vector and its direction angle; selection of the required switching combination for compensation based on the harmonic deviation direction angle, according to a pre-constructed harmonic deviation direction angle-modulation mode mapping table, which divides the voltage vector plane into sectors, with each sector associated with a set of switching combinations capable of generating compensation voltage in that direction; shielding specific single or dual transistors; establishing a linear equation system for the modulation time correction based on the basic voltage vector set corresponding to the selected modulation mode, solving it, and reconstructing the modulation time of the space vector pulse width modulation; shielding the drive pulses of the selected switching combination, performing compensation, and iterating through a closed loop until the harmonic deviation amplitude is less than a preset threshold. This method precisely controls the output voltage harmonics by actively reconfiguring the switching transistor combination. It is implemented purely in software, without changing the main circuit or affecting the fundamental frequency control, effectively reducing the total harmonic distortion rate, and is suitable for high power quality scenarios such as motor drive and new energy grid connection.

[0010] Compared with existing technologies, this method has the following advantages: First, it eliminates the need to change the main circuit topology or add passive filtering devices, achieving harmonic suppression purely in software, significantly reducing hardware cost and size, and avoiding the problem of passive filter parameters being greatly affected by load. Second, it does not rely on a precise mathematical model of the inverter and requires no complex controller parameter tuning. It directly synthesizes the compensation voltage through active reconfiguration of the switch combination, exhibiting strong robustness to system parameter changes and overcoming the sensitivity to modeling accuracy inherent in active harmonic suppression methods such as repetitive control and proportional resonant control. Third, the harmonic suppression process is decoupled from the fundamental wave control. The modulation time correction satisfies the constraint of an unchanged total switching period, without affecting the volt-second balance and dynamic response performance of the fundamental voltage, thus solving the problem of mutual coupling between harmonic suppression and fundamental wave control in traditional methods. Fourth, based on a fast lookup mechanism of the harmonic deviation direction angle-modulation mode mapping table, combined with a closed-loop iterative strategy, it can adaptively track harmonic changes, exhibiting good adaptability to dynamic operating conditions such as sudden load changes, and is superior to selective harmonic elimination methods that require pre-calculation of switching angles. Fifth, through optional single-tube or dual-tube shielding combinations and superimposed equation systems, it supports the simultaneous suppression of single or multiple harmonics (such as 3rd, 5th, and 7th harmonics and harmonics near the switching frequency), offering high flexibility and wide applicability. In summary, this invention achieves efficient harmonic suppression while also considering system dynamic performance, ease of engineering, and cost-effectiveness. Attached Figure Description

[0011] Figure 1 This is a schematic flowchart of the harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation provided in an embodiment of the present invention.

[0012] Figure 2 This is a topology diagram of the main circuit of a T-type three-level inverter provided in an embodiment of the present invention, wherein, Figure 2 In this diagram, DC+ represents the positive terminal of the DC bus, DC- represents the negative terminal of the DC bus, O represents the midpoint potential of the DC bus capacitor, N represents the neutral point of the three-phase load, and u dc This indicates the DC bus voltage, A represents the AC output terminal of phase A, B represents the AC output terminal of phase B, C represents the AC output terminal of phase C, and S represents the DC bus voltage. X1 S represents the upper switch tube of the vertical bridge arm of phase X. X2 S represents the left-side switch of the horizontal bridge arm in phase X. X3 S represents the right-side switch of the horizontal bridge arm in phase X. X4 This represents the switch tube on the lower side of the vertical bridge arm of phase X, where X = {A, B, C}.

[0013] Figure 3 This is a schematic diagram comparing the three-phase output voltage waveforms before and after the harmonic suppression method for a T-type three-level inverter using active reconfiguration switch combination modulation, as provided in this embodiment of the invention. Figure 3 In The line voltage between phase A and phase B. This is the line voltage between phase B and phase C. This is the line voltage between phase C and phase A.

[0014] Figure 4 This is a schematic diagram comparing the output voltage harmonic spectrum before and after the harmonic suppression method of the T-type three-level inverter using active reconfiguration switch combination modulation provided in the embodiment of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0016] refer to Figure 1 , Figure 2 As shown, the first embodiment of the present invention discloses a harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation. This method can be executed by a harmonic suppression device for a T-type three-level inverter with active reconfiguration switch combination modulation (hereinafter referred to as the suppression device), specifically by one or more processors within the suppression device, to implement the following method: Step S1: Acquire the three-phase output voltage of the three-level inverter, preprocess the three-phase output voltage to obtain the voltage vector sequence; Step S1 is as follows: (Microcontroller) Based on a fixed sampling frequency (Preferably 10 times the inverter switching frequency) Real-time data acquisition is performed on the three-level inverter to collect the three-phase output voltage of the three-level inverter. , and ,in, This is the output voltage of phase A. This is the output voltage of phase B. Let be the C-phase output voltage, and k be the sampling point index; before sampling, the three-phase output voltage is band-limited by an analog anti-aliasing filter to suppress high-frequency noise aliasing; The three-phase output voltage is sequentially preprocessed with filtering, normalization, and Clarke transform to obtain two-phase static voltage. Voltage components in coordinate system , And the voltage component data of each sampling point are compared with As a voltage vector, it forms a voltage vector sequence in time order. ,in, for Axis voltage components, for The axis voltage components are as follows: A first-order low-pass digital filter is used to filter the three-phase output voltage to suppress high-frequency switching noise. The filtering formula is as follows: , ,in, This is the filtered three-phase output voltage. These are the filter coefficients, and their values ​​are determined by the filter's cutoff frequency. and sampling frequency Decide, And satisfy A represents phase A, B represents phase B, and C represents phase C; The filtered three-phase output voltage is normalized to eliminate the influence of DC bus voltage fluctuations on subsequent trajectory morphology analysis, thus enhancing the robustness of the method. The amplitude normalization formula is as follows: , , , This is the three-phase output voltage after amplitude normalization. The normalized reference value (this value is the statistical measure of the maximum absolute value of the three-phase voltage within the most recent switching cycle), i is the index of the current sampling point, and N is the number of sampling points within one switching cycle. The switching cycle is defined as the time window; this design decouples the normalized result from the DC bus voltage fluctuation while ensuring that the time window is synchronized with the switching cycle, making it easy to implement in engineering. The three-phase output voltage after amplitude normalization is converted into a two-phase stationary voltage using the Clarke transform. Voltage components in coordinate system Its formula is: ; Obtain voltage component data pairs And the voltage component data of each sampling point are compared with As a voltage vector, it forms a voltage vector sequence in time order. .

[0017] Specifically, in this embodiment, the three-phase output voltage of the T-type three-level inverter is acquired in real time at a fixed sampling frequency using a microcontroller or digital signal processor (DSP). The sampling frequency is preferably 10 times the inverter switching frequency to ensure effective capture of harmonic components. Before sampling, the three-phase output voltage is band-limited by an analog anti-aliasing filter to suppress high-frequency noise aliasing. The acquired discrete sequence of three-phase voltage is first pre-processed by filtering, specifically using a first-order low-pass digital filter to filter each phase voltage. After filtering, high-frequency switching noise can be effectively suppressed, while retaining low-frequency and mid-frequency components useful for harmonic analysis. Subsequently, the filtered three-phase voltage is pre-processed by amplitude normalization. This design decouples the normalization result from the DC bus voltage fluctuation while ensuring that the time window is synchronized with the switching cycle, facilitating engineering implementation. The normalization process eliminates the influence of DC bus voltage fluctuation on subsequent vector trajectory morphology analysis, enhancing the robustness of the method under different operating conditions. This is one of the beneficial effects of the present invention—it can work stably without relying on an accurate DC bus voltage model.

[0018] After normalization preprocessing, the normalized three-phase voltage is converted into a two-phase static voltage using the Clarke transform. The components in the coordinate system, the Lark transform uses a standard three-phase to two-phase transformation matrix, projecting the information of the three-phase system onto an orthogonal coordinate system. On the plane, each sampling point corresponds to a voltage vector, and arranging them in chronological order constitutes a voltage vector sequence. This sequence fully reflects the dynamic trajectory of the inverter output voltage on the complex plane, providing fundamental data for subsequent harmonic analysis.

[0019] Step S2: Perform Fourier decomposition on the voltage vector sequence to obtain the actual harmonic vector and the reference harmonic vector, and calculate the harmonic deviation amplitude and harmonic deviation direction angle based on the actual harmonic vector and the reference harmonic vector. Step S2 is as follows: For the voltage vector sequence Perform Fourier decomposition to obtain the actual harmonic vector of the nth harmonic. (i.e., voltage vector, also known as target harmonic component) and reference harmonic vector Its formula is: , Where n is the target harmonic order (n=1,2,3,...). Let be the amplitude of the actual harmonic vector of the nth harmonic, e be the base of the natural logarithm, and j be the imaginary unit. The phase angle of the actual harmonic vector of the nth harmonic. The actual harmonic vector of the nth harmonic. Axis voltage components, The actual harmonic vector of the nth harmonic. Axis voltage components, The reference harmonic vector for the nth harmonic (for the target harmonic to be suppressed, its reference amplitude is set to...). (i.e., the goal is complete suppression). The phase angle of the reference harmonic vector for the nth harmonic. The reference harmonic vector for the nth harmonic. Axis voltage components, The reference harmonic vector for the nth harmonic. Axis voltage components; Calculate the harmonic deviation vector of the nth harmonic. , , ; Calculate the harmonic deviation amplitude of the nth harmonic. Harmonic deviation direction angle , .

[0020] The target harmonic order n can include one or more combinations of low-order harmonics (3rd, 5th, 7th, etc.) and harmonics near the switching frequency, and can be selected based on the main harmonic components in the actual application scenario; where multiple harmonic components need to be suppressed simultaneously, the total harmonic deviation vector is... , Let be the set of target harmonic orders.

[0021] Specifically, in this embodiment, the voltage vector sequence is subjected to Fourier decomposition to extract information about each harmonic. Specifically, for the nth target harmonic (the value of n can be selected according to the actual application scenario, such as the 3rd, 5th, 7th, and other low-order harmonics, as well as harmonics near the switching frequency; only one type can be selected, or multiple combinations can be suppressed simultaneously), the actual harmonic vector of that harmonic is obtained through Fourier decomposition. This actual harmonic vector is represented in complex form, its amplitude is denoted as the reference harmonic vector, and its phase angle is denoted as the reference harmonic vector. Decomposed into in coordinate system Axis voltage components and The axis voltage component. Simultaneously, a reference harmonic vector for this harmonic is pre-defined, also expressed in complex form, with a given phase angle and corresponding... axis, Axial components. For the target harmonic to be suppressed, the amplitude of the reference harmonic vector is usually set to zero, i.e., to completely eliminate the harmonic. However, a non-zero target value can also be set according to actual needs. By subtracting the reference harmonic vector from the actual harmonic vector, the harmonic deviation vector of the nth harmonic is obtained. This deviation vector also contains... shaft and The component difference in two directions along the axis. Based on the two components of the harmonic deviation vector, its magnitude is calculated as the harmonic deviation amplitude to quantify the degree to which the current harmonic deviates from the ideal state; simultaneously, its direction angle is calculated (obtained through the arctangent function, with a value ranging from 0 to...). The θ, or harmonic deviation direction angle, is used to indicate the direction of the deviation vector. When multiple harmonic components of different orders need to be suppressed simultaneously, the harmonic deviation vectors corresponding to each target harmonic are summed to obtain the total harmonic deviation vector. This total vector comprehensively reflects the overall magnitude and direction of the deviation of all harmonics to be suppressed.

[0022] Through the aforementioned Fourier decomposition and deviation calculation, this method can accurately pinpoint the distortion characteristics of specific harmonics without relying on a precise mathematical model of the inverter. It obtains the error information required for control, demonstrating its insensitivity to system parameter changes and its strong adaptability. The obtained harmonic deviation amplitude is used for termination judgment in subsequent closed-loop iterations, while the harmonic deviation direction angle is directly used to guide the selection of the modulation mode, providing accurate directional basis for active reconfiguration of the switching combination.

[0023] Step S3: Determine the fixed voltage vector deviation direction generated by each power switch combination in the T-type three-level inverter after the drive pulse is actively shielded, construct a harmonic deviation direction angle-modulation mode mapping table, and select the corresponding power switch combination according to the harmonic deviation direction angle and the harmonic deviation direction angle-modulation mode mapping table, and shield its drive pulse. Step S3 is as follows: Based on the topology and switching state of the T-type three-level inverter, the direction of the fixed voltage vector deviation generated by each power switch combination in the T-type three-level inverter after being actively shielded by the drive pulse is predetermined, and the deviation direction angle value of each power switch combination is marked as follows. Each power switch combination corresponds to a fixed deviation direction angle value. Different combinations of power switching transistors correspond to different deviation direction angle values. ; When a single power switch (referred to as a single switch, referring to any one of the four power switches in a phase of a T-type three-level inverter) is shielded from the drive pulse, its deviation direction is along the voltage vector of the phase where that switch is located. In the axial direction on the plane, when two power switching transistors (abbreviated as dual transistors, referring to any two power switching transistors, which can be two in the same phase or two in different phases) are shielded from their drive pulses, their deviation direction is the vector sum of the deviation directions of the two single transistors; For example, shielding the lower side switch S of phase A vertical bridge arm. A4 This generates a deviation along 0°, shielding the upper switch S on the vertical bridge arm of phase C. C1This generates a deviation along a 60° direction, while simultaneously shielding the lower side switch S of phase A vertical bridge arm. A4 and the upper switch S of the vertical bridge arm of phase C C1 This produces a vector sum with a direction of 30°. The deviation direction of other switching transistor combinations can be deduced in the same way.

[0024] Will flat Divided into 12 equal sectors, each sector covers an angle range of 30°. For each power switch combination, the angle value is determined according to its corresponding deviation direction. The sector into which the combination falls is assigned to that sector as a candidate modulation mode for that sector. Each sector receives one or more sets of power switch combinations (all combinations whose deviation direction falls within that sector, i.e., each sector is associated with a set of switch combinations that can generate the directional deviation of that sector), forming a harmonic deviation direction angle-modulation mode mapping table. That is, the harmonic deviation direction angle-modulation mode mapping table is used to... flat It is divided into 12 sectors, each sector pre-stores at least one modulation mode, each modulation mode corresponds to a set of switching transistors that need to be shielded from the drive pulse, and corresponds to a unique set of available basic vectors.

[0025] The principle for selecting modulation modes is as follows: determine the sector based on the current harmonic deviation direction angle, and prioritize the single-transistor mode from the pre-stored modulation modes of that sector; if the compensation amplitude of the single-transistor mode is insufficient or cannot be effective due to current direction limitations, then the dual-transistor mode is selected. Based on the above principles, a harmonic deviation direction angle-modulation mode mapping table is established as shown in Table 1. Table 1 lists the modulation modes corresponding to each sector and the switching transistor combinations that require active shielding of the drive pulse.

[0026] Table 1 Harmonic Deviation Direction Angle-Modulation Mode Mapping Table:

[0027] As shown in Table 1, when the harmonic deviation direction angle Within different ranges, the system automatically selects the corresponding modulation mode (disabling the corresponding switch combination) to generate the compensation voltage in the required direction.

[0028] In actual compensation, the sector to which the harmonic deviation direction angle belongs is determined based on the harmonic deviation direction angle and a power switch combination (preferably a single-tube combination) is selected from the switch combinations corresponding to that sector in the harmonic deviation direction angle-modulation mode mapping table; that is, the switch combination that needs to be actively shielded from the drive pulse. By shielding the drive pulses of a selected group of power switching transistors, the available set of basic voltage vectors is changed (determining the SVPWM sector corresponding to the group of switching transistors and the available set of basic voltage vectors within that sector); thus, the number of switching transistors participating in modulation is not fixed, but rather different combinations of switching transistors (single or dual transistors) are dynamically selected according to the harmonic deviation direction angle, forming an active reconfiguration switching combination modulation strategy.

[0029] Specifically, in this embodiment, for a single power switch (e.g., the upper or lower switch of a vertical bridge arm, or the left or right switch of a horizontal bridge arm), the deviation direction generated by its drive pulse is shielded along the voltage vector of the phase in which the switch is located. The axial direction on the plane; for two power switches (which can be two switches in the same phase or two switches in different phases), the deviation direction generated by shielding their drive pulses is the vector sum of the deviation directions of the two single switches mentioned above. Each switch combination corresponds to a fixed deviation direction angle value, and different combinations correspond to different values. This analysis utilizes the topological redundancy of four switches per phase in a T-type three-level inverter, laying the foundation for flexible selection of modulation modes. Based on this, the present invention will... plane from 0 to The system is divided into 12 equal sectors, each covering a 30° angle range. For each switching transistor combination, based on the specific sector where its deviation direction angle falls, the combination is assigned to that sector and treated as a candidate modulation mode. In this way, each sector obtains one or more switching transistor combinations, thus constructing a harmonic deviation direction angle-modulation mode mapping table. This mapping table directly associates the direction of the harmonic deviation with the executable compensation action, eliminating the need for online optimization calculations and significantly improving the generation speed of compensation commands.

[0030] In the actual compensation process, based on the harmonic deviation direction angle, it is determined which sector the harmonic belongs to. Then, a combination is selected from the corresponding switch combinations in the mapping table (preferably selecting the mode that only shields a single switch; if the compensation amplitude is insufficient, the dual-switch mode is selected). The selected switch combination is the one that needs to be actively shielded from the drive pulse. By shielding the drive pulse of this switch combination, the system dynamically changes the available set of the basic voltage vector in space vector pulse width modulation. Since the switch combinations selected for different sectors and different harmonic deviation directions are different, the number and type of switches involved in modulation are not fixed, but are adjusted in real time with the harmonic deviation direction angle, thus constituting an active reconfiguration switch combination modulation strategy. This strategy does not change the main circuit topology, is implemented purely in software, and has a smooth switching process. It can quickly generate the compensation voltage in the required direction without affecting the fundamental wave control, demonstrating the rapid adaptive capability of this invention to harmonic distortion and effectively overcoming the shortcomings of traditional methods that rely on precise mathematical models, have complex parameter tuning, and slow dynamic response.

[0031] In other embodiments, if the harmonic deviation direction angle is not on the standard angle of the mapping table, the modulation time correction can be calculated by linear interpolation to further improve the compensation accuracy. However, the core protection scope of the present invention is not limited to this. By encrypting the mapping table (e.g., increasing the number of sectors) or adjusting the sector division method, effective compensation for harmonic deviations at any angle can also be achieved.

[0032] Step S4: Based on the power switch combination selected in (Step S3), determine the set of basic voltage vectors available for the corresponding sector, establish a linear equation set for the modulation time correction, solve for the modulation time correction, and reconstruct the modulation time. Step S4 is as follows: Based on the selected power switch combinations, determine the corresponding Space Vector Pulse Width Modulation (SVPWM) sector and the set of available basic voltage vectors within that sector. , (The summation range in the subsequent linear equation system is adjusted accordingly.) );in, The first available basic voltage vector, Let Q be the Qth available basic voltage vector, where Q is the number of available basic voltage vectors in the current sector for each modulation mode; Determine the harmonic compensation requirement vector ,set up Establish a system of linear equations for the modulation time correction (i.e., the compensation requirement is synthesized by the weighted sum of Q basic vectors and the modulation time correction, and a system of linear equations is established). ,in, Vector for harmonic compensation requirements of Axial components, Vector for harmonic compensation requirements of Axial components, For the first The basic vectors Axial components, For the first The basic vectors Axial components, For the first The modulation time correction of each basic vector; the third equation ensures that the overall switching period remains unchanged. It should be noted that the value of Q depends on the currently selected modulation mode. The number of available basic vectors in the current sector may be different under different modulation modes, and it needs to be determined according to the actual situation during implementation.

[0033] The linear equations for the modulation time correction were solved using Gaussian elimination to obtain the first... Modulation time correction of each basic vector The value, and based on the modulation time correction amount Reconstructing the first Modulation time of each fundamental vector , For the first The standard SVPWM modulation time for each basic vector; (must meet) When it is determined At that time, the modulation time of the vector is forced to zero. The remaining effective vector modulation time is then redistributed according to the original proportion, using the following formula: , For the first after allocation The modulation time of the basic vectors, For the first time before allocation The modulation time of the basic vectors, For the first The normal SVPWM modulation time of the basic vectors, For the regular SVPWM modulation time of the l-th fundamental vector, The set of vector indices that are still greater than zero after correction; When the tracking error between the corrected fundamental voltage reference vector and the actual synthesized vector is determined... If the threshold is exceeded (e.g., 5%), switch to an adjacent sector or a suboptimal modulation mode to solve the problem again. For the first A complete vector representation of each basic vector.

[0034] When multiple harmonic components need to be suppressed simultaneously, a superposition-type equation system is used for modulation time reconstruction. A modulation mode is independently selected for each harmonic component, and the compensation requirement vector for each harmonic component is calculated separately. Then, these compensation demand vectors are summed to obtain the total compensation demand vector. ; For each harmonic component, a matching modulation mode is selected. The selection rule is as follows: based on the harmonic deviation direction angle-modulation mode mapping table, the corresponding modulation mode is independently queried according to the harmonic deviation direction angle. For example, the direction angle of the third harmonic deviation. Matching mode M1 (masking S) A4 ), 5th harmonic deviation direction angle Matching mode M2 ​​(masking S) A4 +S C1 If the same mode exists in the selected modulation mode set {M1,M2,...,Mm}, they are combined into a single action, and the compensation amplitude is the algebraic sum of the corrections corresponding to each harmonic.

[0035] A system of linear equations for the total modulation time correction is established. This system of linear equations is a superposition system, and its formula is as follows: m is the number of selected modulation modes. For the first The first modulation mode The basic vectors Axial components, For the first The first modulation mode The basic vectors Axial components, For the first The first modulation mode Modulation time correction of each basic vector Vector of total compensation demand of Axial components, Vector of total compensation demand of Axis components. The modulation time is reconstructed after obtaining the total correction amount by solving the generalized inverse matrix method.

[0036] Specifically, in this embodiment, firstly, based on the selected group of switching transistors, the corresponding space vector pulse width modulation (SVPWM) sector and the currently available set of basic voltage vectors within that sector are determined. Since specific switching transistors are disabled, a portion of the vectors in the original complete vector set is removed. The remaining number of available basic vectors is denoted as Q. The value of Q depends on the selected modulation mode; the number of available vectors may differ under different modes, but all satisfy the following condition: These available vectors form the basis for subsequent compensation synthesis. Based on this, the present invention determines the harmonic compensation requirement vector, which is equal to the opposite vector of the harmonic deviation vector, that is, exactly opposite in direction to the detected harmonic deviation and equal in amplitude.

[0037] To synthesize the compensation vector while keeping the overall switching period constant, this invention establishes a system of linear equations concerning the modulation time correction. This system of equations consists of three equations: the first equation requires that all available basic vectors... The weighted sum of the products of the axial components and their respective corrections equals the compensation demand vector. The axial component is multiplied by the switching period (i.e., the volt-second value); the second equation corresponds to... The third equation requires the sum of all corrections to be zero to ensure the overall switching period remains constant. Through this design, harmonic compensation and fundamental frequency control are decoupled in terms of volt-second balance, without compromising the synthesis accuracy of the fundamental voltage. This invention uses Gaussian elimination to solve this system of linear equations, obtaining the modulation time correction for each available fundamental vector. Subsequently, the conventional SVPWM modulation time is added to the correction to obtain the reconstructed modulation time. During the solution process, if a reconstructed modulation time is found to be negative, it indicates that the vector cannot physically operate with negative time. In this case, the modulation time of that vector is forcibly set to zero, and the modulation times of the remaining effective vectors are redistributed according to the original proportions. The distribution formula utilizes the proportional relationship of the conventional modulation times of each vector to ensure that the overall switching period remains T. S .

[0038] After the allocation is completed, the tracking error between the fundamental voltage reference vector and the actual synthesized vector needs to be monitored. If the tracking error exceeds a preset threshold (e.g., 5%), it indicates that the reconstruction scheme in the current modulation mode cannot guarantee the fundamental tracking accuracy. In this case, the system will actively switch to an adjacent sector or select a suboptimal modulation mode to solve the problem again. This adaptive adjustment mechanism significantly improves the robustness of the method and avoids deterioration of the fundamental output due to overcompensation.

[0039] When multiple harmonic components of different orders need to be suppressed simultaneously, this invention employs a superposition strategy. Specifically, firstly, the compensation demand vector (i.e., the opposite vector of its respective harmonic deviation vector) for each harmonic component is calculated separately. Then, these compensation demand vectors are vector-summed to obtain the total compensation demand vector. Simultaneously, a matching modulation mode is independently selected for each harmonic component: based on the deviation direction angle of that harmonic, the corresponding modulation mode is obtained by looking up the harmonic deviation direction angle-modulation mode mapping table. For example, when the deviation direction angle of the 3rd harmonic falls into a certain sector, the matching mode is M1 (shielding S). A4 When the 5th harmonic deviation direction corner enters another sector, the matching mode is M2 (masking S). A4 +S C1If the selected modulation modes for different harmonics are identical, they are combined into a single action, with the compensation amplitude being the algebraic sum of the corrections for each harmonic. Then, a superposition-type linear equation system is established for the total modulation time correction. This system solves for all available basic vectors and their corrections under all selected modulation modes, where m is the number of selected modulation modes. The first term of the equation, summing the vectors under all modes, equals the volt-second value of the total compensation requirement vector, with the constraint that the sum of the total corrections is zero. This invention uses the generalized inverse matrix method to solve this superposition-type equation system, obtaining the total correction of each basic vector under each mode, and thus reconstructing the modulation time. This superposition method eliminates the need to allocate a separate compensation period for each harmonic, instead completing the cancellation of multiple harmonics simultaneously within the same switching cycle, significantly improving the efficiency of multi-harmonic mitigation. The entire process does not change the main circuit, adds no hardware, and maintains the independence of the fundamental wave control, demonstrating the flexibility and engineering practicality of this invention in complex harmonic environments.

[0040] Step S5: Generate PWM pulses according to the reconstructed modulation time, shield the drive pulses of the switch combination corresponding to the selected modulation mode, and turn on the remaining switches normally according to the reconstructed modulation time to perform harmonic compensation; that is, according to the switch combination corresponding to the selected modulation mode, shield the drive pulses of the switch group to perform harmonic compensation.

[0041] For example, if mode M1 (mask S) is selected A4 ), then S will be used during PWM output. A4 The drive signal is forced to zero, and other switching transistors operate normally according to the reconstructed modulation time.

[0042] Figure 3 The comparison of the three-phase output voltage waveforms before and after applying this method under nonlinear load conditions is shown; among them, Figure 3 (a) in the figure represents the waveform when this method is not used. Figure 3 (b) in the figure shows the waveform after using this method.

[0043] Depend on Figure 3 As can be seen in (a) above, the three-phase output voltage waveform exhibits significant distortion without compensation: obvious dips are visible at the peaks, the apex is uneven, there are jagged irregular jumps near the zero-crossing point, and the three-phase waveform has poor symmetry. Figure 3 As can be seen in (b) of this paper, after implementing this method, the peak clipping and depression are basically eliminated, the waveform envelope tends to be smooth, the transition at the zero point is smooth, the three-phase waveform is restored to symmetry, and the whole waveform is close to the standard sine wave. Figure 3 Arrows indicate the waveform areas with "significant distortion" and "distortion basically eliminated," respectively, and a magnified window shows the differences in detail.

[0044] Step S6: Repeat steps S2 to S5 until the harmonic deviation amplitude is reached. Less than the preset threshold The preset threshold The maximum allowable residual harmonic amplitude is preset to complete harmonic suppression. After compensation, the process returns to step S2 to recalculate the harmonic deviation vector. If the harmonic deviation amplitude is less than the preset threshold, compensation is complete, and normal modulation is restored; otherwise, steps S2 to S5 are repeated until the harmonic deviation amplitude is less than the preset threshold, completing harmonic suppression.

[0045] Specifically, in this embodiment, a corresponding PWM pulse is generated based on the reconstructed modulation time, while the drive pulses of the switching transistor combination corresponding to the selected modulation mode are masked. Specifically, for the selected group of power switching transistors to be masked (e.g., a single transistor or a dual-transistor combination), their drive signals are forcibly set to zero during PWM output, keeping them off throughout the entire switching cycle; the remaining unselected switching transistors are turned on normally according to the conventional SVPWM timing and the newly obtained modulation time. In this way, the actual voltage vector sequence output by the inverter within one switching cycle is purposefully changed, thereby synthesizing a compensation voltage component opposite to the original harmonic deviation direction. This process does not change the main circuit topology, is implemented purely in software, and because the modulation time correction satisfies the constraint of a constant total switching cycle, the volt-second balance of the fundamental voltage remains essentially unchanged, effectively decoupling harmonic suppression and fundamental control.

[0046] After performing harmonic compensation once, proceed to step S6. Repeat steps S2 to S5, i.e., re-perform Fourier decomposition of the harmonic vector to obtain the latest harmonic deviation amplitude and direction angle, re-select the modulation mode based on the updated direction angle, solve for the modulation time correction again, and generate the compensation pulse. This closed-loop iteration continues until the harmonic deviation amplitude is less than the preset maximum allowable harmonic residual amplitude threshold (this threshold can be flexibly set according to the power quality requirements of the application scenario). Once this condition is met, it indicates that the harmonics have been suppressed to an acceptable range, and the system can exit the compensation loop or continue monitoring. Through this closed-loop iterative mechanism, this method can adaptively track harmonic changes. Even if the load or operating conditions fluctuate, it can automatically adjust the compensation amount in subsequent cycles, always maintaining a low harmonic distortion rate, demonstrating the significant advantages of this invention in terms of dynamic adaptability and robustness compared to open-loop control methods.

[0047] Figure 4 A quantitative comparison of the output voltage harmonic spectrum before and after applying this method is presented under the above operating conditions. The horizontal axis represents the harmonic order, and the vertical axis represents the percentage of each harmonic voltage amplitude relative to the fundamental frequency. Light-colored bars correspond to the harmonic content without this method, and dark-colored bars correspond to the harmonic content after applying this method. Among them, [the following is a list of parameters, not a direct translation]... Figure 4As can be seen, the 5th, 7th, 11th, and 13th harmonics exhibit prominent amplitudes and high total harmonic distortion (THD) rates without compensation. After implementing this method, the column heights of each target harmonic are significantly reduced, and the THD rate decreases substantially. The figure shows the suppression amplitude of each key harmonic order.

[0048] In summary, this method achieves active harmonic cancellation at the modulation level without adding hardware or relying on precise models. Specifically, the method transforms harmonic distortion into a vector, quickly selects the modulation mode using a pre-stored mapping table, accurately reconstructs the modulation time by solving a system of linear equations, and actively synthesizes a compensation voltage component that is opposite to the original harmonic deviation, thus achieving harmonic cancellation. This method is implemented purely in software, without changing the main circuit structure, increasing hardware costs, or affecting the dynamic performance of the fundamental wave control. It effectively solves the problems of traditional harmonic suppression methods, such as reliance on precise modeling, complex parameter tuning, and poor dynamic adaptability.

[0049] This method is suitable for applications requiring high power quality, such as motor drives, new energy grid connection, and uninterruptible power supplies. It can effectively reduce output voltage THD and improve system operating efficiency and reliability. Compared with existing technologies, this method has the following advantages: 1. Unlike traditional two-level inverter modulation methods, two-level inverters have only two switching transistors per phase and only eight basic voltage vectors, making it impossible to change the available vector set by shielding the switching transistors. This invention utilizes the topological redundancy of four transistors and 19 basic vectors per phase in a T-type three-level inverter, and dynamically reconstructs the available vector set by actively shielding specific switching transistors to achieve directional harmonic compensation. This is a capability not available in two-level topologies. 2. Unlike conventional three-level SVPWM, conventional three-level SVPWM uses the fundamental reference voltage as the sole tracking target, with a fixed vector sequence and action time that does not adjust with harmonic changes. This invention adds a harmonic deviation closed-loop correction channel, selects the corresponding switching transistor combination for shielding based on the harmonic deviation direction angle, and reconstructs the modulation time, actively canceling harmonic components without affecting the fundamental synthesis. 3. The difference between this invention and the transient compensation method lies in the fact that transient compensation methods target transient conditions such as sudden load changes, aiming to quickly restore the circular voltage trajectory, and the compensation action is brief. This invention focuses on harmonic distortion under steady-state operating conditions, extracting steady-state harmonic components through Fourier decomposition and suppressing them through closed-loop iterative processing. The two methods differ fundamentally in their control objectives, operating time domain, and signal processing methods.

[0050] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation, characterized in that, Includes the following steps: Step S1: Acquire the three-phase output voltage of the three-level inverter, preprocess the three-phase output voltage to obtain the voltage vector sequence; Step S2: Perform Fourier decomposition on the voltage vector sequence to obtain the actual harmonic vector and the reference harmonic vector, and calculate the harmonic deviation amplitude and harmonic deviation direction angle based on the actual harmonic vector and the reference harmonic vector. Step S3: Determine the fixed voltage vector deviation direction generated by each power switch combination in the T-type three-level inverter after the drive pulse is actively shielded, construct a harmonic deviation direction angle-modulation mode mapping table, and select the corresponding power switch combination according to the harmonic deviation direction angle and the harmonic deviation direction angle-modulation mode mapping table, and shield its drive pulse. Step S4: Based on the selected power switch combinations, determine the set of basic voltage vectors available for the corresponding sector, establish a linear equation set for the modulation time correction, solve for the modulation time correction, and reconstruct the modulation time. Step S5: Generate PWM pulses according to the reconstructed modulation time, shield the drive pulses of the switching transistor combination corresponding to the selected modulation mode, and turn on the remaining switching transistors normally according to the reconstructed modulation time to perform harmonic compensation. Step S6: Repeat steps S2 to S5 until the harmonic deviation amplitude is less than the preset threshold.

2. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 1, characterized in that, Step S1 is as follows: Based on a fixed sampling frequency Real-time data acquisition is performed on the three-level inverter to collect the three-phase output voltage of the three-level inverter. , and ,in, This is the output voltage of phase A. This is the output voltage of phase B. Here, k represents the output voltage of phase C, and k is the sampling point index. The three-phase output voltage is sequentially preprocessed with filtering, normalization, and Clarke transform to obtain two-phase static voltage. Voltage components in coordinate system , And the voltage component data of each sampling point are compared with As a voltage vector, it forms a voltage vector sequence in time order. ,in, for Axis voltage components, for Axis voltage component.

3. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 2, characterized in that, The three-phase output voltage is sequentially preprocessed with filtering, normalization, and Clarke transform to obtain two-phase static voltage. Voltage components in coordinate system , And the voltage component of each sampling point As a voltage vector, it forms a voltage vector sequence in time order. Specifically: A first-order low-pass digital filter is used to filter the three-phase output voltage. The filtering formula is as follows: , ,in, This is the filtered three-phase output voltage. These are the filter coefficients, where A represents phase A, B represents phase B, and C represents phase C. The filtered three-phase output voltage is then normalized in amplitude. The amplitude normalization formula is as follows: , , , The three-phase output voltage after amplitude normalization. Here, i is the index of the current sampling point, and N is the number of sampling points within one switching cycle. For switching cycles; The three-phase output voltage after amplitude normalization is converted into a two-phase stationary voltage using the Clarke transform. Voltage components in coordinate system Its formula is: ; Obtain voltage component data pairs And the voltage component data of each sampling point are compared with As a voltage vector, it forms a voltage vector sequence in time order. .

4. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 3, characterized in that, Step S2 is as follows: For voltage vector sequences Perform Fourier decomposition to obtain the actual harmonic vector of the nth harmonic. and reference harmonic vector Its formula is: , Where n is the target harmonic order, Let be the amplitude of the actual harmonic vector of the nth harmonic, e be the base of the natural logarithm, and j be the imaginary unit. The phase angle of the actual harmonic vector of the nth harmonic. The actual harmonic vector of the nth harmonic. Axis voltage components, The actual harmonic vector of the nth harmonic. Axis voltage components, Let n be the reference harmonic vector for the nth harmonic. The phase angle of the reference harmonic vector for the nth harmonic. The reference harmonic vector for the nth harmonic. Axis voltage components, The reference harmonic vector for the nth harmonic. Axis voltage components; Calculate the harmonic deviation vector of the nth harmonic. , , ; Calculate the harmonic deviation amplitude of the nth harmonic. Harmonic deviation direction angle , .

5. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 4, characterized in that, Step S2 further includes: the target harmonic order n can include one or more combinations of low-order harmonics and harmonics near the switching frequency; wherein, when it is necessary to suppress multiple harmonic components simultaneously, the total harmonic deviation vector is... , Let be the set of target harmonic orders.

6. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 1, characterized in that, Step S3 is as follows: Based on the topology and switching states of the T-type three-level inverter, the direction of the fixed voltage vector deviation generated by each power switch combination in the T-type three-level inverter after being actively shielded by the drive pulse is predetermined, and the deviation direction angle value of each power switch combination is marked as follows: Each power switch combination corresponds to a fixed deviation direction angle value. Different combinations of power switching transistors correspond to different deviation direction angle values. ; When a single power switch is shielded from the drive pulse, its deviation direction is along the phase voltage vector of that switch. On the plane, when the two power switching transistors are shielded from their drive pulses, their deviation direction is the vector sum of the deviation directions of the two individual transistors. Will The plane is divided into 12 sectors, each covering a 30° angular range. For each power switch combination, the angle value of its corresponding deviation direction is determined. The sector into which the combination falls is assigned to that sector as a candidate modulation mode for that sector. Each sector obtains one or more sets of power switching transistors to form a harmonic deviation direction angle-modulation mode mapping table.

7. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 6, characterized in that, Step S3 also includes: In actual compensation, the sector to which the harmonic deviation direction angle belongs is determined based on the harmonic deviation direction angle, and a power switch combination is selected from the switch combination corresponding to the sector in the harmonic deviation direction angle-modulation mode mapping table. By shielding the drive pulses of a selected set of power switch combinations, the available set of the basic voltage vector is changed, thus forming an active reconfiguration switch combination modulation strategy.

8. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 5, characterized in that, Step S4 is as follows: Based on the selected power switch combinations, determine the corresponding Space Vector Pulse Width Modulation (SVPWM) sector and the set of available basic voltage vectors within that sector. , ,in, The first available basic voltage vector, Let Q be the Qth available basic voltage vector, where Q is the number of available basic voltage vectors in the current sector for each modulation mode; Determine the harmonic compensation requirement vector ,set up Establish a system of linear equations for the modulation time correction. ,in, Vector for harmonic compensation requirements of Axial components, Vector for harmonic compensation requirements of Axial components, For the first The basic vectors Axial components, For the first The basic vectors Axial components, For the first Modulation time correction of each basic vector; The linear equations for the modulation time correction were solved using Gaussian elimination to obtain the first... Modulation time correction of each basic vector The value, and based on the modulation time correction amount Reconstructing the first Modulation time of each fundamental vector , For the first The standard SVPWM modulation time for each basic vector; When judged At that time, the modulation time of the vector is forced to zero. The remaining effective vector modulation time is then redistributed according to the original proportion, using the following formula: , For the first allocation The modulation time of the basic vectors, For the first time before allocation The modulation time of the basic vectors, For the first The normal SVPWM modulation time of the basic vectors, For the regular SVPWM modulation time of the l-th fundamental vector, The set of vector indices that are still greater than zero after correction; When the tracking error between the corrected fundamental voltage reference vector and the actual synthesized vector is determined... If the threshold is exceeded, switch to an adjacent sector or a suboptimal modulation mode to solve the problem again. For the first A complete vector representation of each basic vector.

9. The harmonic suppression method for a T-type three-level inverter with active reconfiguration switch combination modulation according to claim 8, characterized in that, Step S4 also includes: When multiple harmonic components need to be suppressed simultaneously, the compensation requirement vector for each harmonic component is calculated separately. Then, these compensation demand vectors are summed to obtain the total compensation demand vector. ; For each harmonic component, a matching modulation mode is selected. The selection rule is as follows: based on the harmonic deviation direction angle-modulation mode mapping table, the corresponding modulation mode is independently queried according to the harmonic deviation direction angle. ; A system of linear equations for the total modulation time correction is established. This system of linear equations is a superposition system, and its formula is as follows: m is the number of selected modulation modes. For the first The first modulation mode The basic vectors Axial components, For the first The first modulation mode The basic vectors Axial components, For the first The first modulation mode Modulation time correction of each basic vector Vector of total compensation demand of Axial components, Vector of total compensation demand of Axial components.

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