Flexible circuit voltage regulating unit and voltage regulator

Abstract

This invention provides a flexible line voltage regulating unit and regulator. The voltage regulating unit is equipped with a control module for executing the following flexible zero-crossing soft commutation strategy: when the current phase approaches the target zero-crossing point, the duty cycle of the left bridge circuit of the voltage regulating unit is controlled to converge and transmit, thereby prematurely dissipating the residual electromagnetic energy inside the intermediate stage filter circuit; when the instantaneous voltage drops to a preset safe range, the polarity reversal action is performed by the inverting bridge circuit; after the inverting bridge circuit completes the polarity reversal action, the left bridge circuit is controlled to return to the normal tracking and transmitting state. The voltage regulating unit also includes a left bridge circuit that receives AC input and converts it into a double-frequency voltage sine half-wave, an intermediate stage filter circuit that filters the aforementioned sine half-wave, and an inverting bridge circuit that outputs a sinusoidal combined voltage in conjunction with pulse width modulation. This invention achieves a smooth transition during the polarity switching phase, reducing the operating stress and losses of the switching devices.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, and in particular to a flexible line voltage regulating unit and voltage regulator. Background Technology

[0002] Currently, AC power conversion equipment plays a fundamental regulatory role in industrial control and power transmission. A typical AC voltage regulation architecture usually includes a pre-conversion circuit, an intermediate filter network, and a post-inverter bridge arm. During operation, the pre-conversion circuit converts the input AC power into a unipolar pulsating voltage. The intermediate filter network uses passive energy storage elements to smooth the pulsating waveform. The post-inverter bridge arm then restores the unipolar voltage to an AC sinusoidal waveform with positive and negative half-cycles for output. During this energy transfer process, as the phase of the external AC power supply changes periodically, the post-inverter bridge arm needs to periodically switch its internal conductive paths according to the polarity alternation pattern.

[0003] In the conventional control logic of such converters, polarity switching is typically triggered directly by aligning with the physical zero-crossing point of the AC input voltage. When the input phase reaches the zero-crossing point, due to the continuous energy transfer in the early stages of the system, some undissipated electromagnetic energy often remains in the capacitive or inductive components of the intermediate filter network. This energy retention causes a certain residual transient voltage to be maintained across the intermediate DC bus. If the subsequent circuit directly instructs the semiconductor switching devices to perform state changes in an electrical environment with this residual voltage, the parasitic inductance and capacitance within the circuit will physically interact, generating a large rate of change in current and voltage within a short period of time.

[0004] High electrical change rates can easily induce transient surges at the terminals of switching devices. This localized hard switching increases the operating losses and heat dissipation of semiconductor switching devices during the zero-crossing commutation phase, and also requires the components to withstand additional switching stress with each polarity alternation. In applications where equipment operates continuously for extended periods, the industry has been exploring how to optimize the underlying control timing of the system to rationally release residual internal energy at commutation nodes, thereby mitigating electrical shocks during polarity alternation and maintaining the overall stability of voltage regulating equipment operation. Summary of the Invention

[0005] The purpose of this invention is to provide a flexible line voltage regulating unit and voltage regulator to solve the technical problem that when existing AC voltage regulating equipment performs polarity reversal at the zero crossing point, the residual electromagnetic energy in the intermediate filtering stage causes semiconductor switching devices to suffer transient surge impacts and excessively high operating losses.

[0006] In a first aspect, the present invention provides a flexible line voltage regulation unit, comprising a left bridge circuit, an intermediate stage filter circuit connected to the output of the left bridge circuit, and an inverting bridge circuit connected to the output of the intermediate stage filter circuit; the left bridge circuit receives an AC power input and converts the AC input voltage into a double-frequency voltage sinusoidal half-wave; the intermediate stage filter circuit filters the double-frequency voltage sinusoidal half-wave; the inverting bridge circuit locks in the current phase of the AC power input, alternately performs polarity reversal during the positive half-cycle and the negative half-cycle, and outputs a sinusoidal combined voltage to the load in combination with pulse width modulation. The system is equipped with a control module for executing a flexible zero-crossing soft commutation strategy, which includes: When the current phase approaches the target zero-crossing point, the duty cycle of the left bridge circuit is controlled to converge and emit waves in order to release the residual electromagnetic energy inside the intermediate stage filter circuit in advance. When the instantaneous voltage of the intermediate stage filter circuit drops to within a preset safe range, the reverse bridge circuit is controlled to perform the polarity reversal action to achieve a smooth soft switch. After the inverted bridge circuit completes the polarity reversal action, the left bridge circuit is controlled to resume the normal tracking and wave generation state.

[0007] Optionally, the left bridge circuit is configured to dynamically adjust the amplitude of the double-frequency voltage sinusoidal half-wave when the AC input voltage deviates from the normal power supply reference. The intermediate stage filter circuit includes a commutation inductor and a support capacitor, which work together to smooth and shape the double-frequency voltage sinusoidal half-wave.

[0008] Optionally, the inverted bridge circuit includes a forward conduction power frequency tube, a reverse conduction power frequency tube, a forward chopper high-frequency tube, and a reverse chopper high-frequency tube; The forward-conduction power frequency pipe and the reverse-conduction power frequency pipe perform only a single polarity switching action in each power frequency cycle to reduce action loss.

[0009] Optionally, during the positive half-cycle, the forward conduction power frequency pipe is in a straight-through state, and the forward chopping high-frequency pipe performs the pulse width modulation action to synthesize the positive half-cycle waveform; During the negative half-cycle, the reverse conduction power frequency pipe is in a straight-through state, and the reverse chopping high-frequency pipe performs the pulse width modulation action to synthesize the negative half-cycle waveform; The operating components inside the left bridge circuit, the positive chopper high-frequency component, and the reverse chopper high-frequency component are all made of silicon carbide insulated gate bipolar transistor material. The forward-conducting power frequency pipe and the reverse-conducting power frequency pipe are made of conventional insulated gate bipolar transistor material.

[0010] Optionally, the step of controlling the convergence emission duty cycle of the left bridge circuit when the current phase approaches the target zero-crossing point to prematurely release the residual electromagnetic energy inside the intermediate stage filter circuit includes: The current phase is continuously monitored, and the remaining phase angle difference between the current phase and the target zero-crossing point is calculated. When the remaining phase angle difference decreases to a preset warning phase angle threshold, the predictive energy leakage mechanism is triggered; According to the preset nonlinear attenuation rate, the original transmission duty cycle sent to the left bridge circuit is gradually reduced, forcing the envelope of the double-frequency voltage sinusoidal half-wave to dip downwards in advance.

[0011] Optionally, the preset nonlinear decay rate is associated with the transient sag slope of the AC input voltage; The steeper the transient drop slope, the faster the preset nonlinear decay rate is set, thereby ensuring that the electromagnetic energy remaining inside the intermediate stage filter circuit is fully guided to the load end for consumption before reaching the target zero-crossing point.

[0012] Optionally, the step of controlling the inverting bridge circuit to perform the polarity reversal action when the instantaneous voltage of the intermediate stage filter circuit drops to within a preset safe range, in order to achieve a smooth soft switching, includes: The actual residual voltage across the intermediate stage filter circuit is collected in real time by a voltage sensing element. Compare the actual residual voltage with the preset zero-voltage ride-through threshold; When the actual residual voltage is lower than the preset zero-voltage crossing threshold, a flip permission command is issued to the inverted bridge circuit; The reverse bridge circuit responds to the flip permission command and performs the polarity flipping action in an extremely low voltage environment to complete the internal conduction state change.

[0013] Optionally, if the actual residual voltage does not fall below the preset zero-voltage crossing threshold at the target zero-crossing point, the control module forcibly intercepts the polarity reversal action that was originally scheduled to be triggered, and additionally introduces a dynamic delay dead zone. During the duration of the dynamic delay dead zone, all high-frequency actuators in the left bridge circuit and the inverted bridge circuit remain off until the actual residual voltage dissipates naturally to a safe level before the polarity reversal action is released.

[0014] Optionally, the step of controlling the left bridge circuit to resume normal tracking and waveform transmission state after the inverted bridge circuit completes the polarity reversal operation includes: It has been confirmed that the shoot-through state transition inside the reverse bridge circuit has been firmly established; Based on the preset damping wake-up curve, the waveform duty cycle of the left bridge circuit is controlled to smoothly rise from zero. The synchronous control of the inverted bridge circuit restores the pulse width modulation action, so that the sinusoidal combined voltage is smoothly spliced ​​and continues to follow the standard sinusoidal waveform trajectory.

[0015] In a second aspect, the present invention provides a voltage regulator, including an outer housing and a flexible line voltage regulating unit as described in any of the first aspects; the flexible line voltage regulating unit is installed inside the outer housing.

[0016] The present invention has achieved the following beneficial effects: This invention employs a flexible zero-crossing soft-switching strategy through a configured control module. When the current phase of the AC power input approaches the target zero-crossing point, the left bridge circuit's convergence wave duty cycle is actively controlled, utilizing an external load to pre-dissipate residual electromagnetic energy within the intermediate-stage filter circuit. This timing intervention mechanism based on energy prediction enables the subsequent inverting bridge circuit to perform polarity reversal in a low-voltage environment where the transient voltage in the intermediate stage drops to a preset safe range, avoiding the hard turn-on and turn-off of semiconductor switching devices under conditions with high residual voltage. The combination of feedforward release and low-voltage switching suppresses sudden voltage and current changes during device switching, effectively preventing transient surge impacts induced by parasitic parameters. This smooth zero-crossing soft-switching process reduces the switching stress and dynamic losses of power devices, improves the electromagnetic and thermophysical operating conditions of the underlying voltage regulation unit, and ensures the reliability of the equipment in long-cycle power conversion environments.

[0017] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0018] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the underlying circuit topology of a flexible line voltage regulation unit provided in an embodiment of the present invention; Figure 2 A macroscopic system composition diagram of a flexible line voltage regulator and voltage regulation unit provided in an embodiment of the present invention; Figure 3 A flowchart of the main method for a flexible zero-crossing soft commutation strategy provided in an embodiment of the present invention; Figure 4 A detailed flowchart of the specific implementation of step S10 provided in this embodiment of the invention; Figure 5 A detailed flowchart of the implementation of step S20 provided in this embodiment of the invention; Figure 6 The following is a flowchart illustrating the specific implementation of step S30 in this embodiment of the invention. Detailed Implementation

[0020] The technical solutions in the embodiments will be clearly and completely described below with reference to the examples. Obviously, the described embodiments are only a part of the embodiments, and not all of the embodiments. Based on the embodiments disclosed herein, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection.

[0021] This embodiment discloses a flexible circuit voltage regulation unit, the underlying circuit topology principle is as follows: Figure 1 As shown, the circuit includes a left bridge circuit, an intermediate-stage filter circuit connected to the output of the left bridge circuit, and an inverting bridge circuit connected to the output of the intermediate-stage filter circuit. The left bridge circuit is configured to receive an AC power input. The AC power input has a voltage characteristic of alternating positive and negative polarities according to a preset period and a fixed fundamental frequency. Specifically, the fixed fundamental frequency is calibrated as follows: or The corresponding physical time lengths of the preset period are respectively as follows: or The left bridge circuit internally houses a full-bridge power conversion unit, which is composed of controlled semiconductor switching devices connected in a matrix. An input inductor is connected in series in the input loop of the left bridge circuit to smooth out sudden changes in the AC input current and serve as the energy storage carrier for the boost chopper.

[0022] Specifically, the left bridge circuit converts the AC input voltage into a double-frequency sinusoidal half-wave. The voltage regulation unit is internally equipped with a control module. This control module acquires the instantaneous digital value of the AC power input through a voltage sampling channel and inputs it to the internal phase-locked loop (PLL) algorithm module. The PLL algorithm module extracts the real-time phase data of the AC power input and generates a sinusoidal reference signal synchronized with the real-time phase data. The PLL algorithm module internally includes a phase detector, a loop filter, and a numerically controlled oscillator, cascaded in sequence. Regarding data flow and sub-unit function: the phase detector receives the instantaneous digital value of the AC power input and performs orthogonal multiplication with the local feedback signal to extract the phase error; the loop filter uses a proportional-integral control algorithm to filter out high-frequency ripple and outputs the angular frequency deviation (unit: ...). The numerically controlled oscillator performs discrete-time integration on the deviation to generate a value ranging from... to The real-time phase data with continuously increasing radians (denoted as...) The physical dimensions are The mathematical expression for the generated sinusoidal reference signal is: Subsequently, the control module performs full-wave rectification on the sinusoidal reference signal, extracts the absolute value of the sinusoidal reference signal, and forms a unipolar sinusoidal envelope command with a frequency twice that of the fundamental frequency of the AC power input and an amplitude above zero potential. The mathematical expression for the full-wave rectification mapping to extract the absolute value of the sinusoidal reference signal is: In the aforementioned formula, This is the generated sinusoidal reference signal; This is a unipolar sinusoidal envelope command generated after extracting the absolute value of the sinusoidal reference signal; It is a sine mathematical function; It is an absolute value operator; The independent variable is the continuous physical time (unit: s). After this algebraic operation, the envelope amplitude of the unipolar sinusoidal envelope command is normalized and limited to a dimensionless per-unit value range of 0 to 1.

[0023] Furthermore, the pulse width modulator in the control module compares the unipolar sinusoidal envelope command with a preset high-frequency carrier signal. Through interleaving logic, it outputs a pulse width modulation drive signal with a continuously varying duty cycle. The preset high-frequency carrier signal is a fixed-frequency, bidirectional symmetrical isosceles triangular wave, and its carrier frequency range is set within a certain range. to The transient amplitude was also calibrated between these values. to Within the dimensionless per-unit value range. The specific determination condition of the intersection logic is: within any high-frequency comparison beat, when the transient dimensionless amplitude of the unipolar sinusoidal envelope command is greater than or equal to the transient dimensionless amplitude of the high-frequency carrier signal, the digital comparator outputs a high-level logic to drive the action device to turn on; otherwise, it outputs a low-level logic to drive the action device to turn off. The pulse width modulation drive signal is applied to the control electrode of the semiconductor switching device in the left bridge circuit. Under the control of the pulse width modulation drive signal, the semiconductor switching device alternately enters the on and off states. During the on period, the AC power input magnetizes the input inductor element; during the off period, the magnetic flux energy of the input inductor element is superimposed with the instantaneous energy of the AC power input and transmitted to the subsequent stage through the anti-parallel diode inside the semiconductor switching device. After the aforementioned high-frequency chopping control, the voltage at the output node of the left bridge circuit follows the unipolar sinusoidal envelope command to form the double-frequency voltage sinusoidal half-wave.

[0024] It is understood that the intermediate-stage filter circuit filters the double-frequency voltage sinusoidal half-wave. The voltage waveform output by the left bridge circuit contains high-order harmonics and high-frequency ripple components generated by high-frequency switching. The intermediate-stage filter circuit is connected across the energy transmission path between the left bridge circuit and the inverted bridge circuit, performing a low-pass filtering function. The intermediate-stage filter circuit includes a filter network composed of passive energy storage elements.

[0025] Specifically, when the double-frequency voltage sinusoidal half-wave, mixed with high-frequency ripple, enters the intermediate-stage filter circuit, the inductive elements in the filter network generate a reverse electromotive force, which blocks the changes in the high-frequency pulsating current and suppresses abrupt changes in the current waveform. Simultaneously, the capacitive elements in the filter network absorb and store electromagnetic energy during the voltage rise phase and release charge during the voltage fall phase, clamping the node voltage. Through the synergistic effect of inductive blocking and capacitive absorption, the high-order harmonic energy is weakened, resulting in the voltage waveform passing through the intermediate-stage filter circuit being smoothed and shaped in the time domain, outputting the continuous energy of the double-frequency voltage sinusoidal half-wave to the inverted bridge circuit.

[0026] Furthermore, the inverting bridge circuit locks in the current phase of the AC power input, alternately performing polarity reversal during the positive and negative half-cycles and combining this with pulse width modulation to output a sinusoidal combined voltage to the load. The function of the inverting bridge circuit is to restore the unipolar double-frequency voltage sinusoidal half-wave to an AC sinusoidal voltage with both positive and negative polarities.

[0027] It is understood that the phase-locked loop (PLL) algorithm module inside the control module outputs a phase indicator value in real time to indicate the polarity of the AC power input. This phase indicator value divides the complete power frequency cycle into a positive half-cycle (corresponding to the electrical angle range of the positive polarity) and a negative half-cycle (corresponding to the electrical angle range of the reverse polarity). The semiconductor switching devices inside the inverted bridge circuit are connected as two complementary conductive paths. During the positive half-cycle, the control module outputs a control level, triggering the positive conductive path to conduct and blocking the reverse conductive path; at this time, energy flows into the load as a positive current. During the negative half-cycle, the control module triggers the reverse conductive path to conduct and blocks the positive conductive path; at this time, energy flows into the load as a reverse current. The alternating conduction and blocking states of the aforementioned two complementary conductive paths constitute the polarity reversal operation.

[0028] Specifically, during the synchronization phase of performing the polarity reversal action to establish the current direction, the inverting bridge circuit slices the instantaneous amplitude of the output voltage. The control module sends a high-frequency control signal to the semiconductor switching device responsible for chopping within the inverting bridge circuit, causing the aforementioned switching device to perform the pulse width modulation action. In the conductive path in the on state, the high-frequency switching device adjusts the duty cycle of the double-frequency voltage sinusoidal half-wave input to the inverting bridge circuit using a high-frequency on / off method based on the voltage feedback at the load end and a preset output sinusoidal reference signal. The formula for generating the preset output sinusoidal reference signal is: ,in, The preset output sinusoidal reference signal (unit: V); This is the peak value command (unit: V) of the rated AC output voltage calculated from the outer voltage loop. Based on the preset root mean square reference of the output voltage (Unit: V) multiplied by peak factor The conversion yields, i.e. To ensure the safety and legality of the physical closed-loop calculation (avoiding division by zero overflow during bus drop), the specific mathematical mapping relationship for the duty cycle adjustment is as follows: the instantaneous wave generation duty cycle of the high-frequency switching device. In the formula, The preset output sinusoidal reference signal (unit: V); The instantaneous DC bus voltage sampled in real time at the bridge inlet side (unit: ); The preset minimum voltage reference (with a fixed value) ); This refers to the instantaneous emission duty cycle of the high-frequency switching device. It is an absolute value operator; This is a mathematical function designed to maximize the value of a given parameter sequence within parentheses, thus mitigating the risk of overflow when the denominator is zero. After dividing by quantities of the same dimension (voltage), the output is... It is a non-negative physical dimensionless scalar. Through the synergistic effect of the aforementioned polarity orientation and amplitude chopping, the sinusoidal combined voltage with stable frequency and smooth waveform is spliced ​​and synthesized at the load end.

[0029] Furthermore, the control module is used to execute a flexible zero-crossing soft commutation strategy. When the aforementioned inverting bridge circuit performs the polarity reversal operation, it involves switching the on / off states of different conductive paths. If, at the switching moment, there is a high instantaneous voltage across the output bus of the intermediate-stage filter circuit, the conductive paths will generate corresponding current and voltage change rates during the on / off transient. These high-amplitude voltage and current surges will induce transient surges on the parasitic inductance and capacitance of the semiconductor switching device. To suppress the switching stress caused by the aforementioned on / off switching, the control module pre-intervenes in the energy flow timing.

[0030] The flexible zero-crossing soft commutation strategy includes the following necessary technical steps, such as... Figure 3 As shown: Step S10: When the current phase approaches the target zero-crossing point, control the convergence wave generation duty cycle of the left bridge circuit to release the residual electromagnetic energy inside the intermediate stage filter circuit in advance. Step S20: When the instantaneous voltage of the intermediate stage filter circuit drops to within the preset safe range, control the reverse bridge circuit to perform the polarity reversal action to achieve smooth soft switching; Step S30: After the inverted bridge circuit completes the polarity reversal action, control the left bridge circuit to resume the normal tracking and wave generation state.

[0031] It is understood that, for step S10, the target zero-crossing point represents the phase angle position where the AC voltage scalar value is zero. The digital counter in the control module continuously monitors the value representing the current phase. During normal power transmission periods, the transmission duty cycle is dominated by external closed-loop feedback logic to maintain stable energy injection. When the current phase is detected to enter a range within a preset angle width from the target zero-crossing point, it is determined to be approaching the target zero-crossing point. The specific physical definition of the preset angle width is: the position before the absolute phase angle of the target zero-crossing point. to radian( Within the closed interval. When the current phase calculated in real time falls into this specific phase angle sector, the logic gate array outputs a high-level active instruction to activate this state determination.

[0032] Specifically, such as Figure 4 As shown, step S10 specifically includes the following sub-steps: Step S11: Continuously monitor the current phase and calculate the remaining phase angle difference between the current phase and the target zero-crossing point.

[0033] The arithmetic logic unit of the control module extracts the real-time phase value generated by the phase-locked loop algorithm module as the current phase during each control interrupt cycle. The voltage regulation unit's internal read-only memory pre-programs a set of calibration phase angle constants for the target zero-crossing point. The continuous phase angles of the calibration phase angle constant set are mathematically constructed as a set of discrete constant sequences. (unit: Each discrete constant in this set maps to the absolute synchronous electrical angle of the ideal sinusoidal AC input voltage waveform at the instant it crosses zero potential, where, Pi is a mathematical constant. The index is an incrementing positive integer. The arithmetic logic unit calls a subtraction instruction to subtract the current phase from the nearest future calibration phase angle constant, and outputs the calculated angle difference, which is the remaining phase angle difference value.

[0034] Step S12: When the remaining phase angle difference is reduced to the preset warning phase angle threshold, the predictive energy leakage mechanism is triggered.

[0035] The preset warning phase angle threshold is calculated from the charge / discharge time constant formed by the total equivalent capacitance of the intermediate-stage filter circuit and the rated load impedance. Based on the physical law of constant impedance exponential decay in RC circuits, the specific mathematical formula for its conversion is: [Preset warning phase angle threshold] In the formula: The unit is radians ( ); The fundamental angular frequency of the AC input (unit: ); The calculated equivalent load impedance (unit: ); Total equivalent physical capacitance (unit: farad) ); The peak DC bus voltage of the intermediate stage filter circuit under rated operating conditions (unit: V). A preset safe voltage reference (i.e., the preset zero-voltage ride-through threshold, unit: V) is used to trigger the soft switching of the inverted bridge circuit. This is a natural logarithm mathematical operator. The arithmetic logic unit is internally configured with a comparator subroutine. In each execution cycle, the comparator subroutine compares the calculated remaining phase angle difference with the preset warning phase angle threshold. If the remaining phase angle difference is determined to be equal to or less than the preset warning phase angle threshold, the control logic immediately performs a state transition, sets the trigger bit of the internal control bit, and initiates the pre-judgment energy release mechanism.

[0036] Step S13: According to the preset nonlinear attenuation rate, gradually reduce the original transmission duty cycle sent to the left bridge circuit, forcing the envelope of the double-frequency voltage sinusoidal half-wave to dip down in advance.

[0037] After triggering the predicted energy leakage mechanism, the control module reads the preset nonlinear decay rate constant and generates a gradually decreasing sequence of proportional multipliers. This gradually decreasing sequence of proportional multipliers is generated based on a quadratic parabolic law, and its discrete difference equation is defined as: In the formula, For the first The dimensionless wave decay multiplier of a discrete operation cycle (logic limit in) ); A dimensionless cumulative variable that is calculated from the moment it is triggered; To control the underlying fixed digital operation execution cycle scale (unit: ); The preset nonlinear decay rate constant is defined by its dimension as the reciprocal of the square of time ( ), thereby offset The second square dimension makes both the numbers before and after the minus sign dimensionless pure numbers. Before being output to the hardware pulse generator, the original wave duty cycle is multiplied by the aforementioned proportional multiplier sequence to gradually reduce the value.

[0038] Furthermore, the reduced duty cycle puts the left bridge circuit in a restricted conduction mode, causing a decrease in the rate of electromagnetic energy injection into the intermediate-stage filter circuit. Simultaneously, the load continuously draws energy from the intermediate-stage filter circuit based on its electrical impedance characteristics. This imbalance, where the injected energy rate is lower than the extracted energy rate, causes the port voltage of the energy storage element within the intermediate-stage filter circuit to be unable to maintain its current level. The electromagnetic energy stored in the capacitive element is released and consumed to the load side through the existing conductive path before reaching the target zero-crossing point, achieving an active voltage drop across the bus.

[0039] It is understood that the preset nonlinear decay rate is related to the transient sag slope of the AC input voltage; the larger the transient sag slope, the faster the preset nonlinear decay rate is set, thereby ensuring that the electromagnetic energy remaining inside the intermediate stage filter circuit is guided to the load end for consumption before reaching the target zero-crossing point. The control module continuously captures the AC input voltage sequence through a high-frequency acquisition program and uses a backward differential algorithm to calculate the voltage variation rate between adjacent sampling points in real time. The calculated absolute value of the voltage variation rate is mapped to the transient sag slope. The core discrete mathematical model of the backward differential algorithm is defined as: In the formula, This is the calculated transient drop slope (unit: ); here The positive integer index representing the current voltage polling sampling period; and Each is the current number Shoot and the previous one The captured true voltage transient value (unit: ); A fixed voltage polling sampling time interval constant (unit: The transient drop slope characterizes the degree to which the external voltage approaches zero potential under the current transient environment. The control kernel dynamically addresses the rate mapping table in memory based on the extracted transient drop slope. If the transient drop slope is larger, the control kernel retrieves a higher value decay multiplier from the rate mapping table, making the preset nonlinear decay rate set faster. Combined with the AC low-voltage energy leakage physical time window on the order of milliseconds, the addressing rule for the control parameters of continuous phase angles within the rate mapping table is: when the measured transient drop slope... At that time, the attenuation constant is retrieved via mapping. ;when At that time, mapping retrieval ;when At that time, force matching retrieves the highest grade. So that the longest time is less than The wave multiplier will be quickly and smoothly pushed to zero.

[0040] Specifically, regarding step S20, such as Figure 5 As shown, it specifically includes the following sub-steps: Step S21: The actual residual voltage connected across the intermediate stage filter circuit is collected in real time using a voltage sensing element.

[0041] A voltage sensing element disposed at the connection terminal of the supporting capacitor element converts the continuously decaying potential difference between the capacitor plates into a continuously changing isolated analog signal. An analog-to-digital converter quantizes the isolated analog signal and outputs the actual residual voltage reflecting the true potential level.

[0042] Step S22: Compare the actual residual voltage with the preset zero-voltage crossing threshold.

[0043] The comparison command in the control module continuously compares the instantaneous voltage with the upper limit threshold of the preset safe range. The preset zero-voltage crossing threshold serves as the upper limit coordinate defining the preset safe range. This is to limit the parasitic inductance of semiconductor devices and circuits during the commutation phase (according to the formula...). ,in Transient surge voltage (unit: V) caused by switching action. Equivalent parasitic inductance of semiconductor devices and circuits (unit: H). Transient breaking current (unit: A). Physical time (unit: seconds). For differential operators, The transient surge caused by the rate of change of transient interrupting current with respect to physical time (unit: A / s) is fixedly set as a voltage scalar for the continuous phase angle physical reference of the preset zero-voltage ride-through threshold. Based on this, the preset safety range is clearly defined as the bus crossover potential being within a certain range. to The low-voltage soft-switching electrical operating domain. As the early discharge action proceeds, the digital representation of the actual residual voltage exhibits a monotonically decreasing trajectory.

[0044] Step S23: When the actual residual voltage is lower than the preset zero-voltage crossing threshold, a flip permission command is sent to the inverted bridge circuit; the inverted bridge circuit responds to the flip permission command and performs the polarity flipping action in a low-voltage environment to complete the internal conduction state change.

[0045] The logic gate array of the control module generates an action permission flag. In response to the aforementioned action permission flag, the control module sends a drive level jump command to the inverted bridge circuit. After receiving the flip permission command, the drive module in the inverted bridge circuit extracts charge to turn off the power frequency device that was originally in the conducting state, and after a preset delay compensation, injects charge to turn on the power frequency device on the opposite side that is about to take over the conducting task. The preset delay compensation is the underlying hardware drive dead time, and its specific time constant is set in the range of 2.0μs to 3.5μs; this setting value is calibrated at the underlying logic to be greater than the sum of the maximum turn-off delay time of the power wafer of the same side bridge arm and the natural dissipation time of the tail current, effectively isolating the potential for shoot-through short circuits between the upper and lower transistors from the physical timing level. Since the voltage applied to the inter-electrode terminals of each semiconductor switching device is at a low level at this time, the opening and pinch-off process of the conductive channel of the switching device is not accompanied by large-scale charge migration, thereby achieving smooth soft switching.

[0046] Furthermore, if the actual residual voltage has not fallen below the preset zero-voltage crossing threshold at the target zero-crossing point, the control module forcibly intercepts the originally planned polarity reversal action and introduces an additional dynamic delay dead zone. The duration of the dynamic delay dead zone is derived from the principle of charge conservation, and its formula is as follows: In the formula, The deduced interlocking duration for preventing accidental actions (dimension: The software's highest time clamping protection value is set to ); Equivalent capacitance (unit: ); Excessive residual voltage at the moment of interception (unit: ); The underlying preset zero-voltage pass-through threshold constant is set to 15V. The equivalent constant current parameter formed by the system's static discharge network and the intrinsic leakage current of the semiconductor (unit: When the phase tracking logic indicates that the current phase angle has reached the target zero-crossing point coordinates, the arithmetic logic unit executes a numerical comparison instruction. If the quantized voltage parameter is higher than the preset zero-voltage crossing threshold, it indicates that the residual electromagnetic potential energy was not cleared during the pre-discharge step. The protection logic of the control module is triggered, and a latching instruction is issued to the drive pulse distribution module. The aforementioned latching instruction cuts off the drive signal transmission path to all power frequency and high frequency components in the inverted bridge circuit, thereby freezing the original component turn-on and turn-off timing.

[0047] Understandably, during the duration of the dynamic delay dead zone, all high-frequency operating components within the left bridge circuit and the inverted bridge circuit remain off. At this time, all active energy pumping channels and active high-frequency chopper energy output channels within the voltage regulation unit are isolated. The electromagnetic potential energy remaining between the plates of the supporting capacitor element is naturally dissipated through the static voltage equalization discharge network connected in parallel across the DC bus, the intrinsic leakage current channels of the semiconductor devices, and the external load connected to the output terminals. During this period, the background polling task within the control module continuously samples the actual residual voltage. Only after the digital comparison results of multiple consecutive sampling cycles confirm that the actual residual voltage has naturally dissipated to a safe standard, does the control kernel rescind the latch command for the drive pulse distribution module and allow the polarity reversal operation. The aforementioned safety standard is determined when the latest sampled actual residual voltage value drops below the preset zero-voltage crossing threshold of 15V. The prerequisite logic condition for program release is that the bounce counter inside the control module confirms that the actual residual voltage extracted within 3 to 5 consecutive discrete control sampling cycles is stable and meets the above safety standard requirements without bounce, before the dead zone interception flag can be reset. The opposite-side components in the inverted bridge circuit receive the turn-on level in a low-potential environment, completing the internal conduction state change.

[0048] Specifically, regarding step S30, such as Figure 6 As shown, it specifically includes the following sub-steps: Step S31: Confirm that the direct current state change inside the reverse bridge circuit has been firmly established.

[0049] The execution logic conditions that confirm the successful implementation of this replacement include: the control module detecting the collector-emitter voltage drop of the switching power frequency device via the drive peripheral pins. When discovered The true value of the output state is established only when the voltage drops below the set 2.5V saturation conduction physical threshold and the stable maintenance time of this low potential state is longer than the 2.0μs fixed hardware blanking dead zone designed to filter out high-frequency switching oscillation crosstalk.

[0050] The control module assesses the actual operational status of the conductive power frequency pipe by detecting the returned pipe pressure drop desaturation feedback signal. When the desaturation feedback signal confirms that the conductive power frequency pipe in the new half-cycle has entered the saturated low-resistance region, and the conductive power frequency pipe in the original half-cycle has blocked reverse leakage, the system executes the subsequent energy wake-up action.

[0051] Step S32: Based on the preset damping wake-up curve, control the waveform duty cycle of the left bridge circuit to smoothly rise from zero.

[0052] The wake-up multiplier corresponding to the preset damped wake-up curve follows a first-order exponential damping equation: In the formula, The dimensionless climbing multiplier is the output; The absolute cumulative time (in seconds) is calculated from the date of confirmation of stable establishment. The damping time constant (unit: s) is set between 0.001s and 0.003s. This is the base constant of the natural logarithm. Since the numerator and denominator of the exponential term are both time-dimensional, they cancel each other out when divided. The actual duty cycle of the control pulses issued by the left bridge circuit is the sum of the voltage outer loop reconstruction reference duty cycle and this dimensionless exponent multiplier. The result of arithmetic multiplication.

[0053] The control module retrieves the preset damped wake-up curve stored in the read-only memory. In the initial stage of waveform recovery, the control module performs an arithmetic multiplication of the reference duty cycle generated by the closed loop with the attenuation multiplier output by the preset damped wake-up curve. The actual control pulse width sent to the left bridge circuit starts from zero and gradually increases smoothly with time. The smooth increase in the waveform duty cycle limits the rapid rate of change of the magnetic flux within the input inductor, allowing the electromagnetic energy drawn from the AC power input to be gradually fed back to the intermediate filter circuit at a controlled flow rate, achieving a smooth reconstruction of the bus potential.

[0054] Step S33: Synchronously control the inverted bridge circuit to restore the pulse width modulation action, so that the sinusoidal combined voltage is smoothly spliced ​​and continues to follow the standard sinusoidal waveform trajectory.

[0055] During the period when the duty cycle of the left bridge circuit steadily increases, the control module synchronously releases the pulse blockade on the high-frequency chopper components of the inverting bridge circuit. Based on the real-time phase reference provided by the phase-locked loop algorithm module, the high-frequency chopper module of the inverting bridge circuit performs high-frequency slicing on the bus voltage gradually established by the intermediate stage filter circuit. The alternating voltage waveform at the output node achieves a smooth splicing of a macroscopic sine wave. After splicing, each closed-loop regulator in the system takes over global control again, controlling the output alternating voltage to continue evolving along the standard sine wave trajectory.

[0056] Furthermore, the left bridge circuit is configured to dynamically adjust the amplitude of the double-frequency voltage sinusoidal half-wave when the AC input voltage deviates from the normal power supply reference. The normal power supply reference represents the reasonable range of the rated input voltage for the voltage regulator unit. The rated root-mean-square value connected to this voltage regulator unit is... Taking a single-phase AC distribution network as an example, the specific reasonable range of the normal power supply benchmark is clearly defined as the nominal rated value. to That is, the lower limit hardware judgment threshold of its underlying diagnostic protection is anchored to. The upper limit hardware judgment threshold is anchored as The voltage detection channel of the control module acquires the root mean square (RMS) value of the AC input voltage. When the RMS value of the AC input voltage is lower than the lower limit of the normal power supply reference, the voltage outer loop control node inside the control module calculates the negative deviation. The proportional-integral (PI) regulator processes the negative deviation and outputs a boosted current reference peak value. The negative deviation... The extraction method (unit: V) is as follows: In the formula, here The positive integer sequence number representing the current discrete operation control cycle; The nominal value of the normal power supply reference lower limit (unit: V) set above. For the current number The measured root mean square value of the AC input voltage (unit: V). The specific discrete position increment PI derivation equation executed by the proportional-integral controller is as follows: In the formula, here The positive integer sequence number representing the current discrete operation control cycle; For the current number Reference peak current of the output (unit: A); For the previous one Reference peak current of the output (unit: A); For the current number Negative deviation of the image extracted (unit: V); For the previous one The negative deviation extracted by the test (unit: V); to ensure that both sides of the equation are in the dimension of amperes. (Proportional gain) and The physical dimensions of the equivalent integral gain (covering the time elapsed between the start and end of the circuit) are all Siemens (i.e., A / V), with values ​​set in the ranges of 0.5~2.5A / V and 0.01~0.2A / V, respectively. The left bridge circuit, based on the increased current reference peak value, increases the proportion of time the switching device is in the conduction energy storage phase during each high-frequency switching cycle. During the switching device's conduction period, the magnetic field energy accumulated in the input inductor increases; during the switching device's turn-off period, the enhanced magnetic field energy is released to the output node, generating a voltage pumping effect, which dynamically adjusts the envelope amplitude of the double-frequency voltage sinusoidal half-wave upwards. When the root mean square value of the AC input voltage is higher than the upper limit of the normal power supply reference, the control module generates a positive deviation, reducing the current reference peak value. The left bridge circuit reduces the conduction time proportion based on the reduced current reference peak value, which dynamically suppresses the envelope amplitude of the double-frequency voltage sinusoidal half-wave downwards.

[0057] It is understood that the intermediate-stage filter circuit includes a commutating inductor and a supporting capacitor, which work together to smooth and shape the double-frequency voltage sinusoidal half-wave. The winding coil of the commutating inductor is connected in series on a DC connection bar or printed wire connecting the output node of the left bridge circuit and the input node of the reverse bridge circuit. The metal plates of the supporting capacitor are connected to the rear node of the commutating inductor and the system common reference ground node, respectively. The commutating inductor and the supporting capacitor form a passive low-pass filter topology. When high-order harmonic groups flow through the commutating inductor, an inductive reactance voltage drop is generated on the inductor winding, thus blocking them; when the residual high-frequency alternating components that have passed through the inductor reach the supporting capacitor, the high-frequency current forms a charging and discharging cycle between the capacitor plates and flows back to the common ground, whereby it is absorbed by the bypass.

[0058] Specifically, the reverse bridge circuit includes a forward-conducting power frequency transistor, a reverse-conducting power frequency transistor, a forward-choking high-frequency transistor, and a reverse-choking high-frequency transistor. The forward-conducting power frequency transistor is responsible for constructing the main channel of the forward power supply circuit, and the reverse-conducting power frequency transistor is responsible for constructing the main channel of the reverse power supply circuit. The forward-conducting and reverse-conducting power frequency transistors perform only individual polarity switching actions within each complete power frequency cycle to reduce operating losses. Under a specific power frequency grid system, the control module sends only individual turn-on and individual turn-off level commands to the forward-conducting power frequency transistor and only to the reverse-conducting power frequency transistor within a complete cycle.

[0059] Furthermore, during the positive half-cycle, the forward-conducting power frequency transistor is in a shoot-through state, and the forward-choking high-frequency transistor performs the pulse width modulation action to synthesize the positive half-cycle waveform. The phase-locked loop algorithm module outputs the positive half-cycle logic truth value. The control module applies a positive bias level to the control electrode of the forward-conducting power frequency transistor to maintain the shoot-through state. The control electrode of the forward-choking high-frequency transistor receives a high-frequency pulse train with a duty cycle varying according to a sine law. The electrical energy from the intermediate stage filter circuit flows into the forward-conducting power frequency transistor in the shoot-through state, and then, under the high-frequency cutting and conducting action of the forward-choking high-frequency transistor, is modulated into discrete energy blocks with controlled amplitude envelopes, reconstructing a positive half-cycle waveform in phase with the AC power input.

[0060] Understandably, during the negative half-cycle, the reverse conduction power frequency component is in a direct-through state, and the reverse chopper high-frequency component performs pulse width modulation to synthesize the negative half-cycle waveform. As the current phase crosses the polarity reversal boundary angle, the control module pulls down the aforementioned positive bias level, causing both the forward conduction power frequency component and the forward chopper high-frequency component to revert to a blocking state. Subsequently, the control module establishes a positive bias level on the control electrode of the reverse conduction power frequency component, opening the reverse direct-through conductive path, and applies a duty cycle modulated high-frequency pulse train to the reverse chopper high-frequency component. Through the cross-commutation of the reverse bridge arm and the superposition effect of high-frequency modulation, the double-frequency voltage sinusoidal half-wave generates a reverse potential voltage drop at the load end, synthesizing the negative half-cycle waveform.

[0061] Specifically, the operating transistors, forward chopper high-frequency transistors, and reverse chopper high-frequency transistors within the left bridge circuit are all made of silicon carbide insulated-gate bipolar transistors (IGBTs); the forward conduction power frequency transistors and the reverse conduction power frequency transistors are made of conventional IGBTs. The transistors performing high-frequency chopping have short turn-on and turn-off times. Silicon carbide devices have low parasitic capacitance, resulting in low reverse recovery charge, and compressing the integral loss in the switching overlap region during high-frequency pulse width modulation. The forward conduction power frequency transistors and the reverse conduction power frequency transistors only perform low-frequency, single-polarity switching operations, keeping the switching frequency low; conventional silicon-based IGBTs exhibit low saturation on-state voltage drop characteristics during long-term on-state operation at low frequencies.

[0062] Furthermore, a voltage regulator, the macroscopic structure of the system is as follows: Figure 2As shown, the device includes an outer housing and the aforementioned flexible circuit voltage regulating unit; the flexible circuit voltage regulating unit is installed inside the outer housing. The outer housing is made of a metal alloy material with high thermal conductivity and electromagnetic shielding effectiveness. The flexible circuit voltage regulating unit is physically anchored to the internal chassis of the outer housing by modular mechanical fasteners and insulating thermally conductive pads. The interior of the outer housing is divided into multiple independent compartments based on the heat dissipation characteristics and electromagnetic radiation intensity of the devices. All semiconductor power wafers in the left bridge circuit and the reverse bridge circuit are connected to the bottom heat sink aluminum busbar through a ceramic copper-clad substrate with low thermal resistance. The bottom heat sink aluminum busbar is press-fitted to the external heat dissipation fin area of ​​the outer housing. The heat dissipated by the wafers is conducted step by step through the silicon wafer body, solder layer, insulating dielectric layer, and heat sink aluminum busbar to the external surface of the outer housing.

[0063] Understandably, considering that the effective area of ​​the metallized film supporting the capacitor element will dissipate after long-cycle current ripple erosion in the intermediate-stage filter circuit, leading to a decay in the equivalent energy storage capacity, the control module is configured with online capacitor characteristic extraction logic. During the normal power supply phase of the voltage regulation unit, the high-frequency sampling unit continuously records the bus voltage ripple and the high-frequency alternating current flowing into the capacitor branch within a specific control cycle. The arithmetic logic unit calls the calculus equation, using the current integral divided by the voltage ripple amplitude to calculate the current true capacitance of the supporting capacitor element in real time. The mathematical model for solving calculus is as follows: In the formula, This is the calculated actual capacitance of the supporting capacitor element; and These are the start and end times (in seconds) of the aforementioned switch-off charging pulse width window. The actual high-frequency alternating current flowing into the capacitive plate (unit: A); For time integral infinitesimal elements; For definite integral mathematical operators, represents the integral domain. The physical quantity accumulation calculation is performed within the integral domain, which is matched to a complete charging time window; The starting time Latched transient bus voltage amplitude (unit: V); End time The latched transient bus voltage amplitude (unit: V). The physical unit of the numerator integral result is ampere-second (A / V). That is, the charge coulomb ( The denominator is the difference in bus voltage amplitude latched at both ends of the time window (unit: The control module dynamically reduces the digital constant of the preset warning phase angle threshold proportionally based on the actual capacitance, thereby correcting the control time node for soft commutation within the equipment's operating cycle. The continuous phase angle algebraic mapping equation for this proportional dynamic reduction correction logic is: In the formula, The new effective phase angle threshold issued after proportional conversion (i.e., the corrected preset warning phase angle threshold) (Unit: rad) The reference phase angle constant specified by the equipment manufacturer (i.e., the preset warning phase angle threshold) Initial calibration values ​​(unit: rad). and These are the estimated current actual capacity and the nominal original capacity, respectively (both units are 1 / 3 oz). Dividing capacitors of the same dimension generates a dimensionless coefficient, ensuring that the physical phase angle dimension of the multiplication output remains unchanged.

[0064] Specifically, in AC power grids with multiple superimposed high-order harmonics, the input voltage waveform exhibits a distorted false zero-crossing before reaching the target zero point. The control module is configured with an orthogonal phase-locked loop constructed using a digital generalized integrator (SOGI) with inertial characteristics. The SOGI exhibits gain characteristics at the center fundamental frequency, while displaying a bandpass filter response that attenuates high-order harmonic noise deviating from the center frequency. The core algorithm structure of the SOGI is two parallel Laplace complex frequency domain closed-loop transfer function networks: the instantaneous digital quantity of the AC power input is set as the mapping variable in the complex frequency domain. The output relationship of the direct-axis bandpass filter transfer function for extracting the in-phase components is as follows: The transfer function The output relationship of the cross-axis low-pass filter transfer function for reconstructing the orthogonal hysteresis components is as follows: ,in In the formula, The mapping variable of the instantaneous digital quantity of the AC power input in the complex frequency domain; The transfer function for extracting the in-phase component of the direct-axis bandpass filter; To reconstruct the cross-axis low-pass filter transfer function for the orthogonal hysteresis components; The output relationship of the transfer function for a direct-axis bandpass filter; The output relationship of the transfer function of the cross-axis low-pass filter; For complex frequency domain operators (dimensions: ); The center angular frequency constant of the digital phase-locked loop (corresponding to) That is ); To adjust the dimensionless parameter of damping (assignment) After filtering, the orthogonal components are reconstructed and fed into the arctangent phase angle calculation unit. The closed-loop regulator within the phase angle calculation unit imparts virtual inertia, ensuring the current phase variable maintains a smooth operating trajectory and providing a time reference scale for various control commands. The specific algorithm flow is as follows: the calculation unit, based on the reconstructed orthogonal components output by the aforementioned bandpass and low-pass filter networks... (in, For in-phase component direct-axis transfer function The output is mapped to an instantaneous voltage scalar in the time domain. For orthogonal lag components, cross-axis transfer function The output is mapped to an instantaneous voltage scalar in the time domain, and the arctangent function is called. Extract the original local phase angle (unit: rad); where, This is a four-quadrant arctangent mathematical function used to reconstruct orthogonal components. The combination of positive and negative signs is used to calculate the span. to The program first calculates the precise phase angle values ​​for the entire quadrant; to prevent filtering errors caused by the abrupt shift from 2π to 0 due to periodic back-turning, the program first... Phase unwrapping is performed to generate continuous phase angles. Then, substituting it into the first-order low-pass difference equation with virtual inertia: In the formula, The positive integer index representing the current discrete digital sampling beat; For the current number Continuous phase angle after unwinding and rewinding (unit: rad); For the current number The continuous phase angle of the output after beat filtering and smoothing (unit: rad). For the previous one Continuous phase angle of the output after beat filtering and smoothing (unit: rad); dimensionless inertia coefficient. Set between 0.05 and 0.15, the filtered and smoothed continuous phase angles are re-modulated by 2π, and finally the current phase variable is output safely and smoothly within the left-closed and right-open interval [0, 2π) (i.e. the numerical set of the complete single-cycle physical phase angle).

[0065] Furthermore, to address the flux accumulation problem of the commutation inductor during continuous zero-crossing soft switching, the system is designed with an anti-bias balance control link. The control module integrates a DC component extraction filter in the current sampling channel. This filter is used to remove low-frequency DC deviations from the current flowing through the commutation inductor in real time. When a DC deviation deviates from the standard zero-point reference, the bias compensation unit calculates the duty cycle adjustment and then superimposes this adjustment onto the transmission command in reverse during subsequent normal transmission. The DC component extraction filter is a first-order infinite impulse response (IIR) digital low-pass filter, with the following discrete equation: In the formula, A positive integer index representing the discrete digital sampling time step; For the current number The transient alternating current flowing through the commutating inductor element is captured in real time (unit: A). For the current number Low-frequency DC deviation extracted by the beat calculation (unit: A); For the previous one Low-frequency DC deviation extracted by the test (unit: A); These are dimensionless first-order low-pass filter coefficients. The dimensionless duty cycle fine-tuning amount... The calculation equation is: In the formula This is the bias compensation constant (its physical unit is set to the reciprocal of the ampere). Values Its superposition rule is: calculate the dimensionless... By applying algebraic addition and subtraction based on opposite polarities to the original wave command, the center of the ionized magnetic flux is forced to return to zero. The bias compensation action pulls the center of the ionized magnetic flux back to its original position, avoiding the potential danger of core saturation.

[0066] Understandably, the control module integrates active load descent protection logic for closed-loop monitoring of the thermophysical state of all power semiconductor components in the voltage regulator. A distributed negative temperature coefficient thermistor network continuously converts temperature field data into continuously varying analog electrical signals and inputs them to the control module. The control module compares the real-time regional temperature with multi-level safety temperature thresholds. When the voltage regulator operates under boundary conditions, causing the temperature in a specific region to cross the primary load descent critical point, the control logic actively intervenes in the duty cycle generation mechanism of the left bridge and inverted bridge circuits. The control module superimposes a duty cycle reduction multiplier, moderately reducing the overall equivalent output power amplitude of the system without changing the fundamental frequency and phase evolution of the output voltage, forcing the temperature field distribution to re-establish equilibrium. In the clearly defined physical boundaries of the multi-level safety temperatures: the primary load descent critical point reference value is set as follows: The hardware shutdown limit is set to The superimposed dimensionless duty cycle reduction multiplier It possesses precise mapping rules: when the actual temperature of the measured area... hour, ;when When, execute The deduction operation. In the formula, The temperature measurement unit is ; Depreciation slope constant The value is fixed at 0.025, and its physical dimension is the reciprocal of Celsius ( ). This ensures that the reduced multiplier after the multiplication operation is a dimensionless pure number. If the temperature continues to rise and reaches the hardware shutdown temperature limit, the hardware-level protection circuit of the control module is triggered synchronously, each pulse width modulation generator is reset, and the voltage regulation unit cuts off the power exchange path between the AC power input and the load.

[0067] Specifically, the voltage regulation unit deploys a simulated desaturation protection hardware loop at the hardware execution level. This loop is connected across the collector and emitter of each power wafer, continuously monitoring the saturation voltage drop during conduction. When a short-circuit current exceeding the rated specifications flows through the wafer, the port voltage drop increases. The comparator within the simulated desaturation hardware loop detects that the voltage drop exceeds a preset hardware threshold. Independent of software timing logic, it directly shuts off the power device executing the instruction from the drive pin. Leveraging the high-temperature physical conductivity of silicon carbide (SiC), the protection threshold is fixed at a boundary set by the hardware calibration circuit. The emitter saturation voltage drop warning band. The specific logic condition for triggering the lockout shutdown requires the analog comparator to detect an excessive transient voltage drop, and the duration of this excessive high-potential state must be longer than [a certain value]. The hardware-level blanking and anti-interference time blind zone is eliminated without fallback, and the underlying layer will then toggle the hardware lock-up level. A hardware lock-up interrupt signal is synchronously sent to the control module. In response to the hardware lock-up interrupt signal, the control module immediately terminates all sequence tasks and blocks all chopper channels.

[0068] The above embodiments are only used to objectively illustrate the specific implementation path of the technical solutions, and are not intended to limit the scope of protection. Although this document has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to the described partial technical features; and the aforementioned modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments.

Claims

1. A flexible line voltage regulation unit, comprising a left bridge circuit, an intermediate stage filter circuit connected to the output terminal of the left bridge circuit, and an inverting bridge circuit connected to the output terminal of the intermediate stage filter circuit; the left bridge circuit receives AC power input and converts the AC input voltage into a double-frequency voltage sine half-wave. The intermediate stage filter circuit filters the double-frequency voltage sinusoidal half-wave; the reverse bridge circuit locks in the current phase of the AC power input, alternately performs polarity reversal during the positive half-cycle and negative half-cycle, and outputs a sinusoidal combined voltage to the load in combination with pulse width modulation. Its features are, The system is equipped with a control module for executing a flexible zero-crossing soft commutation strategy, which includes: When the current phase approaches the target zero-crossing point, the duty cycle of the left bridge circuit is controlled to converge and emit waves in order to release the residual electromagnetic energy inside the intermediate stage filter circuit in advance. When the instantaneous voltage of the intermediate stage filter circuit drops to within a preset safe range, the reverse bridge circuit is controlled to perform the polarity reversal action to achieve a smooth soft switch. After the inverted bridge circuit completes the polarity reversal action, the left bridge circuit is controlled to resume the normal tracking and wave generation state.

2. The flexible line voltage regulating unit according to claim 1, characterized in that, The left bridge circuit is configured to dynamically adjust the amplitude of the double-frequency voltage sinusoidal half-wave when the AC input voltage deviates from the normal power supply reference. The intermediate stage filter circuit includes a commutation inductor and a support capacitor, which work together to smooth and shape the double-frequency voltage sinusoidal half-wave.

3. The flexible line voltage regulating unit according to claim 2, characterized in that, The inverted bridge circuit includes a forward conduction power frequency transistor, a reverse conduction power frequency transistor, a forward chopper high-frequency transistor, and a reverse chopper high-frequency transistor. The forward-conduction power frequency pipe and the reverse-conduction power frequency pipe perform only a single polarity switching action in each power frequency cycle to reduce action loss.

4. The flexible line voltage regulating unit according to claim 3, characterized in that, During the positive half-cycle, the positive conduction power frequency pipe is in a straight-through state, and the positive chopping high-frequency pipe performs the pulse width modulation action to synthesize the positive half-cycle waveform; During the negative half-cycle, the reverse conduction power frequency pipe is in a straight-through state, and the reverse chopping high-frequency pipe performs the pulse width modulation action to synthesize the negative half-cycle waveform; The operating components inside the left bridge circuit, the positive chopper high-frequency component, and the reverse chopper high-frequency component are all made of silicon carbide insulated gate bipolar transistor material. The forward-conducting power frequency pipe and the reverse-conducting power frequency pipe are made of conventional insulated gate bipolar transistor material.

5. The flexible line voltage regulating unit according to claim 1, characterized in that, The step of controlling the convergence emission duty cycle of the left bridge circuit to prematurely release the residual electromagnetic energy inside the intermediate stage filter circuit when the current phase approaches the target zero-crossing point includes: The current phase is continuously monitored, and the remaining phase angle difference between the current phase and the target zero-crossing point is calculated. When the remaining phase angle difference decreases to a preset warning phase angle threshold, the predictive energy leakage mechanism is triggered; According to the preset nonlinear attenuation rate, the original transmission duty cycle sent to the left bridge circuit is gradually reduced, forcing the envelope of the double-frequency voltage sinusoidal half-wave to dip downwards in advance.

6. The flexible line voltage regulating unit according to claim 5, characterized in that, The preset nonlinear decay rate is related to the transient drop slope of the AC input voltage; The steeper the transient drop slope, the faster the preset nonlinear decay rate is set, thereby ensuring that the electromagnetic energy remaining inside the intermediate stage filter circuit is fully guided to the load end for consumption before reaching the target zero-crossing point.

7. The flexible line voltage regulating unit according to claim 1, characterized in that, The step of controlling the inverting bridge circuit to perform the polarity reversal action to achieve smooth soft switching when the instantaneous voltage of the intermediate stage filter circuit drops to within a preset safe range includes: The actual residual voltage across the intermediate stage filter circuit is collected in real time by a voltage sensing element. Compare the actual residual voltage with the preset zero-voltage ride-through threshold; When the actual residual voltage is lower than the preset zero-voltage crossing threshold, a flip permission command is issued to the inverted bridge circuit; The reverse bridge circuit responds to the flip permission command and performs the polarity flipping action in an extremely low voltage environment to complete the internal conduction state change.

8. The flexible line voltage regulating unit according to claim 7, characterized in that, If the actual residual voltage does not fall below the preset zero-voltage crossing threshold at the target zero-crossing point, the control module forcibly intercepts the polarity reversal action that was originally triggered and introduces an additional dynamic delay dead zone. During the duration of the dynamic delay dead zone, all high-frequency actuators in the left bridge circuit and the inverted bridge circuit remain off until the actual residual voltage dissipates naturally to a safe level before the polarity reversal action is released.

9. The flexible line voltage regulating unit according to claim 1, characterized in that, The step of controlling the left bridge circuit to return to the normal tracking and transmitting state after the inverted bridge circuit completes the polarity reversal operation includes: It has been confirmed that the shoot-through state transition inside the reverse bridge circuit has been firmly established; Based on the preset damping wake-up curve, the waveform duty cycle of the left bridge circuit is controlled to smoothly rise from zero. The synchronous control of the inverted bridge circuit restores the pulse width modulation action, so that the sinusoidal combined voltage is smoothly spliced ​​and continues to follow the standard sinusoidal waveform trajectory.

10. A voltage regulator, comprising an outer housing, characterized in that, It also includes a flexible line voltage regulating unit as described in any one of claims 1 to 9; the flexible line voltage regulating unit is installed inside the outer housing.

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