Slave state reporting method for stability detection based on Boolean analysis channel

Abstract

This invention discloses a slave device status reporting method based on Boolean parse channel for stability detection, relating to the field of electronic system data acquisition technology. The method includes: an analog-to-digital converter inside the slave device converts analog signals into real-time converted digital signals; the digital signals are input in parallel to a main communication channel and an independent Boolean parse channel; the Boolean parse channel performs real-time stability assessment on the target data signal in the digital signals, generating a binary flag characterizing its stability state; the slave device independently reports the digital signals and the binary flag to a host computer, allowing the host computer to determine the reliability of the received data and make subsequent decisions based on the binary flag. This invention decentralizes stability judgment to the acquisition front end, achieving synchronous reporting of data and quality indicators through a lightweight dual-channel architecture. It does not introduce additional processing delays and does not consume significant system resources, fundamentally avoiding system malfunctions caused by the host computer reading unstable data.

Description

Technical Field

[0001] This invention relates to the field of electronic system data acquisition technology, and in particular to a slave device status reporting method based on Boolean parsing channel for stability detection. Background Technology

[0002] In current electronic system design, the stability of data communication between the host computer and the slave chip directly affects the reliability of the entire system. This is especially true in fields such as industrial control, power monitoring, and IoT devices, where the host computer needs to read real-time status information (such as analog signals like voltage, temperature, and power) reported by the slave chip. Figure 1 As shown, these analog signals are typically converted into digital signals by the analog-to-digital converter (ADC) inside the slave device before being reported to the host computer. This simple transmission mechanism has an inherent flaw: when the analog signal becomes unstable due to insufficient setup time, environmental interference, or hardware failure, the ADC conversion result cannot accurately reflect the true state of the measured quantity. However, because the host computer lacks the ability to judge signal stability, it will still make decisions based on this unreliable data, leading to system malfunctions.

[0003] The aforementioned problems can lead to a series of serious consequences in practical applications. In industrial control scenarios, unstable temperature readings may cause overheat protection to malfunction, resulting in production line shutdowns. In power monitoring systems, fluctuations in voltage or power data may cause errors in energy metering or false triggering of protection circuits. Even more challenging is that these problems are often difficult to trace and debug because, from a data transmission perspective, the message format and verification are completely correct, but the data itself is already distorted during the acquisition phase.

[0004] Existing technologies attempt to address this problem primarily in two directions: one is to smooth analog signals using hardware filtering circuits (such as RC low-pass filters); the other is to use software filtering algorithms to handle signal jitter. However, these methods have significant limitations: hardware filtering increases system cost and size, and its parameters are difficult to adapt to changing conditions once fixed; software filtering introduces processing delays, affecting system real-time performance, and has high computational complexity, making it unsuitable for resource-constrained embedded systems.

[0005] In addition, the prior art (patent application document with application number CN201710093648.9) discloses a signal source stability measurement system that uses Allan variance analysis for frequency stability. However, this method focuses on the long-term frequency stability assessment of the signal source rather than the instantaneous stability judgment during real-time data acquisition. Moreover, it has high implementation complexity and is not suitable for the status monitoring scenario of ordinary slave chips.

[0006] Therefore, there is an urgent need for a resource-efficient and real-time solution to determine the stability of analog signals in real time within the slave device and effectively inform the host computer of the reliability of the data, thereby avoiding erroneous decisions based on unstable data. Summary of the Invention

[0007] The present invention provides a slave status reporting method based on Boolean parsing channel for stability detection. This method is characterized by low resource consumption, high real-time performance, and easy integration, and can solve the technical problem of misjudgment and misoperation caused by the host computer reading unstable analog-to-digital conversion data.

[0008] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0009] A slave device status reporting method based on Boolean parse channel for stability detection includes: an analog-to-digital converter inside the slave device acquires an analog signal and converts it into a digital signal in real time; the real-time converted digital signal is used as a data source and input in parallel to a main communication channel and a Boolean parse channel independent of the main communication channel; the Boolean parse channel performs real-time stability assessment on the target data signal in the real-time converted digital signal and generates a binary flag to characterize the stability state of the target data signal; the slave device reports the real-time converted digital signal to a host computer via the main communication channel and reports the binary flag to the host computer via an independent reporting path, so that the host computer determines the reliability of the currently received digital signal based on the binary flag and makes subsequent decisions.

[0010] Further, the target data signal is the least significant bit data signal of the digital quantity converted in real time; or, the target data signal is the Nth bit data signal shifted from the least significant bit to the higher bits, where N is an integer greater than or equal to 0 and less than or equal to 3.

[0011] Furthermore, the specific process of real-time stability evaluation of the Boolean parsing channel includes: acquiring the base clock within the slave chip, and processing the base clock into clock 1 and clock 2 with the same frequency but misaligned phases through a clock splitter module; using clock 1 as the clock input of the first flip-flop to sample and latch the target data signal, and outputting a first sampled value; using clock 2 as the clock input of the second flip-flop to sample and latch the same target data signal, and outputting a second sampled value; inputting the first sampled value and the second sampled value to the logic operation unit for comparison, and outputting the binary flag based on the comparison result.

[0012] Optionally, the frequencies of clock 1 and clock 2 are half the frequency of the base clock (but not limited to a specific half-frequency division); the logic operation unit is an XOR gate; the first sampled value and the second sampled value are input to the XOR gate, and when the first sampled value and the second sampled value are the same, the XOR gate outputs the binary flag as 1, indicating that the target data signal is in a stable state; when the first sampled value and the second sampled value are different, the XOR gate outputs the binary flag as 0, indicating that the target data signal is in an unstable state. It should be noted that an XOR gate is used in this example, but an XOR gate can also be used, in which case the binary flag is exactly inverted, which is applicable to the concept of this case.

[0013] Furthermore, the target data signal being in a stable state means that the target data signal does not undergo a level change within the phase difference window between the rising edge of clock 1 and the rising edge of clock 2; the target data signal being in an unstable state means that the target data signal undergoes a jump within the phase difference window between the rising edge of clock 1 and the rising edge of clock 2.

[0014] Preferably, both the first and second flip-flops are D-type flip-flops; the target data signal is simultaneously connected to the data input terminals of both D-type flip-flops.

[0015] Furthermore, the D-type flip-flop is implemented using a circuit consisting of an inverter and a MOS switch, with the inverter being cross-coupled. When the clock bit of the D-type flip-flop is high, the logic state of its output changes with the signal logic of the data input. When the clock bit of the D-type flip-flop goes low, the current logic value of the data input is latched in the cross-coupled inverter.

[0016] Specifically, the process by which the host computer determines the reliability of the currently received digital quantity based on the binary flag and makes subsequent decisions includes: when the host computer detects that the currently received binary flag is a first value indicating stability, it determines that the real-time converted digital quantity reported by the slave device is valid and stable, and uses it for subsequent calculations and control decisions; when the host computer detects that the currently received binary flag frequently shows a second value indicating instability, it ignores the digital quantity reported by the slave device, or marks the current digital quantity as suspicious data and records the abnormal event; when the host computer continuously receives the binary flag indicating an unstable second value, it triggers an early warning mechanism to indicate that there is a hardware fault or signal abnormality in the circuit where the slave device is located.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] (1) A parallel dual-channel architecture (master communication channel + Boolean parsing channel) was creatively introduced at the forefront of slave data acquisition, realizing the effective separation of data acquisition and quality assessment. By generating independent binary flags and reporting them along with the data, the host computer can intuitively grasp the reliability of the current data, transforming the traditional "error post-processing mechanism" into a "preventive error avoidance mechanism", fundamentally preventing unreliable data from entering the decision chain and effectively avoiding system misoperation.

[0019] (2) The complex problem of signal stability judgment is cleverly transformed into Boolean algebra operations at the hardware level. A clock-driven flip-flop with phase misalignment is generated by clock splitting, and hardware-level sampling and comparison are performed using XOR gates within an extremely short phase difference window. This scheme does not require the storage resources of the microcontroller or complex mathematical computing power, and can be implemented using only lightweight digital logic circuits. Moreover, the evaluation process and data sampling occur in parallel, introducing almost no additional processing cycle delay, which greatly ensures the system's fast response capability and low cost.

[0020] (3) The slave device directly outputs a highly abstract "0 / 1" binary stability flag to the host computer, which makes the data processing logic of the host computer extremely simple. The host computer no longer needs to run a complex software anti-shake algorithm. It can directly decide whether to use or discard data based on the binary flag. At the same time, for the continuous occurrence of unstable flags, the host computer can directly trigger an early warning mechanism to quickly locate sensor abnormalities or underlying hardware failures, effectively reducing the difficulty of debugging and tracing in industrial sites.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the traditional slave status reporting mode architecture in existing technology;

[0024] Figure 2 This is a schematic diagram of the slave status reporting system architecture and working mode based on Boolean parsing channel for stability detection provided in an embodiment of the present invention;

[0025] Figure 3This is a schematic diagram of a hardware circuit structure for a Boolean parsing channel provided in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the clock signal (base clock, clock 1, clock 2) output by the clock splitter module in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of an internally cross-coupled inverter circuit structure of a D-type flip-flop provided in an embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the working timing of signal stability detection (including unstable region, stable region, and changing region) based on Boolean analysis channel provided in the embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0030] To overcome the technical problem of erroneous operations caused by the lack of signal stability judgment capability in existing technologies, this invention proposes a slave device status reporting method based on Boolean parse channel for stability detection. The core idea of ​​this scheme is to design a parallel dual-channel processing mechanism within the slave device: the main communication channel is responsible for regular data reporting, while the newly added Boolean parse channel is specifically used for signal stability assessment at the very beginning of data acquisition (within the slave device), cleverly avoiding complex data validity verification in the digital domain.

[0031] Figure 2 This is a schematic diagram of the overall system architecture of an embodiment of the present invention, showing the host computer, slave chip, and the communication interface between them. The system acquires analog signals such as temperature, voltage, or power through an analog-to-digital converter (ADC) inside the slave chip and converts them into digital signals in real time. It abandons traditional hardware filtering circuits and software algorithm filtering modules, using the real-time converted digital signals as the data source, inputting them in parallel to the main communication channel and a Boolean parsing channel independent of the main communication channel, forming a parallel processing path. The Boolean parsing channel performs real-time stability evaluation on the target data signal in the real-time converted digital signals and generates a binary flag (0 or 1) to characterize the stability state of the target data signal. The Boolean parsing channel can be considered a lightweight binary stability classifier. The slave chip reports the real-time converted digital signals to the host computer via the main communication channel and also reports the binary flag to the host computer via an independent reporting path, enabling the host computer to determine the reliability of the currently received digital signals based on the binary flag and make subsequent decisions.

[0032] In practical applications, since the least significant bit of the data converted by the analog-to-digital converter is usually the data bit most sensitive to jitter, in this preferred embodiment, the target data signal is the least significant bit data signal of the digital quantity converted in real time.

[0033] The implementation of the method of the present invention based on the aforementioned system will be described in more detail below:

[0034] 1. The specific hardware implementation and working mechanism of the Boolean parsing channel

[0035] The Boolean parsing channel is the core component of this invention. To achieve real-time stability evaluation, this embodiment provides a lightweight hardware circuit implementation based on simple digital logic. Combined with... Figure 3 (Boolean resolver circuit diagram) and Figure 4 As shown in the waveform diagram, the specific process of real-time stability evaluation of the Boolean parse channel is as follows:

[0036] First, the base clock within the slave chip is acquired, and then processed by the clock splitter module into clock 1 and clock 2, which have the same frequency but different phases. In this embodiment, the frequencies of clock 1 and clock 2 are divided by 2 from the base clock (but are not limited to a 2-fold division).

[0037] Next, using clock 1 as the clock input of the first flip-flop DFF1, the target data signal (i.e., the least significant bit of the digital quantity converted by the ADC in real time) is sampled and latched, and the first sampled value N1 is output; synchronously, using clock 2 as the clock input of the second flip-flop DFF2, the same target data signal is sampled and latched, and the second sampled value N2 is output.

[0038] Finally, the first sampled value N1 and the second sampled value N2 are input to the logic operation unit for comparison, and a binary flag is output based on the comparison result.

[0039] In this preferred embodiment, both the first and second flip-flops are D-type flip-flops, and the target data signal is simultaneously connected to the data input terminals (D terminals) of both D-type flip-flops. The logic operation unit is preferably an XORN gate.

[0040] To further reduce resource consumption and meet the requirements of rapid response, combined with Figure 5 As shown, the D-type flip-flop in this embodiment is implemented using a circuit consisting of an inverter and a MOS switch, wherein the inverter is connected by cross-coupling.

[0041] To better understand the working principle, first consider the case where the clock bit CLK is low. At this time, MOS switches Q1 and Q2 are turned off (see attached diagram). Figure 5Q3 and Q4 are MOS switches controlled by the data input signal, working together to achieve data input (the output remains unchanged). For this D-type flip-flop, it's important to note that as long as the clock bit CLK is high, the output changes with the input. Therefore, this flip-flop is not an edge-triggered flip-flop, but a level-sensitive one. To ensure the output voltages (Q and QN) change with the input, the on-resistance within the inverter must be sufficiently large. That is, when the clock bit CLK of the D-type flip-flop is high, as long as the on-resistance within the inverter is large enough, the logic state of its outputs (Q and QN) will change in real time according to the signal logic change at the data input terminal (D terminal).

[0042] 2. Timing and stability evaluation logic based on phase difference window

[0043] The stability evaluation of this invention is entirely driven by the aforementioned clock. (Combined with...) Figure 6 As shown in the (timing diagram), the specific timing analysis is as follows:

[0044] (1) Sampling stage:

[0045] When the rising edge of clock 1 arrives (during the high level period), the first sample value N1 output by the first flip-flop DFF1 immediately samples the target data signal and follows its changes; when clock 1 goes low, it latches the current level value of the target data signal until the next rising edge of clock 1. Similarly, the second sample value N2 output by the second flip-flop DFF2 also samples and latches the target data signal under the high / low level of clock 2.

[0046] (2) Stability assessment phase:

[0047] The XOR gate continuously compares the latched first sample value N1 and the second sample value N2. When the first sample value N1 and the second sample value N2 are the same (same input), the XOR gate outputs a binary flag of 1, indicating that the target data signal is in a stable state; when the first sample value N1 and the second sample value N2 are different (different input), the XOR gate outputs a binary flag of 0, indicating that the target data signal is in an unstable state.

[0048] Explained from a micro perspective of temporal logic:

[0049] In the unstable region: The target data signal is in an unstable state, meaning that the target data signal has undergone a jump within the aforementioned phase difference window (this could be due to the data itself changing normally, or the presence of glitches, timing uncertainties, etc.). At this time, the values ​​of samples N1 and N2 are different, and the binary flag will output "0", thus capturing this subtle timing instability and indicating that the current data bit is unreliable.

[0050] In the stable region: The target data signal is in a stable state, meaning that the target data signal does not undergo any level change within the brief phase difference window between the rising edge of clock 1 and the rising edge of clock 2. At this time, the values ​​sampled by N1 and N2 are the same, and the binary flag continuously outputs "1", indicating that the data is valid and reliable within this clock cycle.

[0051] Similarly, in the changing region: its Boolean parsing binary flag outputs "0" between the two stable regions. This indicates that the "least significant bit of the real-time converted digital quantity" signal has a jump during the sampling monitoring of the two clock cycles 1 and 2. When the parsing result is "0", the data bit is unreliable.

[0052] 3. Integration of host computer decision-making logic

[0053] Since this invention transforms the complex problem of signal stability judgment into a simple Boolean logic output (abstracted as a binary stability flag of 0 and 1), and reports it in parallel with the digital quantity as an independent bit field, it has no negative impact on existing communication protocols and greatly simplifies the data processing logic of the host computer.

[0054] The host computer only needs to monitor the reported binary flags in real time, without needing to execute complex software filtering algorithms for judgment. The specific decision-making process includes:

[0055] (1) Reliability improvement (prevention of misoperation): When the host computer detects that the currently received binary flag is the first value (i.e. "1"), it determines that the real-time converted digital quantity reported by the slave is valid and stable, and safely uses it for subsequent calculation and control decisions such as power metering and protection circuit triggering.

[0056] (2) Anomaly filtering: When the host computer detects that the currently received binary flag frequently shows an unstable second value (i.e., "0"), it indicates that the data may be in a transition period or there may be interference. The host computer can choose to ignore the digital quantity reported by the slave, or mark the current digital quantity as suspicious data and record the abnormal event to prevent unreliable data from entering the decision chain.

[0057] In this invention, the host computer detects that the binary flag "frequently" appears with a second value, meaning that within a preset statistical time window or multiple consecutive sampling periods, the number of times or the proportion of the second value appears reaches a preset interference judgment threshold. For example, in a specific implementation, the host computer can set a sliding window (e.g., a length of 100 sampling periods or 100 milliseconds). Within the sliding window, if the cumulative number of received binary flags as "0" is greater than or equal to a preset threshold M (e.g., M=30 times, i.e., the proportion reaches 30% or more), the host computer objectively determines it as "frequently appearing with a second value." This means that the current signal is in a period of drastic change (such as a switch transition transient or encountering burst interference), and the host computer accordingly performs preventative operations such as ignoring the current data or marking it as suspicious data.

[0058] (3) Fault warning: When the host computer continuously receives a binary flag representing an unstable second value (i.e., "0"), it can trigger the warning mechanism to indicate that there may be a hardware fault (such as insufficient setup time, sensor abnormality, etc.) or a serious signal abnormality in the circuit where the slave device is located, so as to facilitate the maintenance personnel to trace and debug.

[0059] In this invention, the host computer "continuously" receiving a second value indicating instability means receiving this second value without interruption in a time series, and the number of uninterrupted occurrences reaching a set alarm threshold, during which no stable first value appears intermittently. Specifically, the host computer can internally set a counter, incrementing by 1 for each received "0" and resetting to zero upon receiving a "1". When the counter's count reaches a set continuity threshold K (e.g., K=10 times or K=50 times), it is determined to be "continuous". This situation typically indicates that the signal is not affected by occasional or transient jitter interference, but rather by a persistent fault (such as sensor disconnection, ADC reference source failure, or external hardware short circuit), and the host computer will immediately trigger an early warning mechanism.

[0060] In summary, the specific implementation method provided by the present invention not only does not consume a large amount of storage and computing resources and achieves real-time monitoring with zero latency, but also completely separates data acquisition from quality assessment, enabling the host computer to fundamentally avoid erroneous operations based on unstable data.

[0061] It should be noted that in this invention, the target data signal is not limited to the least significant bit of the digital quantity being converted in real time. In practical applications, data bits with specific sensitivity can be selected as the target data signal for Boolean analysis, while still adhering to the core principles of this invention. In this invention, specific sensitivity refers to the degree of response of different data bits in the digital quantity being converted in real time to minor fluctuations or noise interference in the analog quantity. Typically, the least significant bit has the highest sensitivity. In specific implementations, the specific sensitivity can be objectively quantified and selected based on the system's effective resolution, noise floor level, or specific control precision requirements. For example, assuming the analog-to-digital converter is a 12-bit ADC, if testing reveals that inherent thermal noise or environmental interference causes meaningless random transitions in the bottom Bit 0 and Bit 1, then the system should no longer use Bit 0 or Bit 1 as a basis for judgment. In this case, the data bit with specific sensitivity can be objectively set to Bit 2; or, quantized as the Nth bit offset from the least significant bit towards the higher bits (where N is an integer greater than or equal to 0 and less than or equal to 3), thus filtering out known noise and performing Boolean analysis only on signal jitter that truly affects the decision.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A slave device status reporting method based on Boolean parsing channel for stability detection, characterized in that, include: It acquires analog signals from the internal analog-to-digital converter and converts them into digital signals in real time; The real-time converted digital quantity is used as the data source and input in parallel to the main communication channel and a Boolean parsing channel independent of the main communication channel; The Boolean parsing channel performs real-time stability evaluation on the target data signal in the real-time converted digital quantity and generates a binary flag to characterize the stability state of the target data signal. The slave device reports the real-time converted digital quantity to the host computer via the main communication channel, and also reports the binary flag to the host computer via a separate reporting path, so that the host computer can determine the reliability of the currently received digital quantity based on the binary flag and make subsequent decisions.

2. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 1, characterized in that: The target data signal is the least significant bit data signal of the digital quantity converted in real time; or, the target data signal is the Nth bit data signal shifted from the least significant bit to the higher bits, where N is an integer greater than or equal to 0 and less than or equal to 3.

3. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 1, characterized in that, The specific process of real-time stability evaluation of the Boolean parsing channel includes: acquiring the base clock within the slave chip, and processing the base clock into clock 1 and clock 2 with the same frequency but misaligned phases through a clock splitter module; using clock 1 as the clock input of the first flip-flop to sample and latch the target data signal, and outputting a first sampled value; using clock 2 as the clock input of the second flip-flop to sample and latch the same target data signal, and outputting a second sampled value; inputting the first sampled value and the second sampled value to the logic operation unit for comparison, and outputting the binary flag based on the comparison result.

4. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 3, characterized in that: The frequencies of clock 1 and clock 2 are divided by two of the base clock; the logic operation unit is an XOR gate; the first sample value and the second sample value are input to the XOR gate, and when the first sample value and the second sample value are the same, the XOR gate outputs the binary flag as 1, indicating that the target data signal is in a stable state; when the first sample value and the second sample value are different, the XOR gate outputs the binary flag as 0, indicating that the target data signal is in an unstable state.

5. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 4, characterized in that: The target data signal being in a stable state means that the target data signal does not undergo a level change within the phase difference window between the rising edge of clock 1 and the rising edge of clock 2; the target data signal being in an unstable state means that the target data signal undergoes a jump within the phase difference window between the rising edge of clock 1 and the rising edge of clock 2.

6. The slave status reporting method based on Boolean parsing channel for stability detection according to any one of claims 3 to 5, characterized in that: Both the first and second flip-flops are D-type flip-flops; the target data signal is simultaneously connected to the data input terminals of both D-type flip-flops.

7. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 6, characterized in that: The D-type flip-flop is implemented using a circuit consisting of an inverter and a MOS switch, wherein the inverter is cross-coupled. When the clock bit of the D-type flip-flop is at a high level, the logic state of its output changes with the signal logic of the data input. When the clock bit of the D-type flip-flop goes low, the current logic value of the data input is latched into the cross-coupled inverter.

8. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 1, characterized in that, The process by which the host computer determines the reliability of the currently received digital quantity based on the binary flag and makes subsequent decisions includes: when the host computer detects that the currently received binary flag is a first value representing stability, it determines that the real-time converted digital quantity reported by the slave device is valid and stable, and uses it for subsequent calculation and control decisions.

9. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 8, characterized in that, The subsequent decision-making process also includes: when the host computer detects that the currently received binary flag frequently shows an unstable second value, it ignores the digital quantity reported by the slave device, or marks the current digital quantity as suspicious data and records the abnormal event.

10. The slave status reporting method based on Boolean parsing channel for stability detection according to claim 9, characterized in that, The subsequent decision-making process also includes: when the host computer continuously receives the binary flag representing an unstable second value, it triggers an early warning mechanism to indicate that there is a hardware fault or signal abnormality in the circuit where the slave device is located.

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