Display device

Abstract

Embodiments of this disclosure relate to display devices, and more specifically to display devices comprising a plurality of apertures formed in a direction perpendicular to the substrate in a touch metal comprising touch electrodes disposed on an encapsulation layer, thereby increasing light efficiency by transmitting light output from a light-emitting device and solving the problem of uneven brightness in sub-light-emitting regions.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0189821, filed on December 18, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms, and recently various display devices such as liquid crystal displays and organic light-emitting diode displays are being used.

[0005] Among display devices, there are those that provide touch-based input methods that, in addition to conventional input methods such as buttons, keyboards, and mice, allow users to intuitively and conveniently input information or commands.

[0006] Such a display device may include multiple touch electrodes for touch sensing. Because these multiple touch electrodes are arranged on the light-emitting elements of the display device, they may prevent light generated from the light-emitting elements from being output to the outside of the display panel, which may reduce brightness. Summary of the Invention

[0007] Embodiments of this disclosure may provide a display device that can increase brightness by forming sub-light-emitting regions using pixel electrodes including inclined surfaces.

[0008] Embodiments of this disclosure may provide a display device that can increase luminous efficiency by forming an opening region on a touch electrode corresponding to the light-emitting region.

[0009] Embodiments of this disclosure may provide a display device that can increase light efficiency by forming pores in a touch metal included in a touch electrode and transmitting light emitted from a light-emitting device.

[0010] Embodiments of this disclosure may provide a display device that can solve the problem of uneven brightness in the light-emitting area, which may occur because the brightness in the non-corner light-emitting area is higher than that in the corner light-emitting area, by forming a corner aperture with a size larger than that of the non-corner aperture.

[0011] Embodiments of this disclosure may provide a display device that can achieve high brightness with low power by forming apertures in a touch metal to transmit light.

[0012] The tasks of implementing this disclosure are not limited to those mentioned in this disclosure, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

[0013] Embodiments of this disclosure may provide a display device comprising: a substrate including a display area and a non-display area; a plurality of pixel electrodes disposed on the display area of ​​the substrate; a common electrode disposed on the plurality of pixel electrodes; an encapsulation layer disposed on the common electrode; and a touch electrode disposed on the encapsulation layer and including a touch metal having a plurality of opening areas, wherein the touch metal has a plurality of holes perforated in a direction perpendicular to the substrate.

[0014] Embodiments of this disclosure may provide a display device comprising: a substrate including a display area; a pixel electrode including sub-pixels disposed in the display area, the pixel electrode including a flat surface and an inclined surface surrounding the flat surface; a dam disposed on the pixel electrode and having holes overlapping at least a portion of the pixel electrode; and a touch metal disposed above the dam and having a plurality of holes. The light-emitting area of ​​the sub-pixel may include: a first light-emitting area overlapping the flat surface; a second light-emitting area surrounding the first light-emitting area and overlapping at least a portion of the inclined surface; and a third light-emitting area surrounding the second light-emitting area and overlapping at least a portion of the plurality of holes.

[0015] According to embodiments of the present disclosure, a display device can be provided that can increase brightness by forming sub-light-emitting regions using pixel electrodes including inclined surfaces.

[0016] According to embodiments of the present disclosure, a display device can be provided that can increase luminous efficiency by forming an opening region on a touch electrode corresponding to a light-emitting region.

[0017] According to embodiments of the present disclosure, a display device can be provided that can increase light efficiency by forming pores in a touch metal included in a touch electrode and transmitting light emitted from a light-emitting device.

[0018] According to embodiments of the present disclosure, a display device can be provided that can solve the problem of uneven brightness in the light-emitting area that may occur because the brightness in the non-corner light-emitting area is higher than that in the corner light-emitting area by forming a corner aperture with a size larger than that in the non-corner light-emitting area.

[0019] According to embodiments of the present disclosure, a display device can be provided that can achieve high brightness with low power by forming apertures in a touch metal to transmit light.

[0020] The effects of implementing the embodiments of this disclosure are not limited to those mentioned in this disclosure, and those skilled in the art will clearly understand from the description of the claims other effects not mentioned. Attached Figure Description

[0021] This disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0022] Figure 1 A system configuration diagram of a display device according to an embodiment of the present disclosure is shown.

[0023] Figure 2 A display panel according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A touch sensor structure for a display device performing mutual capacitance-based touch sensing according to an embodiment of the present disclosure is shown.

[0025] Figure 4 A touch sensor structure for a display device performing self-capacitance-based touch sensing according to an embodiment of the present disclosure is shown.

[0026] Figure 5 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0027] Figure 6 This is a diagram illustrating the correspondence between grid-type touch electrodes and sub-pixels in a display device according to an embodiment of the present disclosure.

[0028] Figure 7 It is magnification Figure 6 An example of a plan view of the X region of the touch electrode is shown.

[0029] Figure 8 It is magnification Figure 7 An example plan view of region A of the touch electrode is shown.

[0030] Figure 9 It is along Figure 8 The line B-B' shown is a portion of the cross-sectional view of the display panel.

[0031] Figure 10 This is a diagram illustrating a grid-type touch electrode with perforations in a display device according to an embodiment of the present disclosure.

[0032] Figure 11 It is shown in Figure 7 The touch metal of the touch electrode in the middle includes, for example, Figure 10 An example of a plan view of a magnified area A of the touch electrode in the case of pores.

[0033] Figure 12 It is along Figure 11 The line C-C' shown is part of a cross-sectional view of the display panel.

[0034] Figure 13 and Figure 14 This is a plan view showing an example of the shape of the holes arranged in the touch metal.

[0035] Figure 15 It is shown that... Figure 8 The corresponding plan view of the luminous area in the plan view.

[0036] Figure 16 It is shown that... Figure 11 The corresponding plan view of the luminous area in the plan view. Detailed Implementation

[0037] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar parts, even when these parts are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein may be omitted where such detailed descriptions could make the subject matter of some embodiments of the invention quite unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional parts, unless said terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0038] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0039] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted that not only can the first element be "directly connected or coupled to" the second element or "directly in contact with or overlapping" a second element, but a third element can also be "placed" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapped" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled" to each other, or that are "in contact with" or "overlapped" with each other.

[0040] When time-related terms, such as “after,” “later,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless used with the terms “directly” or “immediately.”

[0041] Furthermore, when referring to any size, relative dimensions, etc., the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be taken into account, including tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0042] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0043] Figure 1 A system configuration diagram of a display device 100 according to an embodiment of the present disclosure is shown.

[0044] Reference Figure 1 The display device 100 may include a display panel 110 and a display driving circuit, which are components for displaying images.

[0045] The display driving circuit is a circuit used to drive the display panel 110, and may include a data driving circuit 130, a gate driving circuit 120, and a display controller 140.

[0046] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The non-display area NDA may be an area outside the display area DA and may also be referred to as a border area. All or part of the non-display area NDA may be an area visible from the front side of the display device 100, or a curved area that is not visible from the front side of the display device 100.

[0047] The display panel 110 may include a substrate 200 and a plurality of sub-pixels SP disposed on the substrate 200. Additionally, the display panel 110 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0048] The display device 100 according to embodiments of the present disclosure may be a self-emissive display device in which the display panel 110 emits its own light. However, the display device 100 according to embodiments of the present disclosure is not limited to a self-emissive display device. If the display device 100 according to embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting device. For example, the display device 100 according to embodiments of the present disclosure may be an organic light-emitting display device, wherein the light-emitting device is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to embodiments of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting device is implemented as an inorganic light-emitting diode. As another example, the display device 100 according to embodiments of the present disclosure may be a quantum dot display device, wherein the light-emitting device is implemented as a quantum dot, which is a semiconductor crystal that emits its own light.

[0049] The structure of each of the plurality of sub-pixels SP can vary depending on the type of display device 100. For example, if the display device 100 is a self-emissive display device in which the sub-pixels SP emit light on their own, each sub-pixel SP may include a light-emitting device that emits light on its own, one or more transistors, and one or more capacitors.

[0050] For example, various types of signal lines may include multiple data lines DL that transmit data signals (also known as data voltages or image signals) and multiple gate lines GL that transmit gate signals (also known as scan signals).

[0051] Multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may be arranged to extend in a first direction. Each of the multiple gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction.

[0052] The data driving circuit 130 is used to drive multiple data lines DL and can output data signals to the multiple data lines DL. The gate driving circuit 120 is used to drive multiple gate lines GL and can output gate signals to the multiple gate lines GL.

[0053] The display controller 140 may be an apparatus for controlling the data drive circuit 130 and the gate drive circuit 120 according to the timing implemented in each frame, and may control the driving timing of multiple data lines DL and multiple gate lines GL.

[0054] The display controller 140 can supply a data drive control signal DCS to the data drive circuit 130 to control the data drive circuit 120, and can supply a gate drive control signal GCS to the gate drive circuit 120 to control the gate drive circuit 120.

[0055] The display controller 140 can receive input image data from the host system 150 and supply image data to the data drive circuit 130 based on the input image data.

[0056] The data drive circuit 130 can receive digital image data from the display controller 140 and convert the received image data into analog data signals for output to multiple data lines DL.

[0057] The gate drive circuit 120 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate drive control signals GCS, and can generate a gate signal and supply the generated gate signal to multiple gate lines GL.

[0058] For example, the data drive circuit 130 can be connected to the display panel 110 via tape auto-bonding (TAB), connected to the bonding pads of the display panel 110 via chip on glass (COG) or chip on panel (COP), or implemented and connected to the display panel 110 via chip on film (COF).

[0059] The gate driving circuit 120 can be connected to the display panel 110 via a tape-on-absence (TAB) method, to the bonding pads of the display panel 110 via a chip-on-glass (COG) or chip-on-panel (COP) method, or to the display panel 110 via a chip-on-film (COF) method. Alternatively, the gate driving circuit 120 can be formed in the non-display area NDA of the display panel 110 as a gate-in-panel (GIP) type. The gate driving circuit 120 can be disposed on the substrate or connected to the substrate. That is, if the gate driving circuit is of the GIP type, it can be disposed in the non-display area NDA of the substrate. If the gate driving circuit 120 is of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., it can be connected to the substrate.

[0060] Meanwhile, at least one of the data driving circuit 130 and the gate driving circuit 120 can be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 130 and the gate driving circuit 120 can be configured not to overlap with the sub-pixel SP, or can be configured to partially or completely overlap with the sub-pixel SP.

[0061] The data driving circuit 130 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 130 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 110.

[0062] The gate driving circuit 120 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gate driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 110.

[0063] The display controller 140 can be implemented as a component separate from the data drive circuit 130, or it can be implemented as an integrated circuit by integrating it with the data drive circuit 130.

[0064] The display controller 140 may be a timing controller used in conventional display technologies, or it may be a control device capable of performing other control functions, including those of a timing controller, or it may be a control device other than a timing controller or circuitry within a control device. The display controller 140 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0065] The display controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 130 and the gate drive circuit 120 via the printed circuit board or flexible printed circuit.

[0066] The timing controller 140 can send and receive signals with the data drive circuit 130 according to one or more predefined interfaces. Here, for example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI (Enhanced Peripheral Interface) interface, an SP (Serial Peripheral) interface, etc.

[0067] The display device 100 according to embodiments of the present disclosure may include a touch sensor and a touch sensing circuit, the touch sensing circuit sensing the touch sensor to detect the occurrence of a touch by a touch object such as a finger or pen, or to detect the touch position in order to provide touch sensing functions in addition to image display functions.

[0068] The touch sensing circuit may include a touch driving circuit 160 and a touch controller 170. The touch driving circuit 160 drives and senses the touch sensor to generate and output touch sensing data. The touch controller 170 uses the touch sensing data to detect the occurrence of a touch or the location of a touch.

[0069] A touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes and the touch driving circuitry 160.

[0070] The touch sensor may exist outside the display panel 110 in the form of a touch panel, or it may exist inside the display panel 110. If the touch sensor exists outside the display panel 110 in the form of a touch panel, the touch sensor may be referred to as an external type. If the touch sensor is external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. An external type touch panel may include a substrate for the touch panel and a plurality of touch electrodes on the substrate for the touch panel.

[0071] If the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate 111 together with the signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0072] The touch driving circuit 160 can provide a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0073] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0074] If the touch sensing circuit uses a self-capacitance sensing method to perform touch sensing, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes can be used as a driving touch electrode and can also be used as a sensing touch electrode. The touch driving circuit 160 can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0075] If the touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual capacitance sensing method, the multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 160 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0076] The touch driver circuit 160 and touch controller 170 included in the touch sensing circuit can be implemented as separate devices or as a single device. Additionally, the touch driver circuit 160 and data driver circuit 130 can be implemented as separate devices or as a single device.

[0077] The display device 100 may also include a power supply circuit that supplies various types of power to the display driving circuit and / or touch sensing circuit.

[0078] The display device 100 according to the embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet computer, or a monitor or television (TV) of various sizes, and may be a display of various types and sizes capable of displaying information or images, but is not limited thereto.

[0079] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0080] Reference Figure 2 The display panel 110 according to embodiments of the present disclosure may include a substrate 111 on which a plurality of sub-pixels SP are disposed, and an encapsulation layer 200 on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0081] Reference Figure 2 If the display device 100 according to the embodiments of the present disclosure is a self-emissive display device, then each of the plurality of sub-pixels SP arranged on the substrate 111 may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0082] Reference Figure 2 The sub-pixel circuit SPC may include at least one capacitor and a plurality of transistors for driving the light-emitting device ED, but embodiments of the present disclosure are not limited thereto. In the present disclosure, the sub-pixel circuit SPC can drive the light-emitting device ED by supplying driving current to the light-emitting device ED in a predetermined timing sequence. The light-emitting device ED can be driven by the driving current to emit light.

[0083] The multiple transistors may include a driving transistor DT for driving the light-emitting device ED and a scanning transistor ST that is turned on or off according to the scanning signal SC.

[0084] The driving transistor DT can supply driving current to the light-emitting device ED. The scanning transistor ST can be configured to control the electrical state of the corresponding node within the sub-pixel circuit SPC, or to control the state or operation of the driving transistor DT. At least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0085] To drive the sub-pixel SP, a data signal VDATA, which is an image signal, and a scan signal SC, which is a gate signal, can be applied to the sub-pixel SP. Additionally, to drive the sub-pixel SP, a common drive signal including a drive voltage VDD and a base voltage VSS can be applied to the sub-pixel SP.

[0086] The light-emitting device (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE). The intermediate EL may be disposed between the pixel electrode (PE) and the common electrode (CE).

[0087] For example, the pixel electrode PE can be an electrode disposed in each sub-pixel SP, and the common electrode CE can be an electrode typically disposed in multiple sub-pixels SP. For example, the pixel electrode PE can be an anode and the common electrode CE can be a cathode. In another example, the pixel electrode PE can be a cathode and the common electrode CE can be an anode. In the following, for ease of explanation, the case where the pixel electrode PE is an anode and the common electrode CE is a cathode will be illustrated by example.

[0088] If the light-emitting device ED is an organic light-emitting device, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 can be combined and may be referred to as the common intermediate layer EL_COM.

[0089] The emissive layer EML can be set for each sub-pixel SP, or it can be set commonly across multiple sub-pixel SPs. The common intermediate layer EL_COM can be set commonly across multiple sub-pixel SPs, but the implementation of this disclosure is not limited thereto.

[0090] That is, the light-emitting layer EML can be set in each light-emitting region EA, or it can be set commonly across multiple light-emitting regions EA. The common intermediate layer EL_COM can be set commonly across multiple light-emitting regions EA and non-light-emitting regions, but the implementation of this disclosure is not limited to this.

[0091] For example, the first common intermediate layer COM1 may include a hole injection layer HIL, an electron blocking layer EBL, and a hole transport layer HTL, but the embodiments of this disclosure are not limited thereto. The second common intermediate layer COM2 may include an electron transport layer ETL, a hole blocking layer HBL, and an electron injection layer EIL, but the embodiments of this disclosure are not limited thereto.

[0092] The hole injection layer HIL can inject holes from the pixel electrode PE into the hole transport layer HTL, and the hole transport layer HTL can transport holes to the light-emitting layer EML. The electron injection layer EIL can inject electrons from the common electrode CE into the electron transport layer ETL, and the electron transport layer ETL can transport electrons to the light-emitting layer EML.

[0093] For example, the common electrode CE can be electrically connected to the base voltage line VSSL. A base voltage VSS, as a common voltage type, can be applied to the common electrode CE via the base voltage line VSSL. The pixel electrode PE can be directly or indirectly (via another transistor) electrically connected to the first node Na of the driving transistor DT of each sub-pixel SP. In this disclosure, the base voltage VSS may also be referred to as a first common voltage, a low-potential power supply voltage, or a low-potential voltage, and the base voltage line VSSL may also be referred to as a first common voltage line, a low-potential power supply voltage line, or a low-potential voltage line.

[0094] Each light-emitting device (ED) may include a portion overlapping with the pixel electrode (PE), an emissive layer (EML) in the intermediate layer (EL), and a common electrode (CE). A predetermined light-emitting region (EA) may be formed by each ED. For example, the light-emitting region (EA) of each ED may include a portion overlapping with the pixel electrode (PE), an emissive layer (EML) in the intermediate layer (EL), and a common electrode (CE).

[0095] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting device, a micro LED, or a mini LED, but the embodiments of this disclosure are not limited thereto. For example, if the light-emitting device ED is an organic light-emitting diode OLED, the intermediate layer EL in the light-emitting device ED may include an intermediate layer EL containing organic materials.

[0096] The driving transistor DT can be used to supply driving current to the light-emitting device ED. The driving transistor DT can be connected between the driving voltage line VDDL and the light-emitting device ED.

[0097] The driving transistor DT may include a first node Na, a second node Nb, and a third node Nc. The first node Na may be electrically connected to the light-emitting device ED, the second node Nb may be applied with a data signal VDATA, and the third node Nc may be applied with a driving voltage VDD, which is another type of common voltage from the driving voltage line VDDL. The driving transistor DT may be connected between the first node Na and the third node Nc. In this disclosure, the driving voltage VDD may also be described as a second common voltage, a high-potential power supply voltage, or a high-potential voltage, and the driving voltage line VDDL may also be described as a second common voltage line, a low-potential power supply voltage line, or a low-potential voltage line.

[0098] In the driving transistor DT, the second node Nb can be a gate node, the first node Na can be a source node or a drain node, and the third node Nc can be a drain node or a source node. In the following description, for ease of explanation, the second node Nb in the driving transistor DT can be a gate node, the first node Na can be a source node, and the third node Nc can be a drain node, but the embodiments of this disclosure are not limited thereto.

[0099] Included Figure 2 The scanning transistor ST in the sub-pixel circuit SPC shown can be a switching transistor used to transmit the data signal VDATA, which is an image signal, to the second node Nb, which is the gate node of the driving transistor DT.

[0100] The scan transistor ST can be turned on and off by a scan signal SC, which is a type of gate signal, applied via a scan line SCL, which is a type of gate line GL, thereby controlling the electrical connection between the second node Nb of the drive transistor DT and the data line DL. The drain or source electrode of the scan transistor ST can be electrically connected to the data line DL, the source or drain electrode of the scan transistor ST can be electrically connected to the second node Nb of the drive transistor DT, and the gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0101] The storage capacitor Cst can be electrically connected between the first node Na and the second node Nb of the driving transistor DT. The storage capacitor Cst can include at least one capacitor electrode electrically connected to the first node Na of the driving transistor DT or corresponding to the first node Na of the driving transistor DT, and at least one capacitor electrode electrically connected to the second node Nb of the driving transistor DT or corresponding to the second node Nb of the driving transistor DT.

[0102] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that can serve as an internal capacitor between the first node Na and the second node Nb of the driving transistor DT, but the embodiments of this disclosure are not limited thereto.

[0103] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor, but embodiments of this disclosure are not limited thereto. For example, one of the driving transistor DT and the scanning transistor ST can be either an n-type transistor or a p-type transistor.

[0104] The display panel 110 may have a top-emitting structure or a bottom-emitting structure. If the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC may overlap with at least a portion of the light-emitting device ED in the vertical direction. Therefore, the size of the light-emitting area EA can be increased, and the aperture ratio can be increased. If the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC may not overlap with the light-emitting device ED in the vertical direction.

[0105] Sub-pixel circuits (SPCs) can have a 2T (transistor) 1C (capacitor) structure, which includes, for example... Figure 2 The diagram shows two transistors (e.g., DT and ST) and a capacitor Cst, and may also include one or more transistors or one or more capacitors depending on the specific circumstances.

[0106] As an example, the subpixel circuit SPC can have a 3T1C structure including three transistors and one capacitor. As another example, the subpixel circuit SPC can have an 8T1C structure including eight transistors and one capacitor. As yet another example, the subpixel circuit SPC can have a 6T2C structure including six transistors and two capacitors. As yet another example, the subpixel circuit SPC can have a 7T1C structure including seven transistors and one capacitor; however, embodiments of this disclosure are not limited to these.

[0107] Depending on the structure of the sub-pixel circuit SPC, the type and number of gate signals supplied to the sub-pixel SP, as well as the number of gate lines, may vary. Additionally, depending on the structure of the sub-pixel circuit SPC, the type and number of common drive signals supplied to the sub-pixel SP may also vary.

[0108] Since the circuit elements in each sub-pixel SP (e.g., light-emitting devices ED implemented as organic light-emitting diodes (OLEDs) comprising organic materials) are susceptible to external moisture or oxygen, an encapsulation layer 200 can be provided on the display panel 110. The encapsulation layer 200 prevents external moisture or oxygen from penetrating into the circuit elements (e.g., the light-emitting devices ED). The encapsulation layer 200 can be configured in various ways to prevent the light-emitting devices ED from contacting moisture or oxygen. For example, the encapsulation layer 200 can be configured as two or more layers in which organic and inorganic films are alternately stacked, but embodiments of this disclosure are not limited thereto.

[0109] Reference Figure 2 The display device 100 according to embodiments of the present disclosure may include a touch sensor layer 210 having a touch sensor and a touch sensing circuit. The touch sensing circuit senses the touch sensor formed in the touch sensor layer 210 to determine whether a touch or touch coordinates are present, so as to provide touch sensing functionality. Here, the touch sensor layer 210 may also be referred to as a touch unit or a touch sensing unit.

[0110] For example, the touch sensing circuit may include a touch driving circuit 160 and a touch controller 170. The touch driving circuit 160 is configured to drive and sense the touch sensors formed in the touch sensor layer 210 to generate and output touch sensing data. The touch controller 170 is configured to use the touch sensing data provided by the touch driving circuit 160 to determine whether a touch or touch coordinates are present.

[0111] The touch sensor layer 210 may be a layer in which a touch sensor is formed, and the touch sensor may be configured with multiple touch electrodes.

[0112] For example, the touch sensor layer 210 can be disposed outside the display panel 110 and can be configured as a touch panel separate from the display panel 110. In this case, the touch panel and the display panel 110 can be manufactured separately and combined during the assembly process.

[0113] As another example, the touch sensor layer 210 can be integrated into the display panel 110. If the touch sensor layer 210 is included inside the display panel 110, it can be formed on the substrate 111 along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110. For example, the touch sensor layer 210 can be disposed on the encapsulation layer 200. Hereinafter, for ease of explanation, the case where the touch sensor layer 210 is integrated into the display panel 110 will be described as an example.

[0114] If the touch sensor layer 210 is embedded in the display panel 110, the display panel 110 may include, in addition to multiple touch electrodes corresponding to the touch sensors, multiple touch pads TP electrically connected to the touch driving circuit 160, and multiple touch wirings TL electrically connecting the multiple touch electrodes to the multiple touch pads TP. Here, the multiple touch wirings TL can also be referred to as multiple touch lines. In addition, the multiple touch wirings TL can correspond to multiple touch channels.

[0115] The touch driving circuit 160 can supply a touch driving signal to at least one of the plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0116] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing operations.

[0117] If the touch sensing circuit uses a self-capacitance sensing method to perform touch sensing operations, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.). Depending on the self-capacitance sensing method, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the multiple touch electrodes and sense all or some of the multiple touch electrodes.

[0118] If a touch sensing circuit uses a mutual capacitance sensing method to perform touch sensing, it can perform touch sensing based on the capacitance between two adjacent touch electrodes. According to the mutual capacitance sensing method, multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. A touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes. Touch wiring connected to the driving touch electrodes can be referred to as driving touch wiring, and touch wiring connected to the sensing touch electrodes can be referred to as sensing touch wiring.

[0119] The touch driver circuit 160 and the touch controller 170 can be implemented as separate devices or as a single device. Additionally, the touch driver circuit 160 and the data driver circuit 120 can be implemented as separate devices or as a single device.

[0120] The display device 100 may further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit. The power supply circuit may supply various voltages and electrical voltages related to display driving to the display driving circuit or the display panel 110.

[0121] Meanwhile, the display device 100 according to the embodiments of the present disclosure can sense touch based on the capacitance formed on the touch electrode.

[0122] The display device 100 according to embodiments of the present disclosure can sense touch using a touch sensing method based on mutual capacitance, and can also sense touch using a touch sensing method based on self-capacitance.

[0123] Figure 3 An example of the touch electrode TE being used when the display device 100 uses a touch sensing method based on mutual capacitance to sense a touch is shown, and Figure 4 This is an example diagram of the touch electrode TE in a display device 100 according to an embodiment of the present disclosure, where a touch sensing method based on self-capacitance is used to sense a touch.

[0124] Figure 3 The touch sensor structure of a display device 100 performing mutual capacitance-based touch sensing according to an embodiment of the present disclosure is shown.

[0125] Reference Figure 3 The touch sensor according to embodiments of this disclosure may include a plurality of touch electrodes TE. The plurality of touch electrodes TE may include a plurality of horizontal touch electrodes TE_H and a plurality of vertical touch electrodes TE_V.

[0126] Multiple touch electrodes TE can be arranged in the display area DA and can be arranged on the encapsulation layer 200.

[0127] Each of the multiple horizontal touch electrodes TE_H may include two or more horizontal sub-touch electrodes STE_H arranged in the same row (or column) and one or more horizontal bridge electrodes CL_H electrically connected to the horizontal sub-touch electrodes. For example, in Figure 3 In the example, the two or more horizontal sub-touch electrodes STE_H and one or more horizontal bridge electrodes CL_H constituting a horizontal touch electrode TE_H can be integrated touch metal (e.g., a second touch metal). As another example, in Figure 3 In the example, two or more horizontal sub-touch electrodes STE_H can be set in the second touch metal layer, and one or more horizontal bridge electrodes CL_H can be set in the first touch metal layer.

[0128] Each of the multiple vertical touch electrodes TE_V may include two or more vertical sub-touch electrodes STE_V arranged in the same column (or row) and one or more vertical bridge electrodes CL_V electrically connected to the vertical sub-touch electrodes. For example, the two or more vertical sub-touch electrodes STE_V and one or more vertical bridge electrodes CL_V constituting a vertical touch electrode TE_V may be integrated touch metal (e.g., a second touch metal). As another example, in Figure 3In the example, two or more vertical sub-touch electrodes STE_V can be arranged in the second touch metal layer, and one or more vertical bridge electrodes CL_V can be arranged in the first touch metal layer.

[0129] In the region where the horizontal touch electrode TE_H intersects with the vertical touch electrode TE_V (e.g., the touch electrode intersection region), the horizontal bridge electrode CL_H and the vertical bridge electrode CL_V may also intersect.

[0130] In the area where touch electrodes intersect, if the horizontal bridge electrode CL_H intersects with the vertical bridge electrode CL_V, then the horizontal bridge electrode CL_H and the vertical bridge electrode CL_V must be located in different layers.

[0131] Therefore, in order to arrange multiple horizontal touch electrodes TE_H and multiple vertical touch electrodes TE_V in an intersecting manner, multiple horizontal sub-touch electrodes STE_H, multiple horizontal bridging electrodes CL_H, multiple vertical sub-touch electrodes STE_V, multiple vertical touch electrodes TE_V, and multiple vertical bridging electrodes CL_V can be located in two or more layers.

[0132] Reference Figure 3 The touch sensor structure according to embodiments of this disclosure may further include multiple touch wirings TL. The multiple touch wirings TL may include multiple horizontal touch wirings TL_H and multiple vertical touch wirings TL_V.

[0133] Multiple touch wirings (TLs) can be arranged in the non-display area (NDA). At least a portion of the multiple touch wirings (TLs) (e.g., a portion connected to the touch electrodes) can be located in the display area (DA).

[0134] The touch sensor structure according to embodiments of this disclosure may also include multiple touch pads TP.

[0135] At least one of the two outermost horizontal sub-touch electrodes STE_H arranged in a horizontal touch electrode TE_H can be electrically connected to the touch pad TP through the horizontal touch wiring TL_H.

[0136] At least one of the two outermost vertical sub-touch electrodes STE_V arranged in a vertical touch electrode TE_V can be electrically connected to the touch pad TP through the vertical touch wiring TL_V.

[0137] At the same time, such as Figure 3As shown, multiple horizontal touch electrodes TE_H and multiple vertical touch electrodes TE_V can be disposed on the encapsulation layer 200. Multiple horizontal sub-touch electrodes STE_H and multiple horizontal bridge electrodes CL_H constituting the multiple horizontal touch electrodes TE_H can be disposed on the encapsulation layer 200. Multiple vertical sub-touch electrodes STE_V and multiple vertical bridge electrodes CL_V constituting the multiple vertical touch electrodes TE_V can be disposed on the encapsulation layer 200.

[0138] Figure 4 The touch sensor structure of a display device 100 performing self-capacitance-based touch sensing according to an embodiment of the present disclosure is shown.

[0139] Reference Figure 4 In the case of a touch sensing method based on self-capacitance, each touch electrode TE placed on the encapsulation layer 200 can have both the function of a driving touch electrode (for driving signal application) and a sensing touch electrode (for sensing signal detection).

[0140] That is, a driving signal can be applied to each touch electrode TE, and a sensing signal can be received through the touch electrode TE to which the driving signal is applied. Therefore, in the self-capacitance-based touch sensing method, there is no separate distinction between the driving electrode and the sensing electrode.

[0141] In the case of a touch sensing method based on self-capacitance, the touch sensing circuit can apply a drive signal to one or more touch electrodes TE, receive a sensing signal from the touch electrodes TE to which the drive signal is applied, and detect the presence or absence of touch and / or touch coordinates based on the received sensing signal and the capacitance change between an indicator such as a finger or pen and the touch electrodes TE.

[0142] Reference Figure 4 Each of the multiple touch electrodes TE can be electrically connected to the touch driver circuit 160 via one or more touch lines TL for sending drive signals and sensing signals.

[0143] In this way, the touch display device according to the embodiments of the present disclosure can sense touch using a touch sensing method based on mutual capacitance, or it can sense touch using a touch sensing method based on self-capacitance.

[0144] Furthermore, in the touch display device according to the embodiments of the present disclosure, the touch sensor layer 210 may be an integrated type manufactured together with the display panel 110 and existing inside the display panel 110. That is, the display panel 110 according to the embodiments of the present disclosure may have an integrated touch sensor layer 210.

[0145] Furthermore, in embodiments of this disclosure, the touch electrode TE and the touch line TL are electrodes and signal lines existing inside the display panel 110.

[0146] Figure 5 This is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0147] Reference Figure 5 The display panel 110 according to the embodiments of the present disclosure may include a substrate 111, a transistor section, a light-emitting device section and a packaging section, but the embodiments of the present disclosure are not limited thereto.

[0148] The substrate 111 can be a single layer or multiple layers. If the substrate 111 is multilayered, it may include a first substrate 501, an intermediate substrate layer 502, and a second substrate 503. The intermediate substrate layer 502 may be located between the first substrate 501 and the second substrate 503. For example, each of the first substrate 501 and the second substrate 503 may be a polyimide (PI) layer, but embodiments of this disclosure are not limited thereto. The intermediate substrate layer 502 may be an inorganic insulating layer, but embodiments of this disclosure are not limited thereto. When charge is applied to the first substrate 501, which is a polyimide layer, the intermediate substrate layer 502 can prevent the charge from affecting the transistors disposed on the second substrate 503 through the second substrate 503, which is also a polyimide layer.

[0149] Additionally, the intermediate substrate layer 502 can prevent moisture components from penetrating upward through the first substrate 501. For example, the intermediate substrate layer 502 can be formed from a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), and can also be formed from a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0150] The transistor section may include insulating layers 511, 512, 513, 521, 522 and 523 on substrate 111, thin film transistors TFT1 and TFT2, storage capacitor Cst and various electrodes or signal lines.

[0151] The thin-film transistors included in the transistor section may include a first thin-film transistor TFT1 and a second thin-film transistor TFT2.

[0152] The first thin-film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c.

[0153] The first electrode E1a can be a gate electrode, the second electrode E1b can be a source electrode or a drain electrode, and the third electrode E1c can be a drain electrode or a source electrode. In the following description, for ease of explanation, the first electrode E1a can be a first gate electrode E1a, the second electrode E1b can be a first source electrode E1b, and the third electrode E1c can be a first drain electrode E1c. However, embodiments of this disclosure are not limited thereto.

[0154] The first active layer ACT1 may include a first semiconductor material. For example, the first semiconductor material may include oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but embodiments of this disclosure are not limited thereto. The first thin-film transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, but embodiments of this disclosure are not limited thereto.

[0155] The second thin-film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c.

[0156] The fourth electrode E2a can be a gate electrode, the fifth electrode E2b can be a source electrode or a drain electrode, and the sixth electrode E2c can be a drain electrode or a source electrode. In the following description, for ease of explanation, the fourth electrode E2a can be a second gate electrode E2a, the fifth electrode E2b can be a second source electrode E2b, and the sixth electrode E2c can be a second drain electrode E2c. However, embodiments of this disclosure are not limited thereto.

[0157] The second active layer ACT2 may include a second semiconductor material. For example, the second semiconductor material may include oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but embodiments of this disclosure are not limited thereto. The second thin-film transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, but embodiments of this disclosure are not limited thereto.

[0158] The type of semiconductor material for each of the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 can be as follows.

[0159] For example, the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 may comprise an oxide semiconductor material. In another example, the first active layer ACT1 of the first thin-film transistor TFT1 and the second active layer ACT2 of the second thin-film transistor TFT2 may comprise a low-temperature polycrystalline silicon semiconductor material. In yet another example, the first active layer ACT1 of the first thin-film transistor TFT1 may comprise a low-temperature polycrystalline silicon semiconductor material, and the second active layer ACT2 of the second thin-film transistor TFT2 may comprise an oxide semiconductor material. As yet another example, the first active layer ACT1 of the first thin-film transistor TFT1 may comprise an oxide semiconductor material, and the second active layer ACT2 of the second thin-film transistor TFT2 may comprise a low-temperature polycrystalline silicon semiconductor material.

[0160] The transistors within the display area DA can be utilized as follows.

[0161] As an example, all transistors within each sub-pixel SP can be implemented as a first thin-film transistor (TFT1). As another example, all transistors within each sub-pixel SP can be implemented as a second thin-film transistor (TFT2). As yet another example, some of the transistors within each sub-pixel SP can be implemented as first thin-film transistors (TFT1), and some of the remaining transistors can be implemented as second thin-film transistors (TFT2). That is, each sub-pixel SP may include at least one first thin-film transistor (TFT1) and at least one second thin-film transistor (TFT2).

[0162] If some of all transistors in each sub-pixel SP are implemented as first thin-film transistors TFT1, and the remaining ones are implemented as second thin-film transistors TFT2, then the following example is possible.

[0163] As an example, in each sub-pixel SP, the driving transistor DT can be implemented as a first thin-film transistor TFT1, and other transistors besides the driving transistor DT (e.g., the scanning transistor ST and the light-emitting control transistor) can be implemented as a second thin-film transistor TFT2.

[0164] As another example, in each sub-pixel SP, the driving transistor DT can be implemented as a second thin-film transistor TFT2, and other transistors besides the driving transistor DT (e.g., the scanning transistor ST and the light-emitting control transistor) can be implemented as a first thin-film transistor TFT1.

[0165] exist Figure 5In this configuration, depending on the sub-pixel circuit SPC, the first thin-film transistor TFT1 connected to the pixel electrode PE of the light-emitting device ED can be a driving transistor DT or a transistor different from the driving transistor DT. For example, in Figure 5 In this context, the first thin-film transistor TFT1 connected to the pixel electrode PE of the light-emitting device ED can be a light-emitting control transistor connected between the driving transistor DT and the light-emitting device ED.

[0166] The transistors in the non-display area NDA can be used as follows.

[0167] As an example, the active layer of the transistor included in the gate in-panel (GIP) type gate drive circuit 120 may be composed of an oxide semiconductor material. As another example, the active layer of the transistor included in the gate in-panel (GIP) type gate drive circuit 120 may be composed of a low-temperature polycrystalline silicon semiconductor material. As yet another example, among the transistors included in the gate in-panel (GIP) type gate drive circuit 120, some active layers may be composed of a low-temperature polycrystalline silicon semiconductor material, while others may be composed of an oxide semiconductor material.

[0168] The second active layer ACT2 of the second thin-film transistor TFT2 can be located at a higher position than the first active layer ACT1 of the first thin-film transistor TFT1 from the substrate 111.

[0169] A first buffer layer 511 can be disposed below the first active layer ACT1 of the first thin-film transistor TFT1, and a second buffer layer 521 can be disposed below the second active layer ACT2 of the second thin-film transistor TFT2. For example, the first active layer ACT1 of the first thin-film transistor TFT1 can be located on the first buffer layer 511, and the second active layer ACT2 of the second thin-film transistor TFT2 can be located on the second buffer layer 521. The second buffer layer 521 can be positioned higher than the first buffer layer 511.

[0170] The storage capacitor Cst can be disposed within various metal layers within the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0171] The light-emitting device section may include a plurality of light-emitting devices ED disposed on the planarization layer 530. Each of the plurality of light-emitting devices ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0172] The encapsulation portion may include encapsulation layers 200 on multiple light-emitting devices (EDs). The encapsulation layers 200 may be single-layered or multi-layered, but embodiments of this disclosure are not limited thereto. In addition to the encapsulation layers 200, the encapsulation portion may also include at least one dam DAM to prevent the leakage of material constituting the encapsulation layers 200. Specifically, if the second encapsulation layer 542 included in the encapsulation layer 200 is an organic encapsulation layer made of organic material, the dam DAM can prevent the leakage of organic material.

[0173] In the following text, reference will be made to Figure 5 The structure or vertical structure of the display panel 110 according to embodiments of the present disclosure will be described in more detail.

[0174] Reference Figure 5 A first buffer layer 511 can be disposed on the substrate 111. The first buffer layer 511 can be a single layer or multiple layers, but the embodiments of the present disclosure are not limited thereto. If the first buffer layer 511 is multiple layers, the first buffer layer 511 may include a lower buffer layer 511a and an upper buffer layer 511b.

[0175] A first active layer ACT1 of the first thin-film transistor TFT1 can be disposed on the first buffer layer 511. The first active layer ACT1 may include a channel region having a channel formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0176] A first gate insulating layer 512 may be disposed on the first active layer ACT1 of the first thin-film transistor TFT1. A first gate electrode E1a of the first thin-film transistor TFT1 may be disposed on the first gate insulating layer 512. A first interlayer insulating layer 513 may be disposed on the first gate electrode E1a of the first thin-film transistor TFT1. Here, the metal layer on which the first gate electrode E1a of the first thin-film transistor TFT1 is disposed may be referred to as the first gate metal layer.

[0177] A second buffer layer 521 can be provided on the first interlayer insulation layer 513.

[0178] A second active layer ACT2 of the second thin-film transistor TFT2 can be disposed on the second buffer layer 521. The second active layer ACT2 may include a channel region having a channel formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0179] A second gate insulating layer 522 may be disposed on the second active layer ACT2 of the second thin-film transistor TFT2. A second gate electrode E2a of the second thin-film transistor TFT2 may be disposed. A second interlayer insulating layer 523 may be disposed on the second gate electrode E2a of the second thin-film transistor TFT2. Here, the second gate electrode E2a of the second thin-film transistor TFT2 may be referred to as the second gate metal layer.

[0180] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 can be disposed on the second interlayer insulating layer 523.

[0181] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1 can be connected to the source connection region and the drain connection region of the first active layer ACT1 through holes in the second interlayer insulating layer 523, the second gate insulating layer 522, the second buffer layer 521, the first interlayer insulating layer 513, and the first gate insulating layer 512, respectively.

[0182] The second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 can be connected to the source connection region and the drain connection region of the second active layer ACT2 through the holes of the second interlayer insulating layer 523 and the second gate insulating layer 522, respectively.

[0183] The first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2 may include a first source-drain metal and may be disposed within the first source-drain metal layer.

[0184] Reference Figure 5 As an example, the storage capacitor Cst can be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst can be formed by three or more capacitor electrodes, and can be in the form of two or more capacitors connected in parallel.

[0185] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 can be disposed on various metal layers disposed within the display panel 110.

[0186] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 on the first gate insulating layer 512, and may be disposed within the first gate metal layer; however, embodiments of this disclosure are not limited thereto. For example, the second capacitor electrode CAPE2 may be disposed on the first interlayer insulating layer 513.

[0187] The second source electrode E2b of the second thin-film transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 through holes in the second interlayer insulating layer 523, the second gate insulating layer 522, and the second buffer layer 521.

[0188] For example, if sub-pixel SP is as Figure 2 If configured as described above, then the first thin-film transistor TFT1 can be... Figure 2 The scanning transistor ST, and the second thin-film transistor TFT2 can be Figure 2 The driving transistor DT.

[0189] Reference Figure 5 The transistor section may further include a first shielding pattern BSM1 disposed on the substrate 111. The first shielding pattern BSM1 may overlap with the first active layer ACT1 of the first thin-film transistor TFT1. The first shielding pattern BSM1 may be disposed below the first active layer ACT1 of the first thin-film transistor TFT1. For example, the first shielding pattern BSM1 may be disposed between the substrate 111 and the first buffer layer 511, or it may be disposed between the lower buffer layer 511a and the upper buffer layer 511b.

[0190] The transistor section may further include a second shielding pattern BSM2 disposed on the substrate 111. The second shielding pattern BSM2 may overlap with the second active layer ACT2 of the second thin-film transistor TFT2. The second shielding pattern BSM2 may be disposed below the second active layer ACT2 of the second thin-film transistor TFT2. For example, the second shielding pattern BSM2 may be disposed in a metal layer between the first interlayer insulating layer 513 and the second buffer layer 521. The second shielding pattern BSM2 may be disposed in the same metal layer as the second capacitor electrode CAPE2, but embodiments of the present disclosure are not limited thereto. In another example, the second shielding pattern BSM2 may be disposed in the same first gate metal layer as the first gate electrode E1a of the first thin-film transistor TFT1.

[0191] The planarization layer 530 can be disposed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2, and can be disposed below the light-emitting device ED. The planarization layer 530 can be an organic insulating layer including an organic insulating material.

[0192] As an example, planarization layer 530 may consist of one layer. As another example, planarization layer 530 may include two layers. Planarization layer 530 may include a first planarization layer 531 and a second planarization layer 532. As yet another example, planarization layer 530 may include three or more layers. Planarization layer 530 may include a first planarization layer 531, a second planarization layer 532, and a third planarization layer 533. The first planarization layer 531, the second planarization layer 532, and the third planarization layer 533 may be insulating layers. Embodiments of this disclosure are not limited thereto.

[0193] Reference Figure 5 A first planarization layer 531 can be formed on the first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, and on the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2. For example, the first planarization layer 531 can be formed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. For example, the first planarization layer 531 can be formed to cover both the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0194] Reference Figure 5 A connection electrode RE can be disposed on the first planarization layer 531. The connection electrode RE can electrically connect the first source electrode E1b of the first thin-film transistor TFT1 and the pixel electrode PE.

[0195] The connecting electrode RE can be electrically connected to the first source electrode E1b of the first thin-film transistor TFT1 through the holes in the first planarization layer 531.

[0196] The connecting electrode RE can be disposed within the second source-drain metal layer on the first planarization layer 531, and can include the second source-drain metal.

[0197] A second planarization layer 532 can be provided on the connecting electrode RE.

[0198] Reference Figure 5 A light-emitting device portion can be disposed on the second planarization layer 532. A light-emitting device ED can be formed on the second planarization layer 532. The light-emitting device ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting region EA of the light-emitting device ED can be formed in the region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0199] Reference Figure 5 A third planarization layer 533 can be provided between the second planarization layer 532 and the pixel electrode PE of the light-emitting device portion. The third planarization layer 533 can form an opening in the region where the light-emitting device portion is located. That is, the light-emitting device portion can be disposed within the opening of the third planarization layer 533.

[0200] The third planarization layer 533 may be configured to include the same material as the second planarization layer 532. However, the material included in the third planarization layer 533 is not limited to this.

[0201] At least a portion of the pixel electrode PE can be disposed on the second planarization layer 532 to overlap with the opening of the third planarization layer 533. The pixel electrode PE can be electrically connected to the connection electrode RE through the hole in the second planarization layer 532.

[0202] The pixel electrode PE may include a flat surface PE_F disposed flat along the upper surface of the second planarization layer 532. Alternatively, the pixel electrode PE may include an inclined surface PE_S extending along the side surface of the third planarization layer 533 within an opening of the third planarization layer 533.

[0203] A dam 540 can be formed on the pixel electrode PE. The dam 540 can be configured to cover the sloping surface PE_S of the pixel electrode PE. A hole in the dam 540 can expose a portion of the pixel electrode PE to form the light-emitting region EA. The hole in the dam 540 can overlap with a portion of the pixel electrode PE. Alternatively, the hole in the dam 540 can overlap with the flat surface PE_F of the pixel electrode PE.

[0204] According to embodiments of this disclosure, the embankment 540 may be a transparent embankment comprising a transparent material.

[0205] An intermediate layer EL for the light-emitting device ED can be disposed on a portion of the dam 540 and the pixel electrode PE. A common electrode CE can be disposed on the intermediate layer EL.

[0206] Light emitted from the light-emitting device (ED) can be transmitted through components arranged on the ED to the outside of the display panel 110. The light-emitting region EA can be formed by the light emitted from the ED. In this case, the light-emitting region EA corresponding to the flat surface PE_F of the pixel electrode PE can be the main light-emitting region M-EA.

[0207] Simultaneously, some of the light emitted from the light-emitting device ED can be emitted laterally and reflected on the inclined surface PE_S of the pixel electrode PE. The light reflected on the inclined surface PE_S of the pixel electrode PE can be emitted to the outside of the display panel 110 to form a light-emitting region EA corresponding to the inclined surface PE_S of the pixel electrode PE. In this case, the light-emitting region EA corresponding to the inclined surface PE_S of the pixel electrode PE can be referred to as a sub-light-emitting region S-EA. The sub-light-emitting region S-EA can be formed in a ring shape around the main light-emitting region M-EA, but is not limited to this.

[0208] According to embodiments of the present disclosure, by forming a pixel electrode PE including a tilted surface PE_S, the display device 100 may include a sub-light-emitting region S-EA, thereby providing the effect of increasing the brightness output from the display panel 110.

[0209] Reference Figure 5 An encapsulation portion can be provided on the light-emitting device portion, and the encapsulation portion can be located on the common electrode CE. The encapsulation portion may include an encapsulation layer 200 formed on the common electrode CE.

[0210] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting device (ED). For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the ED. The encapsulation layer 200 can consist of a single layer or multiple layers, but the embodiments of this disclosure are not limited thereto.

[0211] For example, the encapsulation layer 200 may include a first encapsulation layer 541, a second encapsulation layer 542, and a third encapsulation layer 543, but the embodiments of this disclosure are not limited thereto. For example, the first encapsulation layer 541 and the third encapsulation layer 543 may include inorganic encapsulation layers, and the second encapsulation layer 542 may include an organic encapsulation layer, but the embodiments of this disclosure are not limited thereto.

[0212] The display panel 110 according to embodiments of the present disclosure may further include a built-in touch sensor. In this case, the display panel 110 according to embodiments of the present disclosure may include a touch sensor layer 210 disposed on the encapsulation layer 200 and having a touch sensor formed thereon.

[0213] Reference Figure 5 The touch sensor layer 210 may include a plurality of touch electrodes TE corresponding to the touch sensor, and may include at least one touch metal layer for forming the plurality of touch electrodes TE.

[0214] For example, the touch sensor layer 210 may include a first touch metal layer on which a plurality of first touch metals TM1 are disposed, and a second touch metal layer on which a plurality of second touch metals TM2 are disposed, to form a plurality of touch electrodes TE. In this case, the touch sensor layer 210 may also include a touch interlayer insulating layer 552 disposed between the first touch metal layer and the second touch metal layer.

[0215] For example, one of the first touch metal layer and the second touch metal layer can be a sensor metal layer, and the other can be a bridging metal layer.

[0216] As an example, the first touch metal layer can be a bridging metal layer, and the second touch metal layer can be a sensor metal layer. In this case, the plurality of second touch metals TM2 arranged in the second touch metal layer can be sensor metals forming a touch sensor, and the plurality of first touch metals TM1 arranged in the first touch metal layer can be bridging metals electrically connecting the plurality of second touch metals TM2 as sensor metals. For example, two or more second touch metals TM2 and at least one first touch metal TM1 can form a first touch electrode TE1. In this case, the two or more second touch metals TM2 can be electrically connected through at least one first touch metal TM1.

[0217] As another example, the first touch metal layer may be a sensor metal layer, and the second touch metal layer may be a bridging metal layer. In this case, the plurality of first touch metals TM1 arranged in the first touch metal layer may be sensor metals forming a touch sensor, and the plurality of second touch metals TM2 arranged in the second touch metal layer may be bridging metals electrically connecting the plurality of first touch metals TM1 that serve as sensor metals.

[0218] Reference Figure 5 The touch sensor layer 210 may further include a touch buffer layer 551 disposed on the encapsulation layer 200. The touch buffer layer 551 may be disposed between the encapsulation layer 200 and the touch metal layer. For example, a first touch metal layer may be disposed on the touch buffer layer 551, and an interlayer insulating layer 552 may be disposed on the first touch metal layer.

[0219] Reference Figure 5 The touch sensor layer 210 may also include a touch protection layer 553 disposed while covering the touch metal layer. For example, the touch protection layer 553 may be disposed on the second touch metal layer.

[0220] For example, the touch buffer layer 551 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material, the touch interlayer insulation layer 552 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material, and the touch protection layer 553 may be an inorganic layer including inorganic insulating material or an organic layer including organic insulating material.

[0221] For example, at least one of the touch buffer layer 551 and the touch interlayer insulating layer 552 may be configured to extend from the display area DA to the non-display area NDA. The touch protection layer 553 may be configured to extend from the display area DA to the non-display area NDA.

[0222] The touch wiring TL can electrically connect the touch electrode TE and the touch pad TP. The touch wiring TL can consist of at least one of a first touch metal TM1 and a second touch metal TM2.

[0223] For example, a touch wiring TL can be composed of a first touch metal TM1, a second touch metal TM2, or both. If a touch wiring TL is composed of a first touch metal TM1 and a second touch metal TM2, then the first touch metal TM1 and the second touch metal TM2 constituting a touch wiring TL can be electrically connected through the holes in the insulating layer 552.

[0224] For example, a touch wiring TL can include multiple segments, and each of the multiple segments can be a single segment or a double segment. Here, a single segment can be a segment with one signal path, and a double segment can be a segment with two signal paths connected in parallel.

[0225] The touch wiring TL can be arranged along the inclined surface SLP_ENCAP of the package layer 200 and can extend through the top of the dam DAM to the touch pad TP.

[0226] The touch buffer layer 551 may have an opening through which at least a portion of the touch pad TP is exposed. Touch wiring TL can be electrically connected to the touch pad TP through the opening in the touch buffer layer 551. An interlayer insulation layer 552 may be disposed on the touch wiring TL and may extend to the area where the touch pad TP is disposed. A touch protection layer 553 may be disposed only on the display area DA, or may be configured to extend to the non-display area NDA and may be disposed on top of the touch wiring TL. In some cases, the touch protection layer 553 may also extend above the touch pad TP.

[0227] Each of the plurality of touch electrodes TE can be a grid-type electrode having a plurality of open regions OA. In this case, each of the plurality of touch electrodes TE can consist of at least one second touch metal TM2. However, embodiments of the present disclosure are not limited thereto.

[0228] For example, multiple touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. If the first touch metal layer is a bridging metal layer and the second touch metal layer is a sensor metal layer, then two or more second touch metals TM2 forming the first touch electrode TE1 corresponding to the touch sensor can be electrically connected through at least one first touch metal TM1 serving as a bridging metal. For example, two second touch metals TM2 spaced apart from each other can be electrically connected through a first touch metal TM1 to form a first touch electrode TE1.

[0229] Reference Figure 5 Multiple first touch metals TM1 and multiple second touch metals TM2 can be arranged so as not to overlap with the light-emitting device ED. The multiple first touch metals TM1 and multiple second touch metals TM2 can overlap with the embankment 540. Therefore, the luminous efficiency of the light-emitting device ED can be improved.

[0230] If multiple touch electrodes TE are grid-type electrodes with multiple open areas OA, then touch metals TM1 and TM2 can form a grid shape. Figure 6 This is a diagram illustrating the correspondence between the grid-type touch electrode TE and the sub-pixel SP in a display device 100 according to an embodiment of the present disclosure.

[0231] Figure 6 This is a diagram illustrating the correspondence between the grid-type touch electrode TE and the sub-pixel SP in a display device 100 according to an embodiment of the present disclosure.

[0232] Reference Figure 6 Each of the multiple opening regions OA existing in the area of ​​the grid-patterned touch electrode TE, including the touch metal TM, can correspond to the light-emitting region EA of one or more sub-pixels SP.

[0233] For example, each of the multiple opening regions OA existing in the area of ​​a touch electrode TE may correspond to one or more of the light-emitting regions EA of red sub-pixels, green sub-pixels, blue sub-pixels, etc.

[0234] As another example, each of the multiple opening regions OA existing within the area of ​​a touch electrode TE may correspond to one or more of the light-emitting regions EA of the red sub-pixel, green sub-pixel, blue sub-pixel, and white sub-pixel.

[0235] That is, each of the multiple opening regions OA existing in the area of ​​the touch electrode TE can vertically overlap with the pixel electrode PE that forms the light-emitting region EA.

[0236] As described above, in the plan view, since the light-emitting area EA of one or more sub-pixels SP exists in each of the opening areas OA of each touch electrode TE, touch sensing is enabled, and the effect of further increasing the aperture ratio and luminous efficiency of the display panel 110 is also achieved.

[0237] As described above, the general outline of the outer surface of a touch electrode TE can be rhomboid or rectangular (including square), and the opening area OA corresponding to the hole in a touch electrode TE can also have a rhomboid or rectangular (including square) shape.

[0238] However, considering the shape of the sub-pixel SP, the arrangement structure of the sub-pixel SP, and the touch sensitivity, the shape of the touch electrode TE and the shape of the opening area OA can be designed to be modified in various ways.

[0239] Figure 7 It is magnification Figure 6 An example plan view of the X region of the touch electrode TE is shown.

[0240] Reference Figure 7 An opening region OA can be formed according to the shape of each light-emitting region EA corresponding to the sub-pixel SP.

[0241] Some opening regions OA can correspond to the light-emitting region of the red subpixel (EA of the red subpixel). Some opening regions OA can correspond to the light-emitting region of the green subpixel (EA of the green subpixel). Some opening regions OA can correspond to the light-emitting region of the blue subpixel (EA of the blue subpixel).

[0242] Touch Metal™ can be formed into a grid pattern so that it does not overlap with each luminous area (EA).

[0243] Figure 8 It is magnification Figure 7 An example plan view of region A of the touch electrode TE is shown.

[0244] Reference Figure 8 The touch metal TM included in the touch electrode TE can form an opening region OA. A light-emitting region EA can be set in the opening region OA.

[0245] The luminous region EA can include the main luminous region M-EA and the sub-luminous region S-EA.

[0246] Reference Figure 5 and Figure 8 The main light-emitting region M-EA can be the light-emitting region EA that vertically corresponds to the flat surface PE_F of the pixel electrode PE.

[0247] Reference Figure 5 and Figure 8 The sub-emitting region S-EA can be the emitting region EA that vertically corresponds to the inclined surface PE_S of the pixel electrode PE. The sub-emitting region S-EA can be formed around the main emitting region M-EA.

[0248] The Touch Metal™ can be configured to surround the sub-emitting area S-EA. The opening area OA of the Touch Metal™ can overlap with the main emitting area M-EA and the sub-emitting area S-EA.

[0249] The sub-emitting region S-EA can include corner sub-emitting region S-EA(v) and non-corner sub-emitting region S-EA(s).

[0250] Reference Figure 8 The sub-light-emitting region S-EA adjacent to each side of the main light-emitting region M-EA can be a non-corner sub-light-emitting region S-EA(s). In addition, the sub-light-emitting region S-EA adjacent to the corner of the main light-emitting region M-EA can be a corner sub-light-emitting region S-EA(v).

[0251] Depending on the shape of the light-emitting region EA, the amount of light reflected per unit area of ​​the inclined surface PE_S of the pixel electrode PE corresponding to the corner light-emitting region S-EA(v) can be less than the amount of light reflected per unit area of ​​the inclined surface PE_S of the pixel electrode PE corresponding to the non-corner light-emitting region S-EA(s). Therefore, the brightness of the light output from the corner light-emitting region S-EA(v) can be lower than the brightness of the light output from the non-corner light-emitting region S-EA(s).

[0252] Figure 9 It is along Figure 8 A portion of the cross-sectional view of the display panel 110 along line B-B' shown.

[0253] As above Figure 5 As described in, refer to Figure 9 A third planarization layer 533 can be disposed on the second planarization layer 532. The third planarization layer 533 can form an opening in the region where the light-emitting device ED is disposed. That is, the light-emitting device ED can be disposed in the opening of the third planarization layer 533.

[0254] A pixel electrode PE can be disposed within an opening in the third planarization layer 533. The pixel electrode PE can be configured to extend along one side of the opening in the third planarization layer 533 and include a tilted surface PE_S. That is, the pixel electrode PE can be configured to include a flat surface PE_F corresponding to the opening in the third planarization layer 533 and a tilted surface PE_S corresponding to the side portion of the third planarization layer 533. The tilted surface PE_S of the pixel electrode PE can be configured to surround the flat surface PE_F.

[0255] A dam 540 can be provided on the pixel electrode PE. The dam 540 can be configured to include a hole overlapping a portion of the flat surface PE_F of the pixel electrode PE. The dam 540 can be configured to cover the sloping surface of the pixel electrode PE.

[0256] An emitting layer EL can be disposed in the aperture of the dam 540. The emitting layer EL can be disposed adjacent to the pixel electrode PE in the aperture of the dam 540.

[0257] A common electrode CE can be disposed on the light-emitting layer EL. The common electrode CE can extend along the side of the embankment 540.

[0258] The pixel electrode PE, the light-emitting layer EL, and the common electrode CE can overlap to form a light-emitting device ED. The overlapping area of ​​the pixel electrode PE, the light-emitting layer EL, and the common electrode CE can form the main light-emitting region M-EA. The main light-emitting region M-EA can correspond to a portion of the flat surface PE_F of the pixel electrode PE.

[0259] The tilted surface PE_S of the pixel electrode PE can emit light generated from the light-emitting device ED to the outside of the display panel 110 to form a sub-light-emitting region S-EA. In a plan view, the sub-light-emitting region S-EA can correspond to the tilted surface PE_S of the pixel electrode PE. The sub-light-emitting region S-EA can be formed around the main light-emitting region M-EA.

[0260] An encapsulation layer 200 can be provided on the common electrode CE. The encapsulation layer 200 may include a first encapsulation layer 541, a second encapsulation layer 542, and a third encapsulation layer 543.

[0261] A touch buffer layer 551 may be provided on the encapsulation layer 200. A touch interlayer insulating layer 552 may be provided on the touch buffer layer 551. A touch metal TM forming a touch electrode TE may be provided on the touch interlayer insulating layer 552.

[0262] The touch metal TM may include an opening area OA, allowing light emitted from the light-emitting device ED to be emitted to the outside of the display panel 110. The touch metal TM may not be located in the opening area OA. Light emitted from the light-emitting device ED can be emitted to the outside of the display panel 110 through the opening area OA of the touch metal TM.

[0263] The tilted surface PE_S of the pixel electrode PE can be set within the opening area OA of the touch metal TM.

[0264] The Touch Metal™ can be configured to overlap with the Embankment 540. The Touch Metal™ can also be configured not to overlap with the main emitting area M-EA and the sub-emitting area S-EA. Because the Touch Metal™ does not overlap with the main emitting area M-EA and the sub-emitting area S-EA, light extraction efficiency can be increased, thereby increasing brightness.

[0265] Meanwhile, some of the light emitted from the light-emitting device (ED) can travel in an oblique direction and be reflected inside the touch metal TM. The light reflected from inside the touch metal TM may not be emitted to the outside of the display panel 110, which may lead to a reduction in light efficiency.

[0266] Therefore, the display device 100 according to the embodiments of the present disclosure can form pores in the touch metal TM to transmit light output from the light-emitting device ED to increase light efficiency.

[0267] Figure 10 This is a diagram illustrating a grid-type touch electrode TE including apertures 1000 in a display device 100 according to an embodiment of the present disclosure.

[0268] Reference Figure 10 The touch electrode TE may include a touch metal TM patterned as a grid. Each of the multiple opening regions OA present in the area of ​​the touch electrode TE may correspond to the light-emitting region EA of one or more sub-pixels SP.

[0269] That is, each of the multiple opening regions OA in the area of ​​the touch electrode TE can vertically overlap with the pixel electrode PE that forms the light-emitting region EA.

[0270] Meanwhile, the touch metal TM constituting the touch electrode TE may include a plurality of apertures 1000. The touch metal TM may be patterned as a grid and may include a plurality of apertures 1000 perforated in the touch metal TM in a direction perpendicular to the substrate 111. The apertures 1000 may include corner apertures 1000v and non-corner apertures 1000s.

[0271] The corner aperture 1000v can be an aperture 1000 adjacent to each vertex or corner of the opening region OA of the touch electrode TE. The non-corner aperture 1000s can be an aperture 1000 adjacent to each side of the opening region OA of the touch electrode TE. The size of the corner aperture 1000v can be larger than the size of the non-corner aperture 1000s.

[0272] Furthermore, each of the opening regions OA of the touch electrode TE can be larger than the size of each of the plurality of apertures 1000. That is, the opening region OA can be larger than the non-corner aperture 1000s. The opening region OA can be larger than the corner aperture 1000v.

[0273] Multiple apertures 1000 can be arranged to surround the opening region OA along the touch metal TM of the touch electrode TE.

[0274] Figure 11 Is Figure 7 The touch metal TM of the touch electrode TE in the middle includes, for example, Figure 10 Example of a plan view of the magnified region A of the touch electrode TE in the case of a pore size of 1000.

[0275] Reference Figure 11 The touch metal TM included in the touch electrode TE can form an opening region OA. A light-emitting region EA can be set in the opening region OA.

[0276] The luminous region EA can include the main luminous region M-EA and the sub-luminous region S-EA.

[0277] Reference Figure 5 and Figure 11 The main light-emitting region M-EA can be the light-emitting region EA that vertically corresponds to the flat surface PE_F of the pixel electrode PE.

[0278] Reference Figure 5 and Figure 11 The sub-emitting region S-EA can be the emitting region EA that vertically corresponds to the inclined surface PE_S of the pixel electrode PE. The sub-emitting region S-EA can be formed around the main emitting region M-EA.

[0279] The Touch Metal™ can be configured to surround the sub-emitting area S-EA. The opening area OA of the Touch Metal™ can overlap with the main emitting area M-EA and the sub-emitting area S-EA.

[0280] The sub-emitting region S-EA can include corner sub-emitting region S-EA(v) and non-corner sub-emitting region S-EA(s).

[0281] As above Figure 8 As described, depending on the shape of the light-emitting region EA, the amount of light reflected per unit area of ​​the inclined surface PE_S of the pixel electrode PE corresponding to the corner light-emitting region S-EA(v) can be less than the amount of light reflected per unit area of ​​the inclined surface PE_S of the pixel electrode PE corresponding to the non-corner light-emitting region S-EA(s). Therefore, the brightness of the light output from the corner light-emitting region S-EA(v) can be lower than the brightness of the light output from the non-corner light-emitting region S-EA(s). This can lead to uneven brightness.

[0282] Meanwhile, the touch metal™ can include apertures 1000. Apertures 1000 can include corner apertures 1000v and non-corner apertures 1000s. Corner apertures 1000v can be larger than non-corner apertures 1000s.

[0283] The aperture 1000 provides a path for transmitting some of the light output from the light-emitting device ED and outputting it to the outside of the display panel 110. Therefore, light can be output from the touch metal™ area where the aperture 1000 is formed.

[0284] In this case, since the size of the corner aperture 1000v is larger than that of the non-corner aperture 1000s, the amount of light output through the corner aperture 1000v can be greater than that through the non-corner aperture 1000s. Therefore, because more light is output through the corner aperture 1000v than through the non-corner aperture 1000s, the brightness in the region corresponding to the corner aperture 1000v can be higher than the brightness in the region corresponding to the non-corner aperture 1000s.

[0285] Reference Figure 11 The corner aperture 1000v can be arranged adjacent to the corner light-emitting region S-EA(v), and the non-corner aperture 1000s can be arranged adjacent to the non-corner light-emitting region S-EA(s). That is, the corner aperture 1000v, which provides higher brightness than the non-corner aperture 1000s, can be arranged adjacent to the corner light-emitting region S-EA(v), which has lower brightness than the non-corner light-emitting region S-EA(s). Conversely, the non-corner aperture 1000s, which provides lower brightness than the corner aperture 1000v, can be arranged adjacent to the non-corner light-emitting region S-EA(s), which has higher brightness than the corner light-emitting region S-EA(v).

[0286] Therefore, it is possible to compensate for the uneven brightness caused by the corner luminous region S-EA(v) having lower brightness than the non-corner luminous region S-EA(s).

[0287] Figure 12 It is along Figure 11 The line C-C' shown represents a portion of the cross-sectional view of the display panel 110.

[0288] As above Figure 5 and Figure 9 As described in, refer to Figure 11 A third planarization layer 533 can be disposed on the second planarization layer 532. The third planarization layer 533 can form an opening in the region where the light-emitting device ED is disposed. That is, the light-emitting device ED can be disposed in the opening of the third planarization layer 533.

[0289] A pixel electrode PE can be disposed within an opening in the third planarization layer 533. The pixel electrode PE can be configured to extend along one side of the opening in the third planarization layer 533 and include a tilted surface PE_S. That is, the pixel electrode PE can be configured to include a flat surface PE_F corresponding to the opening in the third planarization layer 533 and a tilted surface PE_S corresponding to the side surface of the third planarization layer 533. The tilted surface PE_S of the pixel electrode PE can be configured to surround the flat surface PE_F.

[0290] A dam 540 can be provided on the pixel electrode PE. The dam 540 can be configured to include a hole overlapping a portion of the flat surface PE_F of the pixel electrode PE. The dam 540 can be configured to cover the sloping surface of the pixel electrode PE.

[0291] An emitting layer EL can be disposed within the aperture of the dam 540. The emitting layer EL can be disposed adjacent to the pixel electrode PE within the aperture of the dam 540. The aperture of the dam 540 can have a smaller size than the opening of the second planarization layer 532.

[0292] A common electrode CE can be placed on the light-emitting layer EL. The common electrode CE can extend along the side of the embankment.

[0293] The pixel electrode PE, the light-emitting layer EL, and the common electrode CE can overlap to form a light-emitting device ED. The overlapping area of ​​the pixel electrode PE, the light-emitting layer EL, and the common electrode CE can form the main light-emitting region M-EA. The main light-emitting region M-EA can correspond to a portion of the flat surface PE_F of the pixel electrode PE.

[0294] The tilted surface PE_S of the pixel electrode PE can emit light generated from the light-emitting device ED to the outside of the display panel 110 to form a sub-light-emitting region S-EA. In a plan view, the sub-light-emitting region S-EA can correspond to the tilted surface PE_S of the pixel electrode PE. The sub-light-emitting region S-EA can be formed around the main light-emitting region M-EA.

[0295] An encapsulation layer 200 can be provided on the common electrode CE. The encapsulation layer 200 may include a first encapsulation layer 541, a second encapsulation layer 542, and a third encapsulation layer 543.

[0296] A touch buffer layer 551 may be provided on the encapsulation layer 200. A touch interlayer insulating layer 552 may be provided on the touch buffer layer 551. A touch metal TM forming a touch electrode TE may be provided on the touch interlayer insulating layer 552.

[0297] The touch metal TM may include an opening area OA, allowing light emitted from the light-emitting device ED to be output to the outside of the display panel 110. The touch metal TM may not be located in the opening area OA. Light emitted from the light-emitting device ED can be output to the outside of the display panel 110 through the opening area OA of the touch metal TM.

[0298] The tilted surface PE_S of the pixel electrode PE can be set within the opening area OA of the touch metal TM.

[0299] The Touch Metal™ can be configured to overlap with the Embankment 540. The Touch Metal™ can also be configured not to overlap with the main emitting area M-EA and the sub-emitting area S-EA. Because the Touch Metal™ does not overlap with the main emitting area M-EA and the sub-emitting area S-EA, light extraction efficiency can be increased, thereby increasing brightness.

[0300] Additionally, multiple apertures 1000 can be formed in the touch metal TM. These apertures 1000 can be formed in the touch metal TM in a vertical direction relative to the substrate 111. The multiple apertures 1000 can provide paths for some of the light emitted from the light-emitting device ED to the outside of the display panel 110. Therefore, the touch metal region TMA having multiple apertures 1000 can output light. Furthermore, the touch metal region TMA including the multiple apertures 1000 can be included in the light-emitting region EA.

[0301] Reference Figure 12 Some of the multiple apertures 1000 may vertically overlap with the pixel electrode PE. The remaining apertures 1000 may not vertically overlap with the pixel electrode PE. Additionally, the multiple apertures 1000 may overlap with the embankment 540. The multiple apertures 1000 may not overlap with the light-emitting layer EL.

[0302] Reference Figure 12 The display panel 110 may include a main light-emitting region M-EA corresponding to the flat surface PE_F of the pixel electrode PE, a sub-light-emitting region S-EA corresponding to the tilted surface PE_S of the pixel electrode PE, and a touch metal region TMA corresponding to the touch metal TM of the pixel electrode PE. In this case, light can be output through the aperture 1000 in the touch metal region TMA.

[0303] The sub-emitting area S-EA can be set to surround the main emitting area M-EA. The touch metal area TMA can be set to surround the sub-emitting area S-EA.

[0304] Meanwhile, the holes 1000 in Touch Metal™ can be set to various shapes.

[0305] Figure 13 and Figure 14 This is a plan view showing an example of the shape of the aperture 1000 disposed in the Touch Metal TM.

[0306] For example, the multiple apertures 1000 provided in the Touch Metal™ can all have the same shape. (See reference...) Figure 13 Multiple pores of 1000 can all be squares of the same size.

[0307] Multiple pores 1000 can be formed by patterning Touch Metal™ into a ladder-like pattern.

[0308] As another example, the multiple apertures 1000 disposed in the Touch Metal™ may include apertures 1000 of different shapes. (See reference...) Figure 14The plurality of pores 1000 disposed in the touch metal TM may include a first pore 1000a and a second pore 1000b. The first pore 1000a and the second pore 1000b may have different shapes.

[0309] For example, the first pore 1000a can have a square shape that is rhomboid in shape. The second pore 1000b can have an isosceles triangular shape.

[0310] The first aperture 1000a and the second aperture 1000b can be alternately patterned and arranged on the Touch Metal™ at a ratio of 1:2.

[0311] Figure 15 It shows the relationship with Figure 8 The corresponding luminous area EA in the planar diagram.

[0312] Reference Figure 15 If the touch metal TM constituting the touch electrode TE does not include the aperture 1000, then the touch metal TM may include the main light-emitting region M-EA and the sub-light-emitting region S-EA.

[0313] The main light-emitting region M-EA can be the light-emitting region EA corresponding to the flat surface PE_F of the pixel electrode PE. The sub-light-emitting region S-EA can be the light-emitting region EA corresponding to the tilted surface PE_S of the pixel electrode PE.

[0314] Since the inclined surface PE_S of the pixel electrode PE is set to surround the flat surface PE_F of the pixel electrode PE, the sub-light-emitting region S-EA can be set to surround the main light-emitting region M-EA.

[0315] The sub-emitting region S-EA can include corner sub-emitting region S-EA(v) and non-corner sub-emitting region S-EA(s).

[0316] In this case, as mentioned above Figure 8 and Figure 11 As described in the text, the brightness or luminance of the corner luminous region S-EA(v) and the non-corner luminous region S-EA(s) can differ depending on the shape of the luminous region EA.

[0317] For example, the amount of light reflected per unit area of ​​the tilted surface PE_S of the pixel electrode PE corresponding to the corner emitting region S-EA(v) can be less than the amount of light reflected per unit area of ​​the tilted surface PE_S of the pixel electrode PE corresponding to the non-corner emitting region S-EA(s). Therefore, the brightness of the light output from the corner emitting region S-EA(v) can be dimmer or lower than the brightness of the light output from the non-corner emitting region S-EA(s).

[0318] The size of the apertures in Touch Metal™ can be used to compensate for the brightness issues of the corner luminous area S-EA(v).

[0319] Figure 16 It shows the relationship with Figure 11 The corresponding luminous area EA in the planar diagram.

[0320] Reference Figure 16 If the touch metal TM constituting the touch electrode TE includes multiple pores 1000, then the touch metal TM may include a main light-emitting region M-EA, a sub-light-emitting region S-EA, and a touch metal region TMA.

[0321] Reference Figure 11 and Figure 16 The touch metal area TMA corresponding to the area where the touch metal TM is set may include a plurality of apertures 1000 capable of outputting light to the outside of the display panel 110. Therefore, the touch metal area TMA may be included in the light-emitting area EA.

[0322] The main emitting region M-EA and the sub-emitting region S-EA can be as described above. Figure 15 The main emitting region M-EA and the sub-emitting region S-EA are the same.

[0323] Reference Figure 16 The luminous area EA of the display panel 110 may also include a touch metal area TMA. The touch metal area TMA may be configured to surround the sub-luminous area S-EA.

[0324] The Touch Metal Area (TMA) can include corner Touch Metal Area (EMA(v)) and non-corner Touch Metal Area (EMA(s)).

[0325] Reference Figure 11 and Figure 16 The corner aperture 1000v can correspond to the corner touch metal area EMA(v). That is, the corner touch metal area EMA(v) and the corner aperture 1000v can overlap vertically. Similarly, the non-corner aperture 1000s can correspond to the non-corner touch metal area EMA(s). That is, the non-corner touch metal area EMA(s) and the non-corner aperture 1000s can overlap vertically.

[0326] In this case, the corner aperture 1000v can have a larger size than the non-corner aperture 1000s and can output a greater amount of light. Therefore, the brightness of the corner touch metal area EMA(v) corresponding to the corner aperture 1000v can be higher than the brightness of the non-corner touch metal area EMA(s) corresponding to the non-corner aperture 1000s.

[0327] Additionally, a corner touch metal area EMA(v) with higher brightness than the non-corner touch metal area EMA(s) can be positioned adjacent to a corner sub-light-emitting area S-EA(v) with lower brightness than the non-corner sub-light-emitting area S-EA(s). Conversely, a non-corner touch metal area EMA(s) with lower brightness than the corner touch metal area EMA(v) can be positioned adjacent to a non-corner light-emitting area S-EA(s) with higher brightness than the corner sub-light-emitting area S-EA(v).

[0328] The relatively dark corner light-emitting area S-EA(v) and the relatively bright corner touch metal area EMA(v) can be arranged adjacent to each other, which can reduce the problem of brightness non-uniformity in the light-emitting area caused by the lower brightness of the corner light-emitting area S-EA(v).

[0329] The display device according to embodiments of this disclosure can be briefly described as follows.

[0330] A display device according to embodiments of the present disclosure may include: a substrate, the substrate including a display area and a non-display area; a plurality of pixel electrodes disposed on the display area of ​​the substrate; a common electrode disposed on the plurality of pixel electrodes; an encapsulation layer disposed on the common electrode; and a touch electrode disposed on the encapsulation layer and including a touch metal having a plurality of opening areas, wherein the touch metal has a plurality of holes through which perforations are made in a direction perpendicular to the substrate.

[0331] The size of each of the multiple open regions can be larger than the size of each of the multiple pores.

[0332] Multiple opening regions can vertically overlap with multiple pixel electrodes respectively.

[0333] Each of the multiple apertures may not vertically overlap with at least a portion of the multiple pixel electrodes.

[0334] All pores in a plurality of pores can have the same shape.

[0335] At least one of the multiple pores may have a different shape than the other pores.

[0336] The display device according to embodiments of this disclosure may further include: a first insulating layer disposed between a substrate and a plurality of pixel electrodes; a second insulating layer disposed on the first insulating layer and having an opening overlapping a portion of a first pixel electrode among the plurality of pixel electrodes; a dam disposed on the first pixel electrode, overlapping the opening and having a hole smaller than the opening; and a light-emitting layer disposed on the first pixel electrode. A common electrode may be disposed on the light-emitting layer and extend along a side surface of the dam. The first pixel electrode may include: a flat surface overlapping the opening; and an inclined surface disposed on the first insulating layer in the opening and extending along a side surface of the second insulating layer.

[0337] Multiple pores can overlap with the dike.

[0338] Multiple pores may not overlap with the light-emitting layer.

[0339] An inclined surface can be set within the opening area.

[0340] The display device according to embodiments of the present disclosure may further include: a first light-emitting region overlapping a flat surface; a second light-emitting region overlapping an inclined surface; and a third light-emitting region surrounding the second light-emitting region and overlapping at least a portion of a plurality of apertures.

[0341] The second light-emitting area may include a first corner area and a first non-corner area, wherein the brightness of the first corner area may be lower than the brightness of the first non-corner area. The third light-emitting area may include a second corner area and a second non-corner area, and the brightness of the second corner area may be higher than the brightness of the second non-corner area.

[0342] The multiple pores may include a first pore located in the second corner region and a second pore located in the second non-corner region. The size of each of the first pores may be larger than the size of each of the second pores.

[0343] A display device according to embodiments of the present disclosure may include: a substrate including a display area; a pixel electrode including sub-pixels disposed in the display area, the pixel electrode including a flat surface and an inclined surface surrounding the flat surface; a dam disposed on the pixel electrode and having holes overlapping at least a portion of the pixel electrode; and a touch metal disposed above the dam and having a plurality of holes. The light-emitting area of ​​the sub-pixel may include: a first light-emitting area overlapping the flat surface; a second light-emitting area surrounding the first light-emitting area and overlapping at least a portion of the inclined surface; and a third light-emitting area surrounding the second light-emitting area and overlapping at least a portion of the plurality of holes.

[0344] The second light-emitting area may include a first corner area and a first non-corner area, and the brightness of the first corner area may be lower than the brightness of the first non-corner area.

[0345] The third light-emitting area may include the second corner area and the second non-corner area, and the brightness of the second corner area may be greater than the brightness of the second non-corner area.

[0346] The multiple pores may include a first pore located in the second corner region and a second pore located in the second non-corner region. The size of each of the first pores may be larger than the size of each of the second pores.

[0347] The display device according to embodiments of the present disclosure may further include: a first insulating layer disposed between a substrate and a pixel electrode; a second insulating layer disposed on the first insulating layer and having an opening overlapping a portion of the pixel electrode; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer and extending along a side surface of the embankment. The pixel electrode may be disposed on the first insulating layer within the opening, and the inclined surface may extend along the side surface of the second insulating layer.

[0348] Multiple pores can overlap with the dike.

[0349] Multiple pores may not overlap with the light-emitting layer.

[0350] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of the present invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area; A plurality of pixel electrodes are arranged on the display area of ​​the substrate; A common electrode, which is disposed on the plurality of pixel electrodes; An encapsulation layer is disposed on the common electrode; as well as Touch electrodes, the touch electrodes being disposed on the encapsulation layer and comprising touch metal having multiple opening regions, The touch metal has a plurality of holes perforated in a direction perpendicular to the substrate.

2. The display device according to claim 1, wherein The size of each of the plurality of open regions is larger than the size of each of the plurality of pores.

3. The display device according to claim 1, wherein The plurality of opening regions overlap vertically with the plurality of pixel electrodes respectively.

4. The display device according to claim 1, wherein Each of the plurality of apertures does not vertically overlap with at least a portion of the plurality of pixel electrodes.

5. The display device according to claim 1, wherein All the pores in the plurality of pores have the same shape.

6. The display device according to claim 1, wherein At least one of the plurality of pores has a shape different from the other pores.

7. The display device according to claim 1, further comprising: A first insulating layer is disposed between the substrate and the plurality of pixel electrodes; A second insulating layer is disposed on the first insulating layer and has an opening that overlaps with a portion of the first pixel electrode among the plurality of pixel electrodes; A dam, which is disposed on the first pixel electrode, overlaps with the opening, and has a hole with a smaller size than the opening; as well as A light-emitting layer is disposed on the first pixel electrode. The common electrode is disposed on the light-emitting layer and extends along the side surface of the dam. The first pixel electrode includes: A flat surface, which overlaps with the opening; and An inclined surface is disposed on the first insulating layer in the opening and extends along the side surface of the second insulating layer.

8. The display device of claim 7, wherein, The plurality of pores overlap with the embankment.

9. The display device according to claim 7, wherein The plurality of pores do not overlap with the light-emitting layer.

10. The display device according to claim 7, wherein The inclined surface is disposed within the opening area.

11. The display device according to claim 7, further comprising: A first light-emitting region, which overlaps with the flat surface; The second light-emitting region overlaps with the inclined surface; as well as A third luminescent region surrounds the second luminescent region and overlaps with at least a portion of the plurality of pores.

12. The display device of claim 11, wherein, The second luminescent area includes a first corner area and a first non-corner area. The brightness of the first corner area is lower than that of the first non-corner area. The third luminescent region includes a second corner region and a second non-corner region. The brightness of the second corner area is higher than that of the second non-corner area.

13. The display device of claim 12, wherein, The plurality of pores includes: The first pore located in the second corner region; and The second pore is located in the second non-corner region. The size of each of the first pores is larger than the size of each of the second pores.

14. A display device, comprising: A substrate, the substrate including a display area; A pixel electrode, comprising a sub-pixel disposed in the display area, the pixel electrode comprising a flat surface and an inclined surface surrounding the flat surface; A dam, the dam being disposed on the pixel electrode and having a hole overlapping at least a portion of the pixel electrode; as well as A touch metal element, disposed above the dike and having multiple pores, is used. The light-emitting region of the sub-pixel includes: A first light-emitting region, which overlaps with the flat surface; A second luminescent region, the second luminescent region surrounding the first luminescent region and overlapping at least a portion of the inclined surface; and A third luminescent region surrounds the second luminescent region and overlaps with at least a portion of the plurality of pores.

15. The display device according to claim 14, wherein, The second luminescent area includes a first corner area and a first non-corner area. The brightness of the first corner area is lower than that of the first non-corner area.

16. The display device according to claim 15, wherein, The third luminescent region includes a second corner region and a second non-corner region. The brightness of the second corner region is greater than that of the second non-corner region.

17. The display device according to claim 16, wherein, The plurality of pores includes: The first pore located in the second corner region; and The second pore is located in the second non-corner region. The size of each of the first pores is larger than the size of each of the second pores.

18. The display device according to claim 14, further comprising: A first insulating layer is disposed between the substrate and the pixel electrode; A second insulating layer is disposed on the first insulating layer and has an opening that overlaps with a portion of the pixel electrode; A light-emitting layer is disposed on the pixel electrode; as well as A common electrode, which is disposed on the light-emitting layer and extends along the side surface of the embankment. The pixel electrode is disposed on the first insulating layer in the opening, and the inclined surface extends along the side surface of the second insulating layer.

19. The display device according to claim 14, wherein, The plurality of pores overlap with the embankment.

20. The display device according to claim 18, wherein, The plurality of pores do not overlap with the light-emitting layer.

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