A phase correction method and circuit for an ASIC chip of a smart meter

Abstract

The application relates to a phase correction method and circuit of an intelligent electric meter ASIC chip, and belongs to the field of electric energy metering chips. The method corrects four kinds of relative phase relations among IA channels, U channels and IB channels, a large number of D flip-flop groups with small bit width are arranged at a high sampling rate end after ADC of the IA / IB channels to realize high-precision phase adjustment, and a small number of D flip-flop groups with large bit width are arranged at a low sampling rate end after a decimation filter to realize wide-range phase delay; the U channels are arranged with the same number of D flip-flops as the IA / IB channels at the same position after the decimation filter. The structure of the application is of a hierarchical configuration, and wide-range and high-precision configurable phase correction is realized with the least number of D flip-flops, chip area is effectively saved, and overall power consumption is reduced.

Description

Technical Field

[0001] This invention belongs to the field of energy metering chips and relates to a phase correction method and circuit for a smart meter ASIC chip. Background Technology

[0002] In the development of ASIC chips for smart meters, the front-end conditioning circuit introduces a phase difference (excluding the power angle) between the current and voltage channels, increasing the error in power calculation. Therefore, to correct this error, a configurable number of D flip-flops are introduced into the live wire voltage and current channels during chip design to correct this phase difference. Currently, such as... Figure 1 As shown, a common practice is to connect a low-sampling-rate D flip-flop in the digital circuit after the analog-to-digital converter (ADC) and before the digital decimation filter in the live wire current channel, and introduce a high-sampling-rate digital current D flip-flop in the digital circuit after the digital filter in the live wire voltage channel to deal with the following situations: (1) the phase of the live wire current channel lags behind the live wire voltage channel; (2) the phase of the live wire voltage channel lags behind the live wire current channel. However, the phase correction of the neutral wire current channel is not emphasized. The chip function often does not have phase correction of the neutral wire current channel, or there are logic defects that cannot cover all the situations of phase correction of the three channels. The correction is still mainly based on the live wire channel.

[0003] As the functions and application scenarios of power metering chips expand, there is also a significant market demand for power calculation via the neutral wire current channel. In some applications, it is necessary to ensure that the relative phases of the live wire current channel (IA channel), live wire voltage channel (U channel), and neutral wire current channel (IB channel) remain consistent. Therefore, using the commonly used circuit correction methods for the IA and U channels to simultaneously correct all three channels is no longer effective.

[0004] How to efficiently and cost-effectively correct the relative phase between the three paths has become a pressing technical problem in this field. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a phase correction method and circuit for a smart meter ASIC chip, which effectively solves the problem of the relative phase of the IA, U, and IB channels being ahead or behind in actual use, and ensures that the relative phases of the IA, U, and IB channels are the same.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A phase correction circuit for an ASIC chip in a smart meter includes a live wire current channel (IA channel), a voltage channel (U channel), and a neutral wire current channel (IB channel). Both the IA channel and the IB channel include an analog-to-digital converter (ADC), a first-stage delay unit, a digital decimation filter, and a second-stage delay unit connected in sequence. The U-channel includes an ADC, a digital decimation filter, and a third-stage delay unit connected in sequence. The first-stage delay unit uses system clock sampling to achieve high-precision phase compensation; the second-stage delay unit and the third-stage delay unit use sampling rates reduced by a decimation filter to achieve phase compensation over a wide range.

[0007] Preferably, the first-stage delay unit includes multiple D flip-flops connected in series with a configurable number of gates, whose sampling frequency is equal to the system main frequency and whose data bit width is smaller than the output bit width of the digital decimation filter; Both the second-stage delay unit and the third-stage delay unit include D flip-flops that match the number of decimation filter factors, and their data bit width is consistent with the output bit width of the digital decimation filter.

[0008] Preferably, in the second-stage delay unit or the third-stage delay unit, the phase delay generated by a single D flip-flop is equal to the phase delay generated by the number of D flip-flops configured in the first-stage delay unit that have the same gating factor as the frequency reduction factor.

[0009] Preferably, each delay unit in the IA channel, IB channel and U channel is equipped with a gating switching module; the gating switching module, according to the input control command, causes the data stream of the corresponding channel to flow through a set number of D flip-flops, or bypasses the D flip-flops to enter a pass-through state.

[0010] Furthermore, the phase correction method of this correction circuit specifically includes the following steps: Obtain the initial relative phase relationship between the IA channel, U channel, and IB channel; Based on the initial relative phase relationship, identify the reference channel with the most lagging phase among the three; For non-reference channels, the number of gated units for the first-level delay unit and / or the second-level and third-level delay units in the corresponding channel is configured according to the phase difference value that leads the reference channel. By increasing the delay of the lead channel, the output phases of the IA channel, U channel, and IB channel are made consistent.

[0011] Furthermore, the initial relative phase relationship includes the following four mathematical models: Model 1: The phase of the IA channel lags behind that of the U channel, and the U channel lags behind that of the IB channel. The "<" symbol is used to represent the phase lag, that is, IA < U < IB. During calibration, the third-stage delay unit of the U channel is selected, and the second-stage and first-stage delay units of the IB channel are selected, so that the phases of the U channel and the IB channel lag behind to be consistent with that of the IA channel respectively; Model 2: The phase of the IB channel lags behind that of the U channel, and the U channel lags behind that of the IA channel, that is, IB < U < IA. During calibration, the third-stage delay unit of the U channel is selected, and the second-stage and first-stage delay units of the IA channel are selected, so that the phases of the U channel and the IA channel lag behind to be consistent with that of the IB channel respectively; Model 3: The phases of the IA channel and the IB channel lag behind that of the U channel, that is, IA and IB < U. During calibration, the delay units in the IA channel and the IB channel are selected respectively, so that their phases lag behind to be consistent with that of the U channel; Model 4: The U channel lags behind the IA channel and the IB channel, that is, U < IA and IB. During calibration, the delay units in the IA channel and the IB channel are selected respectively, so that their phases lag behind to be consistent with that of the U channel.

[0012] Furthermore, under Model 1, if the U channel is still ahead of the IA channel after selecting the third-stage delay unit, the first-stage delay unit of the IA channel is further configured to fine-tune the phase until the phases of the IA channel, the U channel, and the IB channel are aligned.

[0013] Furthermore, the user configures the selection status of the delay units in each channel through machine code, and the chip automatically adjusts the number of D flip-flops connected in each channel according to the machine code, thereby completing automatic phase calibration. The beneficial effects of the present invention are as follows: Aiming at the prior art which only focuses on the phase calibration between the live wire current (IA) and the live wire voltage (U) channels and ignores or cannot effectively handle the phase problem of the neutral wire current (IB) channel. The present invention first proposes a complete set of methods and circuit structures, which can simultaneously and efficiently calibrate any relative phase relationship among the IA, U, and IB channels, covering four core phase theory models, and ensuring the consistency of the relative phases of the three channels in complex application scenarios.

[0014] The present invention innovatively utilizes the characteristics of the internal sampling rate change of the chip. A large number of D flip-flop groups with small bit widths are arranged at the high sampling rate end after the ADC to achieve high-precision phase adjustment, and a small number of D flip-flop groups with large bit widths are arranged at the low sampling rate end after the decimation filter to achieve a large range of phase delay. This "hierarchical configuration" structure realizes wide-range and high-precision configurable phase calibration with the smallest circuit overhead (the number of D flip-flops), effectively saving the chip area and reducing the overall power consumption.

[0015] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 A circuit diagram illustrating commonly used calibration methods for traditional IA and U channels; Figure 2 A schematic diagram of the mathematical model for the phase relationship between the IA channel, U channel, and IB channel; Figure 3 A circuit diagram illustrating the calibration methods for IA channel, U channel, and IB channel; Figure 4 This is a schematic diagram of the selection and bypass of the D flip-flop group circuit. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0019] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and cannot be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0020] Embodiment 1: This embodiment provides a phase correction method for an intelligent meter ASIC chip, as Figure 2 shown, there are 4 mathematical theoretical models for the relative phase relationship between the IA channel, the U channel, and the IB channel according to the differences in the circuit implementation structure: Model 1: The phase of the IA channel lags behind the U channel, and the U channel lags behind the IB channel, that is, IA < U < IB (hereinafter, the "<" symbol is used to represent phase lag); Model 2: The phase of the IB channel lags behind the U channel, and the U channel lags behind the IA channel, that is, IB < U < IA; Model 3: The phases of the IA and IB channels lag behind the U channel, and the relative phase relationship between IA and IB has the same implementation structure in this case, IA / IB < U; Model 4: The U channel lags behind IA and IB, and the relative phase relationship between IA and IB has the same implementation structure in this case, that is, U < IA / IB.

[0021] Phase correction is performed for the above four mathematical models of phase relationships, and the correction method is as follows: When correcting Model 1, delay links are respectively added to the IB channel and the U channel to make the phase lag of the IB channel and the U channel reach the same as that of the IA channel.

[0022] When correcting Model 2, delay links are respectively added to the IA channel and the U channel to make the phase lag of the IA channel and the U channel reach the same as that of the IB channel.

[0023] When correcting Model 3, delay links are respectively added to the IA channel and the IB channel to make the phase lag of the IA channel and the IB channel reach the same as that of the U channel.

[0024] When correcting Model 4, delay links are respectively added to the U channel and the channel with a leading phase among the IA channel and the IB channel to make the phase lag of the U channel and the channel with a leading phase among the IA channel and the IB channel reach the same as that of the channel with a lagging phase among the IA channel and the IB channel.

[0025] Embodiment 2: When implementing the circuit, there are multiple preselected schemes. Considering the power consumption and area of the digital circuit, the implementation structure of the circuit is as follows Figure 3 As shown, specifically: The IA / IB channels are after the ADC and are connected to the first stage of the digital circuit. A sufficient number of D flip-flop groups are placed. The sampling rate of the flip-flops here is the system clock, which has the highest frequency and can achieve high-precision phase shift of the circuit, determining the phase correction accuracy. With a large number and a small bit width, the number of D flip-flops matching the decimation filter multiple is placed after the decimation filter. For example, the number of D flip-flops here determines the correction range. With a small number, the bit width is large. If the system clock is 1M, the decimation filter multiple is 64 times, the data bit width after the ADC is 1, and the data bit width after the decimation filter is 32, then the phase correction accuracy is 1M. 64 1-bit registers are placed after the ADC, and the number of D flip-flops placed after the decimation filter is 1 32-bit one, that is, the delay of selecting 1 32-bit D flip-flop after the decimation filter is equal to the delay of selecting 64 D flip-flops after the ADC.

[0026] The U channel places the same number of D flip-flops at the same position as the IA / IB channels after the decimation filter.

[0027] Such as Figure 4 As shown, all the above D flip-flop circuits can be selected. When the phase relationship does not require the selection of D flip-flops, the D flip-flop circuit can be selected to bypass, and the corresponding circuit is in the direct-through state to meet the use of the ASIC chip in different relative phase difference application scenarios.

[0028] Taking the first phase relationship case as an example, that is, IA < U < IB, the IA phase is in the state of the most lag. Then, at this time, it is necessary to select the D flip-flop after the decimation filter of the U channel. At the same time, in order to maintain the relative phase between the U channel and the IB channel, the D flip-flop after the decimation filter of the IB channel is selected. At this time, the IA channel is in the most leading phase, and then the D flip-flop after the ADC of the IA channel is selected to make the IA phase lag to the same relative phase as U. At this time, the U channel and the IB channel still maintain the original phase relationship, so the D flip-flop after the ADC of the IB channel is selected to make the relative phase of the IB channel lag to the same relative phase as the U channel. At this time, the relative phases of the IA channel, the U channel, and the IB channel are all the same. This process occurs in theoretical derivation and circuit implementation. In actual use, after obtaining the phase difference, the user passes the phase difference in the form of machine code and configures the Figure 4 structure in each channel to automatically complete the phase correction.

[0029] This circuit structure is highly efficient. It simplifies the mathematical model solution revealed by the phase correction method to the greatest extent and utilizes the characteristics of chip sampling rate variation to place D flip-flops, thereby saving the number of D flip-flops and reducing chip power consumption.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

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