A three-mode redundant circuit netlist compiling method and device based on state machine conversion

Abstract

The application provides a three-mode redundant circuit netlist compiling method and device based on state machine conversion, belongs to the technical field of anti-radiation integrated circuit netlist compiling processing, and comprises the following steps: generating a netlist ASCII text stream and a keyword-regular set by inputting core source data suitable for an anti-radiation scene, triggering a lexical analyzer, forming an ordered lexical unit sequence through lexical analysis, constructing a state transition graph and checking the state transition graph, integrating the graph and a fragment, extracting a syntax tree, converting the syntax tree into a flow graph data structure, finally generating an IR intermediate representation mapped with SoC hardware, and outputting the IR intermediate representation. The three-mode redundant circuit netlist compiling method and device based on state machine conversion are used, so that the problems of low recognition efficiency, large cost and easy deletion of redundant logic in the process of processing a three-mode redundant circuit netlist by a traditional hardware compiler are solved.

Description

Technical Field

[0001] This invention relates to the field of radiation-resistant integrated circuit netlist compilation and processing technology, and in particular to a method and apparatus for compiling a triple-modular redundancy circuit netlist based on state machine transitions. Background Technology

[0002] In the field of integrated circuit design, especially in radiation-hardened environments with high reliability requirements, such as aerospace, aviation, and nuclear energy, ensuring the stable operation of chips under extreme radiation conditions has become a critical issue that urgently needs to be addressed. Single-event soft errors, as one of the main forms of chip failure in radiation environments, pose a serious threat to the reliability and stability of integrated circuits. To effectively address this challenge, triple mode redundancy design technology has emerged and is widely used in the design of radiation-hardened integrated circuits.

[0003] Triple modular redundancy (TMR) design replicates critical functional modules three times and uses a voter to decide the outputs of the three modules, with the majority vote result becoming the final output. This ensures that the entire system continues to operate correctly even if a single module fails. This design significantly improves the system's fault tolerance and reliability, and is highly effective in avoiding chip-level single-event soft errors. However, with the continuous increase in the scale and complexity of integrated circuits, the design and implementation of TMR circuits face many challenges.

[0004] Traditionally, the design of triple modulo redundancy (TMR) circuits relies heavily on manual coding using Hardware Description Languages ​​(HDLs) and compilation and optimization using general-purpose synthesis tools. However, this approach has significant limitations when dealing with TMR netlists. Specifically, general-purpose synthesis tools often treat TMR circuits as three independent branches, failing to understand the voting relationships between them at the semantic level. This leads to low compilation efficiency, and redundant logic is easily mistakenly deleted during optimization. Furthermore, for custom SoC chips with millions of gates, traditional methods exhibit significant limitations in terms of compilation efficiency, resource consumption, and design cycle time.

[0005] Although some design and simulation tools for triple-modular redundancy (TMR) circuits exist in the current technology, most of these tools reuse commercial simulators and lack specific optimizations for the characteristics of TMR circuits. This results in problems such as low efficiency and high overhead when dealing with large-scale and complex TMR circuits. At the same time, these tools often rely on mature EDA toolchains, which limits the development and application of domestically produced EDA tools.

[0006] Therefore, developing an efficient, reliable compilation method specifically for triple-modular redundancy circuit netlists is of great significance for improving the design efficiency and quality of radiation-hardened integrated circuits and promoting the development of domestic EDA tools. Summary of the Invention

[0007] The purpose of this invention is to provide a method and apparatus for compiling a triple-modular redundancy circuit netlist based on state machine transitions. This solves the problems of low identification efficiency, high overhead, and easy deletion of redundant logic when traditional hardware compilers process triple-modular redundancy circuit netlists. Furthermore, it addresses the issues of long compilation time for netlists of custom chips with millions of gates and reliance on mature EDA tools.

[0008] To achieve the above objectives, this invention provides a method for compiling a netlist for a triple modular redundancy circuit based on state machine transitions, comprising the following steps: S1. Input core source data, which includes a triple redundancy circuit netlist adapted to radiation-resistant scenarios and a triple redundancy recognition word library. Integrate and generate a netlist ASCII text stream and a keyword-regular expression set to trigger the lexical analyzer to start. S2. Based on the keyword-regularity set, perform lexical parsing on the netlist ASCII text stream, extract core elements and label them with type-attribute value-tri-modal redundancy recognition tags to form an ordered lexical unit sequence; S3. Construct a triple-modal redundancy dedicated state transition diagram based on the lexical unit sequence, perform logical verification on the state transition diagram and generate a verification result identifier; S4. Integrate the state transition diagram and syntax logic fragments after successful verification, extract the three-way synchronous syntax tree and convert it into a flow graph data structure with hardware association identifier; S5. Generate an intermediate IR representation that is mapped one-to-one with the three redundant hardware paths of the SoC based on the flow graph data structure, and output the intermediate IR representation to the subsequent compilation simulation device or EDA tool plugin.

[0009] Preferably, in S1, the preprocessing of the netlist text stream includes removing invalid comments and standardizing line breaks.

[0010] Preferably, the regular expressions for the three-modal redundancy recognition word database are uniformly set to [_a-zA-Z][_a-zA-Z0-9]. The corresponding keywords include module naming terms, no fewer than 3 consecutive branch keywords, and no fewer than 3 consecutive assignment statement keywords.

[0011] Preferably, in S2, during the lexical parsing process, the c_parser_peek_token function is called to look ahead and verify the lexical unit type, and the c_parser_consume_token function is called to consume and advance the parsing process.

[0012] Preferably, in S3, the three-modal redundancy dedicated state transition diagram includes three independent initial states, three independent intermediate state sequences, and a final voting state.

[0013] Preferably, in S3, the logic verification includes state transition rationality verification and three-way redundant structure consistency verification. The verification result is identified by a binary identifier, and an error line number and reason explanation are attached when it fails.

[0014] Preferably, in S4, the three-way synchronous syntax trees all contain a hierarchical structure of target-expression-operand, and the terminal syntax consists of expression n and its corresponding operand; the flow graph data structure adopts a hybrid storage method of adjacency matrix + linked list, and the hardware association identifier is marked by XML format tags.

[0015] Preferably, in S5, the IR intermediate representation is output in the LLVMIR standard format, including IR0, IR1, and IR2, which are respectively mapped one-to-one with the SoC's CPU0 / bus0 / memory0, CPU1 / bus1 / memory1, and CPU2 / bus2 / memory2; the IR intermediate representation is independently packaged in .ll format, transmitted via TCP protocol, and supports breakpoint resumption.

[0016] A triple-modular redundancy circuit netlist compilation device based on state machine transitions, comprising: The source data input module is used to receive the triple-mode redundancy circuit netlist and the triple-mode redundancy recognition word library, and outputs the netlist ASCII text stream and keyword-regular expression set. The lexical analysis module, connected to the source data input module, is used to output a labeled sequence of lexical units; The state transition and verification module is connected to the lexical analysis module and is used for state transition diagram construction and logic verification, outputting state transition diagram, AST syntax fragments and verification signals; The flow graph generation module, connected to the state transition and verification module, is used to generate flow graph data structures and output flow graph data blocks with hardware association identifiers. The IR generation and output module is connected to the flow graph generation module and is used for generating and outputting IR intermediate representations, outputting three standardized IR files.

[0017] Therefore, the present invention employs the above-described method and apparatus for compiling a triple-modular redundancy circuit netlist based on state machine transitions, and the technical effects are as follows: 1. Improved compilation efficiency: The netlist text is accurately matched by a pre-set triple redundancy recognition word library, and the jump logic of the circuit control signal is represented by a state transition diagram, which significantly improves compilation efficiency and reduces unnecessary compilation time.

[0018] 2. Optimize compilation overhead: Extract the three-way synchronized syntax tree information through the lexical analyzer and transform the parsed information into a flow graph data structure, which effectively avoids the accidental deletion of redundant logic and optimizes the compilation overhead.

[0019] 3. Enhanced logical consistency: By using state transition diagrams and syntax tree information, logical consistency among modules in the triple-redundant circuit is ensured, thereby improving the reliability and stability of the entire system.

[0020] 4. Promote the development of domestic EDA tools: This technical solution provides strong support for the combination of netlist-level dedicated compiler tools, which helps to create domestic EDA tool plugins and promotes the application and development of domestic EDA tools in the field of radiation-hardened integrated circuit design. Attached Figure Description

[0021] Figure 1 This is a flowchart of a three-modular redundancy circuit netlist compilation method based on state machine transitions according to the present invention; Figure 2 This is the state transition diagram of the triple modular redundancy circuit netlist based on state machine transitions in this invention; Figure 3 This is a schematic diagram of the syntax tree for the triple modular redundancy circuit based on state machine transitions in this invention; Figure 4 This is a schematic diagram of the three-modular redundancy circuit netlist compilation and simulation device based on state machine transitions according to the present invention; Figure 5 This is a schematic diagram illustrating the compilation and application of the custom circuit for a triple-modal redundancy SoC based on state machine transitions, as described in this invention. Detailed Implementation

[0022] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0024] Example 1 like Figure 1 As shown, this invention provides a method for compiling a netlist for a triple-modular redundancy SoC custom circuit based on state machine transitions, including the following steps: S1. Input core source data, which includes a triple-modulus redundancy circuit netlist adapted for radiation-resistant scenarios and a triple-modulus redundancy recognition word library. Integrate and generate the netlist ASCII text stream and keyword-regular expression set, triggering the lexical analyzer to start. The regular expressions for the triple-modulus redundancy recognition word library are uniformly set to [_a-zA-Z][_a-zA-Z0-9]. The corresponding keywords include module naming terms, no fewer than 3 consecutive branch keywords, and no fewer than 3 consecutive assignment statement keywords.

[0025] S2. Based on the keyword-regular expression set, perform lexical parsing on the netlist ASCII text stream, extract core elements, and label them with type-attribute value-tri-modulus redundancy recognition tags to form an ordered sequence of lexical units. During the lexical parsing process, the c_parser_peek_token function is called to look ahead and verify the type of lexical units, and the c_parser_consume_token function is called to consume and advance the parsing process.

[0026] S3. Construct a triple-modular redundancy dedicated state transition graph based on lexical unit sequences, such as... Figure 2 As shown, the state transition diagram includes three independent initial states (s...). 00 ,s 10 ,s 20 ), three independent intermediate state sequences (s 0n ,s 1n ,s 2n ) and final voting status (s n Perform logical checks on the state transition diagram, including checks on the rationality of state transitions and the consistency of the three-way redundant structure, and generate a check result identifier. The check result identifier is a binary identifier, and an error line number and reason explanation are attached if it fails.

[0027] S4. Integrate the state transition diagram and syntax logic fragments after successful integration and verification, extract the three-way synchronous syntax tree, and transform it into a flow graph data structure with hardware association identifiers. For example... Figure 3 As shown, all three synchronous syntax trees contain a hierarchical structure of target-expression-operand, and the terminal syntax consists of expression n and its corresponding operand. The flow graph data structure uses a hybrid storage method of adjacency matrix + linked list, and hardware association identifiers are marked using XML format tags.

[0028] S5. Generates an intermediate IR representation based on the flow graph data structure, which is mapped one-to-one with the SoC's three redundant hardware paths. For example... Figure 5 As shown, the IR intermediate representation is output according to the LLVM IR standard format, including IR0, IR1, and IR2, which are respectively mapped one-to-one with the SoC's CPU0 / bus0 / memory0, CPU1 / bus1 / memory1, and CPU2 / bus2 / memory2. The IR intermediate representation is packaged independently in .ll format, transmitted via TCP protocol, and supports breakpoint resumption. The IR intermediate representation is output to subsequent compilation simulation devices or EDA tool plugins.

[0029] like Figure 4 As shown, to implement the above method, the triple modulo redundancy circuit netlist compilation and simulation device includes a triple modulo redundancy circuit netlist compiler and a circuit simulator. The triple modulo redundancy circuit netlist compiler includes: The source data input module is used to receive the triple-mode redundancy circuit netlist and the triple-mode redundancy recognition word library, and outputs the netlist ASCII text stream and keyword-regular expression set. The lexical analysis module, connected to the source data input module, is used to output a labeled sequence of lexical units; The state transition and verification module is connected to the lexical analysis module and is used for state transition diagram construction and logic verification, outputting state transition diagram, AST syntax fragments and verification signals; The flow graph generation module, connected to the state transition and verification module, is used to generate flow graph data structures and output flow graph data blocks with hardware association identifiers. The IR generation and output module is connected to the flow graph generation module and is used for generating and outputting IR intermediate representations, outputting three standardized IR files.

[0030] Therefore, the present invention adopts the above-mentioned method and apparatus for compiling a triple-modular redundancy circuit netlist based on state machine transition. It accurately matches the netlist text through a preset triple-modular redundancy recognition word library, uses a state transition diagram to represent the circuit control signal jump logic, and combines lexical analysis to extract three-way synchronous syntax tree information and convert it into a flow graph data structure. Finally, it generates an IR intermediate representation mapped to SoC hardware. This effectively solves the problems of low efficiency, high overhead, and easy deletion of redundant logic when traditional compilers process triple-modular redundancy circuit netlists, and significantly improves the degree of automation and logic consistency of radiation-hardened integrated circuit netlist compilation.

[0031] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for compiling a netlist for a triple modular redundancy circuit based on state machine transitions, characterized in that, Includes the following steps: S1. Input core source data, which includes a triple redundancy circuit netlist adapted to radiation-resistant scenarios and a triple redundancy recognition word library. Integrate and generate a netlist ASCII text stream and a keyword-regular expression set to trigger the lexical analyzer to start. S2. Based on the keyword-regularity set, perform lexical parsing on the netlist ASCII text stream, extract core elements and label them with type-attribute value-tri-modal redundancy recognition tags to form an ordered lexical unit sequence; S3. Construct a triple-modal redundancy dedicated state transition diagram based on the lexical unit sequence, perform logical verification on the state transition diagram and generate a verification result identifier; S4. Integrate the state transition diagram and syntax logic fragments after successful verification, extract the three-way synchronous syntax tree and convert it into a flow graph data structure with hardware association identifier; S5. Generate an intermediate IR representation that maps one-to-one with the three redundant hardware paths of the SoC based on the flow graph data structure, and output the intermediate IR representation to the subsequent compilation simulation device or EDA tool plugin.

2. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S1, the preprocessing of the netlist text stream includes removing invalid comments and standardizing line breaks.

3. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, The regular expressions for the three-modal redundancy recognition word database are uniformly set to [_a-zA-Z][_a-zA-Z0-9]. The corresponding keywords include module naming terms, no fewer than 3 consecutive branch keywords, and no fewer than 3 consecutive assignment statement keywords.

4. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S2, during the lexical parsing process, the c_parser_peek_token function is called to look ahead and verify the type of the lexical unit, and the c_parser_consume_token function is called to consume and advance the parsing process.

5. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S3, the three-modal redundancy dedicated state transition diagram includes three independent initial states, three independent intermediate state sequences, and a final voting state.

6. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S3, the logic verification includes state transition rationality verification and three-way redundancy structure consistency verification. The verification result is identified by a binary identifier, and an error line number and reason explanation are attached when it fails.

7. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S4, the three-way synchronous syntax tree all contain a hierarchical structure of target-expression-operand, and the terminal syntax consists of expression n and corresponding operand; the flow graph data structure adopts a hybrid storage method of adjacency matrix + linked list, and the hardware association identifier is marked by XML format tags.

8. The method for compiling a triple-modular redundancy circuit netlist based on state machine transitions according to claim 1, characterized in that, In S5, the IR intermediate represents the output according to the LLVMIR standard format, including IR0, IR1, and IR2, which are respectively mapped one-to-one with the SoC's CPU0 / bus0 / memory0, CPU1 / bus1 / memory1, and CPU2 / bus2 / memory2. IR intermediate means that it is packaged independently in .ll format, transmitted via TCP protocol and supports resuming interrupted downloads.

9. A triple-modular redundancy circuit netlist compilation device based on state machine transitions, used to implement the method described in any one of claims 1-8, characterized in that, include: The source data input module is used to receive the triple-mode redundancy circuit netlist and the triple-mode redundancy recognition word library, and outputs the netlist ASCII text stream and keyword-regular expression set. The lexical analysis module, connected to the source data input module, is used to output a labeled sequence of lexical units; The state transition and verification module is connected to the lexical analysis module and is used for state transition diagram construction and logic verification, outputting state transition diagram, AST syntax fragments and verification signals; The flow graph generation module, connected to the state transition and verification module, is used to generate flow graph data structures and output flow graph data blocks with hardware association identifiers. The IR generation and output module is connected to the flow graph generation module and is used for generating and outputting IR intermediate representations, outputting three standardized IR files.

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