A balancer for electric double layer capacitors

Abstract

The present invention relates to a double layer capacitor balancer for balancing current flowing through a first double layer capacitor and a second double layer capacitor connected in series with each other in sequence between a power line and a common line, which can maximize charging energy efficiency by controlling the same current flowing through both double layer capacitors while allowing deviation within a range in which charging voltages of both double layer capacitors are not problematic. It includes a first resistor, a second resistor, and a third resistor connected in series with each other in sequence between the power line and the common line; a first transistor having a base terminal electrically connected between the first resistor and the second resistor and connected in parallel with the first double layer capacitor; and a second transistor connected in series with the first transistor and having a base terminal electrically connected between the second resistor and the third resistor and connected in parallel with the second double layer capacitor.

Description

Technical Field

[0001] Various embodiments of the present invention relate to a balancer for a double-layer capacitor. Background Technology

[0002] Electric double-layer capacitors (EDLCs) have the advantage of large capacitance due to their structural characteristics, but their disadvantage is a relatively low rated voltage. Therefore, when the voltage required in practical applications is significantly higher than the rated voltage of the EDLC, an EDLC module consisting of multiple EDLC units connected in series is used.

[0003] The multiple double-layer capacitor cells constituting a double-layer capacitor module can have different charging voltages due to variations in capacitance or leakage current. Furthermore, when the double-layer capacitor module is charged at its maximum voltage, some cells with smaller capacitance may be damaged by exceeding their rated voltage. Additionally, individual double-layer capacitor cells have different inherent leakage current parameters; cells with high leakage current and those connected in series with low leakage current will experience an increase in charging voltage over time, eventually exceeding their rated voltage and causing damage.

[0004] Therefore, in a double-layer capacitor module that connects multiple double-layer capacitor units in series, the method to solve the characteristic deviation (unbalance) problem of the double-layer capacitor units can be a passive balancer or an active balancer.

[0005] like Figure 1 As shown, a passive balancer is connected in parallel with double-layer capacitors (C1, C2) and shunt resistors (R1, R2) are added to allow shunt currents (IB1, IB2) that are much larger than the leakage current to flow through the shunt resistors, preventing charging voltage imbalance caused by leakage currents (IL1, IL2). However, the shunt current will lead to power loss, thus causing a decrease in charging efficiency.

[0006] like Figure 2 As shown, the active balancer uses an operational amplifier (OP-AMP) to control the charging voltage to always maintain 1 / 2 of the supply voltage. The active balancer has the advantage of keeping the charging voltage of the double-layer capacitors (C1, C2) constant. However, it is also sensitive to small charging voltage imbalances and has the problem of low charging efficiency due to repeated charging and discharging. Summary of the Invention

[0007] The technical problem to be solved The present invention provides a balancer for electric double-layer capacitors, which allows the charging voltages of the two electric double-layer capacitors to deviate within a problem-free range, while controlling the current flowing to the two electric double-layer capacitor circuits (IC1, IC2 flowing to Q1, Q2) to remain the same, thereby maximizing charging efficiency.

[0008] In addition, the present invention provides a balancer for a double-layer capacitor, wherein the operating point of the two transistors changes with the ambient temperature, thus automatically compensating for the change in the rated voltage of the double-layer capacitor due to the change in ambient temperature, thereby improving safety.

[0009] In addition, the present invention provides a balancer for a double-layer capacitor, which can balance and control the difference in capacitance and leakage current between two double-layer capacitors, while also improving energy efficiency.

[0010] Solution to technical problems According to an embodiment of the present invention, a double-layer capacitor balancer is used to balance and control the current flowing between a power line and a common line through a first double-layer capacitor and a second double-layer capacitor connected in series to maintain the same current. The balancer includes: a first resistor, a second resistor, and a third resistor located between the power line and the common line and connected in series; a first transistor with a base terminal electrically connected between the first resistor and the second resistor, and connected in parallel with the first double-layer capacitor; and a second transistor connected in series with the first transistor, having a base terminal electrically connected between the second resistor and the third resistor, and connected in parallel with the second double-layer capacitor.

[0011] The first terminal of the first resistor is electrically connected to the power line, the collector of the first transistor, and the first terminal of the first double-layer capacitor, and the second terminal is electrically connected to the first terminal of the second resistor and the base of the second transistor.

[0012] The first terminal of the second resistor is electrically connected to the second terminal of the first resistor and the base of the first transistor, and the second terminal is electrically connected to the first terminal of the third resistor and the base of the second transistor.

[0013] The first terminal of the third resistor is electrically connected to the second terminal of the second resistor and the base of the second transistor, and the second terminal is electrically connected to the common line, the collector of the second transistor and the second terminal of the second double-layer capacitor.

[0014] The first transistor is an NPN transistor, and the second transistor is a PNP transistor.

[0015] The base of the first transistor is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, the collector is electrically connected to the power line, the first terminal of the first resistor and the first terminal of the first double-layer capacitor, and the emitter is electrically connected to the emitter of the second transistor, the second terminal of the first double-layer capacitor and the first terminal of the second double-layer capacitor.

[0016] The base of the second transistor is electrically connected to the second terminal of the second resistor and the first terminal of the third resistor, the collector is electrically connected to the common line, the second terminal of the third resistor and the second terminal of the second double-layer capacitor, and the emitter is electrically connected to the emitter of the first transistor, the second terminal of the first double-layer capacitor and the first terminal of the second double-layer capacitor.

[0017] The values ​​of the first resistor, the second resistor, and the third resistor can be set according to the sum of the voltage supplied through the power line and the common line (i.e., the power supply voltage) and the rated voltage of the first double-layer capacitor and the second double-layer capacitor.

[0018] The smaller the second resistor is compared to the first and third resistors, the smaller the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current) are, thereby reducing energy loss. Conversely, the larger the second resistor is compared to the first and third resistors, the larger the first transistor current and the second transistor current are, thereby reducing the deviation in charging voltage between the first and second electric double-layer capacitors.

[0019] The second transistor can operate when the leakage current of the first double-layer capacitor (i.e., the first leakage current) is greater than the leakage current of the second double-layer capacitor (i.e., the second leakage current).

[0020] The first transistor can operate when the leakage current of the second double-layer capacitor (i.e., the second leakage current) is greater than the leakage current of the first double-layer capacitor (i.e., the first leakage current).

[0021] When the capacitance of the first double-layer capacitor is less than that of the second double-layer capacitor, the first double-layer capacitor will discharge using the difference between the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current), while the second double-layer capacitor will charge. This allows the voltage between the first and second double-layer capacitors, i.e., the second voltage, to reach half of the voltage supplied through the power line and the common line, i.e., the power supply voltage.

[0022] When the capacitance of the second double-layer capacitor is less than that of the first double-layer capacitor, the first double-layer capacitor will be charged by the difference between the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current), and the second double-layer capacitor will be discharged. This will allow the voltage between the first double-layer capacitor and the second double-layer capacitor, i.e., the second voltage, to reach half of the voltage supplied through the power line and the common line, i.e., the power supply voltage.

[0023] The beneficial effects of the present invention are as follows: According to an embodiment of the present invention, the balancer of the double-layer capacitor allows the charging voltage of the two double-layer capacitors to deviate within a problem-free range, while keeping the current flowing to the two double-layer capacitor circuits the same by control, thereby maximizing charging efficiency.

[0024] Furthermore, according to an embodiment of the present invention, the balancer of the double-layer capacitor changes the operating point of the two transistors according to the ambient temperature change, which can automatically compensate for the change in the rated voltage of the double-layer capacitor due to the ambient temperature change, thereby improving safety.

[0025] Furthermore, the balancer of the double-layer capacitor according to an embodiment of the present invention can balance and control the difference in capacitance and leakage current between the two double-layer capacitors, while also improving energy efficiency. Attached Figure Description

[0026] Figure 1 This is an example circuit diagram illustrating the passive balancer of a double-layer capacitor; Figure 2 This is an example circuit diagram illustrating the active balancer of a double-layer capacitor; Figure 3 This is a circuit diagram illustrating the balancer of the double-layer capacitor of the present invention.

[0027] 100: Balancer for double-layer capacitors VSS: Power cord; COMMON: Common cord R1: First resistor; R2: Second resistor R3: Third resistor; Q1: First transistor Q2: Second transistor C1: First double-layer capacitor C2: Second double-layer capacitor Detailed Implementation

[0028] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] The embodiments of the present invention are examples provided to more fully illustrate the invention to those skilled in the art. These embodiments can be modified in various ways, and the scope of the invention is not limited to them. Rather, these embodiments are provided to make the invention more comprehensive and complete, and to fully convey the technical concept of the invention to those skilled in the art.

[0030] Furthermore, for ease of explanation and clarity, the thickness or size of each layer in the following figures is exaggerated. The same symbols in the figures represent the same element. As stated in this specification, the term "and / or" includes any one or more combinations of the listed items. Additionally, the term "connection" in this specification refers not only to the direct connection between component A and component B, but also to the indirect connection between component A and component B through the intervention of component C.

[0031] The terminology used in this specification is intended to describe particular embodiments and is not intended to limit the invention. As described herein, the singular form may include the plural form unless the context clearly indicates otherwise. Furthermore, as used herein, "comprise" and / or "comprising" means explicitly including the presence of the stated shape, number, step, action, component, element, and / or combination thereof, and does not exclude the presence or addition of more than one other shape, number, action, component, element, and / or combination thereof.

[0032] In this specification, the terms "1", "2", etc., are intended to describe various components, parts, regions, layers, and / or portions; however, it is self-evident that these components, parts, regions, layers, and / or portions are not limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from other regions, layers, or portions. Therefore, the "1st component, part, region, layer, or portion" described below may refer to a "2nd component, part, region, layer, or portion" without departing from the spirit of the invention.

[0033] Terms such as “below,” “below,” “above,” and “upper” that relate to space are used to ensure easy understanding of the relationship between elements or features shown in the drawing and other elements or features, and are intended to help understand the invention, not to limit it. For example, when an element or feature in the drawing is flipped, an element originally described as “below” or “above” becomes “upper” or “upper.” Therefore, the expression “below” is a holistic spatial concept that includes both “upper” and “below.”

[0034] To ensure that those skilled in the art can easily implement this invention, preferred embodiments of the invention will now be described in detail with reference to the accompanying drawings.

[0035] It should be noted that the same reference numerals are used throughout the specification for components with similar structures and functions. Furthermore, when referring to an electrical connection between one part and another, this includes not only direct connections but also connections made by placing other components between them.

[0036] Figure 3 This is a circuit diagram illustrating the balancer of the double-layer capacitor of this invention. (For example...) Figure 3 As shown, the balancer (100) for the double-layer capacitor includes: a first transistor (Q1), a second transistor (Q2), a first resistor (R1), a second resistor (R2), and a third resistor (R3). Furthermore, the balancer (100) is electrically connected to the power supply line (VCC) and the common line (COMMON) to obtain the power supply voltage. This balancer (100) allows the charging voltages of the series-connected first double-layer capacitor (C1) and second double-layer capacitor (C2) to deviate within a problem-free range, while simultaneously maintaining the same current flowing into the circuits of the two double-layer capacitors (C1, C2) through control.

[0037] Here, the first resistor (R1), the second resistor (R2), and the third resistor (R3) are connected in series, and the power supply voltage can be distributed according to the resistance values.

[0038] The connection relationships of the various components in the balancer (100) of the double-layer capacitor will be explained below.

[0039] The power line (VCC) can be electrically connected to the first terminal (1) of the first resistor (R1), the collector (C) of the first transistor (Q1), and the first terminal (1) of the first double-layer capacitor (C1). Additionally, the common line (COMMON) can be electrically connected to the second terminal (2) of the third resistor (R3), the collector (C) of the second transistor (Q2), and the second terminal (2) of the second double-layer capacitor (C2).

[0040] The first resistor (R1) includes a first terminal (1) and a second terminal (2). The first terminal (1) of the first resistor (R1) can be electrically connected to the power supply line (VCC), the collector (C) of the first transistor (Q1), and the first terminal (1) of the first double-layer capacitor (C1). The second terminal (2) of the first resistor (R1) can be electrically connected to the first terminal (1) of the second resistor (R2) and the base (B) of the first transistor (Q1).

[0041] The second resistor (R2) includes a first terminal (1) and a second terminal (2). The first terminal (1) of the second resistor (R2) can be electrically connected to the second terminal (2) of the first resistor (R1) and the base (B) of the first transistor (Q1). The second terminal (2) of the second resistor (R2) can be electrically connected to the first terminal (1) of the third resistor (R3) and the base (B) of the second transistor (Q2).

[0042] The third resistor (R3) includes a first terminal (1) and a second terminal (2). The first terminal (1) of the third resistor (R3) can be electrically connected to the second terminal (2) of the second resistor (R2) and the base (B) of the second transistor (Q2). The second terminal (2) of the third resistor (R3) can be electrically connected to the common line (COMMON), the collector (C) of the second transistor (Q2), and the second terminal (2) of the second double-layer capacitor (C2).

[0043] The first transistor (Q1) may be an NPN transistor comprising a base (B), a collector (C), and an emitter (E). The base (B) of the first transistor (Q1) may be electrically connected to the second terminal (2) of the first resistor (R1) and the first terminal (1) of the second resistor (R2). The collector (C) of the first transistor (Q1) may be electrically connected to the power line (VCC), the first terminal (1) of the first resistor (R1), and the first terminal (1) of the first double-layer capacitor (C1). The emitter (E) of the first transistor (Q1) may be electrically connected to the emitter (E) of the second transistor (Q2), the second terminal (2) of the first double-layer capacitor (C1), and the first terminal (1) of the second double-layer capacitor (C2).

[0044] The second transistor (Q2) can be a PNP transistor comprising a base (B), a collector (C), and an emitter (E). The base (B) of the second transistor (Q2) can be electrically connected to the second terminal (2) of the second resistor (R2) and the first terminal (1) of the third resistor (R3). The collector (C) of the second transistor (Q2) can be electrically connected to the common line (COMMON), the second terminal (2) of the third resistor (R3), and the second terminal (2) of the second double-layer capacitor (C2). The emitter (E) of the second transistor (Q2) can be electrically connected to the emitter (E) of the first transistor (Q1), the second terminal (2) of the first double-layer capacitor (C1), and the first terminal (1) of the second double-layer capacitor (C2).

[0045] The first double-layer capacitor (C1) includes a first terminal (1) and a second terminal (2). The first terminal (1) of the first double-layer capacitor (C1) can be electrically connected to the power supply line (VCC), the first terminal (1) of the first resistor (R1), and the collector (C) of the first transistor (Q1). The second terminal (2) of the first double-layer capacitor (C1) can be electrically connected to the emitter (E) of the first transistor (Q1), the emitter (E) of the second transistor (Q2), and the first terminal (1) of the second double-layer capacitor (C2).

[0046] The second double-layer capacitor (C2) includes a first terminal (1) and a second terminal (2). The first terminal (1) of the second double-layer capacitor (C2) can be electrically connected to the emitter (E) of the first transistor (Q1), the emitter (E) of the second transistor (Q2), and the second terminal (2) of the first double-layer capacitor (C1). The second terminal (2) of the second double-layer capacitor (C2) can be electrically connected to the common line (COMMON), the second terminal (2) of the third resistor (R3), and the collector (C) of the second transistor (Q2).

[0047] The balancer (100) of this double-layer capacitor allows the charging voltages of the first double-layer capacitor (C1) and the second double-layer capacitor (C2) to deviate within a problem-free range, while maintaining the same current flowing to the circuits of the two double-layer capacitors (C1, C2) through control, thereby maximizing charging efficiency. Furthermore, the voltage (VBE) between the base (B) and emitter (E) of the semiconductor, i.e., the transistor (Q1, Q2), has a negative temperature coefficient, which can be used to address the decrease in rated voltage withstand capability caused by changes in ambient temperature. This transistor (Q1, Q2) can be a bipolar junction transistor (BJT). Additionally, the relationship between the voltage (VBE) between the base (B) and emitter (E) of the transistor (Q1, Q2) and the current (IC) at the collector (C) can be defined using the following mathematical formula 1.

[0048]

Mathematical Formula 1

[0049] Here, Is represents the saturated current of the base (B) and emitter (E) junction of transistors (Q1, Q2), and VBE represents the forward voltage between the base (B) and emitter (E). Additionally, k represents the Boltzmann constant, t represents the absolute temperature, and q represents the elementary charge. VT represents the thermal voltage, which can be expressed as kt / q. Furthermore, when the absolute temperature (t) is 300K (27°C), the thermal voltage (VT) is approximately 26mV.

[0050] The collector current (IC) of these transistors (Q1, Q2) increases tenfold for every 60mV increase in the forward voltage (VBE) between the base and emitter. Furthermore, the forward voltage (VBE) between the base and emitter decreases by approximately 2mV for every 1°C increase in temperature. The balancer (100) of this double-layer capacitor automatically compensates for the change in the rated voltage of the double-layer capacitors (C1, C2) caused by ambient temperature variations, as the operating point of the transistors (Q1, Q2) decreases by approximately 2mV / °C when the ambient temperature rises, thus improving safety.

[0051] Hereinafter, the voltage of the base (B) of the first transistor (Q1) is called the first voltage (V1), the voltage between the emitter (E) of the first transistor (Q1) and the emitter (E) of the second transistor (Q2) is called the second voltage (V2), and the voltage of the base (B) of the second transistor (Q2) is called the third voltage (V3).

[0052] Here, the operating point of the first transistor (Q1) or the second transistor (Q2) can be determined by the voltage (V2) at the connection point of the first double-layer capacitor (C1) and the second double-layer capacitor (C2). That is, the connection point of the first double-layer capacitor (C1) and the second double-layer capacitor (C2) is directly connected to the connection point of the emitter (E) of the first transistor (Q1) and the emitter (E) of the second transistor (Q2). Thus, the voltage (V2) at the connection point of the first double-layer capacitor (C1) and the second double-layer capacitor (C2) can be detected, and therefore the first transistor (Q1) or the second transistor (Q2) can operate.

[0053] The values ​​of the first resistor (R1) and the third resistor (R3) of the balancer (100) of the double-layer capacitor can be the same. In this case, the voltage difference between the power supply voltage and the first voltage (V1) between the power supply line (VCC) and the common line (COMMON) can be the same as the third voltage (V3). That is, when the first resistor (R1) and the third resistor (R3) are the same, the sum of the first voltage (V1) and the third voltage (V3) plus the voltage between the first terminal (1) and the second terminal (2) of the second resistor (R2), i.e., the second resistor voltage (VR2), may be equal to the magnitude of the power supply voltage. Here, the second resistor voltage (VR2) can be arbitrarily set.

[0054] The magnitudes of the first voltage (V1) and the third voltage (V3) can be set by adjusting the values ​​of the first resistor (R1), the second resistor (R2), and the third resistor (R3). Here, the values ​​of the first resistor (R1) and the third resistor (R3) may be the same. In addition, the second resistor (R2) can be set according to the ratio of the rated voltage of the double-layer capacitor (C1, C2) to the power supply voltage.

[0055] As an example, if the power supply voltage is low and there is sufficient margin between the rated voltages of the first double-layer capacitor (C1) and the second double-layer capacitor (C2), the operating points of the first transistor (Q1) and the second transistor (Q2) can be lowered by reducing the resistance of the second resistor (R2) relative to the first resistor (R1) and the third resistor (R3). This allows for a reduction in the collector current (C) of the first transistor (Q1), i.e., the first transistor current (IC1), and the collector current (C) of the second transistor (Q2), i.e., the second transistor current (IC2), under balanced conditions, thereby minimizing energy loss.

[0056] As another example, if the power supply voltage is high and there is no margin between the rated voltages of the first double-layer capacitor (C1) and the second double-layer capacitor (C2), the operating points of the first transistor (Q1) and the second transistor (Q2) can be increased by increasing the resistance of the second resistor (R2) relative to the first resistor (R1) and the third resistor (R3). This allows for a reduction in the allowable range of the charging voltage deviation between the first double-layer capacitor (C1) and the second double-layer capacitor (C2) under balanced conditions, rather than increasing the currents of the first transistor (IC1) and the second transistor (IC2).

[0057] Furthermore, if the first double-layer capacitor (C1) and the second double-layer capacitor (C2) have the same capacitance, the same leakage current, and the first transistor (Q1) and the second transistor (Q2) have the same characteristics, then the first transistor current (IC1) and the second transistor current (IC2) will be the same. Therefore, in this case, additional balancing control may not be necessary.

[0058] That is, if the first transistor (Q1) and the second transistor (Q2) have the same characteristics, and the leakage current of the first double-layer capacitor (C1), i.e., the first leakage current (IL1), is the same as the leakage current of the second double-layer capacitor (C2), i.e., the second leakage current (IL2), then the sum of the first transistor current (IC1) and the first leakage current (IL1) may be equal to the sum of the second transistor current (IC2) and the second leakage current (IL2). Furthermore, the second voltage (V2) being half of the power supply voltage can achieve a balanced state.

[0059] Furthermore, if the first resistor (R1) and the third resistor (R3) are the same, the first transistor (Q1) and the second transistor (Q2) have the same characteristics, the first leakage current (IL1) and the second leakage current (IL2) are the same, and the capacitances of the first double-layer capacitor (C1) and the second double-layer capacitor (C2) are equal, then the second voltage (V2) is half of the power supply voltage. This not only achieves balance, but also ensures that the first transistor current (IC1) and the second transistor current (IC2) are the same. Therefore, the current flowing from the first transistor (Q1) and the second transistor (Q2) to the first double-layer capacitor (C1) and the second double-layer capacitor (C2) can be reduced to 0.

[0060] Based on the above conditions, the balancer (100) of the double-layer capacitor can be designed such that the sum of the current of the first resistor (R1), i.e. the first resistor current (IR1) and the first transistor current (IC1) is less than the rated value of the first leakage current (IL1), and the sum of the current of the third resistor (R3), i.e. the third resistor current (IR2) and the second transistor current (IC2) is less than the rated value of the second leakage current (IL2), thereby minimizing energy loss.

[0061] The working mechanism of the balancer (100) of the double-layer capacitor will now be explained in the case where there is a difference in capacitance between the first double-layer capacitor (C1) and the second double-layer capacitor (C2).

[0062] If the capacitance of the first double-layer capacitor (C1) is greater than that of the second double-layer capacitor (C2), then the charging voltage of the first double-layer capacitor (C1) is higher than that of the second double-layer capacitor (C2). The second voltage (V2) will exceed half of the power supply voltage, thereby causing the first double-layer capacitor (C1) to charge further and the second double-layer capacitor (C2) to discharge further. Therefore, it is necessary to balance the charging voltage caused by the difference in capacitance between the two double-layer capacitors (C1, C2).

[0063] That is, if the capacitance of the first double-layer capacitor (C1) is greater than the capacitance of the second double-layer capacitor (C2), the second voltage (V2) will increase. Consequently, the difference between the second voltage (V2) and the third voltage (V3) is greater than the difference between the first voltage (V1) and the second voltage (V2). Therefore, the second transistor current (IC2) is greater than the first transistor current (IC1). At this time, the second double-layer capacitor (C2) will discharge further with the difference between the second transistor current (IC2) and the first transistor current (IC1), while the first double-layer capacitor (C1) will charge further, thus causing the second voltage (V2) to rise to half of the power supply voltage.

[0064] In this case, the relationship between the second transistor current (IC2) and the first transistor current (IC1) is shown in Equation 2.

[0065]

Mathematical Formula 2

[0066] Here, the thermal voltage (VT) is the same constant value as in Equation 1. According to Equation 2, the charging voltage deviation caused by the capacitance difference between the first double-layer capacitor (C1) and the second double-layer capacitor (C2) decreases, causing the second transistor current (IC2) to decrease as well. As a result, the second voltage (V2) becomes half of the power supply voltage, and the second transistor current (IC2) can become the same as the first transistor current (IC1).

[0067] As another example, since the capacitance of the first double-layer capacitor (C1) is smaller than that of the second double-layer capacitor (C2), when the second voltage (V2) is lower than half of the power supply voltage, the second double-layer capacitor (C2) will be charged and the first double-layer capacitor (C1) will be discharged, thus requiring the voltage deviation caused by the difference in capacitance between the two to be balanced.

[0068] That is, because the capacitance of the first double-layer capacitor (C1) is less than that of the second double-layer capacitor (C2), the second voltage (V2) drops, causing the difference between the first voltage (V1) and the second voltage (V2) to be greater than the difference between the second voltage (V2) and the third voltage (V3). Therefore, the second transistor current (IC2) is less than the first transistor current (IC1). The first double-layer capacitor (C1) will discharge further according to the current difference between the first transistor current (IC1) and the second transistor current (IC2), while the second double-layer capacitor (C2) will charge further, thereby raising the second voltage (V2) to half of the power supply voltage.

[0069] In this case, the relationship between the first transistor current (IC1) and the second transistor current (IC2) is shown in Equation 3.

[0070]

Mathematical Expression 3

[0071] Here, the thermal voltage (VT) is the same constant value as in Equation 1. According to Equation 3, the charging voltage deviation caused by the capacitance difference between the first double-layer capacitor (C1) and the second double-layer capacitor (C2) decreases, causing the first transistor current (IC1) to decrease as well. As a result, the second voltage (V2) becomes half of the power supply voltage, and the first transistor current (IC1) and the second transistor current (IC2) can become the same.

[0072] This charging voltage imbalance problem caused by the capacitance difference between the first double-layer capacitor (C1) and the second double-layer capacitor (C2) has the following characteristics: after the initial balancing is completed by the double-layer capacitor balancer (100), it will no longer be a problem in the subsequent repeated charging and discharging process.

[0073] The following will explain the situation where, although the capacitance of the balancer (100) of the double-layer capacitor is the same as that of the first double-layer capacitor (C1) and the second double-layer capacitor (C2), there is a deviation in the leakage current. If the first leakage current (IL1) and the second leakage current (IL2) in the balancer (100) of the double-layer capacitor are equal, and the characteristics of the first transistor (Q1) and the second transistor (Q2) are consistent, then the first transistor current (IC1) and the second transistor current (IC2) will remain equal, and this current value can be defined as the reference current (ICx).

[0074] If the second leakage current (IL2) is greater than the first leakage current (IL1), the second voltage (V2) will drop below half of the supply voltage. Here, the second voltage (V2) may continue to decrease proportionally over time. If the difference between the second leakage current (IL2) and the first leakage current (IL1) causes the second voltage (V2) to decrease, then the difference between it and the first voltage (V1) and the second voltage (V2) will increase, while the difference between it and the second voltage (V2) and the third voltage (V3) will decrease. Therefore, the first transistor current (IC1) will increase, while the second transistor current (IC2) will decrease, thus enabling balance control so that the sum of the first leakage current (IL1) and the first transistor current (IC1) flowing to the first double-layer capacitor (C1) is equal to the sum of the second leakage current (IL2) and the second transistor current (IC2) flowing to the second double-layer capacitor (C2).

[0075] Here, the relationship between the first transistor current (IC1) and the second transistor current (IC2) can be defined by mathematical formula 4.

[0076]

Mathematical Expression 4

[0077] Of course, here, the thermal voltage (VT) is the same constant value as in Equation 1. In this case, the imbalance value of the second voltage (V2) required for leakage current compensation can be expressed by Equation 5, which allows for a corresponding degree of voltage imbalance so that the sum of the first transistor current (IC1) and the first leakage current (IL1) can be balanced with the sum of the second transistor current (IC2) and the second leakage current (IL2).

[0078]

Mathematical Expression 5

[0079] Of course, here, thermal voltage (VT) is the same constant value as in equation 1.

[0080] For example, if the first transistor current (IC1) is 100 times the reference current (ICx), then the second voltage (V2) is (VS / 2) - 120mV, and the second transistor current (IC2) is the reference current (ICx) divided by 100. That is, if the second leakage current (IL2) is greater than the first leakage current (IL1), the first transistor current (IC1) can be added through the first transistor (Q1) to make its sum with the first leakage current (IL1) the same as the sum of the leakage current of the second double-layer capacitor (C2), i.e., the second leakage current (IL2) and the second transistor current (IC2).

[0081] If the first leakage current (IL1) is greater than the second leakage current (IL2), the second voltage (V2) will be higher than half of the power supply voltage, and the second voltage (V2) will continue to increase proportionally over time. If the difference between the first leakage current (IL1) and the second leakage current (IL2) causes the second voltage (V2) to increase, then the difference between it and the first voltage (V1) and the second voltage (V2) becomes smaller, and the difference between it and the second voltage (V2) and the third voltage (V3) becomes larger. Therefore, the second transistor current (IC2) increases, and the first transistor current (IC1) decreases, so that the sum of the first leakage current (IL1) flowing to the first double-layer capacitor (C1) and the first transistor current (IC1) can be kept the same by balance control as the sum of the second leakage current (IL2) flowing to the second double-layer capacitor (C2) and the second transistor current (IC12).

[0082] Here, the first transistor current (IC1) and the second transistor current (IC2) can be defined using mathematical formula 6.

[0083]

Mathematical Expression 6

[0084] The mathematical expression error caused V2 > (VS / 2), resulting in a negative result for (VS / 2 - V2). There was also an error in the parentheses V2.

[0085] Therefore, the correct expression should be IC2 = ICx * exp((V2 - (VS / 2)) / VT).

[0086] Of course, IC1 = ICx / exp((V2 - (VS / 2)) / VT) holds true.

[0087] Of course, here, the thermal voltage (VT) is the same constant value as in Equation 1. In this case, the unbalanced value of the second voltage (V2) required for leakage current compensation can be expressed by Equation 7, which allows for a corresponding degree of voltage imbalance so that the sum of the first transistor current (IC1) and the first leakage current (IL1) is balanced with the sum of the second transistor current (IC2) and the second leakage current (IL2).

[0088]

Mathematical Expression 7

[0089] Of course, here, thermal voltage (VT) is the same constant value as in equation 1.

[0090] For example, if the second transistor current (IC2) is 100 times the reference current (ICx), then the second voltage (V2) is approximately (VS / 2) + 120mV, and the first transistor current (IC1) is the reference current (ICx) divided by 100. That is, if the first leakage current (IL1) is greater than the second leakage current (IL2), the second transistor current (IC2) can be added through the second transistor (Q2) to make its sum with the second leakage current (IL2) the same as the sum of the leakage current of the first double-layer capacitor (C1), i.e., the first leakage current (IL1) and the first transistor current (IC1).

[0091] The above description is merely one embodiment of the balancer for the double-layer capacitor of the present invention. The present invention is not limited to the described embodiment. As required by the following patent claim scope, various modifications and implementations can be made by those skilled in the art without departing from the spirit of the present invention. This scope should be regarded as the technical spirit of the present invention.

Claims

1. A balancer for a double-layer capacitor, characterized in that: For a balancer of double-layer capacitors that balances the current flowing between the power line and the common line through a first double-layer capacitor and a second double-layer capacitor connected in series, in order to keep the currents flowing the same, the balancer is used to balance the currents flowing between the power line and the common line. It includes: a first resistor, a second resistor, and a third resistor, which are located between the power line and the common line and are connected in series. The first transistor has a base terminal electrically connected between the first resistor and the second resistor, and is connected in parallel with the first double-layer capacitor. The second transistor is connected in series with the first transistor, has a base terminal electrically connected between the second resistor and the third resistor, and is connected in parallel with the second double-layer capacitor.

2. The balancer for a double-layer capacitor according to claim 1, characterized in that: The first terminal of the first resistor is electrically connected to the power line, the collector of the first transistor, and the first terminal of the first double-layer capacitor, and the second terminal is electrically connected to the first terminal of the second resistor and the base of the second transistor.

3. The balancer for a double-layer capacitor according to claim 1, characterized in that: The first terminal of the second resistor is electrically connected to the second terminal of the first resistor and the base of the first transistor, and the second terminal is electrically connected to the first terminal of the third resistor and the base of the second transistor.

4. The balancer for a double-layer capacitor according to claim 1, characterized in that: The first terminal of the third resistor is electrically connected to the second terminal of the second resistor and the base of the second transistor, and the second terminal is electrically connected to the common line, the collector of the second transistor and the second terminal of the second double-layer capacitor.

5. The balancer for a double-layer capacitor according to claim 1, characterized in that: The first transistor is an NPN transistor, and the second transistor is a PNP transistor.

6. The balancer for a double-layer capacitor according to claim 5, characterized in that: The base of the first transistor is electrically connected to the second terminal of the first resistor and the first terminal of the second resistor, the collector is electrically connected to the power line, the first terminal of the first resistor and the first terminal of the first double-layer capacitor, and the emitter is electrically connected to the emitter of the second transistor, the second terminal of the first double-layer capacitor and the first terminal of the second double-layer capacitor.

7. The balancer for a double-layer capacitor according to claim 5, characterized in that: The base of the second transistor is electrically connected to the second terminal of the second resistor and the first terminal of the third resistor, the collector is electrically connected to the common line, the second terminal of the third resistor and the second terminal of the second double-layer capacitor, and the emitter is electrically connected to the emitter of the first transistor, the second terminal of the first double-layer capacitor and the first terminal of the second double-layer capacitor.

8. The balancer for a double-layer capacitor according to claim 1, characterized in that: The values ​​of the first resistor, the second resistor, and the third resistor can be set according to the sum of the voltage supplied through the power line and the common line (i.e., the power supply voltage) and the rated voltage of the first double-layer capacitor and the second double-layer capacitor.

9. The balancer for a double-layer capacitor according to claim 8, characterized in that: The smaller the second resistor is compared to the first resistor and the third resistor, the smaller the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current) are, thereby reducing energy loss. The larger the second resistor is compared to the first resistor and the third resistor, the greater the current of the first transistor and the current of the second transistor, thereby reducing the deviation of the charging voltage of the first double-layer capacitor and the second double-layer capacitor.

10. The balancer for a double-layer capacitor according to claim 1, characterized in that: The second transistor operates when the leakage current of the first double-layer capacitor (i.e., the first leakage current) is greater than the leakage current of the second double-layer capacitor (i.e., the second leakage current).

11. The balancer for a double-layer capacitor according to claim 1, characterized in that: The first transistor operates when the leakage current of the second double-layer capacitor (i.e., the second leakage current) is greater than the leakage current of the first double-layer capacitor (i.e., the first leakage current).

12. The balancer for a double-layer capacitor according to claim 6, characterized in that: When the capacitance of the first double-layer capacitor is less than that of the second double-layer capacitor, the first double-layer capacitor will discharge using the difference between the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current), while the second double-layer capacitor will charge. This allows the voltage between the first and second double-layer capacitors, i.e., the second voltage, to reach half of the voltage supplied through the power line and the common line, i.e., the power supply voltage.

13. The balancer for a double-layer capacitor according to claim 6, characterized in that: When the capacitance of the second double-layer capacitor is less than that of the first double-layer capacitor, the first double-layer capacitor will be charged by the difference between the collector current of the first transistor (i.e., the first transistor current) and the collector current of the second transistor (i.e., the second transistor current), and the second double-layer capacitor will be discharged. This will allow the voltage between the first and second double-layer capacitors, i.e., the second voltage, to reach half of the voltage supplied through the power line and the common line, i.e., the power supply voltage.

Images