A low phase noise phase-locked loop spurious rejection system and method

Abstract

The application relates to the field of frequency synthesis technology and discloses a low-phase-noise phase-locked loop spurious suppression system and method, which comprises a control module, an oscillator module connected with the output end of the control module, wherein the oscillator module comprises a plurality of oscillator units, a mixing and filtering module connected with the output end of the oscillator module, which is used for mixing and filtering a plurality of reference frequency signals output by the oscillator module and outputting a target reference signal, a signal selection switch used for receiving a control instruction sent by a central processing unit, a fractional-N phase-locked loop used for receiving a system reference clock signal and outputting a radio frequency output signal, and the central processing unit used for receiving a target output frequency signal and determining the system reference clock signal based on the target output frequency signal and the target reference signal. While the spurious is suppressed, the super-low phase noise characteristic of the reference source is maintained, the output frequency is continuously and accurately kept before and after switching, and the low phase noise and low spurious are simultaneously realized.

Description

Technical Field

[0001] This invention relates to the field of frequency synthesis technology, specifically to a low-phase-noise phase-locked loop spurious suppression system and method. Background Technology

[0002] Fractional-N PLLs are widely used in modern frequency synthesizers due to their ability to achieve fine frequency steps. However, an inherent drawback of fractional-N architecture is the generation of integer-boundary spurs (IBS). When the output frequency approaches an integer multiple of the phase detection frequency, the spurs fall within the loop bandwidth, severely affecting signal purity and leading to a degraded system performance.

[0003] Related technologies typically employ wideband clock generator chips to generate different reference frequencies by changing the division ratio, or use direct digital frequency synthesizers to generate variable references. However, wideband clock chips contain a large number of digital circuits, and their output signals have high phase noise levels, which degrades the phase noise performance of the entire frequency synthesis link. Therefore, effectively suppressing integer boundary spurious signals is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the present invention provides a low phase noise phase-locked loop spurious suppression system and method to solve the problem of integer boundary spurious emissions.

[0005] In a first aspect, the present invention provides a low-phase-noise phase-locked loop stray suppression system, the system comprising: The control module is used to output multiple control signals based on an external reference signal; An oscillator module is connected to the output terminal of the control module. The oscillator module includes multiple oscillator units, and each oscillator unit corresponds one-to-one with a control signal output by the control module. A mixing and filtering module is connected to the output terminal of the oscillator module and is used to mix and filter multiple reference frequency signals output by the oscillator module to output a target reference signal, wherein the target reference signal is the sum of the multiple reference frequency signals; A signal selection switch, the input terminals of which are respectively connected to the oscillator module and the mixer filter module, is used to receive control commands issued by the central processing unit, the control commands including the system reference clock signal; The fractional-order frequency-locked loop is connected to the output terminal of the signal selection switch and is used to receive the system reference clock signal and output the radio frequency output signal. The central processing unit is connected to the signal selection switch and the fractional frequency-locked loop, respectively, and is used to receive the target output frequency signal and determine the system reference clock signal based on the target output frequency signal and the target reference signal.

[0006] In one optional implementation, the oscillator module includes at least a first oscillator unit and a second oscillator unit, and the control signal includes at least a first control signal and a second control signal. The first oscillator unit outputs a first reference frequency signal based on the first control signal, and the second oscillator unit outputs a second reference frequency signal based on the second control signal.

[0007] In one optional implementation, the oscillator module further includes: A first power divider, connected to the output of the first oscillator unit, is used to divide the first reference frequency signal into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal; wherein, the first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input of the control module; The second power divider is connected to the output of the second oscillator unit and is used to divide the second reference frequency signal into a fourth reference sub-signal and a fifth reference sub-signal; wherein the fourth reference sub-signal is output to the mixing and filtering module, the fifth reference sub-signal is output to the feedback input of the control module, and the target reference signal is the sum of the first reference sub-signal and the fourth reference sub-signal.

[0008] In one optional implementation, the mixing and filtering module includes at least a mixer and a filter. The input terminal of the mixer is connected to each oscillator unit in the oscillator module, and the reference frequency signal output by each oscillator unit is mixed to output a mixed signal. A filter, the input of which is connected to the output of the mixer, is used to filter the mixed signal and output a target reference signal.

[0009] In one optional implementation, receiving the target output frequency signal and determining the system reference clock signal based on the target output frequency signal and the target reference signal includes: Obtain the reference signal currently selected by the signal selection switch as the current reference signal; If the current reference signal is the first reference sub-signal, the target output frequency signal is received, and the difference between the target output frequency signal and an integer multiple of the first reference sub-signal is calculated as the offset of the integer boundary spurious relative to the target output frequency signal. Determine whether the offset is less than a preset threshold; If the offset is less than a preset threshold, a switching command is generated and sent to the signal selection switch, instructing the signal selection switch to select the target reference signal as the system reference clock signal, and to recalculate the division parameters of the fractional frequency division phase-locked loop and configure them to the fractional frequency division phase-locked loop. If the offset is greater than or equal to a preset threshold, the current gating state is maintained.

[0010] In one optional implementation, receiving the system reference clock signal and outputting the radio frequency output signal includes: Receive the system reference clock signal output by the signal selection switch; The frequency division parameters configured by the central processing unit are received, the frequency division parameters including integer frequency division ratio and fractional frequency division ratio; Based on the system reference clock signal and the frequency division parameters, an RF output signal corresponding to the target output frequency signal is generated and output.

[0011] In one alternative implementation, the control module is used to generate and output multiple control signals based on an external reference signal and a reference frequency signal fed back by the oscillator module.

[0012] Secondly, the method, applied to any of the systems described above, includes: The control module outputs multiple control signals based on an external reference signal; Each oscillator unit in the oscillator module generates multiple reference frequency signals according to the corresponding control signal; The mixing and filtering module mixes and filters the plurality of reference frequency signals and outputs a target reference signal, which is the sum of the plurality of reference frequency signals. The central processing unit receives the target output frequency signal, and based on the target output frequency signal and the target reference signal, determines the system reference clock signal and generates control commands. The signal selection switch determines the system reference clock signal from the reference frequency signal output by the oscillator module and the target reference signal output by the mixer filter module according to the control command issued by the central processing unit. The fractional-order frequency-locked loop receives the system reference clock signal and outputs an RF output signal.

[0013] In one optional implementation, determining the system reference clock signal based on the target output frequency signal and the target reference signal includes: Obtain the reference signal currently selected by the signal selection switch as the current reference signal; If the current reference signal is the first reference sub-signal, the target output frequency signal is received, and the difference between the target output frequency signal and an integer multiple of the first reference sub-signal is calculated as the offset of the integer boundary spurious relative to the target output frequency signal. Determine whether the offset is less than a preset threshold; If the offset is less than a preset threshold, a switching command is generated and sent to the signal selection switch, instructing the signal selection switch to select the target reference signal as the system reference clock signal, and to recalculate the division parameters of the fractional frequency division phase-locked loop and configure them to the fractional frequency division phase-locked loop. If the offset is greater than or equal to a preset threshold, the current gating state is maintained.

[0014] In one optional implementation, the oscillator module includes at least a first oscillator unit and a second oscillator unit, the control signal includes at least a first control signal and a second control signal, and the method further includes: The first reference frequency signal output by the first oscillator unit is divided into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal by the first power divider. The first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input terminal of the control module. The second reference frequency signal output by the second oscillator unit is divided into a fourth reference sub-signal and a fifth reference sub-signal by the second power divider. The fourth reference sub-signal is output to the mixing and filtering module, and the fifth reference sub-signal is output to the feedback input terminal of the control module. The control module generates and outputs a first control signal and a second control signal based on the external reference signal, the third reference sub-signal, and the fifth reference sub-signal.

[0015] The low-phase-noise phase-locked loop spurious suppression system provided in this invention locks multiple oscillator units to the same external reference signal through a control module, ensuring phase coherence between the reference frequency signals. The central processing unit determines the system reference clock signal based on the target output frequency signal and the target reference signal. By avoiding integer boundary spurious signals, no external noise source is introduced, thus maintaining the ultra-low phase noise characteristics of the reference source while suppressing spurious signals. Furthermore, the output frequency remains continuous and accurate before and after switching, achieving a balance between low phase noise and low spurious signals. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a low phase-noise phase-locked loop stray suppression system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of another low phase-noise phase-locked loop spurious suppression system according to an embodiment of the present invention; Figure 3 This is a schematic flowchart of a low-phase-noise phase-locked loop stray suppression method according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This embodiment provides a low phase-noise phase-locked loop spurious suppression system. Figure 1 This is a schematic diagram of a low-phase-noise phase-locked loop (PLL) spurious suppression system according to an embodiment of the present invention. The system includes: a control module, an oscillator module, a mixing and filtering module, a signal selection switch, a fractional-order frequency-locked loop (FLL), and a central processing unit (CPU). The control module outputs multiple control signals based on an external reference signal. The oscillator module is connected to the output of the control module and includes multiple oscillator units, each corresponding one-to-one with the control signals output by the control module. The mixing and filtering module is connected to the output of the oscillator module and mixes and filters the multiple reference frequency signals output by the oscillator module to output a target reference signal, which is the sum of the multiple reference frequency signals. The input of the signal selection switch is connected to both the oscillator module and the mixing and filtering module, and receives control commands from the CPU, including a system reference clock signal. The FLL is connected to the output of the signal selection switch and receives the system reference clock signal, outputting a radio frequency (RF) output signal. The CPU is connected to both the signal selection switch and the FLL, receiving the target output frequency signal and determining the system reference clock signal based on the target output frequency signal and the target reference signal.

[0020] The control module outputs multiple control signals based on an external reference signal, which can be a standard frequency signal generated by a high-stability crystal oscillator or an atomic clock, serving as the system's frequency reference. The control module may contain multiple phase-locked loops to lock subsequent oscillator units to this external reference, ensuring high frequency stability and low phase noise at the output of each oscillator unit.

[0021] The oscillator module comprises multiple oscillator units, each corresponding one-to-one with a control signal output from the control module. Each oscillator unit generates a reference frequency signal with a specific frequency based on its corresponding control signal. The oscillator units can employ oven-controlled crystal oscillators (OCXOs) or other ultra-low phase noise oscillators.

[0022] The mixing and filtering module is connected to the output of the oscillator module. It mixes and filters multiple reference frequency signals output by the oscillator module to output a target reference signal. The target reference signal is the sum of the frequencies of the multiple reference frequency signals. For example, if the oscillator module contains two oscillator units that output reference frequency signals with frequencies f1 and f2 respectively, the mixing and filtering module generates a mixed signal including f1+f2, |f1-f2|, and various harmonics through a mixer, and then extracts the sum frequency component f1+f2 as the target reference signal through a bandpass filter.

[0023] The signal selection switch receives control commands from the central processing unit and selects one of the signals as the system reference clock signal output value using a fractional-division phase-locked loop. The signal selection switch can be a high-speed radio frequency switch.

[0024] The fractional-order frequency-locked loop (FLL) contains a fractional-order frequency divider, a phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). It can generate the required radio frequency output signal based on the input system reference clock signal and the set division ratio.

[0025] The central processing unit first acquires the target output frequency signal set by the user or the system. Based on the target output frequency signal and the target reference signal generated by the mixing and filtering module, it dynamically decides which reference signal should be used as the clock source of the fractional frequency division phase-locked loop. For example, it selects from any reference frequency signal output from the oscillator module or the target reference signal.

[0026] Optionally, the central processing unit can calculate the degree of deviation between the target output frequency signal and an integer multiple of the currently selected reference frequency, and determine whether spurious signals at integer boundaries may fall within the bandwidth of the phase-locked loop. If there is a risk of spurious signals, the control signal selection switch is switched to the target reference signal; otherwise, the original reference is maintained.

[0027] Optionally, the central processing unit may pre-store a frequency-reference mapping table and directly look up the table to determine the reference signal to be selected based on the target output frequency signal, thereby reducing real-time computation overhead.

[0028] The central processing unit (CPU) can select the more favorable frequency signal for suppressing integer boundary spurious signals from the reference frequency signal directly output from the oscillator module and the target reference signal output from the mixer-filter module, based on the target output frequency signal. It then configures the division parameters of the fractional-order frequency-locked loop (FLL) accordingly to ensure the accuracy and spectral purity of the RF output frequency. The CPU is connected to the signal selection switch via a control line to send control commands, and to the FLL via a configuration interface to write the division parameters.

[0029] The low-phase-noise phase-locked loop spurious suppression system provided in this invention locks multiple oscillator units to the same external reference signal through a control module, ensuring phase coherence between the reference frequency signals. The central processing unit determines the system reference clock signal based on the target output frequency signal and the target reference signal. By avoiding integer boundary spurious signals, no external noise source is introduced, thus maintaining the ultra-low phase noise characteristics of the reference source while suppressing spurious signals. Furthermore, the output frequency remains continuous and accurate before and after switching, achieving a balance between low phase noise and low spurious signals.

[0030] In some alternative implementations, such as Figure 2 As shown, the oscillator module includes at least a first oscillator unit and a second oscillator unit, and the control signal includes at least a first control signal and a second control signal. The first oscillator unit outputs a first reference frequency signal based on the first control signal, and the second oscillator unit outputs a second reference frequency signal based on the second control signal.

[0031] The oscillator module also includes a first power divider and a second power divider. The first power divider is connected to the output of the first oscillator unit and is used to divide the first reference frequency signal into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal. The first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input of the control module. The second power divider is connected to the output of the second oscillator unit and is used to divide the second reference frequency signal into a fourth reference sub-signal and a fifth reference sub-signal. The fourth reference sub-signal is output to the mixing and filtering module, and the fifth reference sub-signal is output to the feedback input of the control module. The target reference signal is the sum of the first and fourth reference sub-signals.

[0032] Optionally, the first reference frequency signal is 100MHz, and the second reference frequency signal is 10MHz. Based on the external reference signal and the feedback of the third and fifth reference sub-signals, the control module generates a first control signal and a second control signal respectively through an internal dual-channel phase-locked loop, ensuring that both the first and second reference frequency signals are phase-locked with the external reference signal. Since the two oscillator units are locked to the same external reference signal, their output reference frequency signals have a defined phase relationship, maintaining phase coherence. Consequently, the target reference signal generated by their mixing also remains coherent with the main reference signal, laying the foundation for phase continuity for subsequent seamless switching.

[0033] In some alternative implementations, such as Figure 2 As shown, the mixing and filtering module includes at least a mixer and a filter. The input of the mixer is connected to each oscillator unit in the oscillator module to mix the reference frequency signals output by each oscillator unit and output a mixed signal. The input of the filter is connected to the output of the mixer and is used to filter the mixed signal and output a target reference signal.

[0034] The mixer performs mixing processing on multiple received reference frequency signals, for example, on the first reference sub-signal. and the fourth reference sub-signal The mixing process is performed, the mixed signal is output, and then the mixed signal is filtered before the target reference signal is output. ,in, .

[0035] In some alternative implementations, the control module is used to generate and output multiple control signals based on an external reference signal and a reference frequency signal fed back from the oscillator module.

[0036] like Figure 2 As shown, the control module receives the third reference sub-signal returned by the first power divider and the fifth reference sub-signal returned by the second power divider, generates and outputs multiple control signals through internal circuits, and sends them to the corresponding oscillator units respectively, thereby achieving precise locking of the output frequency and phase of each oscillator unit.

[0037] Specifically, the control module may contain dual phase-locked loops, each corresponding to an oscillator unit. Taking the first oscillator unit as an example, the first phase-locked loop receives an external reference signal as a reference and simultaneously receives a feedback third reference sub-signal. A phase detector compares the phase difference between the two signals, generating an error voltage, which is then filtered by a loop to generate a first control signal. This first control signal acts on the first oscillator unit, adjusting its oscillation frequency until the first reference frequency signal and the external reference signal achieve phase lock. Similarly, the second phase-locked loop generates a second control signal based on the external reference signal and the feedback fifth reference sub-signal, ensuring that the second oscillator unit remains phase-locked with the external reference signal. The dual phase-locked structure of the control module ensures long-term frequency stability and phase coherence throughout the system's operation, thereby supporting the entire system to achieve low phase noise and low spurious emissions performance.

[0038] According to an embodiment of the present invention, a method for suppressing stray emissions in a low phase-locked loop is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0039] This embodiment provides a low-phase-noise phase-locked loop (PLL) spurious suppression method, which can be used in the aforementioned low-phase-noise PLL spurious suppression system. Figure 3 This is a flowchart of a low-phase-noise phase-locked loop spurious suppression method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps: In step S301, the control module outputs multiple control signals based on the external reference signal.

[0040] The control module outputs multiple control signals based on an external reference signal. This external reference signal can be a standard frequency signal generated by a high-stability crystal oscillator or an atomic clock, serving as the system's frequency reference. The control module may internally contain multiple phase-locked loops to lock subsequent oscillator units to this external reference, ensuring high frequency stability and low phase noise for each oscillator unit's output frequency.

[0041] In step S302, each oscillator unit in the oscillator module generates multiple reference frequency signals according to the corresponding control signals.

[0042] The oscillator module comprises multiple oscillator units, each corresponding one-to-one with a control signal output from the control module. Each oscillator unit generates a reference frequency signal with a specific frequency based on its corresponding control signal. The oscillator units can employ oven-controlled crystal oscillators (OCXOs) or other ultra-low phase noise oscillators.

[0043] In some optional implementations, the oscillator module includes at least a first oscillator unit and a second oscillator unit, and the control signal includes at least a first control signal and a second control signal. The method further includes: Step S3021: Based on the first power divider, the first reference frequency signal output by the first oscillator unit is divided into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal.

[0044] The first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input terminal of the control module. Step S3022: Based on the second power divider, the second reference frequency signal output by the second oscillator unit is divided into a fourth reference sub-signal and a fifth reference sub-signal.

[0045] The fourth reference sub-signal is output to the mixing and filtering module, and the fifth reference sub-signal is output to the feedback input of the control module. Based on the external reference signal and the third and fifth reference sub-signals, the control module generates and outputs the first and second control signals.

[0046] Based on the external reference signal and the feedback of the third and fifth reference sub-signals, the control module generates a first control signal and a second control signal through an internal dual-channel phase-locked loop, ensuring that both the first and second reference frequency signals are phase-locked with the external reference signal. Since the two oscillator units are locked to the same external reference signal, their output reference frequency signals have a defined phase relationship, maintaining phase coherence. Consequently, the target reference signal generated by their mixing also remains coherent with the main reference signal, laying the foundation for phase continuity for subsequent seamless switching.

[0047] In step S303, the mixing and filtering module mixes and filters multiple reference frequency signals and outputs the target reference signal.

[0048] The target reference signal is the sum of multiple reference frequency signals. The mixing and filtering module is connected to the output of the oscillator module and is used to mix and filter the multiple reference frequency signals output by the oscillator module to output the target reference signal. The target reference signal is the sum of multiple reference frequency signals.

[0049] In some alternative implementations, such as Figure 2 As shown, the mixing and filtering module includes at least a mixer and a filter. The input of the mixer is connected to each oscillator unit in the oscillator module to mix the reference frequency signals output by each oscillator unit and output a mixed signal. The input of the filter is connected to the output of the mixer and is used to filter the mixed signal and output a target reference signal.

[0050] The mixer performs mixing processing on multiple received reference frequency signals, for example, on the first reference sub-signal. and the fourth reference sub-signal The mixing process is performed, the mixed signal is output, and then the mixed signal is filtered before the target reference signal is output. ,in, .

[0051] In step S304, the central processing unit receives the target output frequency signal, determines the system reference clock signal based on the target output frequency signal and the target reference signal, and generates control commands.

[0052] The central processing unit first acquires the target output frequency signal set by the user or the system. Based on the target output frequency signal and the target reference signal generated by the mixing and filtering module, it dynamically decides which reference signal should be used as the clock source of the fractional frequency division phase-locked loop. For example, it selects from any reference frequency signal output from the oscillator module or the target reference signal.

[0053] Optionally, the central processing unit can calculate the degree of deviation between the target output frequency signal and an integer multiple of the currently selected reference frequency, and determine whether spurious signals at integer boundaries may fall within the bandwidth of the phase-locked loop. If there is a risk of spurious signals, the control signal selection switch is switched to the target reference signal; otherwise, the original reference is maintained.

[0054] Optionally, the central processing unit may pre-store a frequency-reference mapping table and directly look up the table to determine the reference signal to be selected based on the target output frequency signal, thereby reducing real-time computation overhead.

[0055] The central processing unit (CPU) can select the more favorable frequency signal for suppressing integer boundary spurious signals from the reference frequency signal directly output from the oscillator module and the target reference signal output from the mixer-filter module, based on the target output frequency signal. It then configures the division parameters of the fractional-order frequency-locked loop (FLL) accordingly to ensure the accuracy and spectral purity of the RF output frequency. The CPU is connected to the signal selection switch via a control line to send control commands, and to the FLL via a configuration interface to write the division parameters.

[0056] In some optional implementations, step S304, determining the system reference clock signal based on the target output frequency signal and the target reference signal, includes: Step 3041: Obtain the reference signal currently selected by the signal selection switch as the current reference signal.

[0057] The central processing unit first reads the current state of the signal selection switch to determine whether the reference signal currently selected and sent to the fractional frequency division phase-locked loop is the reference frequency signal from the oscillator module or the target reference signal from the mixer-filter module.

[0058] Step 3042: If the current reference signal is the first reference sub-signal, receive the target output frequency signal and calculate the difference between the target output frequency signal and an integer multiple of the first reference sub-signal as the offset of the integer boundary spurious relative to the target output frequency signal.

[0059] When the system is currently operating at the first reference frequency signal At 100MHz (for example), the central processing unit acquires the target output frequency signal set by the user or the upper-level system. Calculate the offset ΔF using the following formula:

[0060] Where N is a preset multiple, and N is an integer. The offset represents the frequency distance between the potential integer boundary spurious and the target carrier.

[0061] Step 3043: Determine whether the offset is less than a preset threshold.

[0062] The offset is compared with a preset threshold, which can be set according to the loop bandwidth of the fractional frequency division phase-locked loop, the system spurious suppression requirements, or engineering experience. For example, it can be set to the loop bandwidth value of the phase-locked loop or a certain proportion of it.

[0063] Step 3044: If the offset is less than the preset threshold, a switching command is generated and sent to the signal selection switch, instructing the signal selection switch to select the target reference signal as the system reference clock signal, and recalculate the frequency division parameters of the fractional frequency division phase-locked loop and configure them to the fractional frequency division phase-locked loop.

[0064] If the offset is less than a preset threshold, it indicates that integer boundary spurious signals will fall within the PLL loop bandwidth, significantly degrading the spectral purity of the output signal. At this point, the central processing unit immediately generates a switching command, which is sent to the signal selection switch via control lines such as the general-purpose input / output interface, controlling it to switch to the target reference signal output by the mixer-filter module.

[0065] Simultaneously, the central processing unit (CPU) recalculates the division parameters of the fractional-order frequency-locked loop (FLL) based on the new reference signal (i.e., the target reference signal), including both integer and fractional division ratios. The CPU writes the updated division parameters into the FLL via a configuration interface such as a serial peripheral interface or integrated circuit bus, ensuring that the RF output frequency remains equal to the target output frequency after the reference clock switch.

[0066] Step 3045: If the offset is greater than or equal to the preset threshold, then maintain the current gating state.

[0067] If the offset is greater than or equal to the preset threshold, it indicates that the integer boundary spurious signal is outside the PLL loop bandwidth and its impact on system performance is negligible. In this case, the central processing unit does not need to switch the reference signal, can maintain the current selection state of the signal selection switch, and configure the frequency division parameters of the fractional frequency division PLL according to the current reference signal, so that the system can work normally.

[0068] In step S305, the signal selection switch determines the system reference clock signal from the reference frequency signal output by the oscillator module and the target reference signal output by the mixer filter module according to the control command issued by the central processing unit.

[0069] The signal selection switch receives control commands from the central processing unit and selects one of the signals as the system reference clock signal output value using a fractional-division phase-locked loop. The signal selection switch can be a high-speed radio frequency switch.

[0070] In step S306, the fractional frequency division phase-locked loop receives the system reference clock signal and outputs the radio frequency output signal.

[0071] Specifically, step S306 includes: Step S3061: Receive the system reference clock signal output by the signal selection switch.

[0072] The reference input terminal of the fractional frequency division phase-locked loop is connected to the output terminal of the signal selection switch to receive the selected system reference clock signal in real time.

[0073] Step S3062: Receive the frequency division parameters configured by the central processing unit.

[0074] The frequency division parameters include integer division ratio and fractional division ratio. These parameters are calculated based on the currently selected system reference clock signal and the set target output frequency, specifically comprising two parts: the integer division ratio and the fractional division ratio. The integer division ratio sets the main division factor of the frequency divider, while the fractional division ratio is used to achieve fractional multiplication of the phase detection frequency. When the system reference clock switches, the central processing unit dynamically updates the frequency division parameters and rewrites them into the phase-locked loop to ensure the accuracy of the output frequency.

[0075] Step S3063: Based on the system reference clock signal and frequency division parameters, generate and output an RF output signal corresponding to the target output frequency signal.

[0076] The fractional frequency divider inside the fractional frequency division phase-locked loop divides the output frequency of the voltage-controlled oscillator (VCO) based on the received integer and fractional division ratios, generating a divided signal that is then sent to a phase detector. The phase detector compares this divided signal with the system reference clock signal at the reference input, outputting an error voltage proportional to the phase error. This error voltage is converted into a current signal by a charge pump, then smoothed by a loop filter to form the tuning voltage of the VCO, controlling its output frequency. The entire negative feedback loop ultimately achieves phase lock between the divided signal and the reference clock signal, at which point the VCO output frequency is precisely equal to the target output frequency signal.

[0077] When the system reference clock signal switches between the reference frequency signal output by the oscillator module and the target reference signal output by the mixer filter module, the fractional frequency divider phase-locked loop adjusts its working state according to the reconfigured frequency division parameters so that the frequency of the RF output signal before and after the switch remains continuous and equal to the target output frequency signal.

[0078] The low-phase-noise phase-locked loop spurious suppression method provided in this embodiment locks multiple oscillator units to the same external reference signal through a control module, ensuring phase coherence between the reference frequency signals. The central processing unit determines the system reference clock signal based on the target output frequency signal and the target reference signal. By avoiding integer boundary spurious signals, no external noise source is introduced, thus maintaining the ultra-low phase noise characteristics of the reference source while suppressing spurious signals. Furthermore, the output frequency remains continuous and accurate before and after switching, achieving a balance between low phase noise and low spurious signals.

[0079] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0080] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0081] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.

Claims

1. A low-phase-noise phase-locked loop spurious emission suppression system, characterized in that, The system includes: The control module is used to output multiple control signals based on an external reference signal; An oscillator module is connected to the output terminal of the control module. The oscillator module includes multiple oscillator units, and each oscillator unit corresponds one-to-one with a control signal output by the control module. A mixing and filtering module is connected to the output terminal of the oscillator module and is used to mix and filter multiple reference frequency signals output by the oscillator module to output a target reference signal, wherein the target reference signal is the sum of the multiple reference frequency signals; A signal selection switch, the input terminals of which are respectively connected to the oscillator module and the mixer filter module, is used to receive control commands issued by the central processing unit, the control commands including the system reference clock signal; The fractional-order frequency-locked loop is connected to the output terminal of the signal selection switch and is used to receive the system reference clock signal and output the radio frequency output signal. The central processing unit is connected to the signal selection switch and the fractional frequency-locked loop, respectively, and is used to receive the target output frequency signal and determine the system reference clock signal based on the target output frequency signal and the target reference signal.

2. The system according to claim 1, characterized in that, The oscillator module includes at least a first oscillator unit and a second oscillator unit, and the control signal includes at least a first control signal and a second control signal. The first oscillator unit outputs a first reference frequency signal based on the first control signal, and the second oscillator unit outputs a second reference frequency signal based on the second control signal.

3. The system according to claim 2, characterized in that, The oscillator module also includes: A first power divider, connected to the output of the first oscillator unit, is used to divide the first reference frequency signal into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal; wherein, the first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input of the control module; The second power divider is connected to the output of the second oscillator unit and is used to divide the second reference frequency signal into a fourth reference sub-signal and a fifth reference sub-signal; wherein the fourth reference sub-signal is output to the mixing and filtering module, the fifth reference sub-signal is output to the feedback input of the control module, and the target reference signal is the sum of the first reference sub-signal and the fourth reference sub-signal.

4. The system according to claim 1, characterized in that, The mixing and filtering module includes at least a mixer and a filter. The input terminal of the mixer is connected to each oscillator unit in the oscillator module, and the reference frequency signal output by each oscillator unit is mixed to output a mixed signal. A filter, the input of which is connected to the output of the mixer, is used to filter the mixed signal and output a target reference signal.

5. The system according to claim 3, characterized in that, The step of receiving the target output frequency signal and determining the system reference clock signal based on the target output frequency signal and the target reference signal includes: Obtain the reference signal currently selected by the signal selection switch as the current reference signal; If the current reference signal is the first reference sub-signal, the target output frequency signal is received, and the difference between the target output frequency signal and an integer multiple of the first reference sub-signal is calculated as the offset of the integer boundary spurious relative to the target output frequency signal. Determine whether the offset is less than a preset threshold; If the offset is less than a preset threshold, a switching command is generated and sent to the signal selection switch, instructing the signal selection switch to select the target reference signal as the system reference clock signal, and to recalculate the division parameters of the fractional frequency division phase-locked loop and configure them to the fractional frequency division phase-locked loop. If the offset is greater than or equal to a preset threshold, the current gating state is maintained.

6. The system according to claim 1, characterized in that, The step of receiving the system reference clock signal and outputting a radio frequency output signal includes: Receive the system reference clock signal output by the signal selection switch; The frequency division parameters configured by the central processing unit are received, the frequency division parameters including integer frequency division ratio and fractional frequency division ratio; Based on the system reference clock signal and the frequency division parameters, an RF output signal corresponding to the target output frequency signal is generated and output.

7. The system according to claim 1, characterized in that, The control module is used to generate and output multiple control signals based on an external reference signal and a reference frequency signal fed back by the oscillator module.

8. A method for suppressing stray emissions in a low-phase-noise phase-locked loop, characterized in that, Applied to the system according to any one of claims 1 to 7, the method comprises: The control module outputs multiple control signals based on an external reference signal; Each oscillator unit in the oscillator module generates multiple reference frequency signals according to the corresponding control signal; The mixing and filtering module mixes and filters the plurality of reference frequency signals and outputs a target reference signal, which is the sum of the plurality of reference frequency signals. The central processing unit receives the target output frequency signal, and based on the target output frequency signal and the target reference signal, determines the system reference clock signal and generates control commands. The signal selection switch determines the system reference clock signal from the reference frequency signal output by the oscillator module and the target reference signal output by the mixer filter module according to the control command issued by the central processing unit. The fractional-order frequency-locked loop receives the system reference clock signal and outputs an RF output signal.

9. The method according to claim 8, characterized in that, Determining the system reference clock signal based on the target output frequency signal and the target reference signal includes: Obtain the reference signal currently selected by the signal selection switch as the current reference signal; If the current reference signal is the first reference sub-signal, the target output frequency signal is received, and the difference between the target output frequency signal and an integer multiple of the first reference sub-signal is calculated as the offset of the integer boundary spurious relative to the target output frequency signal. Determine whether the offset is less than a preset threshold; If the offset is less than a preset threshold, a switching command is generated and sent to the signal selection switch, instructing the signal selection switch to select the target reference signal as the system reference clock signal, and to recalculate the division parameters of the fractional frequency division phase-locked loop and configure them to the fractional frequency division phase-locked loop. If the offset is greater than or equal to a preset threshold, the current gating state is maintained.

10. The method according to claim 8, characterized in that, The oscillator module includes at least a first oscillator unit and a second oscillator unit, the control signal includes at least a first control signal and a second control signal, and the method further includes: The first reference frequency signal output by the first oscillator unit is divided into a first reference sub-signal, a second reference sub-signal, and a third reference sub-signal by the first power divider. The first reference sub-signal is output to the mixing and filtering module, the second reference sub-signal is output to the signal selection switch, and the third reference sub-signal is output to the feedback input terminal of the control module. The second reference frequency signal output by the second oscillator unit is divided into a fourth reference sub-signal and a fifth reference sub-signal by the second power divider. The fourth reference sub-signal is output to the mixing and filtering module, and the fifth reference sub-signal is output to the feedback input terminal of the control module. The control module generates and outputs a first control signal and a second control signal based on the external reference signal, the third reference sub-signal, and the fifth reference sub-signal.

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