Method for adjusting clock signal, communication circuit, device, electronic equipment and medium

Abstract

Embodiments of the present application provide a clock signal adjustment method, a communication circuit, a device, an electronic device and a medium. The method is applied to a master device of a communication circuit, the communication circuit comprising: a master device, at least one first slave device, at least one second slave device and a switch selection device; the method comprising: obtaining a first communication mode corresponding to the first slave device, and obtaining a second communication mode corresponding to the second slave device; determining a first clock signal corresponding to the first slave device through the first communication mode; determining a third clock signal corresponding to the second slave device through the second communication mode; determining a preset second clock signal through the first clock signal and the third clock signal; and controlling the gating state of the first clock signal and the second clock signal to adjust the third clock signal. Based on the method provided in the present application, the communication efficiency between the master device and the slave device can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method for adjusting a clock signal, a communication circuit, a device, an electronic device, and a medium. Background Technology

[0002] Communication technology is the cornerstone of electronic system interconnection. Among them, Serial Peripheral Interface (SPI) communication meets the needs of high-speed scenarios and is simple to implement in hardware, so SPI communication is widely used in various aspects of smart hardware. The architecture of SPI communication typically consists of one master device and multiple slave devices. Each slave device must maintain a consistent communication mode with the master device; otherwise, data sampling errors will occur.

[0003] Currently, in related technologies, when the communication modes of different slave devices are different, traditional SPI master controllers only support fixed communication modes. Therefore, it is necessary to reconfigure the master device's communication mode through software to adapt to different slave devices. Consequently, the compatibility between the master and slave devices is poor, leading to low communication efficiency between them. Summary of the Invention

[0004] This application provides a clock signal adjustment method, communication circuit, device, electronic device, and medium to improve the communication efficiency between a master device and a slave device.

[0005] In a first aspect, this application provides a clock signal adjustment method applied to a master device of a communication circuit, wherein the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes; the method includes:

[0006] Obtain the first communication mode corresponding to the first slave device;

[0007] Obtain the second communication mode corresponding to the second slave device;

[0008] The first clock signal corresponding to the first slave device is determined through the first communication mode;

[0009] The third clock signal corresponding to the second slave device is determined through the second communication mode;

[0010] The preset second clock signal is determined by using the first clock signal and the third clock signal;

[0011] The control switch selection device selects the first clock signal and the second clock signal to adjust the third clock signal.

[0012] In one possible implementation, determining a preset second clock signal using a first clock signal and a third clock signal includes:

[0013] Determine the first timing parameters corresponding to the first clock signal, wherein the first timing parameters include the first clock polarity and the first clock phase;

[0014] Determine the second timing parameters corresponding to the third clock signal, wherein the second timing parameters include the second clock polarity and the second clock phase;

[0015] If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a high-level signal.

[0016] If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time of the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time of the third clock signal is the time corresponding to an odd edge, then the second clock signal is determined to be a low-level signal.

[0017] If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time of the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time of the third clock signal is the time corresponding to an odd edge, then the second clock signal is determined to be a high-level signal.

[0018] If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a low-level signal.

[0019] In one possible implementation, the control switch selection device adjusts the third clock signal by controlling the selection state of the first clock signal and the second clock signal, including:

[0020] If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0021] The first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle;

[0022] The second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle;

[0023] Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time;

[0024] Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0025] After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

[0026] In one possible implementation, the control switch selection device adjusts the third clock signal by controlling the selection state of the first clock signal and the second clock signal, including:

[0027] If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0028] The first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle;

[0029] The second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle;

[0030] Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time;

[0031] Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0032] After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

[0033] In one possible implementation, the control switch selection device adjusts the third clock signal by controlling the selection state of the first clock signal and the second clock signal, including:

[0034] If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0035] The first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle;

[0036] The second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle;

[0037] Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time;

[0038] Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0039] After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

[0040] In one possible implementation, the control switch selection device adjusts the third clock signal by controlling the selection state of the first clock signal and the second clock signal, including:

[0041] If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0042] The first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle;

[0043] The second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle;

[0044] Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time;

[0045] Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0046] After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

[0047] Secondly, embodiments of this application provide a communication circuit, which includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes.

[0048] The master device is electrically connected to the first slave device;

[0049] The input terminal of the switch selection device is connected to the main device and is used to receive the first clock signal, the preset second clock signal and the control signal sent by the main device.

[0050] The output of the switch selection device is connected to the second slave device and is used to output a first clock signal or a second clock signal to the second slave device based on the control signal, so as to adjust the clock signal output by the second slave device.

[0051] In one possible implementation, the master device includes: a first master communication pin, a second master communication pin, a master clock pin, a master chip select pin, a first input / output interface, and a second input / output interface; the first slave device and the second slave device each include: a first slave communication pin, a second slave communication pin, a slave chip select pin, and a slave clock pin.

[0052] The first master communication pin of the master device is connected to the first slave communication pin of the first slave device and the first slave communication pin of the second slave device, respectively, for sending data to the first slave device and the second slave device;

[0053] The second master communication pin of the master device is connected to the second slave communication pin of the first slave device and the second slave communication pin of the second slave device, respectively, and is used to receive data sent by the first slave device and the second slave device.

[0054] The master clock pin of the master device is connected to the slave clock pin of the first slave device to send a first clock signal to the first slave device;

[0055] The switch selection device includes a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the switch selection device is connected to the master clock pin of the master device to receive a first clock signal from the master device. The second input terminal of the switch selection device is connected to the first input / output interface of the master device to receive a preset second clock signal. The third input terminal of the switch selection device is connected to the second input / output interface of the master device to receive a control signal.

[0056] The output of the switch selection device is connected to the slave clock pin of the second slave device, and is used to select the first clock signal or the second clock signal to the slave clock pin of the second slave device according to the control signal.

[0057] The slave chip select pins of the first slave device and the second slave device are respectively connected to the master chip select pin on the master device to receive and respond to the chip select signal sent by the master device.

[0058] In one possible implementation, the communication circuit further includes: at least one first resistor module and at least one second resistor module, wherein the number of first resistor modules is the same as the number of first slave devices, and the first resistor module includes a first resistor R1, a second resistor R2 and a third resistor R3; the number of second resistor modules is the same as the number of second slave devices, and the second resistor module includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6.

[0059] One end of the first resistor R1 is connected to the first master communication pin of the master device, and the other end of the first resistor R1 is connected to the first slave communication pin of the first slave device.

[0060] One end of the second resistor R2 is connected to the second master communication pin of the master device, and the other end of the second resistor R2 is connected to the second slave communication pin of the first slave device.

[0061] One end of the third resistor R3 is connected to the master clock pin of the master device, and the other end of the third resistor R3 is connected to the slave clock pin of the first slave device.

[0062] One end of the fourth resistor R4 is connected to the first master communication pin of the master device, and the other end of the fourth resistor R4 is connected to the first slave communication pin of the second slave device.

[0063] One end of the fifth resistor R5 is connected to the second master communication pin of the master device, and the other end of the fifth resistor R5 is connected to the second slave communication pin of the second slave device.

[0064] One end of the sixth resistor R6 is connected to the output terminal of the switch selection device, and the other end of the sixth resistor R6 is connected to the slave clock pin of the second slave device.

[0065] Thirdly, this application provides a clock signal adjustment device applied to a master device of a communication circuit, wherein the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes; the device includes:

[0066] The acquisition module is used to acquire the first communication mode corresponding to the first slave device;

[0067] The acquisition module is also used to acquire the second communication mode corresponding to the second slave device;

[0068] The processing module is used to determine the first clock signal corresponding to the first slave device through the first communication mode;

[0069] The processing module is also used to determine the third clock signal corresponding to the second slave device through the second communication mode;

[0070] The processing module is also used to determine a preset second clock signal through the first clock signal and the third clock signal;

[0071] The processing module is also used to control the selection state of the switch selection device for the first clock signal and the second clock signal, so as to adjust the third clock signal.

[0072] Fourthly, embodiments of this application provide an electronic device, including: a memory and a processor;

[0073] The memory stores the instructions that the computer executes;

[0074] The processor executes computer execution instructions stored in memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0075] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0076] In a sixth aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0077] The clock signal adjustment method, communication circuit, device, electronic device, and medium provided in this application include a control switch selection device in the circuit. The first slave device maintains the same communication clock mode as the master device, while the second slave device has a different communication clock mode. By selectively sending either the first or second clock signal to the second slave device through the control switch selection device, the corresponding third clock signal of the second slave device is adjusted, thereby achieving the purpose of adjusting the communication mode of the second slave device. Therefore, based on the clock signal adjustment method, communication circuit, device, electronic device, and medium provided in this application, by flexibly adjusting the communication mode of the second slave device, it is ensured that each slave device in the communication circuit maintains the same communication mode as the master device, improving the compatibility between the master and slave devices, and thus improving the communication efficiency between the master and slave devices. Attached Figure Description

[0078] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0079] Figure 1 A schematic diagram illustrating the SPI communication scenario provided in this application;

[0080] Figure 2 Flowchart of the clock signal adjustment method provided in this application Figure 1 ;

[0081] Figure 3 This is a schematic diagram illustrating the SPI communication mode as an example.

[0082] Figure 4 Flowchart of the clock signal adjustment method provided in this application Figure 2 ;

[0083] Figure 5 Flowchart of the clock signal adjustment method provided in this application Figure 3;

[0084] Figure 6 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 1 ;

[0085] Figure 7 Flowchart of the clock signal adjustment method provided in this application Figure 4 ;

[0086] Figure 8 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 2 ;

[0087] Figure 9 Flowchart of the clock signal adjustment method provided in this application Figure 5 ;

[0088] Figure 10 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 3 ;

[0089] Figure 11 Flowchart of the clock signal adjustment method provided in this application Figure 6 ;

[0090] Figure 12 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 4 ;

[0091] Figure 13 Schematic diagram of the communication circuit provided in this application Figure 1 ;

[0092] Figure 14 Schematic diagram of the communication circuit provided in this application Figure 2 ;

[0093] Figure 15 Schematic diagram of the communication circuit provided in this application Figure 3 ;

[0094] Figure 16 A schematic diagram of the structure of the clock signal adjustment device provided in this application;

[0095] Figure 17 A schematic diagram of the structure of the electronic device provided in this application.

[0096] The above figures include the following reference numerals:

[0097] R1: First resistor;

[0098] R2: Second resistor;

[0099] R3: Third resistor;

[0100] R4: Fourth resistor;

[0101] R5: Fifth resistor;

[0102] R6: The sixth resistor.

[0103] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0104] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0105] Figure 1 A schematic diagram of the SPI communication scenario provided in this application is shown below. Figure 1 As shown, in an SPI communication scenario, there is one master device and multiple slave devices. Each slave device must maintain a consistent communication mode with the master device; otherwise, data sampling errors will occur. Currently, in related technologies, when the communication modes of the slave devices differ, traditional SPI master controllers only support fixed communication modes. Therefore, it is necessary to reconfigure the master device's communication mode through software to adapt to different slave devices. Consequently, the compatibility between the master and slave devices is poor in related technologies, leading to low communication efficiency between them.

[0106] This application adds a control switch selection device to the circuit. The first slave device maintains the same communication clock mode as the master device, while the second slave device has a different communication clock mode. By selectively sending either the first or second clock signal to the second slave device through the control switch selection device, the communication mode of the second slave device can be adjusted. Therefore, based on the clock signal adjustment method provided in this application, the communication mode of the second slave device can be flexibly adjusted to ensure that each slave device in the communication circuit maintains the same communication mode as the master device, improving the compatibility between the master and slave devices and thus increasing the communication efficiency between them.

[0107] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0108] Figure 2 Flowchart of the clock signal adjustment method provided in this application Figure 1 This is applied to a master device in a communication circuit, wherein the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes, such as... Figure 2 As shown, the method includes:

[0109] S201. Obtain the first communication mode corresponding to the first slave device.

[0110] In scenario examples, the master device is typically a microcontroller unit (MCU), and the slave device is typically a functional module. Communication modes can be represented by clock phase (CPHA) and clock polarity (CPOL). When the clock phase and clock polarity of the slave and master devices are the same, it can be determined that the slave and master devices have the same communication mode. Conversely, when the clock phase and clock polarity of the slave and master devices are different, it can be determined that the slave and master devices have different communication modes. Figure 1 Among multiple slave devices, some share the same communication mode as the master device; these can be designated as the first slave devices. The remaining slave devices do not share the same communication mode as the master device; these can be designated as the second slave devices. Since the master device and the first slave devices share the same communication mode, the CPHA and CPOL data corresponding to the master device and the first slave device can be monitored to determine their respective first communication modes.

[0111] S202, Obtain the second communication mode corresponding to the second slave device.

[0112] Similarly, by monitoring the CPHA and CPOL data of the second slave device, the second communication mode of the second slave device can be determined.

[0113] Specifically, Figure 3 This is a schematic diagram illustrating the SPI communication mode as an example. Figure 3As shown, there are four SPI communication modes: (CPOL=0, CPHA=0), (CPOL=0, CPHA=1), (CPOL=1, CPHA=0), and (CPOL=1, CPHA=1). CPOL represents the clock polarity, indicating the state of the SCK pin when the device is idle. CPOL=0 indicates that SCK is low when the device is idle, and CPOL=1 indicates that SCK is high when the device is idle. Idle state refers to the state before SPI communication begins, or when the device's CS pin is invalid. CPHA represents the clock phase, indicating whether the data sampling occurs on an even-numbered edge or an odd-numbered edge of SCK. CPHA=0 indicates that the signal on the MOSI or MISO pin is sampled on an odd-numbered edge, and CPHA=1 indicates that the signal on the MOSI or MISO pin is sampled on an even-numbered edge.

[0114] Table 1 provides a brief overview of the four SPI communication modes. As shown in Table 1, in mode 1 (CPOL=0, CPHA=0), SCK is low when the device is idle and is sampled on "odd edges". Figure 3 As we can see, odd-numbered edges are rising edges, so data sampling is performed at the time corresponding to the rising edge, and correspondingly, data updates are performed at the time corresponding to the falling edge.

[0115] In mode 2, corresponding to CPOL=0 and CPHA=1, SCK is low when the device is idle and is sampled on an even-numbered edge. Figure 6 As we can see, even-numbered edges are falling edges, so data sampling is performed at the time corresponding to the falling edge, and correspondingly, data updates are performed at the time corresponding to the rising edge.

[0116] In mode 3, corresponding to CPOL=1 and CPHA=0, SCK is high when the device is idle and is sampled on an odd-numbered edge. Figure 3 As we can see, odd-numbered edges are falling edges, so data sampling is performed at the time corresponding to the falling edge, and correspondingly, data updates are performed at the time corresponding to the rising edge.

[0117] In mode 4, corresponding to CPOL=1 and CPHA=1, SCK is high when the device is idle and is sampled on an even-numbered edge. Figure 3 As we can see, even-numbered edges are rising edges, so data sampling is performed at the time corresponding to the rising edge, and correspondingly, data updates are performed at the time corresponding to the falling edge.

[0118] Table 1

[0119]

[0120] S203. Determine the first clock signal corresponding to the first slave device through the first communication mode.

[0121] Based on the scenario example, if the first communication mode is mode 1, then the corresponding first clock signal is a low level when in idle state, and a clock signal sampled along odd-numbered edges.

[0122] S204. Determine the third clock signal corresponding to the second slave device through the second communication mode;

[0123] Based on the scenario example, the embodiments of this application can be used to adjust the clock signal of the second slave device when the CPOL and CPHA of the first slave device and the second slave device are different. Therefore, based on the above example, when the first communication mode is mode 1, the second communication mode can be mode 4, that is, a clock signal that is high when the third clock signal is in the idle state and is sampled along an even number of edges.

[0124] S205. Determine the preset second clock signal using the first clock signal and the third clock signal.

[0125] Based on the scenario example, the difference between the first clock signal and the third clock signal is used to determine whether the second clock signal is high or low, thus determining the corresponding second clock signal.

[0126] Optional, Figure 4 Flowchart of the clock signal adjustment method provided in this application Figure 2 ,like Figure 4 As shown, S205 includes:

[0127] S401. Determine the first timing parameters corresponding to the first clock signal, wherein the first timing parameters include the first clock polarity and the first clock phase.

[0128] Based on the scenario example, the first clock polarity is defined as CPOL1, and the first clock phase is defined as CPHA1.

[0129] S402. Determine the second timing parameters corresponding to the third clock signal, wherein the second timing parameters include the second clock polarity and the second clock phase.

[0130] Based on the scenario example, the second clock polarity is defined as CPOL2, and the first clock phase is defined as CPHA2. CPOL1 is the opposite of CPOL2, and CPHA1 is the opposite of CPHA2.

[0131] S403. If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a high-level signal.

[0132] In the example scenario, the first clock polarity indicates that the first clock signal is low when idle, i.e., CPOL1=0. The first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, i.e., CPHA1=0. In this case, the master device and the first slave device operate in mode 1. The second clock polarity indicates that the third clock signal is high when idle, i.e., CPOL2=1. The second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, i.e., CPHA2=1. In this case, the second slave device operates in mode 4. Under this condition, the second clock signal can be set to a high level.

[0133] S404. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, then the second clock signal is determined to be a low-level signal.

[0134] In the example scenario, the first clock polarity indicates that the first clock signal is high when idle, i.e., CPOL1=1. The first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, i.e., CPHA1=1. In this case, the master device and the first slave device operate in mode 4. The second clock polarity indicates that the third clock signal is low when idle, i.e., CPOL2=0. The second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, i.e., CPHA2=0. In this case, the second slave device operates in mode 1. Under this condition, the second clock signal can be set to low.

[0135] S405. If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, then the second clock signal is determined to be a high-level signal.

[0136] In the example scenario, the first clock polarity indicates that the first clock signal is low when idle, i.e., CPOL1=0. The first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, i.e., CPHA1=1. In this case, the master device and the first slave device operate in mode 2. The second clock polarity indicates that the third clock signal is high when idle, i.e., CPOL2=1. The second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, i.e., CPHA2=0. In this case, the second slave device operates in mode 3. Under this condition, the second clock signal can be set to a high level.

[0137] S406. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a low-level signal.

[0138] In the example scenario, the first clock polarity indicates that the first clock signal is high when idle, i.e., CPOL1=1. The first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, i.e., CPHA1=0. In this case, the master device and the first slave device operate in mode 3. The second clock polarity indicates that the third clock signal is low when idle, i.e., CPOL2=0. The second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, i.e., CPHA2=1. In this case, the second slave device operates in mode 2. Under this condition, the second clock signal can be set to low.

[0139] Based on the method provided in this example, the type of the second clock signal can be flexibly determined to suit the specific operating conditions of the first slave device and the second slave device.

[0140] S206. The control switch selection device selects the first clock signal and the second clock signal to adjust the third clock signal.

[0141] Based on the scenario example, the selection of the first clock signal and the second clock signal is switched by the control switch selection device, and the phase of the third clock signal is adjusted to be the same as the phase of the first clock signal, so as to ensure that the clock signals of the first slave device and the second slave device are the same.

[0142] Optional, Figure 5 Flowchart of the clock signal adjustment method provided in this application Figure 3 ,like Figure 5 As shown, S206 includes:

[0143] S501. If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0144] Combined with scenario examples, Figure 6 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 1 ,like Figure 6 As shown, the first slave device operates in mode 1, and the second slave device operates in mode 4. The first clock cycle is defined as T1, the first sampling time corresponding to the first clock signal is defined as time t1, and the last sampling time is defined as time t2. When the master and slave devices communicate, the chip select signal CS can be active one clock cycle earlier. The chip select signal is active when it is low. Therefore, one T1 cycle earlier than time t1, the chip select signals corresponding to the first and second slave devices can be adjusted to low level, and one T1 cycle later than time t2, the chip select signals corresponding to the first and second slave devices can be adjusted to high level.

[0145] S502. Determine the first target time using the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle.

[0146] Combined with scenario examples, such as Figure 6 As shown, the first target time is t3, and the time difference between t3 and t1 is half a time T1.

[0147] S503. Determine the second target time by using the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle.

[0148] Combined with scenario examples, such as Figure 6 As shown, the second target time is t4, and the time difference between t4 and t2 is half a time T1.

[0149] S504. Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time.

[0150] Combined with scenario examples, such as Figure 6 As shown, Figure 6The dashed line in the diagram represents the third clock signal in the example. Before time t3, the second clock signal is activated. Following the scheme in the S403 example, when the first slave device is operating in mode 1 and the second slave device is operating in mode 4, the second clock signal is high. Therefore, before time t3, by activating the second clock signal through the control switch selection device, the third clock signal can be adjusted to a high level.

[0151] S505. Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0152] Combined with scenario examples, such as Figure 6 As shown, between time t3 and time t4, by controlling the switch selection device to select the first clock signal, the third clock signal can be adjusted to be the same as the first clock signal.

[0153] S506. After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

[0154] Combined with scenario examples, such as Figure 6 As shown, after time t4, the third clock signal can be adjusted to a high level by selecting the second clock signal through the control switch selection device.

[0155] Based on the method provided in this example, when the first slave device is in mode 1 and the second slave device is in mode 4, the third clock signal of the second slave device can be adjusted to be the same as the first clock signal of the master device by selecting a high-level second clock signal through a control switch selection device, thereby achieving compatibility between the master device and the first and second slave devices and improving the communication efficiency between the master device and the first and second slave devices.

[0156] Optional, Figure 7 Flowchart of the clock signal adjustment method provided in this application Figure 4 ,like Figure 7 As shown, S206 also includes:

[0157] S701. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0158] Combined with scenario examples, Figure 8 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 2 ,like Figure 8 As shown, the first slave device operates in mode 4, and the second slave device operates in mode 1. The first clock cycle is defined as T1, the first sampling time corresponding to the first clock signal is defined as time t1, and the last sampling time is defined as time t2. When the master and slave devices communicate, the chip select signal CS can be active one clock cycle earlier. The chip select signal is active when it is low. Therefore, one T1 cycle earlier than time t1, the chip select signals corresponding to the first and second slave devices can be adjusted to low level, and one T1 cycle later than time t2, the chip select signals corresponding to the first and second slave devices can be adjusted to high level.

[0159] S702. Determine the first target time using the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle.

[0160] Combined with scenario examples, such as Figure 8 As shown, the first target time is t3, and the time difference between t3 and t1 is half a time T1.

[0161] S703. Determine the second target time by using the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle.

[0162] Combined with scenario examples, such as Figure 8 As shown, the second target time is t4, and the time difference between t4 and t2 is half a time T1.

[0163] S704. Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time.

[0164] Combined with scenario examples, such as Figure 8 As shown, Figure 8 The dashed line in the diagram represents the third clock signal in the example. Before time t3, the control switch selection device activates the second clock signal. Following the scheme in the S404 example, when the first slave device is operating in mode 4 and the second slave device is operating in mode 1, the second clock signal is at a low level. Therefore, by activating the second clock signal through the control switch selection device before time t3, the third clock signal can be adjusted to a low level.

[0165] S705. Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0166] Combined with scenario examples, such as Figure 8 As shown, between time t3 and time t4, by controlling the switch selection device to select the first clock signal, the third clock signal can be adjusted to be the same as the first clock signal.

[0167] S706. After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

[0168] Combined with scenario examples, such as Figure 8 As shown, after time t4, the third clock signal can be adjusted to a low level by selecting the second clock signal through the control switch selection device.

[0169] Based on the method provided in this example, when the first slave device is operating in mode 4 and the second slave device is operating in mode 1, the third clock signal of the second slave device can be adjusted to be the same as the first clock signal of the master device by using a low-level second clock signal, so as to achieve compatibility between the master device and the first and second slave devices, thereby improving the communication efficiency between the master device and the first and second slave devices.

[0170] Optional, Figure 9 Flowchart of the clock signal adjustment method provided in this application Figure 5 ,like Figure 9 As shown, S206 also includes:

[0171] S901. If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0172] Combined with scenario examples, Figure 10 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 3 ,like Figure 10As shown, the first slave device operates in mode 2, and the second slave device operates in mode 3. The first clock cycle is defined as T1, the first sampling time corresponding to the first clock signal is defined as time t1, and the last sampling time is defined as time t2. When the master and slave devices communicate, the chip select signal CS can be active one clock cycle earlier. The chip select signal is active when it is low. Therefore, one T1 before time t1, the chip select signals corresponding to the first and second slave devices can be adjusted to low level, and one T1 after time t2, the chip select signals corresponding to the first and second slave devices can be adjusted to high level.

[0173] S902. Determine the first target time using the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle.

[0174] Combined with scenario examples, such as Figure 10 As shown, the first target time is t3, and the time difference between t3 and t1 is half a time T1.

[0175] S903. Determine the second target time by using the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle.

[0176] Combined with scenario examples, such as Figure 10 As shown, the second target time is t4, and the time difference between t4 and t2 is half a time T1.

[0177] S904. Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time.

[0178] Combined with scenario examples, such as Figure 10 As shown, Figure 10 The dashed line in the diagram represents the third clock signal in the example. Before time t3, the control switch selection device activates the second clock signal. Following the scheme in the S405 example, when the first slave device is operating in mode 2 and the second slave device is operating in mode 3, the second clock signal is at a high level. Therefore, by activating the second clock signal through the control switch selection device before time t3, the third clock signal can be adjusted to a high level.

[0179] S905. Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0180] Combined with scenario examples, such as Figure 10As shown, between time t3 and time t4, by controlling the switch selection device to select the first clock signal, the third clock signal can be adjusted to be the same as the first clock signal.

[0181] S906. After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

[0182] Combined with scenario examples, such as Figure 10 As shown, after time t4, the third clock signal can be adjusted to a high level by selecting the second clock signal through the control switch selection device.

[0183] Based on the method provided in this example, when the first slave device is operating in mode 2 and the second slave device is operating in mode 3, the third clock signal of the second slave device can be adjusted to be the same as the first clock signal of the master device through a high-level second clock signal, so as to achieve compatibility between the master device and the first and second slave devices, thereby improving the communication efficiency between the master device and the first and second slave devices.

[0184] Optional, Figure 11 Flowchart of the clock signal adjustment method provided in this application Figure 6 ,like Figure 11 As shown, S206 also includes:

[0185] S1101. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock period corresponding to the first clock signal are determined.

[0186] Combined with scenario examples, Figure 12 A schematic diagram of clock signal adjustment for a second slave device as an example. Figure 4 ,like Figure 12 As shown, the first slave device operates in mode 3, and the second slave device operates in mode 2. The first clock cycle is defined as T1, the first sampling time corresponding to the first clock signal is defined as time t1, and the last sampling time is defined as time t2. When the master and slave devices communicate, the chip select signal CS can be active one clock cycle earlier. The chip select signal is active when it is low. Therefore, one T1 cycle earlier than time t1, the chip select signals corresponding to the first and second slave devices can be adjusted to low level, and one T1 cycle later than time t2, the chip select signals corresponding to the first and second slave devices can be adjusted to high level.

[0187] S1102. Determine the first target time using the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle.

[0188] Combined with scenario examples, such as Figure 12 As shown, the first target time is t3, and the time difference between t3 and t1 is half a time T1.

[0189] S1103. Determine the second target time by using the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle.

[0190] Combined with scenario examples, such as Figure 12 As shown, the second target time is t4, and the time difference between t4 and t2 is half a time T1.

[0191] S1104. Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time.

[0192] Combined with scenario examples, such as Figure 12 As shown, Figure 12 The dashed line in the diagram represents the third clock signal in the example. Before time t3, the control switch selection device activates the second clock signal. Following the scheme in the S406 example, when the first slave device is operating in mode 3 and the second slave device is operating in mode 2, the second clock signal is low. Therefore, by activating the second clock signal through the control switch selection device before time t3, the third clock signal can be adjusted to a low level.

[0193] S1105. Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time.

[0194] Combined with scenario examples, such as Figure 12 As shown, between time t3 and time t4, by controlling the switch selection device to select the first clock signal, the third clock signal can be adjusted to be the same as the first clock signal.

[0195] S1106. After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

[0196] Combined with scenario examples, such as Figure 12 As shown, after time t4, the third clock signal can be adjusted to a low level by selecting the second clock signal through the control switch selection device.

[0197] Based on the method provided in this example, when the first slave device is operating in mode 2 and the second slave device is operating in mode 3, the third clock signal of the second slave device can be adjusted to be the same as the first clock signal of the master device by using a low-level second clock signal, so as to achieve compatibility between the master device and the first and second slave devices, thereby improving the communication efficiency between the master device and the first and second slave devices.

[0198] Therefore, based on the clock signal adjustment method provided in this application, the communication mode of the second slave device can be flexibly adjusted to ensure that each slave device in the communication circuit maintains the same communication mode as the master device, thereby improving the compatibility between the master device and the slave device and thus improving the communication efficiency between the master device and the slave device.

[0199] Figure 13 Schematic diagram of the communication circuit provided in this application Figure 1 ,like Figure 13 As shown, the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes.

[0200] The master device is electrically connected to the first slave device;

[0201] The input terminal of the switch selection device is connected to the main device and is used to receive the first clock signal, the preset second clock signal and the control signal sent by the main device.

[0202] The output of the switch selection device is connected to the second slave device and is used to output a first clock signal or a second clock signal to the second slave device based on the control signal, so as to adjust the clock signal output by the second slave device.

[0203] In scenario examples, the master device is typically a microcontroller (MCU), and the slave device is typically a functional module. Communication modes can be represented by clock phase (CPHA) and clock polarity (CPOL). When the clock phase and clock polarity of the slave and master devices are the same, it can be determined that the slave and master devices share the same communication mode. Conversely, when the clock phase and clock polarity of the slave and master devices are different, it can be determined that the slave and master devices have different communication modes. Figure 1 Among multiple slave devices, some slave devices share the same communication mode as the master device; these slave devices can be designated as the first slave devices. The remaining slave devices do not share the same communication mode as the master device; these slave devices can be designated as the second slave devices.

[0204] Since the first slave device operates in the same CPHA / CPOL mode as the master device, it can be directly connected to the master device. However, the second slave device differs from the master device in CPHA / CPOL mode. Therefore, a switch selection device is added between the second slave device and the master device, allowing the second slave device to connect to the master device via this switch selection device. The switch selection device switches between a first clock signal and a second clock signal for the second slave device based on the difference in CPHA or CPOL between the two devices. The first clock signal is the SCK (Serial Clock) signal issued by the master device, used for synchronizing communication data. The second clock signal is a clock input / output (IO) signal issued by the master device, which can be high or low, used to adjust the CPHA / CPOL of the second slave device to ensure that its CPHA / CPOL remains the same as the master device's.

[0205] Based on the communication circuit provided in this example, the communication mode of the second slave device can be flexibly adjusted through the switch selection device to ensure that each slave device in the communication circuit maintains the same communication mode as the master device, thereby improving the compatibility between the master device and the slave device and thus improving the communication efficiency between the master device and the slave device.

[0206] Optional, Figure 14 Schematic diagram of the communication circuit provided in this application Figure 2 ,like Figure 14 As shown, the master device includes: a first master communication pin, a second master communication pin, a master clock pin, a master chip select pin, a first input / output interface, and a second input / output interface. The first slave device and the second slave device both include: a first slave communication pin, a second slave communication pin, a slave chip select pin, and a slave clock pin.

[0207] The first master communication pin of the master device is connected to the first slave communication pin of the first slave device and the first slave communication pin of the second slave device, respectively, for sending data to the first slave device and the second slave device;

[0208] The second master communication pin of the master device is connected to the second slave communication pin of the first slave device and the second slave communication pin of the second slave device, respectively, and is used to receive data sent by the first slave device and the second slave device.

[0209] The master clock pin of the master device is connected to the slave clock pin of the first slave device to send a first clock signal to the first slave device;

[0210] The switch selection device includes a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the switch selection device is connected to the master clock pin of the master device to receive a first clock signal from the master device. The second input terminal of the switch selection device is connected to the first input / output interface of the master device to receive a preset second clock signal. The third input terminal of the switch selection device is connected to the second input / output interface of the master device to receive a control signal.

[0211] The output of the switch selection device is connected to the slave clock pin of the second slave device, and is used to select the first clock signal or the second clock signal to the slave clock pin of the second slave device according to the control signal.

[0212] The slave chip select pins of the first slave device and the second slave device are respectively connected to the master chip select pin on the master device to receive and respond to the chip select signal sent by the master device.

[0213] In the scenario example, the first master communication pin is the Master Output / Slave Input (MOSI) pin on the master device, and the first slave communication pin is the MOSI pin on the slave device. The MOSI pin on the master device is connected to the MOSI pins of each first slave device and each second slave device, forming a signal line between the master device and each first slave device, and each second slave device. Data from the master device is output through this signal line, and data sent by the master device is read by the slave device through this signal line; that is, the direction of data on this signal line is from the master device to the slave device.

[0214] The second master communication pin is the Master Input / Slave Output (MISO) pin on the master device, and the second slave communication pin is the MISO pin on the slave device. The MISO pin on the master device is connected to the MISO pins of each first slave device and each second slave device, forming another signal line between the master device and each first slave device and each second slave device. Data from the slave devices is output from this signal line, and the master device reads data sent by the slave devices from this signal line; that is, the direction of data on this signal line is from slave device to master device.

[0215] The master clock pin is the SCK pin on the master device, and the slave clock pin is the SCK pin on the slave device. The SCK pin on the master device is connected to the SCK pin on the first slave device, forming a clock signal line between the master device and the first slave device. The master device sends a first clock signal to the first slave device through this clock signal line to synchronize communication data with the first slave device.

[0216] The master chip select pin is the CS (Chip Select) pin on the master device, and the slave chip select pin is the CS pin on the slave device. The master device has multiple CS pins (CS1-CSn), and the slave device has one CS pin. Each slave device's CS pin is connected to one of the master device's CS pins, forming the CS signal lines between the master device and each slave device. The master device uses these CS signal lines to locate each slave device.

[0217] The first input / output interface is the IO1 interface on the master device, and the second input / output interface is the IO2 interface on the master device. The SCK pin on the master device is connected to the first input terminal of the switch selection device, used to send a first clock signal to the switch selection device. The IO1 pin on the master device is connected to the second input terminal of the switch selection device, used to send a second clock signal to the switch selection device, which can be high or low. The IO2 pin on the master device is connected to the third input terminal of the switch selection device, used to send IO control to the switch selection device to control whether to output the first or second clock signal. The output terminal of the switch selection device is connected to the SCK pin of the second slave device, forming a clock signal line between the two devices. When the switch selection device outputs the first clock signal to the second slave device through this clock signal line, the CPHA / CPOL mode of the second slave device remains the same as that of the master device. When the switch selection device outputs the second clock signal to the second slave device through this clock signal line, the CPHA / CPOL mode of the second slave device can be adjusted to high or low.

[0218] Optional, Figure 15 Schematic diagram of the communication circuit provided in this application Figure 3 ,like Figure 15 As shown, the communication circuit further includes: at least one first resistor module and at least one second resistor module, wherein the number of first resistor modules is the same as the number of first slave devices, and the first resistor module includes a first resistor R1, a second resistor R2 and a third resistor R3; the number of second resistor modules is the same as the number of second slave devices, and the second resistor module includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6.

[0219] One end of the first resistor R1 is connected to the first master communication pin of the master device, and the other end of the first resistor R1 is connected to the first slave communication pin of the first slave device.

[0220] One end of the second resistor R2 is connected to the second master communication pin of the master device, and the other end of the second resistor R2 is connected to the second slave communication pin of the first slave device.

[0221] One end of the third resistor R3 is connected to the master clock pin of the master device, and the other end of the third resistor R3 is connected to the slave clock pin of the first slave device.

[0222] One end of the fourth resistor R4 is connected to the first master communication pin of the master device, and the other end of the fourth resistor R4 is connected to the first slave communication pin of the second slave device.

[0223] One end of the fifth resistor R5 is connected to the second master communication pin of the master device, and the other end of the fifth resistor R5 is connected to the second slave communication pin of the second slave device.

[0224] One end of the sixth resistor R6 is connected to the output terminal of the switch selection device, and the other end of the sixth resistor R6 is connected to the slave clock pin of the second slave device.

[0225] Based on the scenario example, for each slave device, adding a first resistor R1 to the signal line formed by the MOSI interfaces of the master device and the slave device improves the anti-interference capability of the signal on this line, ensuring the stability of signal transmission. Similarly, adding a second resistor R2 to the signal line formed by the MISO interfaces of the master device and the slave device improves the anti-interference capability of the signal on this line, ensuring the stability of signal transmission. Likewise, adding a third resistor R3 to the clock signal line formed by the SCK interfaces of the master device and the slave device improves the anti-interference capability of the clock signal on this line, ensuring the stability of clock signal transmission. The resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 can be determined according to the actual situation.

[0226] For each second slave device, a fourth resistor R4 is added to the signal line formed by the MOSI interface of the master device and the MOSI interface of the second slave device. This improves the anti-interference capability of the signal in this signal line, ensuring the stability of signal transmission. Similarly, a fifth resistor R5 is added to the signal line formed by the MISO interface of the master device and the MISO interface of the second slave device. This improves the anti-interference capability of the signal in this signal line, ensuring the stability of signal transmission. Likewise, a sixth resistor R6 is added to the clock signal line formed by the output terminal of the switch selection device and the SCK interface of the second slave device. This improves the anti-interference capability of the clock signal in this clock signal line, ensuring the stability of clock signal transmission. The resistance values ​​of the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 can be determined according to the actual situation.

[0227] Figure 16 A schematic diagram of the structure of the clock signal adjustment device provided in this application is shown below. Figure 16 As shown, it includes:

[0228] The acquisition module 161 is used to acquire the first communication mode corresponding to the master device and each first slave device.

[0229] The acquisition module 161 is also used to acquire the second communication mode corresponding to each second slave device.

[0230] The processing module 162 is used to determine the first clock signal corresponding to the first slave device through the first communication mode.

[0231] The processing module 162 is also used to determine the third clock signal corresponding to the second slave device through the second communication mode.

[0232] The processing module 162 is also used to determine a preset second clock signal through the first clock signal and the third clock signal.

[0233] The processing module 162 is also used to control the strobe state of the first clock signal and the second clock signal in order to adjust the third clock signal.

[0234] The clock signal adjustment device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0235] Figure 17 A schematic diagram of the structure of the electronic device provided in this application. Figure 17 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0236] In a specific implementation, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.

[0237] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0238] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0239] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0240] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0241] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the device identifier update method when running.

[0242] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0243] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the device identifier update method embodiments described above.

[0244] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described device identifier update method embodiments.

[0245] It should be noted that the division of units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0246] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0247] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0248] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0249] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0250] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0251] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation.

[0252] The foregoing has provided a detailed description of a device identification update system, method, electronic device, medium, and product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for adjusting a clock signal, characterized in that, A master device is applied to a communication circuit, wherein the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes; the method includes: Obtain the first communication mode corresponding to the first slave device; Obtain the second communication mode corresponding to the second slave device; The first clock signal corresponding to the first slave device is determined through the first communication mode; The third clock signal corresponding to the second slave device is determined through the second communication mode; A preset second clock signal is determined using the first clock signal and the third clock signal; The switch selection device controls the selection state of the first clock signal and the second clock signal to adjust the third clock signal.

2. The method according to claim 1, characterized in that, The step of determining a preset second clock signal using the first clock signal and the third clock signal includes: Determine the first timing parameters corresponding to the first clock signal, wherein the first timing parameters include the first clock polarity and the first clock phase; Determine the second timing parameters corresponding to the third clock signal, wherein the second timing parameters include the second clock polarity and the second clock phase; If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a high-level signal. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, then the second clock signal is determined to be a low-level signal. If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, then the second clock signal is determined to be a high-level signal. If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the second clock signal is determined to be a low-level signal.

3. The method according to claim 2, characterized in that, The control switch selection device adjusts the third clock signal by selecting the first clock signal and the second clock signal, including: If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock cycle corresponding to the first clock signal are determined. A first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle; A second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle; Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time; Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time; After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

4. The method according to claim 2, characterized in that, The control switch selection device adjusts the third clock signal by selecting the first clock signal and the second clock signal, including: If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd-numbered edge, then the first sampling time, the last sampling time, and the first clock cycle corresponding to the first clock signal are determined. A first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle; A second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle; Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time; Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time; After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

5. The method according to claim 2, characterized in that, The control switch selection device adjusts the third clock signal by selecting the first clock signal and the second clock signal, including: If the first clock polarity indicates that the first clock signal is low when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an even edge, the second clock polarity indicates that the third clock signal is high when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an odd edge, then the first sampling time, the last sampling time, and the first clock cycle corresponding to the first clock signal are determined. A first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle; A second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle; Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is high before the first target time; Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time; After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is high after the second target time.

6. The method according to claim 2, characterized in that, The control switch selection device adjusts the third clock signal by selecting the first and second clock signals, including: If the first clock polarity indicates that the first clock signal is high when idle, the first clock phase indicates that the sampling time corresponding to the first clock signal is the time corresponding to an odd-numbered edge, the second clock polarity indicates that the third clock signal is low when idle, and the second clock phase indicates that the sampling time corresponding to the third clock signal is the time corresponding to an even-numbered edge, then the first sampling time, the last sampling time, and the first clock cycle corresponding to the first clock signal are determined. A first target time is determined by the first sampling time and the first clock cycle, wherein the first target time is before the first sampling time and the difference between the two is half of the first clock cycle; A second target time is determined by the last sampling time and the first clock cycle, wherein the second target time is after the last sampling time and the difference between the two is half of the first clock cycle; Before the first target time, the control switch selection device selects the second clock signal so that the third clock signal is low before the first target time; Between the first target time and the second target time, the control switch selection device selects the first clock signal so that the third clock signal is the same as the first clock signal between the first target time and the second target time; After the second target time, the control switch selection device selects the second clock signal so that the third clock signal is low after the second target time.

7. A communication circuit, characterized in that, The communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes. The master device is electrically connected to the first slave device; The input terminal of the switch selection device is connected to the main device and is used to receive a first clock signal, a preset second clock signal, and a control signal sent by the main device. The output terminal of the switch selection device is connected to the second slave device and is used to output the first clock signal or the second clock signal to the second slave device based on the control signal, so as to adjust the clock signal output by the second slave device.

8. The circuit according to claim 7, characterized in that, The master device includes: a first master communication pin, a second master communication pin, a master clock pin, a master chip select pin, a first input / output interface, and a second input / output interface. The first slave device and the second slave device each include: a first slave communication pin, a second slave communication pin, a slave chip select pin, and a slave clock pin. The first master communication pin of the master device is connected to the first slave communication pin of the first slave device and the first slave communication pin of the second slave device, respectively, for sending data to the first slave device and the second slave device; The second master communication pin of the master device is connected to the second slave communication pin of the first slave device and the second slave communication pin of the second slave device respectively, and is used to receive data sent by the first slave device and the second slave device. The master clock pin of the master device is connected to the slave clock pin of the first slave device, and is used to send a first clock signal to the first slave device; The switch selection device includes a first input terminal, a second input terminal, and a third input terminal. The first input terminal of the switch selection device is connected to the main clock pin of the master device and is used to receive a first clock signal sent by the master device. The second input terminal of the switch selection device is connected to the first input / output interface of the master device and is used to receive the preset second clock signal. The third input terminal of the switch selection device is connected to the second input / output interface of the master device and is used to receive the control signal. The output terminal of the switch selection device is connected to the slave clock pin of the second slave device, and is used to select the first clock signal or the second clock signal to the slave clock pin of the second slave device according to the control signal. The slave chip select pin of the first slave device and the slave chip select pin of the second slave device are respectively connected to the master chip select pin of the master device, and are used to receive and respond to the chip select signal sent by the master device.

9. The circuit according to claim 8, characterized in that, The communication circuit further includes: at least one first resistor module and at least one second resistor module, wherein the number of first resistor modules is the same as the number of first slave devices, and the first resistor module includes a first resistor (R1), a second resistor (R2) and a third resistor (R3); the number of second resistor modules is the same as the number of second slave devices, and the second resistor module includes a fourth resistor (R4), a fifth resistor (R5) and a sixth resistor (R6). One end of the first resistor (R1) is connected to the first master communication pin of the master device, and the other end of the first resistor (R1) is connected to the first slave communication pin of the first slave device. One end of the second resistor (R2) is connected to the second master communication pin of the master device, and the other end of the second resistor (R2) is connected to the second slave communication pin of the first slave device; One end of the third resistor (R3) is connected to the master clock pin of the master device, and the other end of the third resistor (R3) is connected to the slave clock pin of the first slave device; One end of the fourth resistor (R4) is connected to the first master communication pin of the master device, and the other end of the fourth resistor (R4) is connected to the first slave communication pin of the second slave device; One end of the fifth resistor (R5) is connected to the second master communication pin of the master device, and the other end of the fifth resistor (R5) is connected to the second slave communication pin of the second slave device; One end of the sixth resistor (R6) is connected to the output terminal of the switch selection device, and the other end of the sixth resistor (R6) is connected to the slave clock pin of the second slave device.

10. A clock signal adjustment device, characterized in that, A master device is applied to a communication circuit, wherein the communication circuit includes: a master device, at least one first slave device, at least one second slave device, and a switch selection device, wherein the first slave device and the master device have the same communication mode, and the second slave device and the master device have different communication modes; the device includes: The acquisition module is used to acquire the first communication mode corresponding to the first slave device; The acquisition module is also used to acquire the second communication mode corresponding to the second slave device; The processing module is used to determine the first clock signal corresponding to the first slave device through the first communication mode; The processing module is further configured to determine the third clock signal corresponding to the second slave device through the second communication mode; The processing module is further configured to determine a preset second clock signal using the first clock signal and the third clock signal; The processing module is also used to control the selection state of the switch selection device for the first clock signal and the second clock signal, so as to adjust the third clock signal.

11. An electronic device, characterized in that, include: Memory, processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory, causing the processor to perform the method as described in any one of claims 1-6.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

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