Sequence detection decoding method and device, equipment and storage medium

Abstract

The application discloses a sequence detection decoding method, device and equipment and a storage medium. In the application, after an initial discrete sequence is acquired, the initial discrete sequence needs to be preprocessed so as to converge the ISI effective memory length to a predetermined range, thereby reducing the calculation complexity of an sMLSE sequence detector. Furthermore, the sMLSE sequence detector and a soft decision decoder are adopted to perform an iterative detection decoding process. The soft decision decoder will continue to participate in the sMLSE sequence detector to perform the next round of iteration according to the extrinsic information generated in the current round of iteration. In this way, the discrimination ability for a correct symbol sequence can be gradually enhanced and the decoding performance can be improved under a strong ISI condition.

Description

Technical Field

[0001] This application relates to the field of sequence detection and decoding technology, and in particular to a sequence detection and decoding method, apparatus, device and storage medium. Background Technology

[0002] In intensity modulation / direct detection short-range optical interconnect systems, the need to increase the net rate per channel is driving the continuous development of multi-level modulation, such as 4 / 6 / 8-level pulse amplitude modulation, towards higher baud rates. As the symbol rate increases, the bottleneck in link performance often shifts from noise-limited to bandwidth-limited: the limited bandwidth of the transmitter driver and modulator, and the photodetector and analog-to-digital converter at the receiver, along with frequency response roll-off and group delay distortion, can cause waveform distortion and long-memory inter-symbol interference (ISI). Therefore, the receiver needs to perform equalization and sequence recovery with controllable complexity and provide reliable soft information to soft decision-making processes to release error correction gain.

[0003] Currently, methods for suppressing strong ISI and generating soft information mainly include FFE (Feedforward equalizer), DFE (Decision feedback equalizer), and MLSE (Maximum likelihood sequence estimation). However, with FFE, when there is a significant bandwidth roll-off or null in the link, FFE often requires a large gain to suppress ISI, thus amplifying noise and quantization errors in the attenuated frequency band, leading to increased noise and causing residual ISI and noise to compress the decision margin. With DFE, once a misjudgment occurs under strong ISI or low signal-to-noise ratio conditions, the error will continue to accumulate through feedback and propagate to subsequent symbols, forming burst errors or error planes, and this method still has limited robustness in suppressing long-memory ISI. With MLSE, the number of MLSE states increases exponentially with the memory length, and the complexity is unacceptable under long-memory ISI. Moreover, it often outputs hard decisions and lacks high-quality soft interfaces, making it difficult to form efficient collaboration with LDPC and other methods while keeping the complexity under control.

[0004] Therefore, how to enhance the ability to distinguish correct symbol sequences and improve decoding performance in strong ISI scenarios is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a sequence detection decoding method, apparatus, device, and storage medium to enhance the ability to distinguish correct symbol sequences and improve decoding performance in strong ISI scenarios.

[0006] Firstly, this application provides a sequence detection decoding method, including: The initial discrete sequence is preprocessed to obtain the target discrete sequence; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range. The target discrete sequence is input into the sMLSE sequence detector, and an iterative detection and decoding process is performed through the sMLSE sequence detector and the soft decision decoder. Each iteration process is as follows: using the sMLSE sequence detector and the soft decision decoder to generate the external information generated in the previous iteration, the bit-level soft information of the current iteration is generated; using the soft decision decoder and the soft information of the current iteration, the external information of the current iteration is generated, and the next iteration process continues. After the iteration is completed, the decoding result output by the soft decision decoder is obtained.

[0007] Optionally, bit-level soft information for the current iteration is generated using the sMLSE sequence detector and the extrinsic information generated in the previous iteration by the soft-decision decoder, including: A first posterior log-likelihood ratio is generated using the sMLSE sequence detector and the first prior log-likelihood ratio; wherein, the first prior log-likelihood ratio is generated by interleaving the extrinsic information generated by the soft-decision decoder in the previous iteration. Subtracting the first posterior log-likelihood ratio from the first prior log-likelihood ratio generates bit-level soft information for this iteration.

[0008] Optionally, generating a first posterior log-likelihood ratio using the sMLSE sequence detector and the first prior log-likelihood ratio includes: The Viterbi algorithm based on bidirectional recursion calculates the branch metric based on the first prior log-likelihood ratio, and calculates the forward metric and the backward metric based on the branch metric; using the forward metric and the backward metric, the first posterior log-likelihood ratio is determined.

[0009] Optionally, the external information generated for this iteration, through the soft-decision decoder and the soft information of this iteration, includes: After the soft information is deinterleaved, it is sent to the soft decision decoder as the second prior log-likelihood ratio. The soft decision decoder uses the second prior log-likelihood ratio to perform internal iterative decoding to generate the second posterior log-likelihood ratio. Subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio generates extrinsic information for the current iteration. This extrinsic information is then interleaved and used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration.

[0010] Optionally, after the iteration is complete, obtaining the decoding result output by the soft-decision decoder includes: Determine whether the number of iterations in the decoding process has reached the predetermined number of iterations; If so, the iteration is determined to be over, and a final decision is made based on the second posterior log-likelihood ratio obtained by the soft-decision decoder in the last iteration process, generating the decoding result.

[0011] Optionally, after subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio to generate the extrinsic information for this iteration, the method further includes: An adjustment operation is performed on the extrinsic information of the current iteration, and the adjusted extrinsic information is interleaved and used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration; wherein, the adjustment operation includes any one of the following: extrinsic information scaling operation, extrinsic information truncation operation, and extrinsic information normalization calibration operation.

[0012] Optionally, the initial discrete sequence is preprocessed to obtain the target discrete sequence, including: The initial discrete sequence is preprocessed by a feedforward equalizer to bring the effective memory length of the ISI of the initial discrete sequence to a predetermined range, thus obtaining a preprocessed sequence. The preprocessed sequence is noise-whitened using a noise whitening filter to obtain the target discrete sequence.

[0013] Secondly, this application provides a sequence detection decoding apparatus, comprising: The preprocessing module is used to preprocess the initial discrete sequence to obtain the target discrete sequence, and input the target discrete sequence into the sMLSE sequence detector; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range; The detection and decoding module is used to perform an iterative detection and decoding process using the sMLSE sequence detector and the soft decision decoder. After the iteration is completed, the decoding result output by the soft decision decoder is obtained. Each iteration process is as follows: using the sMLSE sequence detector and the external information generated by the soft decision decoder in the previous iteration, bit-level soft information for the current iteration is generated; using the soft decision decoder and the soft information for the current iteration, external information for the current iteration is generated, and the next iteration process continues.

[0014] Thirdly, this application provides an electronic device, comprising: Memory, used to store computer programs; A processor is used to implement the steps of the sequence detection decoding method described above when executing the computer program.

[0015] Fourthly, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the sequence detection decoding method described above.

[0016] Compared with the prior art, the technical solutions provided in this application have the following advantages: This application discloses a sequence detection decoding method, apparatus, device, and storage medium. In this application, after obtaining the initial discrete sequence, it is necessary to preprocess the initial discrete sequence to converge the effective memory length of ISI to a predetermined range, thereby reducing the computational complexity of the sMLSE sequence detector; furthermore, this application uses an sMLSE sequence detector and a soft-decision decoder to perform an iterative detection decoding process. The extrinsic information generated by the soft-decision decoder in this iteration will continue to participate in the next iteration of the sMLSE sequence detector. This method can gradually enhance the ability to distinguish correct symbol sequences and improve decoding performance under strong ISI conditions. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a schematic flowchart of a sequence detection and decoding method provided in an embodiment of this application; Figure 2 A flowchart of sMLSE-LDPC technology is provided for an embodiment of this application; Figure 3 A schematic diagram of bidirectional state transition provided in an embodiment of this application; Figure 4 A schematic diagram illustrating the relationship between bit error rate performance and tap coefficients in pre-filtering, provided for embodiments of this application; Figure 5 A schematic diagram illustrating the relationship between bit error rate performance and received optical power provided for an embodiment of this application; Figure 6 Another schematic diagram illustrating the relationship between bit error rate performance and received optical power provided for an embodiment of this application; Figure 7 A schematic diagram of a sequence detection decoding device provided in an embodiment of this application; Figure 8 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0021] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of this application.

[0022] It should be noted that, in the optional embodiments of this application, the data related to object information, when applied to specific products or technologies, requires the permission or consent of the object. Furthermore, the collection, use, and processing of this data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. In other words, if the embodiments of this application involve data related to an object, it must be obtained with the object's authorization and consent, the authorization and consent of relevant departments, and in accordance with the relevant laws, regulations, and standards of the country and region. If the embodiments involve personal information, the acquisition of all personal information requires the individual's consent. If sensitive information is involved, the separate consent of the information subject is required. The embodiments also need to be implemented with the object's authorization and consent.

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Furthermore, the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document, unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship. To better understand and illustrate the solutions of the embodiments of this application, some technical terms involved in the embodiments of this application are briefly explained below.

[0025] IM / DD (intensity-modulation / direct-detection) is a modulation and detection method in optical communication systems. The transmitting end carries the signal by changing the intensity (power) of the optical carrier (intensity modulation), while the receiving end directly converts the received optical power changes into electrical signals using a photodetector (direct detection).

[0026] PAM-4 / 6 / 8 (4 / 6 / 8-ary Pulse amplitude modulation) is a multilevel modulation technique.

[0027] ADC (Analog-to-digital conversion) is the process of converting a continuous analog signal (such as an electrical signal received from an optical fiber after photoelectric conversion) into a discrete digital signal.

[0028] Inter-symbol interference (ISI) occurs when adjacent symbols overlap and widen during transmission due to channel bandwidth limitations or dispersion, causing the energy of the current symbol to diffuse into the time slots of adjacent symbols, thus interfering with them.

[0029] FFE (Feedforward equalizer) is a type of linear equalizer that compensates for channel distortion and eliminates part of ISI by weighted summation of the received signal and its delay (preamble and postamble symbols).

[0030] DFE (Decision Feedback Equalizer) is a type of nonlinear equalizer. After making a decision on the current symbol, it processes the decision result through a feedback filter to subtract the ISI caused by the current symbol in subsequent symbols.

[0031] MLSE (Maximum Likelihood Sequence Estimation) is an optimal nonlinear equalization / detection algorithm. Instead of making decisions for each symbol individually, it searches for the transmitted sequence that is "most similar" to the received sequence as the output, taking into account channel memory effects, based on the entire received signal sequence.

[0032] FEC (Forward Error Correction) involves the sender adding specific redundant information (check bits) to the original data. The receiver then uses this redundant information to directly detect and correct errors that occur during transmission without needing to request retransmission via the reverse channel.

[0033] SD-FEC (soft decision forward error correct) is an error correction coding technique. Unlike hard decision FEC, which only uses "0" or "1" hard information, SD-FEC decoders utilize finer "soft information" from the received signal (such as the confidence level of the signal's distance from the decision threshold) for decoding, which can significantly improve error correction capability, thereby extending transmission distance or reducing the requirements for optical signal-to-noise ratio.

[0034] SOVA (soft output Viterbi algorithm) is an improved Viterbi algorithm. While the traditional Viterbi algorithm outputs hard decisions (i.e., the most likely bit sequence), SOVA not only provides the decision result but also outputs soft information about the reliability of each decision (the soft information is the log-likelihood ratio LLR). This soft information can be used as input to the next-stage SD-FEC decoder.

[0035] sMLSE (soft-output Maximum likelihood sequence estimation) is a maximum likelihood sequence estimation method with soft-output capability. Similar to SOVA, it can generate soft information (LLR) about the reliability of each output bit while performing maximum likelihood sequence detection (MLSE), which can be used by subsequent soft-decision error correction codes to further improve system performance.

[0036] In digital communication, LLR (Log-likelihood ratio) is a measure of the relative confidence that a received signal is either 0 or 1. LLR is a mathematical representation of soft information; a larger positive value indicates that the signal is more likely to be 1, a larger absolute negative value indicates that the signal is more likely to be 0, and a value close to zero indicates low reliability.

[0037] ROP (Received optical power) refers to the actual optical signal power measured at the input port of an optical receiver, usually measured in dBm. It is a direct physical quantity that measures the strength of the signal energy at the receiving end.

[0038] RPS (Received Power Sensitivity) refers to the minimum average optical power that a receiver can receive while ensuring the system meets specific performance indicators (such as a bit error rate below a certain threshold). Higher sensitivity (lower numerical value) indicates a stronger ability of the receiver to detect weak signals.

[0039] DWF (Noise Whitening Filter) converts colored noise in the received signal (such as noise with a non-flat spectrum after equalization) into white noise, making the subsequent maximum likelihood sequence estimation (MLSE) metric based on Euclidean distance optimal.

[0040] The LDPC decoder (Low-Density Parity-Check decoder) uses soft information (LLR) for iterative decoding, approaching the Shannon limit, and is a powerful forward error correction (FEC) module in modern high-speed communication systems.

[0041] SNR (Signal-to-Noise Ratio) is the ratio of signal power to noise power in an electronic device or communication system, usually expressed in decibels. A higher SNR means a clearer signal, less noise interference, and generally a lower bit error rate.

[0042] In intensity modulation / direct detection short-range optical interconnect systems, the need to increase the net rate per channel is driving the development of multi-level modulation such as 4 / 6 / 8-level pulse amplitude modulation to higher baud rates. As the symbol rate increases, the bottleneck in link performance often shifts from noise-limited to bandwidth-limited: the limited bandwidth of front-end devices such as transmitter drivers and modulators, and receiver photodetectors and analog-to-digital converters, along with frequency response roll-off and group delay distortion, cause pulse broadening and waveform distortion, significantly enhancing inter-symbol correlation. The equivalent impulse response spans multiple symbol intervals, resulting in strong inter-symbol interference and a significant memory effect. Under these conditions, the receiver can no longer rely on simple decision-making to reliably recover data; instead, it must perform more effective equalization and sequence recovery against the backdrop of sequence interference, providing reliable decision information for error correction decoding. Especially when bandwidth limitations are more severe or transmission distances increase (dispersion effects are more pronounced), residual inter-symbol interference often becomes the dominant limiting factor for the system's bit error rate. Even with strong error correction codes configured in subsequent stages, if the front-end fails to effectively suppress or properly handle inter-symbol interference, leading to bias or insufficient reliability of the input soft / hard information, the error correction gain cannot be fully realized.

[0043] Therefore, constructing a receiving and processing mechanism that can output decision information that more closely matches the true statistical characteristics, focusing on the suppression and compensation of strong inter-symbol interference, is a key fundamental issue for high-speed IM / DD PAM systems to achieve highly reliable transmission.

[0044] Against this backdrop, existing IM / DD PAM receivers typically employ linear equalization (FFE) to combat long-memory ISI caused by bandwidth constraints, with feedforward equalizers (FFEs) being the most common. FFEs approximate the inverse channel using finite-tap FIR filters (Finite Impulse Response filters), simultaneously suppressing upstream and downstream interference and offering easy adaptive updates, thus possessing strong engineering versatility. However, when the link exhibits significant bandwidth roll-off, the inverse filtering nature of FFE inevitably amplifies noise and quantization errors in the attenuated frequency band, resulting in noise enhancement. Simultaneously, since real-world links are often not strictly minimum phase or possess frequency response nulls, finite-tap FFEs struggle to completely eliminate long-tail ISI without introducing additional distortion, and residual interference still significantly compresses the decision margin. Especially in high-order PAM scenarios, where symbol spacing is smaller, the noise enhancement caused by FFE and residual ISI are more likely to jointly dominate bit errors, leading to insufficient reliability of the soft / hard information seen in subsequent decoding stages.

[0045] To further enhance ISI suppression, decision feedback equalizers (DFEs) introduce a feedback branch in addition to the feedforward branch, utilizing decided symbols to reconstruct and cancel downstream interference. Compared to pure FFEs, DFEs can achieve stronger downstream suppression with a more moderate feedforward gain in certain bandwidth-constrained scenarios, and are therefore widely used in PAM receivers.

[0046] However, DFE's reliance on hard-decision feedback inherently carries the risk of error propagation: misjudgment under low signal-to-noise ratio or strong ISI conditions can lead to the continuous accumulation of errors in subsequent symbols, resulting in a chain of errors or even a layered error structure. Furthermore, DFE has limited ability to suppress upstream ISI; when facing long-memory interference caused by bandwidth roll-off and dispersion, it may still require stronger feedforward support, but increasing the feedforward gain will reintroduce noise amplification. In other words, while DFE can improve some downstream interference, there is an unavoidable contradiction between its performance stability and error propagation.

[0047] When FFE or FFE+DFE (including DFE) fails to effectively control residual ISI, sequence detection becomes an important option for improving performance. A representative method is Maximum Likelihood Sequence Estimation (MLSE), which typically uses the Viterbi algorithm to search for the most likely symbol sequence on a trellis (grid graph). MLSE can explicitly utilize the channel memory structure, and its ability to suppress strong ISI is significantly better than symbol-by-symbol decision-based equalization, thus exhibiting outstanding theoretical performance advantages in bandwidth-constrained links. However, the applicability of MLSE is limited by two key factors: first, the number of states in a trellis expands exponentially with the effective memory length; the long memory caused by bandwidth constraints leads to a rapid expansion of the state space, resulting in significant computational and storage overhead; second, MLSE is sensitive to channel model matching and parameter estimation accuracy; model mismatch caused by link drift, device nonlinearity, and quantization effects weakens its sequence detection gain. More importantly, traditional MLSEs often output hard decision symbols or bits, making it difficult to form soft information concatenation with modern soft decision error correction codes (such as LDPC (Low-Density Parity-Check) codes), thus limiting the release of gain in subsequent decoding stages.

[0048] To adapt to soft-decision forward error correction (SD-FEC) such as LDPC, some technical solutions propose simplified soft-output MLSE for bandwidth-constrained scenarios. These solutions mainly focus on improving the quality and performance of the MLSE→FEC soft interface. Overall, they still closely resemble the serial structure where the detector outputs soft information and the decoder consumes soft information. Therefore, coding constraints are difficult to systematically utilize during the detection phase.

[0049] Based on the above discussion, existing technologies concerning strong ISI suppression and soft information generation can be summarized into the following categories: 1. Linear / Nonlinear Equalization (FFE / DFE) and Error Propagation Suppression: Many receivers use FFE or FFE+DFE to combat bandwidth-limited ISI; In response to the DFE error propagation / burst error problem, existing patents have proposed introducing modules such as maximum likelihood sequence detection / error detection and correction after DFE to locate and repair suspected burst errors.

[0050] 2. MLSE / MLSD Sequence Detection and Its Complexity Reduction Implementation: To further improve the sequence recovery performance under strong ISI conditions, the published scheme uses Viterbi / MLSD to perform sequence search on trellis, but the number of states increases exponentially with the memory length; therefore, receiver schemes that reduce complexity by means of pseudo-partial response, MLSD, or state reduction / block parallelism have emerged.

[0051] 3. Soft output MLSE and SD-FEC soft interface: In order to adapt to soft decision decoding such as LDPC, existing patents have proposed to output soft decision values ​​in the MLSE module and feed them into the subsequent FEC to improve error correction performance, and it is clear that it can be used in optical communication receiving scenarios; in addition, there are also implementation schemes for soft output Viterbi (SOVA) sliding window decoding / soft information generation.

[0052] However, the aforementioned prior art has at least the following technical drawbacks in IM / DD PAM links with strong ISI bandwidth limitations: 1. Because FFE is essentially an inverse filter, when there is a significant bandwidth roll-off or null in the link, FFE often requires a large gain to suppress ISI, thereby amplifying the noise and quantization error on the attenuated frequency band, resulting in increased noise and causing the residual ISI and noise to compress the decision margin together; therefore, even if the subsequent stage is equipped with SD-FEC, the input LLR may still have bias or insufficient reliability, and the error correction gain is difficult to fully release.

[0053] 2. Because DFE relies on hard decision feedback to offset downstream ISI, once a misjudgment occurs under strong ISI or low SNR conditions, the error will continue to accumulate through feedback and propagate to subsequent symbols, forming burst errors or error planes. Therefore, there is an inherent contradiction between performance and stability in DFE, and its robust suppression capability against long memory ISI is still limited.

[0054] 3. Because the number of states in traditional MLSE / Viterbi on trellis increases exponentially with the length of effective memory, the long memory caused by bandwidth limitations will bring unacceptable computation and storage overhead. At the same time, traditional implementations often output hard decisions or lack high-quality soft information interfaces. Therefore, it is difficult to form efficient collaboration with SD-FEC such as LDPC under the premise of controllable engineering complexity.

[0055] 4. Because existing sMLSE schemes mainly focus on reducing MLSE complexity and improving the soft interface of MLSE->FEC, most public implementations still adopt a serial cascaded structure: after the detector generates an LLR once, the decoder independently iterates and decodes it. The soft information generated by the decoder is usually not fed back in the form of external information and participates in the next round of trellis path competition (or only performs weak coupling processing such as LLR scaling / truncation); therefore, the coding constraints cannot play a role in the detection stage, and the path aliasing caused by residual ISI is difficult to be effectively suppressed by the decoding soft constraints, and the statistical consistency of soft information and the sustainability of iterative gain are limited.

[0056] Therefore, how to achieve coordinated optimization of sequence detection and soft decision decoding under strong ISI conditions, and fully exploit the gain of soft information in the sequence detection-decoding link, has become a key issue for improving the achievable net rate and robustness of high-speed IM / DD PAM short-range interconnect receivers. It is urgent to propose a coordinated reception processing method that can take into account the statistical consistency and stability of soft information under the premise of controllable engineering complexity.

[0057] To address the aforementioned technical problems, this application discloses a sequence detection decoding method, apparatus, device, and storage medium. This application enables the coordinated optimization of sequence detection and soft-decision decoding in strong ISI scenarios with engineering-achievable complexity. Specifically, by constructing an external information closed-loop iteration between sMLSE soft output sequence detection and SD-FEC (such as LDPC) soft-decision decoding at the receiver, the external information generated by the decoder is extracted as a priori and embedded into the branch metric / path metric update of sMLSE, thus coupling the error correction code verification constraint and the channel memory constraint within the same iterative framework. Furthermore, by combining memory compression preprocessing (such as FFE) with low-complexity trellis implementation, soft information quantization, and damping / termination criteria, the reliability and convergence stability of LLR are improved, thereby effectively reducing the bit error rate and improving receiver sensitivity or threshold performance without significantly increasing hardware costs.

[0058] See Figure 1 The above is a schematic flowchart of a sequence detection and decoding method provided in an embodiment of this application. The method includes the following steps: S101. The initial discrete sequence is preprocessed to obtain the target discrete sequence; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range.

[0059] The sequence detection and decoding method described in this application is executed by the receiving end of the communication. The receiving end first needs to acquire the preprocessed initial discrete sequence after photoelectric detection and sampling. In strong ISI scenarios caused by bandwidth constraints, the equivalent discrete model with finite memory can be used to characterize it as follows: (1) in, To transmit PAM (Pulse Amplitude Modulation) symbols, k is the sampling point index, used to represent the k-th sampling point. For the equivalent discrete channel impulse response taps, L is the effective memory length, and l is the tap index used to represent the l-th tap. This is the noise term.

[0060] To reduce the processing complexity of the sMLSE sequence detector, this application performs linear pre-equalization on the initial discrete sequence before entering iterative detection and decoding, so that the effective memory length of the residual ISI converges from a longer tail to a shorter range. This application refers to the shorter range as the predetermined range, which can be set according to the actual situation, such as 2–3. That is, the target discrete sequence obtained by preprocessing the initial discrete sequence has 2–3 symbol memories.

[0061] In another embodiment of this application, preprocessing the initial discrete sequence to obtain the target discrete sequence includes: preprocessing the initial discrete sequence using a feedforward equalizer to converge the effective memory length of the initial discrete sequence to a predetermined range, thereby obtaining a preprocessed sequence; and whitening the preprocessed sequence using a noise whitening filter to obtain the target discrete sequence.

[0062] In this application, when preprocessing the initial discrete sequence, a feedforward equalizer (FFE) can be used to converge the effective ISI memory length of the initial discrete sequence to a predetermined range, resulting in a preprocessed sequence. This step improves the input conditions for subsequent sMLSE sequence detector detection, effectively reducing the complexity of the sMLSE sequence detector. Furthermore, considering that FFE can cause colored noise enhancement, this application extends a single FFE to FFE + a simplified PF (Prefilter) or other linear filter combinations to further shorten the effective ISI memory length and improve soft information consistency. Specifically, the PF can be a noise whitening filter, used to whiten the noise in the preprocessed sequence. The response of this noise whitening filter is... ;in, This represents the tap coefficients of the filter. It represents a delay of one unit of time.

[0063] It should be noted that after FFE processing, the noise often becomes colored noise (which is correlated). Therefore, this application uses a noise whitening filter to make the output noise no longer correlated between different time points (i.e., whitened). This method can avoid problems such as measurement calculation errors and increased bit error rate that occur when directly sending colored noise into the sMLSE sequence detector. Through this method, convergence performance and stability can be optimized under different link conditions.

[0064] S102. Input the target discrete sequence into the sMLSE sequence detector, and perform an iterative detection and decoding process through the sMLSE sequence detector and the soft decision decoder.

[0065] Each iteration process is as follows: using the sMLSE sequence detector and the soft decision decoder to generate the external information generated in the previous iteration, the bit-level soft information of the current iteration is generated; using the soft decision decoder and the soft information of the current iteration, the external information of the current iteration is generated, and the next iteration process continues. S103. After the iteration is completed, obtain the decoding result output by the soft decision decoder.

[0066] It should be noted that this application proposes an ISI equalization scheme based on soft information iteration. This scheme constructs an extrinsic information iteration process for the MLSE sequence detector and soft decision decoder at the receiver. Each iteration is a detection and decoding process. The process of each iteration is as follows: the bit-level soft information output by the sMLSE sequence detector is fed into the soft decision decoder. The extrinsic information generated by the soft decision decoder is then fed back to the sMLSE sequence detector as a priori constraint to participate in the next round of trellis detection. This gradually enhances the ability to distinguish correct symbol sequences and improves decoding performance under strong ISI conditions. The soft decision decoder (SD-FEC) can be an LDPC decoder.

[0067] In another embodiment of this application, the process of generating bit-level soft information for the current iteration using the sMLSE sequence detector and the soft-decision decoder based on the extrinsic information generated in the previous iteration specifically includes: generating a first posterior log-likelihood ratio using the sMLSE sequence detector and the first prior log-likelihood ratio; wherein, the first prior log-likelihood ratio is generated by interleaving the extrinsic information generated by the soft-decision decoder in the previous iteration; subtracting the first posterior log-likelihood ratio from the first prior log-likelihood ratio to generate the bit-level soft information for the current iteration; accordingly The process of generating extrinsic information for the current iteration using the soft decision decoder and the soft information of the current iteration specifically includes: deinterleaving the soft information and sending it as the second prior log-likelihood ratio to the soft decision decoder; using the second prior log-likelihood ratio for internal iterative decoding to generate the second posterior log-likelihood ratio; subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio to generate the extrinsic information for the current iteration; and interleaving the extrinsic information of the current iteration as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration.

[0068] It should be noted that the target discrete sequence, after being processed by the FFE and noise whitening filter, will be further input into the soft information iterative detection and decoding algorithm proposed in this scheme, which is implemented by an sMLSE sequence detector and a soft decision decoder. Specifically, when inputting the target discrete sequence into the sMLSE sequence detector, since there is no prior log-likelihood ratio (prior LLR), the prior log-likelihood ratio of the sMLSE sequence detector needs to be set to a uniform prior.

[0069] See Figure 2 This document provides a flowchart of an sMLSE-LDPC technology embodiment. The solution mainly includes: FFE, NWF (Noise Whitening Filter), sMLSE (sMLSE sequence detector), Interleaver, Deinterleaver, and LDPC Decoder. The entire processing flow is as follows: The initial discrete sequence is preprocessed using FFE and NWF to converge the effective memory length of ISI to a predetermined range and whiten noise. The processed target discrete sequence then enters... Figure 2 sMLSE in the context of the target discrete sequence; sMLSE utilizes the first prior log-likelihood ratio (... This process generates a first posterior log-likelihood ratio at the bit level. );Will and Subtraction generates bit-level soft information for this iteration. ); After deinterleaving (restoring the original order) using Deinterleaver, the second prior log-likelihood ratio is sent to the soft-decision decoder. Since the content of the second prior log-likelihood ratio and the soft information remain unchanged, only the order has changed, this embodiment also represents the second prior log-likelihood ratio as... , Channel information used as the LDPC Decoder. The LDPC Decoder utilizes the second prior log-likelihood ratio (...). Internal iterative decoding is performed to generate the second posterior log-likelihood ratio ( ). );Will and Subtraction generates external information for this round of iteration. ), will be the basis for this round of iterations After interleaving (re-shuffling the order) using Interleaver, the result is used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration. Similarly, since the content of the extrinsic information in this iteration is the same as the content of the interleaved first prior log-likelihood ratio, only the order is different, this application also expresses the interleaved first prior log-likelihood ratio as... In this way, the sequence detector and the soft-decision decoder iteratively exchange external information.

[0070] It should be noted that, in this application, the implementation algorithm of the sMLSE sequence detector can be Max-log-BCJR (Maximum Logarithm Bahl-Cocke-Jelinek-Raviv algorithm), Log-MAP (Logarithmic Maximum A Posteriori algorithm) / BCJR (Maximum A Posteriori decoding algorithm), SOVA (Soft Output Viterbi Algorithm), or other equivalent soft output sequence detection algorithms, and is not specifically limited here. At the same time, the trellis of the sMLSE sequence detector implementation algorithm can be implemented by using a full-length trellis (a complete trellis containing all state transitions), a sliding window trellis (only retaining a finite length of trellis structure near the current processing time), state pruning / reduction, etc. (simplifying the trellis structure by deleting invalid states or redundant branches with extremely low probabilities in the trellis), or by limiting the value of the effective memory length L (only considering the state transitions corresponding to the L most recent input bits of the encoder) and using different state definition methods to construct an equivalent trellis. The above changes are all equivalent replacements for the implementation path of sequence detection, and can still achieve the core effect of prior constraints participating in path competition.

[0071] In summary, this application provides a receiver-side collaborative soft-output iterative sequence detection and decoding method for strong ISI scenarios. It constructs a closed-loop external information interaction structure between the sMLSE soft-output sequence detector and the SD-FEC soft-decision decoder at the receiver, allowing the information obtained from decoding, beyond the soft constraints, to be fed back to the sequence detection and participate in trellis path competition. This achieves iterative enhancement through "detection—decoding—feedback—re-detection," effectively mitigating ISI caused by system bandwidth limitations.

[0072] In another embodiment of this application, generating a first posterior log-likelihood ratio using the sMLSE sequence detector and the first prior log-likelihood ratio includes: The Viterbi algorithm based on bidirectional recursion calculates the branch metric based on the first prior log-likelihood ratio, and calculates the forward metric and the backward metric based on the branch metric; using the forward metric and the backward metric, the first posterior log-likelihood ratio is determined.

[0073] Specifically, in this embodiment, the sMLSE sequence detector implemented using Max-log-BCJR is used as an example for explanation. The key to this implementation is the Viterbi algorithm based on bidirectional recursion. The process of generating the first posterior log-likelihood ratio by the sMLSE sequence detector is explained here. For ease of explanation, this application will use the PAM-4 format as an example. Let the PAM-4 constellation be... A ={-3, -1, 1, 3}, where q is the number of bits carried by each PAM symbol. In PAM-4, each symbol carries 2 bits, and q is 2.

[0074] For PAM-4 symbols using Gray coding, the first posterior log-likelihood ratio includes the log-likelihood ratio of the most significant bit (MSB) (L1) and the log-likelihood ratio of the least significant bit (LSB) (L2), where L1 can be expressed as Equation (2) and L2 can be expressed as Equation (3): (2) (3) in, To send symbols at time k The log-likelihood ratio of the most significant bit (MSB), To send symbols at time k The log-likelihood ratio of the least significant bit (LSB); The received symbol sequence (target discrete sequence) at time k is Under the condition that the transmitted symbol is The probability, that is: This indicates that the received symbol sequence at time k is Under the condition that the transmitted symbol is The probability of being -3; This indicates that the received symbol sequence at time k is Under the condition that the transmitted symbol is The probability of being -1; This indicates that the received symbol sequence at time k is Under the condition that the transmitted symbol is The probability of being 3; This indicates that the received symbol sequence at time k is Under the condition that the transmitted symbol is The probability is 1.

[0075] Understandably, the key to sMLSE is its implementation based on a bidirectional recursive Viterbi algorithm, see [link / reference]. Figure 3 This is a schematic diagram of bidirectional state transition provided in an embodiment of this application, where the forward metric is defined as... The backward metric is ,in, , , This represents the forward probability of state s at time k, such as... Figure 3 In This indicates that the state at time k-1 is The forward probability, and so on; This represents the backward probability of state s at time k, such as... Figure 3 In This indicates that the state at time k-1 is The backward probability, and so on; Indicates from state Transition to state The branching metric incorporates prior information (first prior log-likelihood ratio). This indicates that at time k, from state Transition to state The transition probability includes prior information (first prior log-likelihood ratio), such as Figure 3 In , indicating that at time k, from state Transition to state The transition probability includes prior information (the first prior log-likelihood ratio), because Figure 3 Other forward probabilities, backward probabilities, and transition probabilities have only some parameters changed, but their overall meaning is the same. Therefore, other parameters of the same type will not be explained separately.

[0076] Among them, trellis state The set of historical symbols corresponding to the representation and memory length L (e.g., composed of the most recent L symbols). Any state transition. Corresponding to a candidate current symbol 'm' is the constellation point index, that is, the current symbol actually transmitted by the sender at time 'k'. , is the constellation set of modulation symbols A The m-th specific symbol value in and its corresponding bit tag , For corresponding symbols The most significant bit, Corresponding symbols The least significant bit. Therefore It can be calculated using the following formula under the Max-log criterion: (4) As can be seen from formula (4), when the received sequence is Under the condition that the transmitted symbol is The logarithmic probability is equal to the probability of all pairs of pairs at time k. In the relevant state s, its forward metric and backward metric The maximum value of the sum. and It can be calculated using the Viterbi algorithm, as follows: (5) As can be seen from formula (5), in calculating the forward metric... When this happens, it is necessary to check all previous states s′ that can reach state s; and take the forward metric of the previous state s′. In addition, the branch metric for transitioning from state s′ to state s This yields the sum corresponding to each previous state s′. From all possible s′, the maximum sum is selected as the forward metric for the current state s. Similarly, in calculating the backward metric... At this point, it is necessary to examine all possible next-time states s that can be reached from state s′; and then take the backward metric of the next-time state s. Add the branch metric for transitioning from state s′ to state s This yields the sum for each state s. From all possible s, the maximum sum is selected as the backward metric for the previous state s′. .

[0077] It can be seen that for PAM-4, the four branches are merged into one state, and... Choose the one with the highest probability. It is calculated through the same process in reverse recursion. Indicates from state Transition to state The branch metric, which incorporates prior information, is calculated using the following formula: (6) in, This indicates a symbolic pattern containing ISI, used to represent the prediction from the state. Transition to state The received signal value containing ISI; q is the number of bits carried by each PAM symbol, which is determined according to the number of constellation points. For example, q is 2 in PAM-4 and 3 in PAM-8. The value of q is different when applied to different formats of pulse amplitude modulation; j represents the bit index, indicating the j-th bit. This represents the value of the j-th bit corresponding to the m-th constellation point. This represents the j-th bit at time k. Represents the bits obtained from the output of the interleaving decoder. The first prior log-likelihood ratio is generated by the soft-decision decoder after interleaving the extrinsic information generated in the previous iteration.

[0078] In summary, this application utilizes the bidirectional Viterbi algorithm to determine the branch metric based on the first prior log-likelihood ratio generated after interleaving the extrinsic information generated by the soft-decision decoder in the previous iteration. Then, it calculates the bit-level first posterior log-likelihood ratio with the forward and backward metrics to obtain the soft information. In this way, the soft information output by sMLSE can be directly and naturally matched with soft-decision decoders such as LDPC, avoiding additional data format conversion.

[0079] This application proposes a prior soft information embedding mechanism for sMLSE path contention. The prior soft information output by SD-FEC is directly embedded into the sMLSE trellis branch metric or equivalent path metric update expression in the form of a first prior log-likelihood ratio or equivalent probability term. This allows the coding constraints to take effect during the path contention stage, generating bit-level extrinsic information (LLR) output for use by soft decision decoders such as LDPC in iterations. The bit-level soft information output by sMLSE can directly and naturally match with soft decision decoders such as LDPC, avoiding additional data format conversions. Furthermore, compared to interface methods that only perform post-hoc corrections to detection results or only scale / truncate LLR, this mechanism enhances the ability to suppress path aliasing caused by residual ISI and improves the reliability of soft information and the stability of iteration gain.

[0080] In another embodiment of this application, after the iteration ends, obtaining the decoding result output by the soft decision decoder includes: determining whether the number of iterations in the detection decoding process has reached a predetermined number of iterations; if so, determining that the iteration has ended, and making a final decision based on the second posterior log-likelihood ratio obtained by the soft decision decoder in the last iteration process to generate the decoding result.

[0081] In this application, during the iterative execution of the above-described detection and decoding process, the termination of the iteration can be determined based on the total number of iterations. Specifically, if the number of iterations in the detection and decoding process reaches a predetermined number, the iteration is considered complete, and a final decision is made based on the second posterior log-likelihood ratio obtained by the soft-decision decoder in the last iteration, generating the decoding result. If the number of iterations in the detection and decoding process does not reach the predetermined number, the next iteration process continues. Furthermore, in addition to employing a fixed outer iteration count strategy, this application can also employ an adaptive termination strategy, such as determining whether the performance reaches a threshold. If the threshold is reached, the iteration stops, and this performance indicator can be the bit error rate.

[0082] In another embodiment of this application, after subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio to generate the extrinsic information for the current iteration, the method further includes: performing an adjustment operation on the extrinsic information for the current iteration, and interleaving the adjusted extrinsic information as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration; wherein the adjustment operation includes any one of the following: extrinsic information scaling operation, extrinsic information truncation operation, and extrinsic information normalization calibration operation.

[0083] Specifically, this application allows for modifications to the construction and scheduling of external information without altering the closed-loop constraints of the detection end outputting soft information and the decoding end feeding back external information as prior information for the next round of detection. After performing adjustments on the external information and interleaving it, it becomes the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration. This approach generates a more reliable prior log-likelihood ratio, improving system performance. The adjustments can include external information scaling, external information damping, external information truncation, external information saturation, external information normalization calibration, and so on.

[0084] In summary, this application provides an engineering implementation suitable for strong ISI long memory scenarios. sMLSE can adopt a low-complexity trellis implementation strategy (including window-limited / segmented trellis, etc.), combined with soft information fixed-point quantization and metric normalization / saturation processing. At the same time, it introduces external information weighting / damping and iteration stopping criteria between detection and decoding, thereby achieving a practical closed-loop iterative detection and decoding without introducing the large-scale storage and computational overhead required for long memory ISI.

[0085] To illustrate the effectiveness of this solution, a 92Gband (gigabaud) IMDD PAM4 experimental system was used to verify its superiority. First, the tap coefficients of the 2-tap noise whitening filter were optimized; see [link to relevant documentation]. Figure 4 This is a schematic diagram illustrating the relationship between bit error rate performance and tap coefficients in pre-filtering, provided in an embodiment of this application. Figure 4 The figure describes the measured LDPC output bit error rate (BER) performance and its relationship with the tap coefficient α in the pre-filtering (PF). I=1 in the figure represents the non-iterative case, i.e., a simple cascade of sMLSE and LDPC decoding without any outer iterations. It can be observed that the optimal BER performance is achieved when α=0.6, regardless of whether I=1 or I=3.

[0086] See Figure 5 The diagram illustrates the relationship between bit error rate performance and received optical power, as provided in an embodiment of this application. (See attached image.) Figure 6 This is another schematic diagram illustrating the relationship between bit error rate performance and received optical power provided in an embodiment of this application.Figure 5 and Figure 6 This demonstrates the relationship between received optical power (ROP) and different external sMLSE–LDPC iteration numbers. Figure 5 This demonstrates the case where the internal LDPC decoder iterations are fixed at 1. Figure 6 This demonstrates the case where the internal LDPC decoder iterations are fixed at 5. Figure 5 In this context, since the LDPC decoder only performs one internal iteration, introducing an outer iteration (I>1) already brings a significant performance improvement compared to the non-iterative case. However, this improvement gradually saturates, reaching its optimal state after several outer iterations. Figure 6 In this design, the number of iterations of the internal LDPC decoder is increased to 5, which significantly improves the prior information fed back to sMLSE, thereby increasing the performance ceiling of the outer iteration. Under the KP4-FEC (KP4 forward error correction coding) threshold, when using the outer hard decision, the case of 4 outer sMLSE-LDPC iterations achieves an improvement of more than 2dB in received power sensitivity (RPS) compared to the non-iterative case (I=1), while the pure FFE scheme cannot even achieve this bit error rate level.

[0087] As can be seen from the above, this application addresses the reception performance bottleneck caused by strong ISI in existing bandwidth-constrained IM / DD optical links. Existing FFE / DFE exhibits significant residual ISI under strong memory effects, making it difficult for traditional MLSE to effectively coordinate with soft decision error correction codes. Furthermore, while MAP equalization based on BCJR can output soft information, it carries a large computational burden. Existing cascaded schemes of sMLSE and SD-FEC (such as LDPC) mostly rely on a cascaded structure where the detection end outputs an LLR once and the decoding end decodes once. This fails to fully utilize the soft information generated by the decoder to reconstrain sequence detection, preventing coding constraints from playing a role in the detection stage. Consequently, in severely bandwidth-constrained scenarios, the error correction gain is insufficient, and performance improvement is limited.

[0088] To address this, this invention proposes an sMLSE–LDPC extrinsic information iterative reception scheme: Before iteration, the receiver can preprocess the equivalent channel using FFE to compress the effective memory length of residual ISI to a shorter range (e.g., 2–3 symbol memories). Subsequently, sMLSE based on Max-log-BCJR is used to generate bit-level soft information, and the LDPC decoding output is extracted and fed back as the a priori constraint of sMLSE, so that the channel memory constraint (trellis sequence constraint) and error correction code verification constraint are iteratively coupled in a unified closed loop. In each iteration, the extrinsic information output by the decoder is no longer only used for the final decision, but directly participates in the next round of trellis branch metric / path competition, thereby gradually strengthening the preference for the correct symbol sequence and suppressing residual ISI, achieving more full utilization of soft information and more effective joint detection decoding compared to unidirectional serial sMLSE cascaded LDPC.

[0089] The technical effects or advantages of this solution include the following: 1) Through the closed-loop mechanism of external information extraction and feedback of prior constraints, the coding constraints of LDPC can play a role in the sequence detection stage, breaking through the limitation of traditional cascade structures that only use LLR once, thus releasing the net coding gain of SD-FEC more fully under strong ISI conditions.

[0090] 2) Trellis-based sMLSE can explicitly utilize the channel memory structure and combine decoding priors to apply soft constraints on path contention, which can more effectively suppress long-tail ISI caused by bandwidth limitations and improve receiver robustness and bit error rate performance.

[0091] 3) Introducing FFE memory shortening before iteration can compress the effective channel memory to a shorter range (such as 2–3), providing more controllable equivalent channel conditions for subsequent sequence detection and iterative processing, which is beneficial for engineering deployment and parameter configuration.

[0092] 4) The scheme is applicable to multi-order PAM such as PAM-4 / 8 and can be extended to higher-order modulation and different link conditions; the external information iteration framework is decoupled from the modulation order and code rate selection, which is convenient for reuse under different system indicators.

[0093] 5) In scenarios where severe bandwidth limitation or increased transmission distance leads to aggravated ISI, it can significantly improve the reception threshold performance and transmission reliability, reduce the dependence on single linear equalization capability, and better meet the application requirements of high-speed IM / DD optical interconnect.

[0094] The sequence detection decoding apparatus provided in the embodiments of this application is described below. The sequence detection decoding apparatus described below can be referred to in correspondence with the sequence detection decoding method described above.

[0095] See Figure 7, Figure 7 This application provides a schematic diagram of a sequence detection decoding device, which specifically includes: Preprocessing module 11 is used to preprocess the initial discrete sequence to obtain the target discrete sequence, and input the target discrete sequence into the sMLSE sequence detector; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range; The detection and decoding module 12 is used to perform an iterative detection and decoding process using the sMLSE sequence detector and the soft decision decoder. After the iteration is completed, the decoding result output by the soft decision decoder is obtained. Each iteration process is as follows: using the sMLSE sequence detector and the external information generated by the soft decision decoder in the previous iteration, bit-level soft information for the current iteration is generated; using the soft decision decoder and the soft information for the current iteration, external information for the current iteration is generated, and the next iteration process continues.

[0096] As an optional embodiment, the detection decoding module includes: The first determining unit is used to generate a first posterior log-likelihood ratio using the sMLSE sequence detector and the first prior log-likelihood ratio; wherein the first prior log-likelihood ratio is generated by the soft decision decoder after interleaving the extrinsic information generated in the previous iteration. The soft information generation unit is used to subtract the first posterior log-likelihood ratio from the first prior log-likelihood ratio to generate bit-level soft information for the current iteration.

[0097] As an optional embodiment, the first determining unit is specifically used for: The Viterbi algorithm based on bidirectional recursion calculates the branch metric based on the first prior log-likelihood ratio, and calculates the forward metric and the backward metric based on the branch metric; using the forward metric and the backward metric, the first posterior log-likelihood ratio is determined.

[0098] As an optional embodiment, the detection decoding module includes: The second determining unit is used to deinterleave the soft information and send it as a second prior log-likelihood ratio to the soft decision decoder. The soft decision decoder uses the second prior log-likelihood ratio to perform internal iterative decoding to generate a second posterior log-likelihood ratio. The extrinsic information generation unit is used to subtract the second posterior log-likelihood ratio from the second prior log-likelihood ratio to generate extrinsic information for the current iteration. The extrinsic information for the current iteration is interleaved and used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration.

[0099] As an optional embodiment, the detection decoding module includes: The judgment unit is used to determine whether the number of iterations in the decoding process has reached the predetermined number of iterations; if so, it determines that the iteration has ended and triggers the decoding result generation unit. The decoding result generation unit is used to make a final decision based on the second posterior log-likelihood ratio obtained by the soft-decision decoder in the last iteration process, and generate the decoding result.

[0100] As an optional embodiment, the device further includes: The extrinsic information adjustment module is used to perform adjustment operations on the extrinsic information of the current iteration, and interleave the adjusted extrinsic information as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration; wherein, the adjustment operation includes any one of the following: extrinsic information scaling operation, extrinsic information truncation operation, and extrinsic information normalization calibration operation.

[0101] As an optional embodiment, the preprocessing module includes: The first processing unit is used to preprocess the initial discrete sequence through a feedforward equalizer to converge the effective memory length of the initial discrete sequence to a predetermined range, thereby obtaining a preprocessed sequence. The second processing unit is used to whiten the preprocessed sequence with noise using a noise whitening filter to obtain the target discrete sequence.

[0102] Figure 8 A structural diagram of an electronic device provided in an embodiment of the present invention is shown in the figure, comprising: Memory 20 is used to store computer programs; The processor 21 is configured to implement the steps of the sequence detection decoding method as described in the above embodiments when executing a computer program.

[0103] The electronic devices provided in this embodiment may include, but are not limited to, smartphones, tablets, laptops, or desktop computers.

[0104] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0105] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the sequence detection decoding method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc.

[0106] In some embodiments, the electronic device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0107] Those skilled in the art will understand that Figure 8 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0108] In another exemplary embodiment, a computer storage medium is also provided, wherein the program instructions, when executed by a processor, implement the steps of the data deduplication method described in any of the above method embodiments.

[0109] It is understood that if the sequence detection decoding method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0110] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” used herein may also mean the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a specific order described or illustrated, unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0111] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0112] The above are only some embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A sequence detection decoding method, characterized in that, include: The initial discrete sequence is preprocessed to obtain the target discrete sequence; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range. The target discrete sequence is input into the sMLSE sequence detector, and an iterative detection and decoding process is performed through the sMLSE sequence detector and the soft decision decoder. Each iteration process is as follows: using the sMLSE sequence detector and the soft decision decoder to generate the external information generated in the previous iteration, the bit-level soft information of the current iteration is generated; using the soft decision decoder and the soft information of the current iteration, the external information of the current iteration is generated, and the next iteration process continues. After the iteration is completed, the decoding result output by the soft decision decoder is obtained.

2. The sequence detection decoding method according to claim 1, characterized in that, The sMLSE sequence detector and the soft decision decoder generate bit-level soft information for the current iteration using the extrinsic information generated in the previous iteration, including: A first posterior log-likelihood ratio is generated using the sMLSE sequence detector and the first prior log-likelihood ratio; wherein, the first prior log-likelihood ratio is generated by interleaving the extrinsic information generated by the soft-decision decoder in the previous iteration. Subtracting the first posterior log-likelihood ratio from the first prior log-likelihood ratio generates bit-level soft information for this iteration.

3. The sequence detection decoding method according to claim 2, characterized in that, Generating a first posterior log-likelihood ratio using the sMLSE sequence detector and the first prior log-likelihood ratio includes: The Viterbi algorithm based on bidirectional recursion calculates the branch metric based on the first prior log-likelihood ratio, and calculates the forward metric and the backward metric based on the branch metric; using the forward metric and the backward metric, the first posterior log-likelihood ratio is determined.

4. The sequence detection decoding method according to claim 2, characterized in that, The external information generated for this iteration, through the soft-decision decoder and the soft information of this iteration, includes: After the soft information is deinterleaved, it is sent to the soft decision decoder as the second prior log-likelihood ratio. The soft decision decoder uses the second prior log-likelihood ratio to perform internal iterative decoding to generate the second posterior log-likelihood ratio. Subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio generates extrinsic information for the current iteration. This extrinsic information is then interleaved and used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration.

5. The sequence detection decoding method according to claim 4, characterized in that, After the iteration is complete, the decoding result output by the soft-decision decoder is obtained as follows: Determine whether the number of iterations in the decoding process has reached the predetermined number of iterations; If so, the iteration is determined to be over, and a final decision is made based on the second posterior log-likelihood ratio obtained by the soft-decision decoder in the last iteration process, generating the decoding result.

6. The sequence detection decoding method according to claim 4, characterized in that, After subtracting the second posterior log-likelihood ratio from the second prior log-likelihood ratio to generate the extrinsic information for this iteration, the process also includes: An adjustment operation is performed on the extrinsic information of the current iteration, and the adjusted extrinsic information is interleaved and used as the first prior log-likelihood ratio input to the sMLSE sequence detector in the next iteration; wherein, the adjustment operation includes any one of the following: extrinsic information scaling operation, extrinsic information truncation operation, and extrinsic information normalization calibration operation.

7. The sequence detection decoding method according to any one of claims 1 to 6, characterized in that, The initial discrete sequence is preprocessed to obtain the target discrete sequence, which includes: The initial discrete sequence is preprocessed by a feedforward equalizer to bring the effective memory length of the ISI of the initial discrete sequence to a predetermined range, thus obtaining a preprocessed sequence. The preprocessed sequence is noise-whitened using a noise whitening filter to obtain the target discrete sequence.

8. A sequence detection decoding device, characterized in that, include: The preprocessing module is used to preprocess the initial discrete sequence to obtain the target discrete sequence, and input the target discrete sequence into the sMLSE sequence detector; wherein the effective memory length of the ISI of the target discrete sequence has converged to a predetermined range; The detection and decoding module is used to perform an iterative detection and decoding process using the sMLSE sequence detector and the soft decision decoder. After the iteration is completed, the decoding result output by the soft decision decoder is obtained. Each iteration process is as follows: using the sMLSE sequence detector and the external information generated by the soft decision decoder in the previous iteration, bit-level soft information for the current iteration is generated; using the soft decision decoder and the soft information for the current iteration, external information for the current iteration is generated, and the next iteration process continues.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the sequence detection decoding method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the sequence detection decoding method as described in any one of claims 1 to 7.

Images