A source follower for an infrared focal plane readout circuit and a readout method thereof
By introducing a pre-charge switch and a nanoampere-level auxiliary constant current source into the infrared focal plane readout circuit, the high static power consumption and IR drop problems of traditional source followers are solved, enabling high-speed signal swing and steady-state signal establishment, thereby improving image quality and frame rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2026-03-18
- Publication Date
- 2026-06-23
AI Technical Summary
In traditional infrared focal plane readout circuits, source followers suffer from high static power consumption, severe IR drop effect, and a contradiction between setup time and power consumption, resulting in uneven image brightness and limited frame rate.
A novel source follower structure is adopted, which uses signal control to control the conduction timing of the precharge switch and the gating switch transistor, enabling it to operate in three stages: precharge, dynamic discharge, and steady-state following. A nanoampere-level auxiliary constant current source is introduced to control the leakage current of the input transistor to achieve a fixed signal setup time.
Achieving high-speed signal oscillation with zero static bias power consumption eliminates the IR drop effect, improves signal integrity, and reduces static power consumption, resolving the contradictions of traditional source followers and achieving extremely fast signal establishment.
Smart Images
Figure CN122269159A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a source follower for an infrared focal plane readout circuit and a readout method thereof. Background Technology
[0002] In traditional infrared focal plane array readout circuits, the pixel output voltage is typically read out to the column lines via a source follower. To drive the column lines with large parasitic capacitances, traditional source followers usually require a large constant bias current source (typically in the microamplitude range) at the column level. Existing technologies suffer from the following significant drawbacks: 1. High static power consumption: In large-scale pixel arrays, the constant high current across thousands of columns leads to extremely high overall chip static power consumption. 2. Severe IR drop: Large column currents on long column lines generate a significant parasitic resistance voltage drop, causing inconsistent pixel readout levels at the top and bottom of the array, resulting in brightness gradients or fixed-pattern noise in the image. 3. A trade-off between setup time and power consumption: Simply reducing the bias current to lower power consumption and IR drop weakens the source follower's ability to charge and discharge column capacitors, significantly increasing setup time and limiting the maximum frame rate. Summary of the Invention
[0003] In view of the above problems, this application proposes a source follower for an infrared focal plane readout circuit and a readout method thereof to overcome the shortcomings of the prior art.
[0004] In a first aspect, embodiments of this application provide a source follower for an infrared focal plane readout circuit, comprising: The input transistor has its gate connected to the output voltage signal of the infrared focal plane pixel, and its drain grounded. A gating switch transistor, the drain of which is electrically connected to the source of the input transistor, the source of which is electrically connected to the output node, and the gate of which is connected to the inverted signal of the row gating control signal; The source of the precharge switch is electrically connected to a high-level power supply, the drain of the precharge switch is electrically connected to the output node, and the gate of the precharge switch is connected to the inverted signal of the precharge clock signal. An auxiliary constant current source is connected in parallel across the precharge switch. The input terminal of the auxiliary constant current source is electrically connected to the high-level power supply, and the output terminal of the auxiliary constant current source is electrically connected to the output node. The input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors; the output node outputs the analog voltage corresponding to the pixel. The output current of the auxiliary constant current source is in the nanoampere range.
[0005] Optionally, when the precharge switch is closed, the gating switch transistor is turned off, and the voltage of the output node is clamped to the voltage generated by the high-level power supply; When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor operates in the strong inversion saturation region and generates a discharge current. This discharge current rapidly discharges the charge on the column line load capacitor to ground through the input transistor. When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the steady-state follower stage after the dynamic discharge stage. During the steady-state follower stage, the input transistor operates in the weak inversion region or the medium inversion region, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source. During the steady-state following phase, the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source, and the transconductance of the input transistor is a defined non-zero lower limit value, so that the signal setup time constant of the output node is a fixed and controllable value.
[0006] Optionally, the precharge switch is controlled by the inverted signal of the precharge clock signal; the precharge switch is closed during the high level of the precharge clock signal and open during the low level of the precharge clock signal. The gating switch transistor is controlled by the inverted signal of the row gating control signal. During the high level of the row gating control signal, the gating switch transistor is closed, and during the low level of the row gating control signal, the gating switch transistor is open. The precharge clock signal and the row selection control signal are two signals that do not overlap.
[0007] Secondly, embodiments of this application provide another source follower for an infrared focal plane readout circuit, comprising: The input transistor has its gate connected to the output voltage signal of the infrared focal plane pixel, and its drain is electrically connected to a high-level power supply. A gating switch transistor, the drain of which is electrically connected to the source of the input transistor, the source of which is electrically connected to the output node, and the gate of which is connected to a row gating control signal; A precharge switch with its source grounded, the drain of the precharge switch electrically connected to the output node, and the gate of the precharge switch connected to a precharge clock signal; An auxiliary constant current source is connected in parallel across the precharge switch. The input terminal of the auxiliary constant current source is electrically connected to the output node, and the output terminal of the auxiliary constant current source is grounded. The input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors; the output node outputs the analog voltage corresponding to the pixel. The output current of the auxiliary constant current source is in the nanoampere range.
[0008] Optionally, when the precharge switch is closed, the gating switch transistor is turned off, and the voltage of the output node is clamped to ground voltage; When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor operates in the strong inversion saturation region and generates a charging current. This charging current charges the column line load capacitor rapidly through the input transistor. When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the steady-state follower stage after the dynamic discharge stage. During the steady-state follower stage, the input transistor operates in the weak inversion region or the medium inversion region, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source. During the steady-state following phase, the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source, and the transconductance of the input transistor is a defined non-zero lower limit value, so that the signal setup time constant of the output node is a fixed and controllable value.
[0009] Optionally, the precharge switch is controlled by the precharge clock signal; during a high level of the precharge clock signal, the precharge switch is closed, and during a low level of the precharge clock signal, the precharge switch is open. The gating switch transistor is controlled by the row gating control signal. During the high level of the row gating control signal, the gating switch transistor is closed, and during the low level of the row gating control signal, the gating switch transistor is pre-opened. The precharge clock signal and the row selection control signal are two signals that do not overlap.
[0010] Thirdly, embodiments of this application provide a readout method, which is applied to the source follower described in any of the first aspects, or to the source follower described in any of the second aspects, the readout method comprising: Within one cycle, the precharge switch is first closed and the gating switch transistor is turned off for a first preset time. The source follower is in the precharge phase. During the precharge phase, if the input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors, the voltage of the output node is clamped to the voltage generated by the high-level power supply. If the input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors, the voltage of the output node is clamped to the ground voltage. After a first preset time, the precharge switch is turned off and the gating switch transistor is turned on. The source follower is in a dynamic discharge phase. During the dynamic discharge phase, if the input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors, the input transistor generates a discharge current. If the input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors, the input transistor generates a charging current. With the precharge switch open and the selector switch transistor on, as the voltage of the output node decreases or increases, the discharge current or the charging current gradually decreases until the leakage current of the input transistor and the current of the auxiliary constant current source reach a dynamic balance. The dynamic discharge stage ends, the source follower is in the steady-state following stage, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source.
[0011] Optionally, the source follower is in a dynamic discharge phase, the input transistor operates in a strong inversion saturation region, and the resulting discharge current or charging current satisfies the following equation based on the square-law characteristic of a long-channel transistor:
[0012] In the above formula, I D The discharge current or the charging current is represented by μ, where μ represents mobility and C is the charge current. ox The transistor's capacitance per unit area is represented by W, where W represents the width of the transistor and L represents its length. Represents the absolute value of the source-gate voltage of a transistor. This represents the absolute value of the transistor threshold voltage, where... Much larger .
[0013] Optionally, the source follower is in a steady-state following phase, and the input transistor operates in the weak inversion region or the moderate inversion region, with its transconductance g m Satisfy the following formula:
[0014] In the above formula, I keep This represents the current value of the auxiliary constant current source, and n represents the subthreshold slope factor. Indicates thermal voltage; The signal setup time constant of the output node is a fixed and controllable value, satisfying the following formula:
[0015] In the above formula, τ settling C represents the signal settling time constant. colThis indicates the capacitance value of the column line load capacitor.
[0016] Optionally, when the source follower is in the steady-state following phase, the output impedance of the output node to the small AC signal satisfies the following formula:
[0017] In the above formula, R out This indicates the output impedance.
[0018] The source follower for an infrared focal plane readout circuit proposed in this application includes: an input transistor whose gate is connected to the output voltage signal of an infrared focal plane pixel and whose drain is grounded; a gating switch transistor whose drain is electrically connected to the source of the input transistor, whose source is electrically connected to the output node, and whose gate is connected to a row gating control signal.
[0019] The source of the precharge switch is electrically connected to the high-level power supply, the drain of the precharge switch is electrically connected to the output node, and the gate of the precharge switch is connected to the precharge clock signal; the auxiliary constant current source is connected in parallel across the two ends of the precharge switch, the input of the auxiliary constant current source is electrically connected to the high-level power supply, and the output of the auxiliary constant current source is electrically connected to the output node.
[0020] The input transistor, gating switch transistor, and precharge switch all use PMOS transistors; alternatively, NMOS transistors can be used. If NMOS transistors are used, the gate of the input transistor is connected to the output voltage signal of the infrared focal plane pixel, and its drain is connected to a high-level power supply. The drain of the gating switch transistor is connected to the source of the input transistor, and its source is connected to the output node. Its gate is connected to the horizontal gating control signal. The source of the precharge switch is grounded, its drain is connected to the output node, and its gate is connected to the precharge clock signal. An auxiliary constant current source is connected in parallel across the precharge switch, with its input connected to the output node and its output grounded.
[0021] Regardless of the NMOS transistor structure used in the source follower, its output node outputs the analog voltage corresponding to the pixel; while the output current of the auxiliary constant current source is in the nanoampere range. The output current of the auxiliary constant current source is much smaller than the large-signal charging and discharging current of the column line load capacitor connected to the circuit's output node.
[0022] Unlike traditional source follower structures, this application creatively proposes a novel source follower structure. By controlling the conduction timing of the pre-charge switch and the gating switch transistors, the source follower operates in three stages. In the initial pre-charge stage, the output node voltage is clamped to either a high-level voltage or ground. Then, in the dynamic discharge stage, combined with the clamped output node voltage, the input transistor operates in the strong inversion saturation region, generating a discharge or charging current to charge or discharge the column-line load capacitor. Thus, with zero static bias power consumption, a large transient current is used to achieve large-amplitude, high-speed signal oscillation, resolving the contradiction that traditional source followers require a large static current to achieve a high slew rate.
[0023] Simultaneously, a nanoampere-level micro-auxiliary current source is introduced, which forces the leakage current of the input transistor to be clamped as the output current of the auxiliary constant current source when the source follower is in steady state. This design forces the input transistor to remain in the weak inversion region or the medium inversion region. Therefore, the transconductance of the input transistor has a definite non-zero lower limit, thereby making the time constant of the source follower proposed in this application change from infinity to a controllable constant at the end of the setup, achieving extremely fast final setup.
[0024] Furthermore, in steady state, the output impedance presented by the output node to small AC signals makes the column line no longer a high-impedance floating node. Any noise charge coupled from neighboring columns... All signals are rapidly discharged through this low-impedance path, significantly improving the signal integrity of the pixel array. The output current of the auxiliary constant current source is only in the nanoampere range, at least two orders of magnitude lower than traditional architectures. Therefore, the ohmic voltage drop approaches the microvolt level, completely eliminating the vertical brightness gradient phenomenon in the image caused by different physical locations. The source follower proposed in this application has broad application prospects and high practicality. Attached Figure Description
[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a structural diagram of a source follower for an infrared focal plane readout circuit according to an embodiment of this application; Figure 2 This is a structural diagram of another source follower for an infrared focal plane readout circuit according to an embodiment of this application; Figure 3 This is a timing diagram illustrating the operation of a source follower for an infrared focal plane readout circuit, as exemplified in the embodiments of this application. Detailed Implementation
[0026] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0027] In infrared focal plane array readout circuits, pixel arrays are typically arranged in a row-column matrix. When a pixel in a row is selected for readout, the charge generated by photoelectric conversion within the pixel is converted into an analog voltage signal. The inventors discovered that in order to transmit this signal losslessly to the readout circuitry (such as an analog-to-digital converter) outside the column array, a buffer amplifier, i.e., a source follower, must be placed inside the pixel. The source follower needs to drive a column line that runs through the entire pixel array, carrying a large amount of parasitic capacitance (typically in the picofarad pF range) and parasitic resistance.
[0028] The traditional approach to solving the above problems is a constant current source bias source follower. In this architecture, the gate of the input transistor is connected to the output node of the pixel, the source is connected to the column line, and a constant current source is configured on the column line to provide static bias current. Further research by the inventors revealed that the traditional structure has the following two problems: 1. Extremely high static power consumption: Due to the extremely large parasitic capacitance of the column lines, in order for high frame rate sensors to complete signal establishment in a short time (meeting the slew rate SR requirement), a large constant bias current must be set, which is usually a few microamps to tens of microamps. In large-scale arrays with thousands of columns, this continuous static current will cause the overall power consumption of the chip to soar, leading to serious heat generation problems.
[0029] 2. Severe IR Drop (voltage drop) effect leads to brightness gradients in the image: Because column lines not only have large capacitance but also significant parasitic metallic resistance, when a pixel at the bottom of the array is selected, the readout current needs to flow through the entire column line, generating a huge ohmic voltage drop; while the voltage drop is minimal for pixels at the top of the array. Due to the large constant bias current, this difference in voltage drop caused by physical location results in a noticeable uneven brightness in the sensor's output image.
[0030] To address the aforementioned problems, the inventors, through extensive research, have creatively proposed a source follower for an infrared focal plane readout circuit and its readout method, as described in this application. The technical solution of this application is explained and described in detail below.
[0031] This application discloses a source follower for an infrared focal plane readout circuit, referring to... Figure 1The diagram shows a source follower for an infrared focal plane readout circuit, which includes: an input transistor M1, a gating switch transistor M2, a precharge switch M3, and an auxiliary constant current source I.
[0032] Input transistor M1, whose gate is connected to the output voltage signal V of the infrared focal plane pixel. FD The drain of the selector transistor M2 is grounded; its drain is electrically connected to the source of the input transistor M1, and the source of the selector transistor M2 is connected to the output node V. OUT Electrical connection: The gate of the selection switch transistor M2 is connected to the inverted signal of the row selection control signal. .
[0033] The source of precharge switch M3 is electrically connected to the high-level power supply, and the drain of precharge switch M3 is connected to the output node V. OUT Electrical connection: The gate of precharge switch M3 is connected to the inverted signal of the precharge clock signal. Auxiliary constant current source I is connected in parallel across the precharge switch M3. The input terminal of auxiliary constant current source I is electrically connected to the high-level power supply, and the output terminal of auxiliary constant current source I is connected to the output node V. OUT Electrical connection.
[0034] The above Figure 1 In the circuit, the input transistor M1, the gating switch transistor M2, and the precharge switch M3 all use PMOS transistors; the output node V OUT The analog voltage corresponding to the output pixel; the output current of the auxiliary constant current source I is in the nanoampere range, and the output current of the auxiliary constant current source I is much smaller than the output node V of the circuit. OUT Line load capacitor ( Figure 1 (The large signal charging and discharging current is not shown in the diagram for simplicity.)
[0035] based on Figure 1 As shown in the structure, the precharge switch is controlled by M3 and is inverted by the precharge clock signal RST. During the high level of the precharge clock signal RST, the precharge switch M3 is closed; during the low level of the precharge clock signal RST, the precharge switch M3 is open. The gating switch transistor M2 is controlled by the inverted signal of the horizontal gating control signal SEL. During the high level of the horizontal strobe control signal SEL, the strobe switch transistor M2 is closed; during the low level of the horizontal strobe control signal SEL, the strobe switch transistor M2 is open. The precharge clock signal RST and the horizontal strobe control signal SEL are two non-overlapping signals; therefore, the precharge switch M3 and the horizontal strobe transistor M2 do not close or open simultaneously.
[0036] In one embodiment of this application, when the precharge switch M3 is closed, the selection switch transistor M2 is open, and the output node V... OUTThe voltage is clamped to the voltage generated by the high-level power supply; this stage is the pre-charge stage. When the pre-charge switch M3 is open, the selector switch transistor M2 is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor M1 operates in the strong inversion saturation region, generating a discharge current. This discharge current rapidly discharges the charge on the column line load capacitor to ground through the input transistor M1.
[0037] When the precharge switch M3 is open, the selector switch transistor M2 is closed. After the dynamic discharge stage, the source follower is in the steady-state follower stage. During the steady-state follower stage, the input transistor M1 operates in the weak inversion region or the medium inversion region. The leakage current of the input transistor M1 is clamped to be equal to the current of the auxiliary constant current source I.
[0038] During the steady-state follow-up phase, the leakage current of the input transistor M1 is clamped to be equal to the current of the auxiliary constant current source I. Therefore, the transconductance of the input transistor M1 has a defined non-zero lower limit, causing the output node V... OUT The signal setup time constant is a fixed and controllable value.
[0039] The above describes the structure of a source follower based on a PMOS transistor. Given the common knowledge of MOS transistors, it is also possible to construct one using an NMOS transistor, as described above. Figure 2 The diagram shows another source follower for an infrared focal plane readout circuit, which includes: an input transistor M1, a gating switch transistor M2, a precharge switch M3, and an auxiliary constant current source I.
[0040] Input transistor M1, whose gate is connected to the output voltage signal V of the infrared focal plane pixel. FD The drain of transistor M2 is connected to the high-level power supply; the drain of transistor M2 is electrically connected to the source of input transistor M1, and the source of transistor M2 is connected to the output node V. OUT Electrically connected, the gate of the strobe switch transistor M2 is connected to the row strobe control signal SEL.
[0041] The precharge switch M3 has its source grounded, and its drain is connected to the output node V. OUT Electrically connected, the gate of precharge switch M3 is connected to the precharge clock signal RST; auxiliary constant current source I is connected in parallel across the two ends of precharge switch M3, and the input terminal of auxiliary constant current source I is connected to the output node V. OUT Electrical connection, the output terminal of auxiliary constant current source I is grounded.
[0042] The above Figure 2 In the circuit, the input transistor M1, the gating switch transistor M2, and the precharge switch M3 all use NMOS transistors; the output node V OUT This is also the analog voltage corresponding to the output pixel; the output current of the auxiliary constant current source I is in the nanoampere range, and the output current of the auxiliary constant current source I is much smaller than the output node V of the circuit.OUT Line load capacitor ( Figure 2 (The large signal charging and discharging current is not shown in the diagram for simplicity.)
[0043] based on Figure 2 As shown in the diagram, the precharge switch M3 is controlled by the precharge clock signal RST. During a high level of the precharge clock signal RST, the precharge switch M3 is closed; during a low level of the precharge clock signal RST, the precharge switch M3 is open. The gating switch transistor M2 is controlled by the horizontal gating control signal SEL. During a high level of the horizontal gating control signal SEL, the gating switch transistor M2 is closed; during a low level of the horizontal gating control signal SEL, the gating switch transistor M2 is open. Here, the precharge clock signal RST and the horizontal gating control signal SEL are two non-overlapping signals; therefore, the precharge switch M3 and the horizontal gating transistor M2 cannot be closed or opened simultaneously.
[0044] In one embodiment of this application, when the precharge switch M3 is closed, the selection switch transistor M2 is open, and the output node V... OUT The voltage is clamped to ground voltage, and this stage is the pre-charge stage. When the pre-charge switch M3 is open, the selector switch transistor M2 is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor M1 operates in the strong inversion saturation region and generates a charging current. This charging current charges the column line load capacitor through the input transistor M1.
[0045] When the precharge switch M3 is open, the selector switch transistor M2 is closed. After the dynamic discharge stage, the source follower is in the steady-state follower stage. During the steady-state follower stage, the input transistor M1 operates in the weak inversion region or the medium inversion region. The leakage current of the input transistor M1 is clamped to be equal to the current of the auxiliary constant current source I.
[0046] During the steady-state follow-up phase, the leakage current of the input transistor M1 is clamped to be equal to the current of the auxiliary constant current source I. Therefore, the transconductance of the input transistor M1 has a defined non-zero lower limit, causing the output node V... OUT The signal setup time constant is a fixed and controllable value.
[0047] This application creatively proposes a novel source follower structure, which utilizes signals to control the conduction timing of the precharge switch M3 and the gating switch transistor M2, enabling the source follower to operate in three stages. The initial precharge stage causes the output node V... OUT The voltage is clamped to either the high-level voltage (in a circuit using a PMOS transistor) or the ground voltage (in a circuit using an NMOS transistor), and then enters the dynamic discharge phase, combined with the clamped output node voltage V. OUTThis causes the input transistor M1 to operate in the strong inversion saturation region, generating a discharge (using a PMOS transistor) or charging current (using an NMOS transistor) to charge or discharge the column line load capacitor. In this way, with zero static bias power consumption, a large transient current is used to achieve a large amplitude and high speed swing of the signal, solving the contradiction that traditional source followers require a large static current to obtain a high slew rate.
[0048] Simultaneously, a nanoampere-level micro-auxiliary current source I is introduced, which forces the leakage current of the input transistor M1 to be clamped as the output current of the auxiliary constant current source I when the source follower is in steady state. This design forces the input transistor M1 to remain in the weak inversion region or the medium inversion region. Therefore, the transconductance of the input transistor M1 has a definite non-zero lower limit, thereby making the time constant of the source follower proposed in this application change from infinity to a controllable constant at the end of the setup, achieving extremely fast final setup.
[0049] Based on the structure of the source follower described above, this application also proposes a readout method, which is applied to the above... Figure 1 or Figure 2 The source follower shown includes the following readout method: Step A1: Within one cycle, first control the precharge switch M3 to close and the gating switch transistor M2 to turn off for a first preset time. The source follower is in the precharge phase. During the precharge phase, if the input transistor M1, the gating switch transistor M2, and the precharge switch M3 are all PMOS transistors, then the output node V will be... OUT The voltage is clamped to the voltage generated by the high-level power supply. If the input transistor M1, the gating switch transistor M2, and the precharge switch M3 are all NMOS transistors, then the output node V will be clamped to the voltage generated by the high-level power supply. OUT The voltage is clamped to ground voltage; Step A2: After the first preset time, the precharge switch M3 is turned off and the gating switch transistor M2 is turned on. The source follower is in the dynamic discharge stage. During the dynamic discharge stage, if the input transistor M1, the gating switch transistor M2, and the precharge switch M3 are all PMOS transistors, the input transistor M1 will generate a discharge current. If the input transistor M1, the gating switch transistor M2, and the precharge switch M3 are all NMOS transistors, the input transistor M1 will generate a charging current. Step A3: Keep the precharge switch M3 open and the selection switch transistor M2 on. As the voltage of the output node decreases (when using a PMOS transistor) or increases (when using an NMOS transistor), the discharge current or charging current gradually decreases until the leakage current of the input transistor M1 and the current of the auxiliary constant current source I reach a dynamic balance. The dynamic discharge stage ends, and the source follower is in the steady-state following stage. The leakage current of the input transistor M1 is clamped to be equal to the current of the auxiliary constant current source I.
[0050] To better understand the source follower and its working principle for the infrared focal plane readout circuit proposed in this application, please refer to... Figure 3 The diagram shown is a sequence diagram of operation, combined with... Figure 1 , Figure 2 The structural diagram shows the working principle of the source follower proposed in this application for the infrared focal plane readout circuit: The first stage is the pre-charge stage, during which the pre-charge switch M3 is closed. The voltage generated by the high-level power supply... (The circuit is constructed using PMOS transistors) or ground voltage. (The circuit is constructed using NMOS transistors) directly charges and discharges the column line load capacitors. Output node V OUT The voltage is forcibly clamped to: or At the same time, the selector transistor M2 is turned off.
[0051] The second stage is the dynamic discharge stage. In this stage, the pre-charge switch M3 is open, and the selection transistor M2 is turned on. At this time, the source-gate voltage of the input transistor (PMOS transistor) M1... The source-gate voltage of the input transistor (NMOS transistor) M1 , V PD This represents the voltage obtained by integrating the current generated by the photodiode across the capacitor. At this point... Much greater than the absolute value of the threshold voltage This gives the input transistor M1 extremely strong conduction capability. Because the input transistor M1 is in the strong inversion saturation region, it generates a huge instantaneous discharge current. It can be approximated by the long-channel square law:
[0052] In the above formula, I D Represents the discharge current or charging current, μ represents the mobility, and C ox The transistor's capacitance per unit area is represented by W, where W represents the width of the transistor and L represents its length. Represents the absolute value of the source-gate voltage of a transistor. This represents the absolute value of the transistor threshold voltage, where... Much larger .
[0053] This huge current I D The line-load capacitors are rapidly charged or discharged. At this time, the initial slew rate (SR) of the circuit is extremely high. , C colThis indicates the capacitance value of the column line load capacitor. Therefore, this stage achieves large-amplitude, high-speed oscillation of the signal using transient high current under the premise of zero static bias power consumption, solving the contradiction that traditional source followers require large static current to obtain high slew rate.
[0054] The third stage is the steady-state stage, during which, as... The input transistor M1 is continuously decreasing. Gradually decrease. When Approaching the final target level ( If there is no auxiliary current source I, then the input transistor M1 will enter the deep subthreshold region, and its leakage current will decrease exponentially. At this time, the transconductance of the input transistor M1 The value rapidly approaches zero, leading to the establishment of a time constant. This results in a severe "long tail effect." However, this application introduces an auxiliary current source I, for example, at the 100nA level. According to Kirchhoff's Current Law (KCL), in steady state, current flows into the output node V. OUT The current must be equal to the current flowing out of the node, meaning the leakage current of the input transistor M1 is forcibly clamped to: , I KEEP This represents the current value of the auxiliary current source I. This design forces the input transistor M1 to remain in the weak inversion region or the moderate inversion region, at which point the transconductance of the input transistor M1... It has a definite non-zero lower limit, namely the transconductance g m Satisfy the following formula:
[0055] In the above formula, I keep This represents the current value of the auxiliary constant current source, and n represents the subthreshold slope factor. This represents the thermal voltage, which is approximately 26 mV at room temperature. Therefore, the time constant τ at the establishment end of the source follower proposed in this application... settling Fixed at: As can be seen from the formula, due to the introduction of the auxiliary current source I, the settling time constant changes from infinity to a controllable constant, thus achieving extremely rapid final settling.
[0056] Furthermore, the source follower proposed in this application for infrared focal plane readout circuits has the characteristics of anti-interference and IRDrop elimination, specifically: 1. Interference immunity: In steady state, the output impedance presented by the output node VOUT to small AC signals is... R out for: This means that the column line is no longer a high-resistivity floating node. Any noise charge coupled from neighboring columns... All signals will be rapidly discharged through this low-impedance path, thereby significantly improving the signal integrity of the pixel array.
[0057] 2. Eliminating the IR Drop Effect: As mentioned above, the current of a traditional source follower can reach the microampere level, leading to increased parasitic resistance. Pressure drop great, I bias This represents the current of a traditional source follower. However, in this application, At only nanosafety level, this reduces performance by at least two orders of magnitude compared to traditional architectures. Therefore, the source follower proposed in this application... Approaching the microvolt level, it completely eliminates the phenomenon of vertical brightness gradient in images caused by different physical positions.
[0058] It should be noted that when those skilled in the art encounter the aforementioned problems of high power consumption and severe IR drop in traditional source followers, the logical evolution direction is to "completely eliminate static bias current." This leads to a strong technical bias: adding a static current source is absolutely forbidden, otherwise it would be "going backwards." Therefore, current technical solutions proposed by those skilled in the art to address the problems of this traditional structure are all designed with the idea of "completely eliminating static bias current" in mind. However, as explained above, the source follower proposed in this application creatively breaks this technical bias, taking the opposite approach by adding a nanoampere-level auxiliary current source and combining it with a pre-charge switch, proposing a corresponding operating timing sequence, and solving the problems of the traditional structure with very few components. This is something that those skilled in the art have not yet achieved.
[0059] In summary, the source follower for the infrared focal plane readout circuit proposed in this application includes: the gate of the input transistor is connected to the output voltage signal of the infrared focal plane pixel, and the drain is grounded; the drain of the gating switch transistor is electrically connected to the source of the input transistor, the source of the gating switch transistor is electrically connected to the output node, and the gate of the gating switch transistor is connected to the row gating control signal.
[0060] The source of the precharge switch is electrically connected to the high-level power supply, the drain of the precharge switch is electrically connected to the output node, and the gate of the precharge switch is connected to the precharge clock signal; the auxiliary constant current source is connected in parallel across the two ends of the precharge switch, the input of the auxiliary constant current source is electrically connected to the high-level power supply, and the output of the auxiliary constant current source is electrically connected to the output node.
[0061] The input transistor, gating switch transistor, and precharge switch all use PMOS transistors; alternatively, NMOS transistors can be used. If NMOS transistors are used, the gate of the input transistor is connected to the output voltage signal of the infrared focal plane pixel, and its drain is connected to a high-level power supply. The drain of the gating switch transistor is connected to the source of the input transistor, and its source is connected to the output node. Its gate is connected to the horizontal gating control signal. The source of the precharge switch is grounded, its drain is connected to the output node, and its gate is connected to the precharge clock signal. An auxiliary constant current source is connected in parallel across the precharge switch, with its input connected to the output node and its output grounded.
[0062] Regardless of the NMOS transistor structure used in the source follower, its output node outputs the analog voltage corresponding to the pixel; while the output current of the auxiliary constant current source is in the nanoampere range. The output current of the auxiliary constant current source is much smaller than the large-signal charging and discharging current of the column line load capacitor connected to the circuit's output node.
[0063] Unlike traditional source follower structures, this application creatively proposes a novel source follower structure. By controlling the conduction timing of the pre-charge switch and the gating switch transistors, the source follower operates in three stages. In the initial pre-charge stage, the output node voltage is clamped to either a high-level voltage or ground. Then, in the dynamic discharge stage, combined with the clamped output node voltage, the input transistor operates in the strong inversion saturation region, generating a discharge or charging current to charge or discharge the column-line load capacitor. Thus, with zero static bias power consumption, a large transient current is used to achieve large-amplitude, high-speed signal oscillation, resolving the contradiction that traditional source followers require a large static current to achieve a high slew rate.
[0064] Simultaneously, a nanoampere-level micro-auxiliary current source is introduced, which forces the leakage current of the input transistor to be clamped as the output current of the auxiliary constant current source when the source follower is in steady state. This design forces the input transistor to remain in the weak inversion region or the medium inversion region. Therefore, the transconductance of the input transistor has a definite non-zero lower limit, thereby making the time constant of the source follower proposed in this application change from infinity to a controllable constant at the end of the setup, achieving extremely fast final setup.
[0065] Furthermore, in steady state, the output impedance presented by the output node to small AC signals makes the column line no longer a high-impedance floating node. Any noise charge coupled from neighboring columns... All signals are rapidly discharged through this low-impedance path, significantly improving the signal integrity of the pixel array. The output current of the auxiliary constant current source is only in the nanoampere range, at least two orders of magnitude lower than traditional architectures. Therefore, the ohmic voltage drop approaches the microvolt level, completely eliminating the vertical brightness gradient phenomenon in the image caused by different physical locations. The source follower proposed in this application has broad application prospects and high practicality.
[0066] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0067] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0068] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.
Claims
1. A source follower for an infrared focal plane readout circuit, characterized in that, include: The input transistor has its gate connected to the output voltage signal of the infrared focal plane pixel, and its drain grounded. A gating switch transistor, the drain of which is electrically connected to the source of the input transistor, the source of which is electrically connected to the output node, and the gate of which is connected to the inverted signal of the row gating control signal; The source of the precharge switch is electrically connected to a high-level power supply, the drain of the precharge switch is electrically connected to the output node, and the gate of the precharge switch is connected to the inverted signal of the precharge clock signal. An auxiliary constant current source is connected in parallel across the precharge switch. The input terminal of the auxiliary constant current source is electrically connected to the high-level power supply, and the output terminal of the auxiliary constant current source is electrically connected to the output node. The input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors; the output node outputs the analog voltage corresponding to the pixel. The output current of the auxiliary constant current source is in the nanoampere range.
2. The source follower according to claim 1, characterized in that, When the precharge switch is closed, the gating switch transistor is turned off, and the voltage of the output node is clamped to the voltage generated by the high-level power supply; When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor operates in the strong inversion saturation region and generates a discharge current. This discharge current rapidly discharges the charge on the column line load capacitor to ground through the input transistor. When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the steady-state follower stage after the dynamic discharge stage. During the steady-state follower stage, the input transistor operates in the weak inversion region or the medium inversion region, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source. During the steady-state following phase, the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source, and the transconductance of the input transistor is a defined non-zero lower limit value, so that the signal setup time constant of the output node is a fixed and controllable value.
3. The source follower according to claim 1, characterized in that, The precharge switch is controlled by the inverted signal of the precharge clock signal. During the high level of the precharge clock signal, the precharge switch is closed, and during the low level of the precharge clock signal, the precharge switch is open. The gating switch transistor is controlled by the inverted signal of the row gating control signal. During the high level of the row gating control signal, the gating switch transistor is closed, and during the low level of the row gating control signal, the gating switch transistor is open. The precharge clock signal and the row selection control signal are two signals that do not overlap.
4. A source follower for an infrared focal plane readout circuit, characterized in that, include: The input transistor has its gate connected to the output voltage signal of the infrared focal plane pixel, and its drain is electrically connected to a high-level power supply. A gating switch transistor, the drain of which is electrically connected to the source of the input transistor, the source of which is electrically connected to the output node, and the gate of which is connected to a row gating control signal; A precharge switch with its source grounded, the drain of the precharge switch electrically connected to the output node, and the gate of the precharge switch connected to a precharge clock signal; An auxiliary constant current source is connected in parallel across the precharge switch. The input terminal of the auxiliary constant current source is electrically connected to the output node, and the output terminal of the auxiliary constant current source is grounded. The input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors; the output node outputs the analog voltage corresponding to the pixel. The output current of the auxiliary constant current source is in the nanoampere range.
5. The source follower according to claim 4, characterized in that, When the precharge switch is closed, the gating switch transistor is turned off, and the voltage of the output node is clamped to ground voltage; When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the dynamic discharge stage. During the dynamic discharge stage, the input transistor operates in the strong inversion saturation region and generates a charging current. This charging current charges the column line load capacitor rapidly through the input transistor. When the precharge switch is open, the gating switch transistor is closed, and the source follower is in the steady-state follower stage after the dynamic discharge stage. During the steady-state follower stage, the input transistor operates in the weak inversion region or the medium inversion region, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source. During the steady-state following phase, the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source, and the transconductance of the input transistor is a defined non-zero lower limit value, so that the signal setup time constant of the output node is a fixed and controllable value.
6. The source follower according to claim 4, characterized in that, The precharge switch is controlled by the precharge clock signal. During the high level of the precharge clock signal, the precharge switch is closed, and during the low level of the precharge clock signal, the precharge switch is open. The gating switch transistor is controlled by the row gating control signal. During the high level of the row gating control signal, the gating switch transistor is closed, and during the low level of the row gating control signal, the gating switch transistor is pre-opened. The precharge clock signal and the row selection control signal are two signals that do not overlap.
7. A readout method, characterized in that, The readout method is applied to the source follower according to any one of claims 1-3, or to the source follower according to any one of claims 4-6, and the readout method includes: Within one cycle, the precharge switch is first closed and the gating switch transistor is turned off for a first preset time. The source follower is in the precharge phase. During the precharge phase, if the input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors, the voltage of the output node is clamped to the voltage generated by the high-level power supply. If the input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors, the voltage of the output node is clamped to the ground voltage. After a first preset time, the precharge switch is turned off and the gating switch transistor is turned on. The source follower is in a dynamic discharge phase. During the dynamic discharge phase, if the input transistor, the gating switch transistor, and the precharge switch are all PMOS transistors, the input transistor generates a discharge current. If the input transistor, the gating switch transistor, and the precharge switch are all NMOS transistors, the input transistor generates a charging current. With the precharge switch open and the selector switch transistor on, as the voltage of the output node decreases or increases, the discharge current or the charging current gradually decreases until the leakage current of the input transistor and the current of the auxiliary constant current source reach a dynamic balance. The dynamic discharge stage ends, the source follower is in the steady-state following stage, and the leakage current of the input transistor is clamped to be equal to the current of the auxiliary constant current source.
8. The readout method according to claim 7, characterized in that, The source follower is in a dynamic discharge phase, and the input transistor operates in the strong inversion saturation region. The resulting discharge current or charging current satisfies the following equation based on the square-law characteristic of a long-channel transistor: In the above formula, I D The discharge current or the charging current is represented by μ, where μ represents mobility and C is the charge current. ox The transistor's capacitance per unit area is represented by W, where W represents the width of the transistor and L represents its length. Represents the absolute value of the source-gate voltage of a transistor. This represents the absolute value of the transistor threshold voltage, where... Much larger .
9. The readout method according to claim 7, characterized in that, The source follower is in a steady-state following phase, and the input transistor operates in the weak inversion region or the moderate inversion region, with its transconductance g m Satisfy the following formula: In the above formula, I keep This represents the current value of the auxiliary constant current source, and n represents the subthreshold slope factor. Indicates thermal voltage; The signal setup time constant of the output node is a fixed and controllable value, satisfying the following formula: In the above formula, τ settling C represents the signal settling time constant. col This indicates the capacitance value of the column line load capacitor.
10. The readout method according to claim 9, characterized in that, When the source follower is in the steady-state following phase, the output impedance of the output node to a small AC signal satisfies the following formula: In the above formula, R out This indicates the output impedance.